WO2018121131A1

WO2018121131A1 - Junction field-effect transistor and fabricating method thereof

Info

Publication number: WO2018121131A1
Application number: PCT/CN2017/112262
Authority: WO
Inventors: 林中瑀
Original assignee: 无锡华润上华科技有限公司
Priority date: 2016-12-30
Filing date: 2017-11-22
Publication date: 2018-07-05
Also published as: CN108269857B; CN108269857A

Abstract

A junction field-effect transistor and a fabricating method thereof. The junction field-effect transistor comprises a substrate (100), and an epitaxial layer (200) and a dielectric mask layer sequentially arranged on the substrate. A first conductive type well region (210) is arranged in the epitaxial layer (200). A drain region (213) and a source region (211) are arranged in the first conduction type well region (210). The dielectric mask layer is used to define the source region (211) and the drain region (213). The dielectric mask layer corresponding to the drain region (213) comprises a plurality of separate mask sub-units separating the drain region into a plurality of separated drain region sub-units (2131). The drain region sub-units (2131) and the mask sub-units are arranged to have a one-to-one correspondence.

Description

Junction field effect transistor and manufacturing method thereof

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a junction field effect transistor and a method of fabricating the same.

Background technique

Electrostatic discharge refers to charge transfer caused by objects with different electrostatic potentials coming close to each other or directly contacting each other. In the case of electrostatic discharge, a large current that will be generated in a short period of time will cause fatal damage to the integrated circuit, which is an important problem causing failure in the production of integrated circuits. For example, Human Body Model Electrostatic Discharge (HBM), which usually occurs in a few hundred nanoseconds, may have a maximum current peak of several amps; and machine model (MM), charged device model (CDM) static electricity The discharge takes less time and the current is larger. Such a large current flows through the integrated circuit in a short period of time, and the power consumption will be severely exceeded by the maximum value that it can withstand, thereby causing serious physical damage to the integrated circuit and eventually failing.

The problem of electrostatic discharge is generally solved by two inventions of the external environment and the circuit itself. One: application of materials that are not easy to generate static electricity, increase of environmental humidity, grounding of operators and equipment to reduce the generation of static electricity and timely elimination of static electricity; second: mainly to increase the electrostatic discharge tolerance of the integrated circuit itself, for example, add extra The electrostatic protection device or circuit protects the internal circuitry of the integrated circuit from electrostatic discharge damage.

However, for the application environment of the Junction Field-Effect Transistor (JFET), no external ESD protection device or circuit is allowed to protect, and the ability of the traditional junction field effect transistor to resist ESD by itself is compared. weak.

Summary of the invention

Based on this, it is necessary to provide a junction field effect transistor capable of improving its own electrostatic discharge protection capability and a method of fabricating the same.

A junction field effect transistor includes: a substrate, an epitaxial layer and a mask dielectric layer sequentially disposed on the substrate;

The epitaxial layer includes a first conductivity type well region, and the first conductivity type well region is provided with a drain region and a source region;

The mask dielectric layer defines the source region and the drain region, wherein the mask dielectric layer disposed corresponding to the drain region includes a plurality of separately arranged mask sub-units, so that the drain region is separated into multiple One drain sub-unit, and the drain sub-unit is disposed in one-to-one correspondence with the mask sub-unit.

In addition, a method of fabricating a junction field effect transistor is provided, including:

Providing a substrate and forming an epitaxial layer on the substrate;

Forming a first conductivity type well region in the epitaxial layer by ion implantation;

Forming a mask dielectric layer on the epitaxial layer;

Etching the mask dielectric layer to divide the mask dielectric layer into a plurality of separately arranged mask sub-units, wherein the plurality of separately arranged mask sub-cells are located in the first conductive region Corresponding to the location of the drain region in the type well region;

The plurality of separately arranged mask sub-cells are removed, and the first conductivity type ions are implanted into the first conductivity type well region to form a drain region, and a plurality of separately arranged drain region sub-cells are formed.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and those skilled in the art can obtain drawings of other embodiments according to the drawings without any creative work.

1 is a schematic diagram of a junction field effect transistor pattern in an embodiment;

Figure 2 is a cross-sectional view taken along line A-A of Figure 1;

Figure 3 is a cross-sectional view taken along line B-B of Figure 1;

4 is a schematic diagram of a drain region of a junction field effect transistor in an embodiment;

5 is a schematic diagram of a drain region of a junction field effect transistor in another embodiment;

6 is a schematic diagram of a drain region of a junction field effect transistor in still another embodiment;

7 is a schematic diagram of a drain region of a junction field effect transistor in still another embodiment;

8 is a flow chart showing a method of fabricating a junction field effect transistor in an embodiment;

9 to 15 are schematic views showing the structure in the process of fabricating a junction field effect transistor.

detailed description

In order to facilitate the understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the understanding of the present disclosure will be more fully understood.

All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. The terminology used in the description of the present invention is for the purpose of describing particular embodiments and is not intended to limit the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

1 is a schematic diagram of a junction field effect transistor pattern in FIG. 1; FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1; and FIG. 3 is a schematic cross-sectional view taken along line B-B of FIG. Referring to FIGS. 1 through 3, a junction field effect transistor includes a substrate 100, an epitaxial layer 200 and a mask dielectric layer 300 sequentially disposed on the substrate 100 (refer to FIGS. 12-14). A first conductivity type well region 210 is disposed in the epitaxial layer 200, and a drain region 213 and a source region 211 are disposed in the first conductivity type well region 210. The mask dielectric layer 300 is configured to define the source region 211 and the drain region 213, wherein the mask dielectric layer 300 disposed corresponding to the drain region 213 includes a plurality of separately arranged mask sub-units, such that The drain region 213 is separated into a plurality of drain sub-units 2131, and the drain sub-units 2131 are disposed in one-to-one correspondence with the mask sub-units.

When a large current impinges on a certain drain subunit 2131, the temperature of the struck drain subunit 2131 rises, and the resistance thereof also increases, thereby reducing the ability of current to flow, and the current is gradually Dispersing into other drain sub-units 2131 adjacent thereto, the effect of current sharing is achieved, the anti-static discharge capability of the junction field effect transistor is improved, and the self-protection function is provided.

In an embodiment, the substrate 100 may be a Si, Ge, SiGe, GaAs substrate 100 or other II-VI, III-V and IV-IV binary or ternary compound semiconductor substrate 100, on insulator A silicon-on-insulator (SOI) substrate 100 or a germanium-on-insulator (GOI) substrate 100 on an insulator. In the present embodiment, a trivalent element is doped in the silicon substrate 100 to form a P-type semiconductor substrate 100, wherein the P-type semiconductor substrate 100 has a higher resistivity, and thus the substrate 100 can be depleted. In other embodiments, the pentavalent element may also be doped in the silicon substrate 100 to form the N-type semiconductor substrate 100.

An epitaxial layer 200 is disposed on the substrate 100. The epitaxial layer 200 is formed by ion implantation to form a buried layer 110, and the epitaxial layer 200 is epitaxially formed by the buried layer 110. In the present embodiment, the P-type buried layer 110 is formed by implanting trivalent ions, and the epitaxial layer 200 is formed by epitaxial techniques for the P-type buried layer 110.

A first conductivity type well region 210 is formed by implanting a first conductivity type ion in the epitaxial layer 200 and a long time high temperature push well. Wherein, the first conductivity type ion is a phosphorus ion, which forms an N-type well region. The N-type well region includes a high voltage N-type well region 210a and a low voltage N-type well region 210b. In one embodiment, the high-voltage N-type well region 210a is first formed by phosphorus ion implantation, an implantation energy of 100 keV, and subsequent high temperature annealing at a temperature of 1000 ° C to 1150 ° C for several hours. In the formed high-voltage N-type well region 210a, phosphorus ion implantation is again performed, the implantation energy is 300 keV, and then high-temperature annealing is performed at a temperature of 1000 ° C to 1150 ° C for several hours to form a low-pressure N-type well region 210b.

Wherein, a source region 211 is formed by doping a high concentration of phosphorus ions in the high voltage N-type well region 210a, and a high concentration of phosphorus ions is doped in the low-voltage N-type well region 210b to form a drain region 213.

In an embodiment, the junction field effect transistor further includes a second conductivity type well region 220, the second conductivity type well region 220 is located outside the first conductivity type well region 210, and surrounds the first conductive region Type well region 210; wherein the first conductivity type well region 210 is opposite to the conductivity type of the second conductivity type well region 220. The second conductivity type well region 220 is a P-type well region. The P-type well region is an isolation region for isolating the junction FET and the peripheral logic circuit. At high pressure Both sides of the N-type well region 210a are also formed by two boron ion implantations, and a high-temperature push well forms a deep P well region 220a and a low voltage P-type well region 220b.

The mask dielectric layer 300 is located above the epitaxial layer 200, and the mask dielectric layer 300 may be silicon oxide, silicon nitride, silicon oxynitride or other high-k material dielectric layers. In the present embodiment, the mask dielectric layer 300 is formed by depositing silicon nitride on the epitaxial layer 200. The mask dielectric layer 300 defines a source region 211 and a drain region 213, that is, the mask dielectric layer 300 is etched by a photoresist, and the source region 211 and the drain region 213 are defined. Wherein, when the drain region 213 is defined, the mask dielectric layer 300 disposed corresponding to the drain region 213 is etched into a plurality of separately arranged mask sub-units by a lithography plate. Referring to FIG. 4, when the drain region 213 is formed, the drain region 213 formed therein also forms a plurality of drain region sub-units 2131 according to the arrangement of the mask sub-units, wherein the drain region sub-unit 2131 and the mask The membrane subunits are arranged one by one.

The junction field effect transistor further includes a field oxide layer 400 on the epitaxial layer 200. The mask dielectric layer 300 is etched away, and after the source region 211 and the drain region 213 are defined, the mask dielectric layer 300 is used as a mask at a position corresponding to the source region 211 and the drain region 213, and is generated by a thermal oxidation process. Field oxide layer 400. Since, when the drain region 213 is defined, the mask dielectric layer 300 disposed corresponding to the drain region 213 is etched into a plurality of separately arranged mask sub-units by a lithography plate. That is, a plurality of separately arranged through holes are formed in the field oxide layer 400 disposed corresponding to the drain region 213, and the plurality of separately arranged via holes are in one-to-one correspondence with the plurality of separately arranged mask sub-units.

The mask dielectric layer 300 for defining the source region 211 and the drain region 213 is removed using the field oxide layer 400 as a mask. The source region 211 and the drain region 213 are formed by implanting phosphorus ions in the corresponding source region 211 and drain region 213. Since, when the drain region 213 is defined, the mask dielectric layer 300 disposed corresponding to the drain region 213 is etched into a plurality of separately arranged mask sub-units by a lithography plate. After a plurality of separately arranged mask sub-units are etched away, a plurality of drain sub-units 2131 having the same arrangement as the mask sub-units may be formed by implanting phosphorus ions at corresponding positions, wherein the drain regions The subunit 2131 is disposed in one-to-one correspondence with the mask subunit. That is, the plurality of drain sub-units 2131 are isolated by the field oxide region, and then the plurality of drain sub-units 2131 are separately disposed. When a large current impinges on any of the plurality of drain sub-units 2131, the temperature of the damaged drain sub-unit 2131 rises, and its resistance It also becomes larger, thereby reducing the ability of current to flow, and the current is gradually dispersed to the other drain sub-units 2131 adjacent thereto, thereby achieving the effect of current sharing and improving the antistatic discharge of the junction field effect transistor. The ability to have a self-protection function.

In an embodiment, the plurality of drain sub-units 2131 are arranged in a regular matrix. That is, the plurality of drain sub-units 2131 are arranged in a single row or in a single column.

In an embodiment, referring to FIG. 5, if the required drain area requirement is large, the plurality of drain sub-units 2131 may be arranged in a matrix form of multiple rows and columns, and the specific arrangement manner may be according to actual needs. set up.

In an embodiment, a plurality of the drain sub-units 2131 are equally spaced. In the actual working process, the position of the current impinging on the drain sub-unit 2131 is random. If a plurality of the drain sub-units 2131 are equally spaced, the shunting capability of the plurality of drain sub-units 2131 is the same.

In an embodiment, a plurality of the drain sub-units 2131 may also be disposed from the center to the periphery. Of course, it is also possible to count the probability of the position where the large current appears in actual operation, the pitch of the plurality of drain sub-units 2131 at the position where the probability is high is small, and the pitch of the plurality of drain sub-units 2131 at the position where the probability is low. Big. The spacing of the plurality of drain sub-units 2131 can be set according to actual needs.

In an embodiment, referring to FIG. 6 and FIG. 7, the cross section of the drain sub-unit 2131 along the plane of the substrate 100 is at least one of a circle, a rectangle, a diamond, a triangle, and a hexagon. In this embodiment, the cross section of the drain sub-unit 2131 along the plane of the substrate 100 is circular, and a plurality of circular drain sub-units 2131 are arranged at equal intervals in a single column, as shown in FIG. In other embodiments, the plurality of drain sub-units 2131 within the same drain region 213 may also include circular, rectangular or other shapes. The number, arrangement, shape, and pitch of the plurality of drain sub-units 2131 included in the drain region 213 may be arbitrarily combined, and are not limited to the description in the above embodiment.

In an embodiment, the junction field effect transistor further includes a polysilicon gate 500 on the field oxide layer 400. Wherein, the polysilicon gate 500 extends from the source region 211 to above the field oxide layer 400.

In addition, a method for fabricating a junction field effect transistor is also provided. Referring to FIG. 8, the method includes the following steps:

Step S810: providing a substrate and forming an epitaxial layer on the substrate.

Referring to FIG. 9, a substrate 100 is provided, wherein the substrate 100 may be a Si, Ge, SiGe, GaAs substrate 100 or other binary or ternary compound semiconductor substrate of Groups II-VI, III-V and IV-IV. 100. A silicon-on-insulator (SOI) substrate 100 or a germanium-on-insulator (GOI) substrate 100 on an insulator. In the present embodiment, a trivalent element is doped in the silicon substrate 100 to form a P-type semiconductor substrate 100.

A buried layer 110 is formed on the substrate 100 by ion implantation, and an epitaxial layer 200 is formed by epitaxial formation of the buried layer 110. In the present embodiment, the P-type buried layer 110 is formed by implanting trivalent ions, and the epitaxial layer 200 is formed by epitaxial techniques for the P-type buried layer 110.

Step S820: forming a first conductivity type well region in the epitaxial layer by ion implantation, with reference to FIGS. 10-11.

The first conductivity type well region 210 is formed by implanting the first conductivity type ions in the epitaxial layer 200 by using a long time high temperature push well. The N-type well region includes a high voltage N-type well region 210a and a low voltage N-type well region 210b. Wherein, the first conductivity type ion is phosphorus ion, the implantation energy is 100 KeV, and the high temperature N-type well region 210a is formed by pushing the well at a high temperature for a long time (1000 ° C to 1150 ° C).

In one embodiment, it is further included on both sides of the high voltage N-type well region 210a, and also through the boron ion implantation, the high temperature push well forms the deep P well region 220a.

In the formed high-voltage N-type well region 210a, phosphorus ion implantation is again performed, the implantation energy is 300 keV, and then high-temperature annealing is performed at a temperature of 1000 ° C to 1150 ° C for several hours to form a low-pressure N-type well region 210 b.

In one embodiment, the method further includes implanting boron ions in the deep P well region 220a, and the high temperature push well forms the low voltage P-well region 220b. Among them, the deep P well region 220a and the low voltage P type well region 220b function as isolation.

Step S830: depositing a mask dielectric layer 300 on the epitaxial layer 200.

In one embodiment, referring to FIG. 12, a mask dielectric layer 300 is formed by depositing silicon nitride on epitaxial layer 200. In other embodiments, the mask dielectric layer 300 can also be formed by depositing silicon oxide, silicon oxynitride, or other high-k materials on the epitaxial layer 200.

Step S840: etching the mask dielectric layer to divide the mask dielectric layer into a plurality of separately arranged mask subunits, wherein the plurality of separately arranged mask subunits are located in the same area as the The position of the drain region formed in the well region of the first conductivity type corresponds to.

The mask dielectric layer 300 defines a source region 211 and a drain region 213, that is, the mask dielectric layer 300 is etched by a photoresist plate. Referring to FIG. 13, the source region 211 and the drain region 213 are defined. Wherein, when the drain region 213 is defined, the mask dielectric layer 300 disposed corresponding to the drain region 213 is etched into a plurality of separately arranged mask sub-units by a lithography plate. Then, when the drain region 213 is formed, the drain region 213 formed is formed in a plurality of drain region sub-units 2131 according to the arrangement of the mask sub-units, wherein the drain region sub-unit 2131 and the mask are formed. The subunits are set one by one.

The method also includes the step of depositing a field oxide layer 400 on the epitaxial layer 200, with reference to FIG.

The mask dielectric layer 300 is etched away, and after the source region 211 and the drain region 213 are defined, the mask dielectric layer 300 is used as a mask at a position corresponding to the source region 211 and the drain region 213, and is generated by a thermal oxidation process. Field oxide layer 400. Since, when the drain region 213 is defined, the mask dielectric layer 300 disposed corresponding to the drain region 213 is etched into a plurality of separately arranged mask sub-units by a lithography plate. That is, a plurality of separately arranged through holes are formed in the field oxide layer 400 disposed corresponding to the drain region 213, and the plurality of separately arranged via holes are in one-to-one correspondence with the plurality of separately arranged mask sub-units.

Step S850: removing the plurality of separately arranged mask sub-units, injecting first conductivity type ions into the first conductive type well region to form a drain region, and forming a plurality of separately arranged drain region sub-units.

A plurality of separately arranged mask dielectric layers 300 for defining the source region 211 and the drain region 213 are removed by using the field oxide layer 400 as a mask. The source region 211 and the drain region 213 are formed by injecting a high concentration of the first conductivity type ions (phosphorus ions) in the corresponding source region 211 and drain region 213, with reference to FIG. Since, when the drain region 213 is defined, the mask dielectric layer 300 disposed corresponding to the drain region 213 is etched into a plurality of separately arranged mask sub-units by a lithography plate. After a plurality of separately arranged mask sub-units are etched and removed, a plurality of first conductivity type ions (phosphorus ions) can be implanted at corresponding positions to form a plurality of drain regions having the same arrangement as the mask sub-units. Subunit 2131, wherein the drain subunit 2131 is arranged in one-to-one correspondence with the mask subunits. That is, the plurality of drain sub-units 2131 are isolated by the field oxide region, and then the plurality of drain sub-units 2131 are separately disposed.

In one embodiment, the drain sub-unit 2131 has a circular cross section along the plane of the substrate 100, and a plurality of circular drain sub-units 2131 are arranged at equal intervals in a single row. When a large current impinges on any of the plurality of drain sub-units 2131, the temperature of the struck sub-cell 2131 is increased, and the resistance thereof is also increased, thereby reducing the ability of current to flow. The current is gradually dispersed to the other drain sub-units 2131 adjacent thereto, which has the effect of current sharing, improves the anti-static discharge capability of the junction field effect transistor, and has the function of self-protection.

The technical features of the above-described embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be considered as the scope of this manual.

The above-described embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims

A junction field effect transistor includes: a substrate, an epitaxial layer and a mask dielectric layer sequentially disposed on the substrate;

a first conductivity type well region is disposed in the epitaxial layer, and a drain region and a source region are disposed in the first conductivity type well region;

The mask dielectric layer is configured to define the source region and the drain region, wherein the mask dielectric layer disposed corresponding to the drain region includes a plurality of separately arranged mask sub-units to separate the drain region And forming a plurality of drain sub-units, and the drain sub-units are disposed in one-to-one correspondence with the mask sub-units.
The junction field effect transistor of claim 1, wherein the plurality of drain sub-units are arranged in a regular matrix.
The junction field effect transistor of claim 1, wherein a plurality of said drain sub-units are equally spaced.
A junction field effect transistor according to claim 1, wherein a plurality of said drain sub-units are disposed from the center to the periphery.
The junction field effect transistor according to claim 1, wherein a cross section of the drain region sub-unit along a plane of the substrate is at least one of a circle, a rectangle, a diamond, a triangle, and a hexagon.
The junction field effect transistor of claim 1 wherein said first conductivity type well region comprises a low voltage well region and a high voltage well region; said source region is located in said high voltage well region, said drain region being located in said Low pressure well zone.
The junction field effect transistor of claim 1 further comprising a second conductivity type well region, said second conductivity type well region being located outside said first conductivity type well region and surrounding said first conductivity type a well region; wherein the first conductivity type well region and the second conductivity type well region have opposite conductivity types.
The junction field effect transistor of claim 7, wherein the first conductivity type well region is an N type well region and the second conductivity type well region is a P type well region.
The junction field effect transistor of claim 8 wherein said P-type well region comprises Deep P-well region and low-voltage P-well region.
The junction field effect transistor of claim 1 further comprising a field oxide layer on said epitaxial layer; said field oxide layer disposed corresponding to said drain region is provided with a plurality of separately arranged via holes, The through holes are disposed in one-to-one correspondence with the mask subunits.
The junction field effect transistor of claim 10 further comprising a polysilicon gate over said field oxide layer, said polysilicon gate extending from said source region to said field oxide layer .
A method for fabricating a junction field effect transistor, comprising:

Providing a substrate and forming an epitaxial layer on the substrate;

Forming a first conductivity type well region in the epitaxial layer by ion implantation;

Forming a mask dielectric layer on the epitaxial layer;

Etching the mask dielectric layer to divide the mask dielectric layer into a plurality of separately arranged mask sub-units, wherein the plurality of separately arranged mask sub-cells are located in the first conductive region Corresponding to the location of the drain region in the type well region;

The plurality of separately arranged mask sub-cells are removed, and the first conductivity type ions are implanted into the first conductivity type well region to form a drain region, and a plurality of separately arranged drain region sub-cells are formed.
The method according to claim 12, wherein said first conductivity type well region is an N-type well region; said said first conductivity type well region is formed in said epitaxial layer by ion implantation, said ion implantation ,include:

By injecting phosphorus ions, the well is formed to form a high voltage N-type well region;

A low-pressure N-type well region is formed by annealing by phosphorus ion implantation in the formed high-voltage N-type well region.
The method of claim 13 further comprising:

Forming a deep P-well region on the two sides of the high-voltage N-type well region by boron ion implantation;

Boron ions are implanted again in the deep P well region, and the well is formed to form a low voltage P-type well region.
The method of claim 12, wherein the plurality of drain sub-units are arranged in a regular matrix.
The method according to claim 12, wherein the cross section of the drain sub-unit along the plane of the substrate is at least one of a circle, a rectangle, a diamond, a triangle, and a hexagon.
The method of claim 12 further comprising the step of depositing a field oxide layer on said epitaxial layer.