WO2018120006A1

WO2018120006A1 - Printed circuit board with integrated positive temperature coefficient device

Info

Publication number: WO2018120006A1
Application number: PCT/CN2016/113459
Authority: WO
Inventors: Ellen Li; Steven Hu; Bing Wang; Jesse ZHOU
Original assignee: Littelfuse Electronics (Shanghai) Co., Ltd.
Priority date: 2016-12-30
Filing date: 2016-12-30
Publication date: 2018-07-05
Also published as: CN110741524A; TW201841450A; CN110741524B

Abstract

An apparatus includes a first cable plug (104) assembly. The apparatus further includes a printed circuit board (PCB) (116) having a plurality of layers, the PCB (116) to couple to the first cable plug (104) assembly. A positive temperature coefficient (PTC) device (102) may be disposed on a first layer (302) of the plurality of layers, and a second layer (304) of the plurality of layers may be disposed over the first layer (302) of the plurality of layers.

Description

PRINTED CIRCUIT BOARD WITH INTEGRATED POSITIVE TEMPERATURE COEFFICIENT DEVICE

BACKGROUND

Field

The present disclosure generally relates to printed circuit boards (PCBs) . In particular, the present disclosure relates to a PCB that has an integrated positive temperature coefficient (PTC) device that may be used with a Universal Serial Bus (USB) cable.

Description of Related Art

A Universal Serial Bus (USB) interface includes a differential pair of signals (D+and D-) for signaling and also provides power and ground. With regard to the delivery of power, a USB cable can only provide a certain amount of current. For example, the USB 2.0 standard allows for a maximum output current of 500 mA whereas the USB 3.0 standard allows a maximum output current of 900 mA. Traditionally, the delivery of power through a USB cable occurs using an output voltage of 5V. But modern mobile device batteries typically have a storage capacity of several thousand milliamps. The charging of such batteries, even at the increased output currents allowed in the USB 3.0 standard, would thus be delayed if the power is delivered using a 5V output voltage. This charging delay is exacerbated since a switching power supply associated with the USB cable, the USB cable, and the receiving device all present a resistance to the output current.

To enable a rapid charge mode in light of the output current limitations and associated losses from device resistances, it is conventional to use markedly higher output voltages over the USB cable. For example, rather than use the default USB output voltage of 5V, rapid charging modes have been developed that use 9V, 12V, or even 19V. The increased voltages allow the switching power supply to deliver more power over the USB cable without exceeding the maximum output current limitations.

Although rapid charging modes are advantageous, problems have arisen with regard to their implementation. For example, the USB cable interface may get dirty such that a dust particle or other slightly conductive object couples between the supply voltage pin (the pin delivering the output voltage) and one of the differential signaling pins D+ and D-. Alternatively, the USB cable itself may become frayed from twisting by a user such that a slightly conductive path exists between the supply voltage wire and one of the wires for the D+ and D-signals. The result is a short between supply voltage and one of the differential data signals in the USB cable. A short between supply voltage and one of the differential data signals in the USB cable may cause overheating and damage to the USB cable and/or a device coupled to the USB cable.

Accordingly, there is a need in the art for improved protection against shorts over data interfaces. Other problems with conventional short protection techniques in USB cables and other implementations will become apparent in view of the disclosure below.

SUMMARY

This Summary is provided to introduce a selection of concepts in a simplified form further described below in the Detailed Description. This Summary is not intended to identify key or essential features of the claimed subject matter, nor is this Summary intended as an aid in determining the scope of the claimed subject matter.

According to one implementation, an apparatus includes a first cable plug assembly. The apparatus further includes a printed circuit board (PCB) having a plurality of layers, the PCB to couple to the first cable plug assembly. A positive temperature coefficient (PTC) device may be disposed on a first layer of the plurality of layers, a second layer of the plurality of layers may be disposed over the first layer of the plurality of layers.

According to another implementation, a printed circuit board (PCB) apparatus may include first and second PCB layers. The PCB apparatus may also include a third PCB layer disposed between the first and second PCB layers. A PTC device may be disposed on the third PCB layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates Universal Serial Bus cable arrangement, according to an exemplary embodiment of this disclosure；

FIG. 2 illustrates a printed circuit board (PCB) , according to an exemplary embodiment of this disclosure；

FIG. 3 illustrates a cross section view of the PCB, as viewed from the perspective of line I-I shown in FIG. 2, according to an exemplary implementation； and

FIG. 4 illustrates a positive temperature coefficient (PTC) device embodied as a PTC chip, according to an exemplary embodiment of this disclosure.

DETAILED DESCRIPTION

FIG. 1 illustrates Universal Serial Bus (USB) cable arrangement 100, according to an exemplary embodiment of this disclosure. Other types of cable arrangements may also be implemented in the manner described in this disclosure.

The USB cable arrangement 100 may include a first cable plug assembly 104 and a second cable plug assembly 106. In one implementation, the first cable plug assembly 104 may be coupled to a user equipment, such as a mobile telephone, a tablet computer, consumer wearable device, or the like. In general, the first cable plug assembly 104 is to be coupled to a load device, such as user equipment, that receives at least a voltage via the USB cable arrangement 100. Furthermore, the second plug assembly 106 may be coupled to another user equipment, such as an AC to DC power supply, a computing device, or the like. In general, the second plug assembly 106 is to be coupled to a voltage supply device, such as a user equipment, that supplies a voltage that is to be conveyed by the USB cable arrangement 100.

The USB cable arrangement 100 may include a plurality of

signal lines

108, 110, 112 and 114. The signal line 108 is coupled to ground. The

signal lines

110 and 112 are associated with differential data signals, such as D- and D+, respectively. Although not illustrated, additional differential data signal lines, or other data signal lines, may be included with the cable arrangement 100. The signal line 114 is coupled to a voltage source, where the voltage source is to provide a voltage, such as 5V, 9V, 12V or 19V that is conveyed over the signal line 114.

The USB cable arrangement 100 may further include a positive temperature coefficient (PTC) device 102. In one to implementation, the PTC device 102 is a coupled between the voltage in (Vin) of the second cable plug assembly 106 and the voltage out (Vout) of the first cable plug assembly 104.

The PTC device 102 may be, in one implementation, a conducting polymer layer that separates two or more electrodes. When current that passes through the PTC device 102 exceeds a rated limit, the polymer layer of the PTC device 102 will begin to heat and turn from a solid to a semisolid state, expanding as it does so. The expansion causes conductive layers within the polymer of the PTC device 102 to begin to break so that the PTC device 102 shifts from a low resistance state to a high resistance state. As a result, current flow through the PTC device 102 drops dramatically. Once the fault is eliminated and current flow returns to normal, the polymer cools and contracts, returning to its low-resistance state as the conducting chains come back into contact with each other. Therefore, the PTC device 102 is functional to prevent an excessive current on the signal line 114 from reaching a load coupled to the first cable plug assembly 104.

In one implementation, the PTC device 102 may be associated with a printed circuit board (PCB) 116. The PCB 116 may be an integral part of the USB cable arrangement 100. In a particular implementation, the PCB 116 may directly interface with the first cable plug assembly 104. In another implementation, the PCB 116 may be an integral part of the first cable plug assembly 114. As will be described in the following, the PTC device 102 may be integrated between layers of the PCB 116.

FIG. 2 illustrates the PCB 116, according to an exemplary implementation. The PCB 116, as already disclosed, may include the PTC device 102. The PCB 116 may include a plurality of circuit trace lines 202 that are usable to couple the PCB 116 to the first cable plug assembly 104. Furthermore, the PCB 116 may include one or more circuit coupling points 204. The signal lines 108, 110, 112 and 114 may be coupled to the one or more circuit coupling points 204 using solder or the like. Similarly, the plurality of circuit trace lines 202 may be coupled to the first cable plug assembly 104 using solder or the like.

FIG. 3 illustrates a cross section view of the PCB 116, as viewed from the perspective of line I-I shown in FIG. 2, according to an exemplary implementation. The PCB 116 may include a plurality of PCB layers. In particular, the PCB 116 may include a first layer 302, a second layer 304 disposed over the first layer 302 and a third layer 306 also disposed over the first layer 302. In one implementation, the first layer 302 is sandwiched between the second layer 304 and the third layer 306. In a particular implementation, the second layer 304 is disposed above the first layer 302, and the third layer 306 is disposed below the first layer 302. In one implementation, at least a portion of the second layer 304 is in direct contact with the first layer 302. Similarly, at least a portion of the third layer 306 may be in direct contact with the first layer 302.

In one implementation, the PTC device 102 is encapsulated by the first layer 302. For example, the PTC device 102 may be entirely or at least partially surrounded by an encapsulant material 308. The encapsulant material 308 may be a resin, epoxy, or the like. In another example, the PTC device 102 is mounted to a surface of the first layer 302. In yet another example, the PTC device 102 is encapsulated by a material of the first layer 302. As described in the following, the PTC device 102 may be a PTC chip.

The PTC device 102 may be electrically coupled to the second layer 304 by way of one or more vias 310, and the one or more vias 310 may be coupled to one or more circuit trace lines 311 associated with the second layer 304. Furthermore, the PTC device 102 may be electrically coupled to the third layer 306 by way of one or more vias 312, and the one or more vias 312 may be coupled to one or more circuit trace lines 313 associated with the third layer 306. The one or more

circuit trace lines

311 and 313 may be made of copper foil, copper plating, or the like. A contact pad 314 may be disposed on a surface of the second layer 304. Similarly, a contact pad 316 may be disposed on a surface of the third layer 306. The

contact pads

314 and 316 provide electrical contact to the PTC device 102 by way of the

vias

310 and 312 and the one or more

circuit trace lines

311 and 313.

In one implementation, the PCB 116 may be arranged and coupled as part of a cable arrangement to allow current to flow through the PTC device 102 by way of the one or

more vias

310 and 312. For example, the one or more the vias 310 may be coupled to Vin via the signal line 114, and the one or more vias 312 may be coupled to Vout also via the signal line 114. In one implementation, the Vin is solder coupled to the PTC device 102 by way of the contact pad 314, and the Vout is solder coupled to the PTC device 102 by way of the contact pad 316. Therefore, the PTC device 102 may be functional to mitigate an undesirable overcurrent condition on the signal line 114.

FIG. 4 illustrates the PTC device 102 embodied as a PTC chip 400, according to an exemplary embodiment of this disclosure. As illustrated, the PTC chip 400, in one implementation, includes a conductive particle filled polymer layer 402. The conductive particle filled polymer layer 402 may be disposed between a first electrode 404 and a second electrode 406. The conductive particle fill may include gold, nickel, silver metal material, or the like, and carbon, TiC , tungsten carbide (WC) , or the like, semiconductor material； and the polymer may be polyethylene and/or polypropylene high crystal polymer. When current that passes through the PTC chip 400 exceeds a rated limit, the polymer layer 402 of the PTC chip 400 will begin to heat and turn from a crystalline state to an amorphous state, expanding as it does so. The expansion causes conductive layers within the polymer of the PTC chip 400 to begin to break so that the PTC chip 400 shifts from a low resistance state to a high resistance state. As a result, current flow through the PTC chip 400 drops dramatically. Once the fault is eliminated and current flow returns to normal, the polymer layer 402 cools and contracts, returning to its low-resistance state as the conducting chains come back into contact with each other. Therefore, the PTC chip 400 is functional, when implemented for example with the PCB 116, to prevent an excessive current on the signal line 114 from reaching a load coupled to the first cable plug assembly 104.

While exemplary USB cable arrangements and PCBs having integrated PTC devices are disclosed, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the claims of the application. Other modifications may be made to adapt a particular situation or material to the teachings disclosed above without departing from the scope of the claims. Therefore, the claims should not be construed as being limited to any one of the particular embodiments disclosed, but to any embodiments that fall within the scope of the claims.

Claims

An apparatus, comprising:

a first cable plug assembly；

a printed circuit board (PCB) having a plurality of layers, the PCB to couple to the first cable plug assembly； and

a positive temperature coefficient (PTC) device disposed on a first layer of the plurality of layers, a second layer of the plurality of layers disposed over the first layer of the plurality of layers.
The apparatus according to claim 1, wherein a third layer of the plurality of layers disposed over the first layer of the plurality of layers.
The apparatus according to claim 2, wherein the first layer of the plurality of layers is sandwiched between the second and third layers of the plurality of layers.
The apparatus according to claim 1, further comprising a supply voltage line coupled to the first cable plug assembly, the PTC device coupled to the supply voltage line.
The apparatus according to claim 4, further comprising a second cable plug assembly, the supply voltage line coupled between the first cable plug assembly and the second cable plug assembly.
The apparatus according to claim 1, further comprising at least one via disposed through the second layer of the plurality of layers, the at least one via electrically coupled to the PTC device.
The apparatus according to claim 1, further comprising at least a plurality of vias disposed through the second layer of the plurality of layers, the plurality of vias electrically coupled to the PTC device.
The apparatus according to claim 2, further comprising first via disposed through the second layer of the plurality of layers, the first via electrically coupled to the PTC device.
The apparatus according to claim 2, further comprising a second via disposed through the third layer of the plurality of layers, the second via electrically coupled to the PTC device.
The apparatus according to claim 1, wherein the first cable assembly is a Universal Serial Bus (USB) plug to couple to a user equipment.
An printed circuit board (PCB) apparatus, comprising:

first and second PCB layers；

a third PCB layer disposed between the first and second PCB layers； and

a positive temperature coefficient (PTC) device disposed on the third PCB layer.
The PCB apparatus according claim 11, further comprising a Universal Serial Bus (USB) plug coupled to the PCB apparatus.
The PCB apparatus according to claim 11, wherein the first PCB layer includes a first via disposed therein and the second PCB layer includes a second via disposed therein, the first and second vias coupled to the PTC device.
The PCB apparatus according to claim 11, further comprising a supply voltage line coupled to the PTC device.