WO2018119900A1 - 数据读取方法及闪存设备 - Google Patents

数据读取方法及闪存设备 Download PDF

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Publication number
WO2018119900A1
WO2018119900A1 PCT/CN2016/113085 CN2016113085W WO2018119900A1 WO 2018119900 A1 WO2018119900 A1 WO 2018119900A1 CN 2016113085 W CN2016113085 W CN 2016113085W WO 2018119900 A1 WO2018119900 A1 WO 2018119900A1
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state
data
reference voltage
region
flash
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PCT/CN2016/113085
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English (en)
French (fr)
Inventor
常乐
石亮
李乔
王元钢
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华为技术有限公司
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Priority to CN201680091823.7A priority Critical patent/CN110100236B/zh
Priority to PCT/CN2016/113085 priority patent/WO2018119900A1/zh
Publication of WO2018119900A1 publication Critical patent/WO2018119900A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Definitions

  • the present invention relates to the field of storage technologies, and in particular, to a data reading method and a flash memory device.
  • LDPC decoding is implemented by a belief propagation algorithm, which is divided into hard decision decoding and soft decision decoding.
  • the read request time is associated with the error rate, and the data read request for the high error rate takes longer.
  • the read request time includes two parts: one part is to compare the comparison time of the adjacent state with the plurality of reference voltages, and the other part is that the increased area needs more bit information bits to represent, thus the bit information is from the flash memory chip. It takes longer to transfer to the controller.
  • the hard decision decoding efficiency is high, and the required read time and decoding time are relatively short, but only data with low error rate can be decoded.
  • Soft decisions enable correct decoding of data with higher error rates, but require longer read latency and decoding delay. Therefore, although LDPC can solve the problem of the reliability of flash memory becoming worse, the performance of flash memory is also affected.
  • the present application provides a data reading method and a flash memory device, which can reduce the data reading time and improve the read operation performance of the flash memory device by increasing the data decoding rate.
  • the present application provides a data reading method.
  • the method is applied to a flash memory device for reading data in a flash memory device.
  • the flash device receives a read request for reading a target flash page in the flash device, the flash device reads from the target flash page according to a reference voltage in the first reference voltage set Take the first data.
  • the target flash page includes a plurality of storage units, and each storage unit is configured to store data.
  • the number of reference voltages of a region is not more than the number of reference voltages of the second region, and the reference voltage of the first region is used to distinguish whether the voltage state in the memory cell is the first state or the second state, the second region
  • the reference voltage is used to distinguish whether the voltage state in the memory cell is the third state or the fourth state, wherein the first state, the second state, the third state, and the fourth state are voltage states of the set memory cells, A data error rate between the three states and the fourth state is higher than a data error rate between the first state and the second state.
  • the data reading method in consideration of the erroneous asymmetry between different states, when data in the read flash memory device is erroneous, it does not increase between different adjacent states at the same time.
  • the same number of reference voltages but preferentially increase the reference voltage between adjacent states with higher error rates. Therefore, it is possible to reduce the number of reference voltages as much as possible while ensuring the probability of reading correct data, thereby reducing the number of voltage comparisons and shortening the time for reading out correct data.
  • the number of reference voltages is small, the state range of the voltage of the memory cell is small, and thus the time for transmitting the state information is also relatively short. Therefore, the execution time of the read operation is shortened.
  • the number of reference voltages of the second area is greater than the number of reference voltages of the first area.
  • the number of reference voltages of the first region is not more than seven, and the number of reference voltages of the second region is not more than seven.
  • the flash memory device further checks the first data according to a low density check code LDPC to determine whether the first data is correct data.
  • the present application provides a flash memory device.
  • the flash memory device includes a controller and a flash memory chip coupled to the controller.
  • the flash chip includes a plurality of flash pages for storing data.
  • the controller is configured to perform the data reading method described in the foregoing first aspect and any one of the possible implementation manners of the first aspect.
  • the present application provides yet another flash memory device.
  • the flash memory device includes a receiving module and a reading module.
  • the receiving module is configured to receive a read request for reading a target flash page in the flash device.
  • the target flash page includes a plurality of storage units, and each storage unit is configured to store data.
  • the reading module is configured to read the first data from the target flash page according to a reference voltage in the first reference voltage set. Wherein, in the first reference voltage set, the number of reference voltages of the first region is not more than the number of reference voltages of the second region. The reference voltage of the first region is used to distinguish whether the voltage state in the memory cell is the first state or the second state.
  • the reference voltage of the second region is used to distinguish whether the voltage state in the memory cell is the third state or the fourth state.
  • the first state, the second state, the third state, and the fourth state are voltage states of the set memory cells.
  • a data error rate between the third state and the fourth state is higher than a data error rate between the first state and the second state.
  • the reading module is further configured to read data from the target flash page according to a reference voltage in the second reference voltage set when determining that the first data is erroneous data.
  • the second set of reference voltages increases the number of reference voltages of the second region on the basis of the first set of reference voltages without increasing the number of reference voltages of the first region.
  • the flash memory device further includes a reference voltage management module and a verification module.
  • the reference voltage management module is configured to set a reference voltage in the first reference voltage set and a reference voltage in the second reference voltage set.
  • the verification module is configured to check the first data according to a low density check code LDPC to determine whether the first data is correct data.
  • the number of reference voltages of the second region is greater than the number of reference voltages of the first region.
  • the number of reference voltages of the first region is not more than seven, and the number of reference voltages of the second region is not more than seven.
  • the present application provides a computer program product comprising a computer readable storage medium storing program code, the program code comprising instructions for performing the foregoing first aspect and any one of the first aspects The method described in the possible implementation.
  • FIG. 1 is a schematic structural diagram of a flash memory device according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a reference voltage in a hard decision decoding process according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a reference voltage in a soft decision decoding process according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a flash memory array according to an embodiment of the present invention.
  • FIG. 5-A is a schematic diagram of a read state of an LSB page in a flash memory device according to an embodiment of the present disclosure
  • FIG. 5-B is a schematic diagram of a read state of an MSB page in a flash memory device according to an embodiment of the present disclosure
  • FIG. 6 is a flowchart of a data reading method according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a reference voltage according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of setting a reference voltage according to an embodiment of the present invention.
  • 9-A is a schematic diagram of still another reference voltage setting according to an embodiment of the present invention.
  • 9-B is a schematic diagram of still another reference voltage setting according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a flash memory device according to an embodiment of the present invention.
  • flash device 100 is a hardware structural diagram of another flash memory device according to an embodiment of the present invention.
  • the flash device is a flash-based storage device, such as a Solid State Drive (SSD).
  • SSD Solid State Drive
  • flash device 100 can include controller 102, host interface 106, and flash array 108.
  • the host interface 106 is used to connect to the host and communicate with the host. For example, it is used to receive an I/O request issued by the host, or return data read from the flash array 108 to the host.
  • the host interface 106 may include a Serial Advanced Technology Attachment (SATA) interface, a Universal Serial Bus (USB) interface, a Fibre Channel (FC) interface, or a fast peripheral interconnection.
  • SATA Serial Advanced Technology Attachment
  • USB Universal Serial Bus
  • FC Fibre Channel
  • PCI-E Peripheral Component Interconnect Express
  • a flash array 108 for storing data can be a plurality of memory cell groups to make.
  • flash array 108 may also be referred to as a flash chip, and a memory unit in flash array 108 refers to a minimum storage medium unit for storing data.
  • the flash array 108 may use a single-level cell (SLC) or a multi-level cell (MLC), where each SLC cell stores 1 bit of information, and each MLC cell may store More than 1 bit of data.
  • the memory cells in the flash array 108 are multi-level memory cells MLC. For example, an MLC in which each storage unit stores 2-bit data may be included, and a third-order storage unit (Trinary-Level Cel, TLC) in which each unit stores 3-bit data may be included.
  • the controller 102 mainly includes a processor 1022, a cache 1024, and a flash interface 1026.
  • the processor 1022, the cache 1024, and the flash interface 1026 complete communication with each other over the communication bus.
  • the cache 1024 is a temporary memory located between the processor 1022 and the memory. Its capacity is smaller than the memory but the exchange speed is faster than the memory.
  • the cache 1024 is used to cache data that the processor 1022 is to write to the flash array 108 or data that is read from the flash array 108 for buffering memory transfers.
  • a flash interface 1026 coupled to the flash array 108, is used to communicate with the flash array 108 to control data transfer with the flash array 108. For example, it can be used to manage access commands to the flash array 108 issued by the processor 1022 and to perform data transmission. It can be appreciated that a plurality of communication channels can be included in the flash interface 1026 for connecting different memory cells in the flash array 108.
  • the processor 1022 can be a central processing unit CPU, or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.
  • a software program is installed in the processor 1022, and different software programs can be regarded as one processing module having different functions.
  • the processor 1022 can implement an access request to the flash array 108, or manage data in the flash array 108, and the like. For example, the processor 1022 can receive the input and output I/O requests forwarded by the host interface 106 through the communication bus, and access the flash array 108 through the flash interface 1026 according to the I/O request issued by the host, and write data to the flash array 108 or Data is read from flash array 108.
  • the processor 1022 includes a check error correction module to perform error detection and correction during data reading.
  • the verification error correction module inside the processor 1022 can generate an ECC signature according to the data.
  • the ECC signature is generally stored in the back of the flash page. Use area (Spare Area, SA).
  • SA Separate Area
  • the verify error correction module reads the ECC signature and determines whether a data error has occurred based on the read data and the ECC signature. If it is detected that the read data contains error bits, then the ECC algorithm is needed to correct the detected errors.
  • the ECC algorithm may be BCH coding or LDPC coding or the like.
  • the embodiment of the present invention describes the solution by using LDPC coding, but it should be understood that the embodiment of the present invention does not limit the coding algorithm used by the ECC.
  • flash memory cells represent data by storing a certain amount of charge.
  • the voltage of the memory cell can be divided into four different states: S0, S1, S2, and S3. Specifically, in one case, S0 is used to indicate the voltage state of the memory cell when the data is 11, S1 is used to indicate the voltage state of the memory cell when the data is 10, and S2 is used to indicate the voltage state of the memory cell when the data is 00. S3 is used to indicate the voltage state of the memory cell when the data is 01.
  • S0 is used to indicate the voltage state of the memory cell when the data is 11
  • S1 is used to indicate the voltage state of the memory cell when the data is 10
  • S2 can be used to indicate the voltage state of the memory cell when the data is 01.
  • S3 is used to indicate the voltage state of the memory cell when the data is 00.
  • the specific coding mode is not limited in the embodiment of the present invention.
  • the LDPC error correction mechanism is generally used to correct the read data.
  • the LDPC code is used as the check code, and the unit storage unit stores the 2-bit data for illustration.
  • the scheme of the read operation generally adopts LDPC hard decision decoding first.
  • Figure 2 shows the reference voltage distribution of the LDPC hard decision. There is only one reference voltage between two adjacent states. There are a total of three reference voltages between the four states: V1, V2 and V3.
  • V1, V2 and V3 three reference voltages between the four states.
  • Figure 3 shows the reference voltage distribution for the LDPC soft decision. As shown in Figure 3, there may be multiple reference voltages between adjacent two states. In Figure 3, there are five reference voltages between the two states for illustration. The four states have a total of 15 reference voltages. These 15 reference voltages divide the voltage of the memory cell into 16 regions. During a read operation, the voltage of each memory cell of the read data page is compared to 15 reference voltages to determine the state of the voltage in the memory cell.
  • the flash array 108 reads data in the memory cells in accordance with the set reference voltage will be described below.
  • the three basic operations of a flash device are read operations, write operations, and erase operations.
  • the page of the read operation and the write operation is the basic operation unit, and the erase operation is a block as a basic operation unit.
  • FIG. 4 is a schematic structural diagram of a flash block in a flash array 108 according to an embodiment of the present invention. It will be appreciated that flash array 108 may be in the form of a flash chip. As shown in FIG. 4, one flash block can be composed of an array of a plurality of memory cells. One row of memory cells is connected to one word line (WL), and one column of memory cells is connected to one bit line (BL). A row of storage units can contain one or more pages. In this manner, one flash block can include multiple pages, and each page can include multiple storage units. For a flash array using SLC, each storage unit stores 1 bit of information, and a row of storage units represents one page.
  • WL word line
  • BL bit line
  • each storage unit can store at least 2 bits of information, and a row of storage units can represent two pages: an LSB page and an MSB page.
  • the storage of the 2-bit information MLC by each storage unit is mainly taken as an example for description.
  • a sense amplifier is connected to each BL, and data in the memory cells on the BL can be read from each of the BL-connected amplifiers.
  • V ref reference voltage
  • V pass is a voltage that is set higher than the voltage value in all memory cells. Since the voltage values in the memory cells of other rows are not higher than Vpass , the memory cells in the other rows do not have current to be transferred to the amplifier, so that data cannot be read from the memory cells of other rows.
  • FIG. 5-A and FIG. 5-B are schematic diagrams showing a read operation voltage according to an embodiment of the present invention.
  • FIG. 5-A when the data in the LSB page is read, because the lower bits of the data are stored in the LSB page, the data state in the memory cell is the same as the data represented in the state S0 and the state S1, in the storage unit. The data state is the same when the state of the state S2 and the state of the state S3 is the same.
  • the data in the memory cell when the voltage state in the memory cell is the S0 and S1 states, the data in the memory cell is “1”; when the voltage state in the memory cell is the S2 and S3 states, the data in the memory cell is “1”. ". .
  • the data in the storage unit may have an error between the S1 and S2 states, resulting in an unrecognized state whether the storage unit is in the S1 state or the S2 state. Therefore, for the data of the LSB page, it is only necessary to determine the state of the voltage of the memory cell by the reference voltage between the S1 and S2 states (for example, V b in 5-A), and thus can be set according to the The encoding method reads the data stored in the storage unit.
  • the data stored in the MSB page is the high order of the data stored in the storage unit.
  • state S0 indicates that the stored data is 11
  • state S1 indicates that the stored data is 10
  • state S2 indicates that the stored data is 00
  • state S2 indicates that the stored data is 01. example.
  • the data stored in the MSB page “1", "0", "0", and "1", respectively. Since the data indicated by the state S0 and the state S1 are different in the MSB page shown in FIG. 5-B, the data represented by the state S2 and the state S3 are different, and thus, the memory cell may have an error between the state S0 and the state S1.
  • V ref may first take V a and then V c in FIG. 5-B.
  • V a when the voltage in the memory cell is lower than Va, it can be judged that the data in the memory cell is "1".
  • V c when the memory cell is higher than the voltage Va, it can not be determined, it needs to be further determined by the reference voltage V c.
  • state S0 indicates that the stored data is 11
  • state S1 indicates that the stored data is 10
  • state S2 indicates that the stored data is 01
  • state S2 indicates that the stored data is 00 as an example
  • the data represented by the state S0 and the state S1 are different
  • the data represented by the state S1 and the state S2 are different
  • the data represented by the state S2 and the state S3 are also different, and thus, the storage unit may be in the state S0 and the state S1.
  • An error occurs between the two, and an error may occur between the state S1 and the state S2, and an error may occur between the state S2 and the state S3.
  • it may be necessary to determine the state of the voltage in the memory cell by three reference voltages.
  • the specific method of reading data is similar to the method of reading the data of the MSB page shown in FIG. 5-B described above, and details are not described herein again.
  • the time of a read operation mainly includes two parts: the data read time and the data transfer time.
  • the read time is positively correlated with the number of reference voltages
  • the transmission time is positively correlated with the amount of data transmitted.
  • ceil(Log 2 (N+1)) bits are required to represent N+1 voltage regions.
  • the read time is positively correlated with N
  • the transmission time is positively correlated with ceil(Log 2 (N+1))
  • ceil() is rounded up.
  • the read time is short.
  • ceil (Log 2 (4)) 2 bits is required to record information, and the transmission time is short.
  • the comparison voltage since the comparison voltage is large, the read time is long when decoding by soft decision.
  • ceil (Log 2 (16)) 4 bits is required to record information, and the time for transmitting state information is relatively long. If the read data still fails to decode, the read accuracy can be improved by sequentially increasing the number of reference voltages between adjacent states until the data to be read is correctly decoded.
  • the present application proposes a method for reading data, which can shorten the accuracy of the data. Read operation time.
  • the method of reading data in the present application can be implemented by the processor 1022 in FIG.
  • the data reading method in the present application will be described in detail below with reference to FIG. 1.
  • FIG. 6 is a flowchart of a data reading method according to an embodiment of the present invention, which may be specifically executed by the flash memory device 100 shown in FIG. 1. As shown in Figure 6, the method can include the following steps.
  • step 602 flash device 100 receives a read request.
  • the basic unit of read operation of flash device 100 is a page.
  • the flash device 100 can convert the logical address to be accessed in the read request into a physical address. Thereby, the flash memory device can determine the flash page to be accessed by the current read operation according to the physical address obtained by the conversion.
  • the flash memory device reads data by comparing the voltage of each of the memory cells in the flash memory page to be read with the set reference voltage, respectively.
  • the flash memory device 100 may read the data D i flash page in accordance with the reference set of the reference voltage SV i in the set.
  • i is used to describe the number of times the data is read
  • i is a natural number not less than 1
  • SV i is used to represent the ith reference voltage set
  • D i is used to represent the ith read data.
  • the processor 1022 in the flash memory device 100 can select a reference voltage required for reading the data according to a preset reference voltage value, and send the selected reference voltage to the flash array 108, so that the flash array 108 is to be read.
  • the voltage in the memory cells in the flash page is compared to the set reference voltage to read the data in the memory cells and transfer the read data to the processor 1022.
  • at least two reference voltages are required.
  • the present application is mainly for optimizing performance when reading data of an MSB page.
  • the reference voltage set by the processor 1022 is referred to as a reference voltage set.
  • one reference voltage set includes at least two reference voltages.
  • the reference voltage value required during the read operation may be preset in the processor 1022.
  • the processor 1022 can set a reference voltage required for the current read operation according to a preset reference voltage value.
  • FIG. 7 is an example of a reference voltage value provided by an embodiment of the present invention. As shown in FIG. 7, an example provided in the embodiment of the present invention includes 15 reference voltage values, which can divide the voltage of the storage unit into 16 states. As described above, since the data error rates appearing between different states are different, in the embodiment of the present invention, the set reference voltage values are mainly concentrated in the intersection regions between adjacent states, and the values of the reference voltages are non-uniform. Set.
  • the processor 1022 can determine whether the data to be read is the data of the LSB page or The data of the MSB page is used to select the corresponding reference voltage.
  • the data of the MSB page is read as an example.
  • the reference voltage selected by the processor 1022 needs to include at least two regions of reference voltage: as shown in FIG. 5-B.
  • the reference voltage of the first region is used to distinguish whether the voltage in the storage unit is in the S0 state or the S1 state
  • the reference voltage of the second region is used to distinguish whether the voltage in the storage unit is in the S2 state or the S3 state.
  • the reference voltage SV1 set by the processor 1022 includes two references: 2.549V and 3.605V as an example. Among them, 2.549 is the reference voltage of the first region, and 3.605 is the reference voltage of the second region.
  • the flash array 108 can respectively apply voltages of 2.549V and 3.605V on the word line to which the flash page to be read is connected to read the data D1 in the flash page to be read.
  • the flash memory device 100 determines whether the read data Di is correct. For example, after the flash array 108 reads the data D1 from the flash array according to the reference voltage set by the processor 1022, the flash array 108 can transfer the read data D1 to the processor 1022, thereby correcting the error in the processor 1022.
  • the verification module can perform error correction on the data D1 read this time by using the ECC algorithm to determine whether the data D1 is correct data.
  • the read first data may be decoded by using an LDPC decoding manner to determine whether the first data is correct data.
  • the specific decoding mode is not limited.
  • step 606 when it is determined that the read data D i is correct data, the method proceeds to step 608, and the current read operation ends.
  • the method returns to step 604, the reference voltage in the reference voltage set SV i is reset by the processor 1022, and the flash array 108 is based on the reset reference.
  • the reference voltage in the voltage set SVi reads data from the flash page to be read.
  • the processor 1022 since the erroneous asymmetry between the different states is considered, and since it is found through research, the probability of error between the states S3 and S2 is large. Therefore, in order to correctly read the data, the processor 1022 needs to increase the number of reference voltages. However, in order to shorten the reading time, in the embodiment of the present invention, the processor 1022 does not simultaneously increase the same voltage amount between all states when resetting the reference voltage. Specifically, the processor 1022 can preferentially increase the reference voltage for distinguishing the states S3 and S2 without simultaneously increasing the reference voltages for distinguishing the states S0 and S1. Change a table In the mode, the processor 1022 can preferentially increase the reference voltage of the second region in FIG. 5-B.
  • the number of reference voltages used to distinguish the states S3 and S2 is larger in the reset reference voltage set.
  • the flash memory device 100 reads the data in the flash page to be accessed according to the reference voltage in the reset reference voltage set.
  • the reference voltage set set by the processor at the ith time is referred to as a first reference voltage set
  • the reference voltage set by the processor at the i+1th time is referred to as a second reference voltage set.
  • the processor 1022 sets a reference voltage in the first region and the second region for the first time as an example.
  • the processor 1022 can increase only the number of reference voltages of the second region without increasing the number of reference voltages for the first region.
  • the processor 1022 in the process of setting the reference voltage set for the second time, includes the second reference voltage set and the reference voltage of the first region.
  • reference voltages may be included: 2.549V, 3.605V, and 3.503V. Specifically, as shown in Figure 9-A.
  • the reference voltage in order to reduce the number of voltage comparisons and shorten the time for reading data, when the reference voltage is increased, at most one reference voltage can be added in one area at a time. Of course, in practical applications, it is also possible to add up to two reference voltages in one area at a time according to actual conditions.
  • the increased voltage value is not specifically limited as long as it is the voltage of the corresponding region.
  • step 604 the flash array 108 will again re-access the data in the flash page in accordance with the reference voltage in the second set of reference voltages set by the processor 1022.
  • the data read by the flash memory device 108 according to the reference voltage in the second reference voltage set may be referred to as second data.
  • step 606 the processor 1022 determines whether the second data read is correct. If correct, the current read operation ends. If the error occurs, the method returns to step 604, and the processor sets the reference voltage again.
  • the reference voltage set set by the processor 1022 at the i+2th time is referred to as a third reference voltage set.
  • the processor 1022 can simultaneously increase the reference voltages of the first region and the second region.
  • the processor can set the reference voltages separately: 2.549V, 2.665V, 3.605V, 3.503V, and 3.72V.
  • the flash array 108 reads the data D3 in the flash page to be read according to the set third reference voltage set.
  • step 606 the processor determines whether the read data D3 is correct data. If not, the method also proceeds to step 604 where the flash device 100 resets the reference voltage again.
  • the reset reference voltage can be as shown in Figure 9-B and the data is read based on the reset reference voltage. In the embodiment of the present invention, if the data is incorrect, steps 604 and 606 may be performed cyclically until the correct data is read, and the read operation ends.
  • the reference voltage for each zone can be increased by up to seven.
  • how the processor 1022 sets the reference voltages of different regions may be as shown in FIG. 8.
  • the reference voltage of the second region is increased each time, but the reference voltage of the first region does not increase every time.
  • the reference voltage of the second region can be increased, the reference voltage of the first region can be increased once.
  • the reference voltage of the first region is only increased at the 3rd, 5th, and 7th. After the reference voltages of the second region are all increased, if the data is still incorrect, the reference voltage of the first region may be sequentially increased. It can be understood that the order and the number of increasing reference voltages shown in FIG.
  • the reference voltage of the first region may be increased in other orders, as long as the reference voltage of the second region is preferentially increased. Just fine.
  • the reference voltage of the second region when the reference voltage is increased, the reference voltage of the second region may be preferentially increased, and the reference voltage for the first region may be increased in a plurality of manners. According to this manner, in the process of resetting the reference voltage, the number of reference voltages of the second region may exceed the number of reference voltages of the first region.
  • the same number is not simultaneously added between different adjacent states.
  • the reference voltage but preferentially increases the reference voltage between adjacent states with a higher error rate. Therefore, it is possible to reduce the number of reference voltages as much as possible while ensuring the probability of reading correct data, thereby reducing the number of voltage comparisons and shortening the time for reading out correct data.
  • the number of reference voltages is small, the state range of the voltage of the memory cell is small, and thus the time for transmitting the state information is also relatively short. Therefore, the execution time of the read operation is shortened.
  • FIG. 10 is a schematic structural diagram of still another flash memory device according to an embodiment of the present invention.
  • the flash memory device 1000 includes a receiving module 1002, a reference voltage management module 1004, a reading module 1006, and a verification module 1008.
  • the receiving module 1002 is configured to receive, for reading, the flash memory.
  • the target flash page includes a plurality of storage units, and each storage unit is configured to store data.
  • the reference voltage management module 1004 is configured to set a reference voltage in a first reference voltage set required for a read operation performed according to the read request. Wherein, in the first reference voltage set, the number of reference voltages of the first region is not more than the number of reference voltages of the second region. The reference voltage of the first region is used to distinguish whether the voltage state in the memory cell is the first state or the second state. The reference voltage of the second region is used to distinguish whether the voltage state in the memory cell is the third state or the fourth state. The first state, the second state, the third state, and the fourth state are voltage states of the set memory cells. A data error rate between the third state and the fourth state is higher than a data error rate between the first state and the second state.
  • the reading module 1004 is configured to read the first data from the target flash page according to a reference voltage in the first reference voltage set.
  • the verification module 1008 is configured to check the first data read by the reading module 1004 to determine whether the first data is correct data. Specifically, the verification module 1005 can verify the read data by using ECC coding. In the embodiment of the present invention, the verification module 1005 may check the first data according to the low density check code LDPC to determine whether the first data is correct data.
  • the reference voltage management module 1004 is further configured to set a reference voltage in the second reference voltage set when the verification module 1008 determines that the first data is erroneous data.
  • the second set of reference voltages increases the number of reference voltages of the second region on the basis of the first set of reference voltages without increasing the number of reference voltages of the first region.
  • the reading module 1006 is further configured to: when the verification module 1008 determines that the first data is erroneous data, read data from the target flash page according to a reference voltage in the second reference voltage set .
  • each module in the flash memory device 1000 is used to perform each step in the foregoing method embodiments.
  • each module in the flash memory device 1000 reference may be made to the detailed description of the steps in the foregoing method embodiments.
  • the embodiment of the present invention further provides a computer program product for a data reading method, comprising: a computer readable storage medium storing program code, the program code comprising instructions for executing the method flow described in any one of the foregoing method embodiments .
  • a person skilled in the art can understand that the foregoing storage medium includes: a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a random access memory (RAM), a solid state disk (SSD), or a nonvolatile.
  • a non-transitory machine readable medium that can store program code, such as a non-volatile memory.
  • each component in the above embodiment may have another division manner in actual implementation.
  • multiple modules or components may be combined or integrated into another device, or some features may be omitted or not performed.
  • the coupling or direct coupling or communication connection of the components shown or discussed may be through some communication interface, indirect coupling or communication connection of the modules, and may include electrical, mechanical, or other forms of connection.

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Abstract

一种数据读取方法及闪存设备（1000），在读取的数据出现错误时，所述闪存设备（1000）优先增加错误率较高的相邻状态之间的参考电压，从而，能够在保证读取正确数据的概率基础上尽量减少参考电压的数量，从而能够减少读数数据过程中的电压比较次数，缩短读取出正确数据的时间，进而缩短了读操作的执行时间。

Description

数据读取方法及闪存设备 技术领域
本发明涉及存储技术领域，尤其涉及一种数据读取方法及闪存设备。
背景技术
近年来，闪存技术迅速发展，存储密度由单比特存储单元发展到最近的多比特存储单元，如6比特，制造工艺由65纳米展到最近的10纳米。这些发展使得闪存的存储密度快速增加，同时也使得闪存的可靠性大大降低，因此需要纠错能力更强的纠错码来正确编码和译码数据。
为了解决闪存的可靠性问题，当前普遍采用的解决方案是使用低密度奇偶校验码(Low Density Parity Check Code，LDPC)纠错机制。LDPC译码通过置信传播算法实现，分为硬判决译码和软判决译码。使用LDPC作为校验码时，读请求时间和错误率存在关联，对高错误率的数据读请求所需时间更长。其中，读请求时间包含两部分：一部分是为了区分相邻状态与多个参考电压进行比较的比较时间，另一部分是增多的区域需要更多的比特信息位来表示，因而将比特信息从闪存芯片传输到控制器的时间更长。硬判决译码效率高，所需读取时间和译码时间都比较短，但只能对错误率低的数据译码。软判决能对错误率更高的数据实现正确的译码，但需要更长的读取时延和译码时延。因此，LDPC虽然能解决闪存日益变差的可靠性问题，但是闪存性能也因此受到影响。
发明内容
本申请提供了一种数据读取方法及闪存设备，能够在提高数据译码率的基础上减少数据的读取时间，提高闪存设备的读操作性能。
第一方面，本申请提供了一种数据读取方法。所述方法应用于闪存设备中，用于读取闪存设备中的数据。在所述方法中，当闪存设备接收用于读取所述闪存设备中的目标闪存页的读请求之后，所述闪存设备根据第一参考电压集合中的参考电压从所述目标闪存页中读取第一数据。其中，所述目标闪存页包含有多个存储单元，每个存储单元用于存储数据。在所述第一参考电压集合中，第 一区域的参考电压的数量不多于第二区域的参考电压的数量，所述第一区域的参考电压用于区分存储单元中的电压状态为第一状态还是第二状态，所述第二区域的参考电压用于区分存储单元中的电压状态为第三状态还是第四状态，所述第一状态、第二状态、第三状态和第四状态为设置的存储单元的电压状态，所述第三状态和所述第四状态之间的数据错误率高于所述第一状态和所述第二状态之间的数据错误率。当所述闪存设备确定所述第一数据为错误数据时，所述闪存设备根据第二参考电压集合中的参考电压从所述目标闪存页中读取数据。其中，所述第二参考电压集合在所述第一参考电压集合的基础上增加了第二区域的参考电压的数量，而没有增加第一区域的参考电压的数量。
在本发明实施例提供的数据读取方法中，考虑到不同状态之间错误的非对称性，在读取的闪存设备中的数据出现错误时，并不同时在不同的相邻状态之间增加相同数量的参考电压，而是优先增加错误率较高的相邻状态之间的参考电压。从而，能够在保证读取正确数据的概率基础上尽量减少参考电压的数量，从而能够减少电压比较次数，缩短读取出正确数据的时间。并且，由于参考电压的数量较少，存储单元的电压的状态区间较少，因此传输状态信息的时间也相对较短。因此，缩短了读操作的执行时间。
在一种可能的实现方式中，在所述第二参考电压集合中，所述第二区域的参考电压的数量多于所述第一区域的参考电压的数量。
在又一种可能的实现方式中，所述第一区域的参考电压的数量不多于7个，所述第二区域的参考电压的数量不多于7个。
在又一种可能的实现方式中，所述闪存设备还根据低密度校验码LDPC对所述第一数据进行校验以确定所述第一数据是否为正确数据。
第二方面，本申请提供了一种闪存设备。所述闪存设备包括控制器以及与所述控制器连接的闪存芯片。所述闪存芯片中包括用于存储数据的多个闪存页。所述控制器用于执行前述第一方面以及第一方面的任意一种可能的实现方式中所述的数据读取方法。
第三方面，本申请提供了又一种闪存设备。所述闪存设备包括接收模块和读取模块。所述接收模块用于接收用于读取所述闪存设备中的目标闪存页的读请求。其中，所述目标闪存页包含有多个存储单元，每个存储单元用于存储 数据。所述读取模块用于根据所述第一参考电压集合中的参考电压从所述目标闪存页中读取第一数据。其中，在所述第一参考电压集合中，第一区域的参考电压的数量不多于第二区域的参考电压的数量。所述第一区域的参考电压用于区分存储单元中的电压状态为第一状态还是第二状态。所述第二区域的参考电压用于区分存储单元中的电压状态为第三状态还是第四状态。所述第一状态、第二状态、第三状态和第四状态为设置的存储单元的电压状态。所述第三状态和所述第四状态之间的数据错误率高于所述第一状态和所述第二状态之间的数据错误率。所述读取模块还用于在确定所述第一数据为错误数据时，根据第二参考电压集合中的参考电压从所述目标闪存页中读取数据。其中，所述第二参考电压集合在所述第一参考电压集合的基础上增加了第二区域的参考电压的数量，而没有增加第一区域的参考电压的数量。
在一种可能的实现方式中，所述闪存设备还包括参考电压管理模块以及校验模块。所述参考电压管理模块用于设置所述第一参考电压集合中的参考电压以及所述第二参考电压集合中的参考电压。所述校验模块用于根据低密度校验码LDPC对所述第一数据进行校验以确定所述第一数据是否为正确数据。
在又一种可能的实现方式中，在所述第二参考电压集合中，所述第二区域的参考电压的数量多于所述第一区域的参考电压的数量。
在又一种可能的实现方式中，所述第一区域的参考电压的数量不多于7个，所述第二区域的参考电压的数量不多于7个。
第四方面，本申请提供了一种计算机程序产品，包括存储了程序代码的计算机可读存储介质，所述程序代码包括的指令用于执行前述第一方面以及所述第一方面的任意一种可能的实现方式中所述的方法。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例。
图1为本发明实施例提供的一种闪存设备的结构示意图；
图2为本发明实施例提供的一种硬判决解码过程中的参考电压示意 图；
图3为本发明实施例提供的一种软判决解码过程中的参考电压示意图；
图4为本发明实施例提供的一种闪存阵列的结构示意图；
图5-A为本发明实施例提供的读取闪存设备中的LSB页的读取状态示意图；
图5-B为本发明实施例提供的读取闪存设备中的MSB页的读取状态示意图；
图6为本发明实施例提供的一种数据读取方法的流程图；
图7为本发明实施例提供的一种参考电压示意图；
图8为本发明实施例提供的一种参考电压设置示意图；
图9-A为本发明实施例提供的又一种参考电压设置示意图；
图9-B为本发明实施例提供的又一种参考电压设置示意图；
图10为本发明实施例提供的一种闪存设备的结构示意图。
具体实施方式
为了使本领域的技术人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。
图1为本发明实施例提供的另一种闪存设备的硬件结构图。闪存设备为基于闪存的存储设备，例如可以为固态硬盘(Solid State Drive，SSD)。如图1所示,闪存设备100可以包括控制器102、主机接口106以及闪存阵列108。
主机接口106用于连接主机，与主机进行通信。例如，用于接收主机下发的I/O请求，或将从闪存阵列108中读出的数据返回给主机。其中，主机接口106可以包括串行高级技术附件(Serial Advanced Technology Attachment，SATA)接口、通用串行总线(Universal Serial Bus，USB)接口、光纤通道技术(Fibre Channel，FC)接口或快捷外设互联标准(Peripheral Component Interconnect Express,PCI-E)接口等。
闪存阵列108，用于存储数据。闪存阵列108可以是多个存储单元组 成。在本发明实施例中，闪存阵列108又可被称为闪存芯片，闪存阵列108中的存储单元是指用于存储数据的最小存储介质单元。闪存阵列108可以使用单阶存储单元(Single-level cell，SLC)或多阶存储单元(Multi-level cell，MLC)，其中，每个SLC单元存储1比特的信息，每个MLC单元则可以存储1比特以上的数据。在本发明实施例中，闪存阵列108中的存储单元为多阶存储单元MLC。例如，可以包括每个存储单元存储2比特数据的MLC，还可以包括每个单元存储3比特数据的三阶存储单元(Trinary-Level Cel，TLC)。
控制器102主要包括处理器(processor)1022、缓存(cache)1024以及闪存接口(flash interface)1026。处理器1022、缓存1024、以及闪存接口1026通过通信总线完成相互间的通信。
缓存1024是位于处理器1022与内存之间的临时存储器，它的容量比内存小但是交换速度却比内存要快。缓存1024用于缓存处理器1022待写入闪存阵列108的数据或者用于缓存内存传输的从闪存阵列108读取的数据。
闪存接口1026，与闪存阵列108连接，用于与闪存阵列108进行通信，控制与闪存阵列108之间的数据传输。例如，可以用于管理对处理器1022下发的对闪存阵列108的访问命令以及进行数据传输。可以理解的是，闪存接口1026中可以包括多个通信通道，用于连接闪存阵列108中不同的存储单元。
处理器1022可以是一个中央处理器CPU，或者是特定集成电路(Application Specific Integrated Circuit，ASIC)，或者是被配置成实施本发明实施例的一个或多个集成电路。在处理器1022中安装有软件程序，不同的软件程序可以视作一个处理模块，具有不同的功能。处理器1022可以实现对闪存阵列108的访问请求，或者对闪存阵列108中的数据进行管理等等。例如，处理器1022可以通过通信总线接收主机接口106转发的输入输出I/O请求，并根据主机下发的I/O请求通过闪存接口1026访问闪存阵列108，向闪存阵列108中写入数据或者从闪存阵列108中读取数据。
本领域技术人员可以知道，为了保证数据的准确性，在闪存设备中设置有校验纠错机制。例如，处理器1022中包括校验纠错模块，以便在数据读取时进行差错检测和修正。具体的，当数据写入的时候，处理器1022内部的校验纠错模块可以根据数据生成ECC签名。ECC签名一般保存于闪存页后部的备 用区(Spare Area，SA)。当从闪存页中读取数据的时候，校验纠错模块读取ECC签名，并根据读取的数据和ECC签名判断是否出现数据错误。如果检测到读取的数据包含错误比特，就需要使用ECC算法来修正检测到的错误。通常，ECC算法可以为BCH编码或LDPC编码等。本发明实施例以LDPC编码对方案进行描述说明，但应了解，本发明实施例并不对ECC采用的编码算法进行限定。
上面对闪存设备100的硬件结构进行了简单的介绍。本领域技术人员可以知道，闪存存储单元通过存储一定量的电荷来表示数据。例如，对于存储2比特数据的MLC，存储单元的电压可以被分为4个不同的状态：S0、S1、S2和S3。具体的，一种情况下，S0用于表示数据为11时存储单元的电压状态，S1用于表示数据为10时存储单元的电压状态，S2用于表示数据为00时存储单元的电压状态，S3用于表示数据为01时存储单元的电压状态。在另一种情况下，S0用于表示数据为11时存储单元的电压状态，S1用于表示数据为10时存储单元的电压状态，S2可以用于表示数据为01时存储单元的电压状态，S3用于表示数据为00时存储单元的电压状态。在本发明实施例中不对具体的编码方式进行限定。
如图2所示，当存储单元中存储的数据不存在错误时，四个电压状态彼此分开，没有交叉。然而，在保存时间、编程干扰等的影响下，闪存存储单元中的电压可能会发生变化，电压状态偏移至相邻状态，在这种情况下，会导致读取的数据发生错误。如图3所示。例如，S0和S1这两个电压状态之间会存在交叉，使得数据发生错误。类似的，S1和S2以及S2和S3之间也会存在交叉。经研究表明，闪存设备中的数据错误存在非对称特性，不同电压状态发生错误概率存在差异。如图3所示，状态S0和S1之间错误率最低，状态S2和S3之间错误率最高。
为了提高数据的准确性，现有技术中在读数据的过程中通常采用LDPC纠错机制对读取的数据进行纠错。以采用LDPC编码作为校验码，单位存储单元存储2bit数据进行举例说明。实际应用中，读操作的方案一般是先采取LDPC硬判决译码。图2为LDPC硬判决的参考电压分布，相邻两个状态之间只有1个参考电压，在4个状态之间总共有3个参考电压：V1、V2和V3。读操作时，将读取的数据页的每一个存储单元的电压与这三个参考电压分别进行比较， 以确定存储单元中电压所处的状态。在读出数据后，如果校验成功，则读取成功。如果校验不成功，则需要再使用软判决重新进行译码。图3为LDPC软判决的参考电压分布。如图3所示，相邻两个状态之间可以有多个参考电压。图3中以两个状态之间有5个参考电压进行举例说明，则四个状态共有15个参考电压。这15个参考电压将存储单元的电压分成16个区域。读操作时，将读取的数据页的每一个存储单元的电压与15个参考电压进行比较，以确定存储单元中电压所处的状态。
为了描述清楚，下面将对闪存阵列108如何根据设置的参考电压读取存储单元中的数据进行详细描述。本领域技术人员可以知道，闪存设备的三个基本操作为读操作、写操作和擦除操作。读操作和写操作的以页(page)为基本操作单位，而擦除操作是以块(block)为基本操作单位。
图4为本发明实施例提供的一种闪存阵列108中的闪存块的组织结构示意图。可以理解的是，闪存阵列108可以是以闪存芯片的形式存在。如图4所示，一个闪存块可以由多个存储单元组成的阵列构成。一行存储单元连接一条字线(word line，WL)，一列存储单元连接一条位线(bit line，BL)。一行存储单元可以包含一个或者多个页。根据这种方式，一个闪存块可以包括多个页，每个页可以包括多个存储单元。对于使用SLC的闪存阵列来说，每个存储单元存储1bit信息，一行的存储单元表示一个页。对于使用MLC的闪存阵列来说，每个存储单元可以存储至少2bit信息，则一行存储单元可以表示两个页：LSB页和MSB页。在本发明实施例中主要以每个存储单元存储2bit信息MLC为例进行描述。
如图4所示，每条BL上连接有放大器(sense amplifier，SA)，可以从每条BL连接的放大器中读出这条BL上的存储单元中的数据。当需要读取某一页的数据时，需要在待读取的一行存储单元所连接的字线WL上加参考电压Vref(reference voltage)，而在其他行的WL上加电压Vpass。其中，Vpass为设置的高于所有存储单元中的电压值的电压。由于其他行的存储单元中电压值不会高于Vpass，因此，其他行中的存储单元不会有电流传输到放大器，从而无法从其他行的存储单元中读取数据。对于待读取的一行存储单元，当某个存储单元中电压小于Vref时，则其所在BL没有电流到放大器。当某个存储单元中电压大于Vref时， 则其所在BL会有电流到放大器。根据这种方式，可以获得存储单元中的电压所处的状态，进而能够根据获得的电压状态以及设置的编码方式读出该行的存储单元中存储的数据。
本领域技术人员可以知道，在使用MLC的闪存设备中，读取LSB页和MSB页时所需的参考电压值不同。图5-A和图5-B是本发明实施例提供的一种读操作电压的示意图。如图5-A所示，当读取LSB页中的数据时，因为LSB页中存储的是数据的低位，存储单元中的电压状态处于状态S0和状态S1时表示的数据相同，存储单元中的电压状态处于状态S2和状态S3状态时表示的数据相同。例如，当存储单元中的电压状态为S0和S1状态时，存储单元中的数据都为“1”；当存储单元中的电压状态为S2和S3状态时，存储单元中的数据都为“1”。。存储单元中的数据在S1和S2状态之间可能会出现错误导致无法识别存储单元是处于S1状态还是S2状态，。因此，对于LSB页的数据来说，只需要通过S1和S2状态之间的参考电压(例如与5-A中的Vb)就可以确定该存储单元的电压处于什么状态，进而能够根据设置的编码方式读取存储单元中存储的数据。
结合图4，假设现在要读取连接WL2的LSB页的数据，则设置的Vref电压可以为Vb(例如，Vb＝3.159V)，其他所有WL上加电压Vpass为5V。由于WL2上连接BL1和BL4的存储单元的电压都高于Vref，而WL2上连接BL2和BL3的存储单元的电压低于Vref，因此，通过增加参考电压Vb，可以确定上连接BL1和BL4的存储单元的电压处于状态S2或状态S3，而连接BL2和BL3的存储单元的电压处于状态S0或状态S1。进而，根据预设的编码方式，可以读取连接WL2的LSB页的数据为0110。
对于MLC来说，由于MSB页中存储的数据是存储单元中存储的数据的高位。如图5-B所示，若以编码方式为：状态S0表示存储的数据为11，状态S1表示存储的数据为10，状态S2表示存储的数据为00以及状态S2表示存储的数据为01为例。则MSB页中存储的数据：分别为“1”、“0”、“0”和“1”。由于在图5-B所示的MSB页中，状态S0和状态S1表示的数据不同，状态S2和状态S3表示的数据不同，从而，存储单元可能会在状态S0与状态S1之间发生错误，也可能会在状态S2和状态S3之间可能会发生错误。因此，实际应用中，为了正确读取MSB页的数据，需要增加状态S0和状态S1之间的参考电压(例 如，图5-B中的Va)以区分存储单元中的电压处于S0状态还是S1状态。并且，还需要增加状态S2和状态S3之间的参考电压(例如，图5-B中的Vc)以区分存储单元中的电压处于S2状态还是S3状态。
具体的，当需要读MSB页的数据时，Vref可以先取图5-B中Va再取Vc。如图5-B所示，当存储单元中的电压低于Va时，则可以判断该存储单元中的数据为“1”。当存储单元中的电压高于Va时，则无法确定，需要再通过参考电压Vc进一步进行判断。如果存储单元中的电压小于Vc则确定该存储单元中的数据为“0”，如果存储单元中的电压大于Vc则确定该存储单元中的数据为“1”。换一种表达方式，在读取MSB页的数据时，当存储单元中的电压小于Va时，则判断该存储单元中的数据为“1”。当存储单元中的电压大于Va且小于Vc时，则判断该存储单元中的数据为“0”。当存储单元中的电压大于Vc时，则判断该存储单元中的数据为“1”。
可以理解的是，若编码方式为：状态S0表示存储的数据为11，状态S1表示存储的数据为10，状态S2表示存储的数据为01以及状态S2表示存储的数据为00为例，则MSB页中存储的数据：分别为“1”、“0”、“1”和“0”。根据这种编码方式，状态S0和状态S1表示的数据不同，状态S1和状态S2表示的数据不同，并且状态S2和状态S3表示的数据也不同，从而，存储单元可能会在状态S0与状态S1之间发生错误，在状态S1和状态S2之间也可能发生错误，并且，也可能会在状态S2和状态S3之间发生错误。在这种情况下，读取MSB页的数据时，可能需要通过3个参考电压来确定存储单元中的电压到底处于什么状态。具体的读数据方式与前面描述的读取图5-B所示的MSB页的数据的方法类似，在此不再赘述。
下面仍然以读取图4中连接WL2的MSB页的数据为例对具体如何读取MSB页的数据进行描述。假设Va＝2.549V，Vc＝3.605V，闪存阵列108首先将Va加在WL2上，由于连接BL3的存储单元的电压为2.3V，低于2.549V，则可以确定连接WL2和BL3的存储单元中存储的数据为1，对于其他的存储单元的数据则无法确定。然后，闪存阵列108设置Vref＝Vc，将Vc施加在WL2上，以读取通过参考电压Va尚未读取的存储单元的数据。根据这种方式，可以根据参考电压Vc读取WL2上连接BL1、BL2和BL4的存储单元中的数据。具体的， 由于连接BL1和BL2的存储单元的电压均小于Vc(Vc＝3.605V)，因此，通过将存储单元中的电压与Vc比较，可以得到连接BL1和BL2的存储单元的数据为0。由于连接BL4的存储单元的电压为4.2V，则该存储单元的值为1。通过对WL2分别设置电压Va和Vc,从而能够获得连接WL2的MSB页的数据为：0011。
本领域技术人员可以知道，一个读操作的时间主要包括数据的读取时间和数据的传输时间两部分。从上述描述可知，读取时间与参考电压数目呈正相关关系，而传输时间与传输的数据量呈正相关关系。假设有N个参值电压，将闪存存储单元中的电压值分为N+1个区域，则需要ceil(Log2(N+1))个bit来表示N+1个电压区域。其中，读取时间与N呈正相关关系，传输时间与ceil(Log2(N+1))呈正相关关系，ceil()表示向上取整。在采用LDPC硬判决译码的情况下，如图2所示，由于只有三个参考电压，所以读取时间较短。由于存储单元的电压被分为4个状态，需要ceil(Log2(4))＝2个bit来记录信息，传输时间较短。在采用LDPC软判决译码的情况下，由于比较的电压较多，因此通过软判决译码时其读取时间较长。如图3所示，由于存储单元的电压被分为16个状态，需要ceil(Log2(16))＝4个bit来记录信息，传输状态信息的时间也相对较长。如果读取的数据仍然译码失败，则可以通过逐次增加相邻状态之间参考电压的数目来提高读取精度，直到正确译码出待读取的数据。
可以理解的是，软判决的参考电压分布不限于图3中的示例，相邻两个状态之间的参考电压数目是可变的。实际应用中，两个状态之间最多可以设置7个参考电压。当两个状态之间设置7个参考电压时，这四个状态之间总共有21个参考电压，这21个参考电压可以将存储单元的电压分为22个区域，总共需要ceil(Log2(22))＝5个bit来记录信息。相邻两个状态之间的参考电压数目决定了LDPC译码能容忍的数据的错误率大小。参考电压数目越多，能容忍的错误率越高，可正确译码的概率越高。然而，如前所述，在读取MSB页的数据时，至少需要两个区域的参考电压，并且参考电压数目越多，读操作的时间越长。为了优化闪存设备的读操作性能，尤其是为了优化使用MLC的闪存设备中读取MSB页的读操作性能，本申请提出了一种读数据的方法，能够在提高数据的准确性的基础上缩短读操作时间。本申请中的读数据的方法可以由图1中的处理器1022来实现。下面将结合图1对本申请中的数据读取方法进行详细描述。
图6为本发明实施例提供的一种数据读取方法的流程图，该方法具体可以由图1中所示的闪存设备100来执行。如图6所示，该方法可以包括下述步骤。
在步骤602中，闪存设备100接收读请求。本领域技术人员可以知道，闪存设备100的读操作的基本单位是页(page)。实际应用中，当闪存设备100接收到读请求时，闪存设备100可以将读请求中待访问的逻辑地址转换为物理地址。从而闪存设备能够根据转换获得的物理地址确定本次读操作待访问的闪存页。
如前所述，闪存设备是通过将待读取的闪存页中的每一个存储单元的电压与设置的参考电压分别进行比较来读取数据。在接收到读请求时，在步骤604中，闪存设备100可以根据设置的参考电压集合SVi中的参考电压读取闪存页中的数据Di。其中，i用于表述读取数据的次数，i为不小于1的自然数，SVi用于表述第i参考电压集合，Di用于表示第i次读取的数据。具体的，闪存设备100中的处理器1022可以按照预设的参考电压值选择本次读取数据所需的参考电压，并向闪存阵列108发送选择的参考电压，从而闪存阵列108将待读取的闪存页中的存储单元中的电压与设置的参考电压进行比较以读取存储单元中的数据，并向处理器1022传输读取的数据。如前所述，当需要读取MSB页的数据时，至少需要两个参考电压。本申请主要为了优化读取MSB页的数据时的性能，为了描述方便，在本发明实施例中，将处理器1022设置的参考电压称为参考电压集合。其中，一个参考电压集合中至少包括两个参考电压。
实际应用中，读操作过程中所需的参考电压值可以预先设置在处理器1022中。处理器1022可以根据预设的参考电压值设置本次读操作所需的参考电压。图7是本发明实施例提供的一种参考电压值的示例。如图7所示，在本发明实施例提供的一种示例包含有15个参考电压值，这15个参考电压值可以将存储单元的电压分为16个状态。如前所述，由于不同状态之间出现的数据错误率不同，因此，在本发明实施例中，设置的参考电压值主要集中在相邻状态之间的交叉区域，参考电压的值的是非均匀设置的。如前所述，由于读取LSB页和读取MSB页的数据时，所需要选择的参考电压的数值不同。因此，实际应用中，在设置参考电压时，处理器1022可以根据待读取的数据是LSB页的数据还是 MSB页的数据来选择对应的参考电压。在本发明实施例中以读取MSB页的数据为例。
根据上述描述可知，在步骤404中，当处理器1022确定需要读取MSB中的数据时，处理器1022选择的参考电压至少需要包括两个区域的参考电压：如图5-B中所示的第一区域和第二区域。其中，第一区域的参考电压用于区分存储单元中的电压是处于S0状态还是S1状态，第二区域的参考电压用于区分存储单元中的电压是处于S2状态还是S3状态。
在本发明实施例中，以处理器1022设置的参考电压SV1中包含两个参考：2.549V和3.605V为例。其中，2.549为第一区域的参考电压，3.605为第二区域的参考电压。在本步骤中，闪存阵列108可以分别在待读取的闪存页所连接的字线上施加电压2.549V和3.605V，以读取待读取的闪存页中的数据D1。
在步骤606中，闪存设备100判断读取的数据Di是否正确。例如，当闪存阵列108根据处理器1022设置的参考电压从闪存阵列中读取了数据D1之后，闪存阵列108可以将读取的数据D1传输给处理器1022，从而处理器1022中的纠错校验模块可以采用ECC算法对本次读取的数据D1进行校验纠错，以确定所述数据D1是否为正确数据。在本发明实施例中，可以采用LDPC解码方式对读取的所述第一数据进行解码，以确定所述第一数据是否为正确数据。在本发明实施例中，不对具体的解码方式进行限定。
如图6所示，在步骤606中，当确定读取的数据Di为正确数据时，该方法进入步骤608，本次读操作结束。当确定读取的数据Di为错误数据时，令i＝i+1，该方法返回步骤604，由处理器1022重新设置参考电压集合SVi中的参考电压，闪存阵列108根据重新设置的参考电压集合SVi中的参考电压从待读取的闪存页中读取数据。
在本发明实施例中，由于考虑到不同状态之间错误的非对称性，并且，由于经过研究发现，在状态S3和S2之间出错的概率较大。因此为了正确读取数据，处理器1022需要增加参考电压的数量。但是，为了缩短读取时间，在本发明实施例中，处理器1022在重新设置参考电压时，并不同时在所有状态之间增加相同的电压数量。具体的，处理器1022可以优先增加用于区分状态S3和S2的参考电压，而不同时增加用于区分状态S0和S1的参考电压。换一种表 达方式，处理器1022可以优先增加如图5-B中第二区域的参考电压。根据这种方式，在本发明实施例中，当处理器确定读取的数据错误需要重新设置参考电压时，在重新设置的参考电压集合中，用于区分状态S3和S2的参考电压的数量多于用于区分状态S0和S1的参考电压的数量。下面将结合图8和图6对本发明实施例如何具体增加参考电压的方式进行详细描述。
如图6所示，当在步骤606中，处理器1022判断读取的数据Di为错误数据时，闪存设备100根据重新设置的参考电压集合中的参考电压读取待访问的闪存页中的数据。为了描述清楚，在本发明实施例中，将处理器第i次设置的参考电压集合称为第一参考电压集合，将处理器在第i+1次设置的参考电压称为第二参考电压集合。如图8所示，在本发明实施例中，以处理器1022第一次在第一区域和第二区域分别设置了一个参考电压为例。当该方法返回步骤604时，处理器1022可以只增加第二区域的参考电压的数量而不增加第一区域的参考电压的数量。换一种表达方式，处理器1022在第二次设置参考电压集合的过程中，设置的第二参考电压集合中包含有2个第二区域的参考电压以及1个第一区域的参考电压。例如，在设置的第二参考电压集合中，可以包括参考电压：2.549V、3.605V以及3.503V。具体如图9-A所示。
在本发明实施例中，为了减少电压比较次数，缩短读取数据的时间，在增加参考电压时，每次在一个区域可以最多增加一个参考电压。当然，实际应用中，还可以根据实际情况，每次在一个区域最多增加两个参考电压。在本发明实施例中，不对增加的电压值进行具体的限定，只要是相应区域的电压即可。
在步骤604中，闪存阵列108将按照处理器1022设置的第二参考电压集合中的参考电压再次待访问的闪存页中的数据。具体读取数据的方法可以参见前述对读取MSB页的数据的方法的描述。在本发明实施例中，可以将闪存设备108根据第二参考电压集合中的参考电压读取的数据称为第二数据。
该方法再次进入步骤606，处理器1022判断读取的第二数据是否正确，如果正确则本次读操作结束，如果错误，则该方法返回步骤执行步骤604，处理器再次设置参考电压。为了描述方便，将处理器1022在第i+2次设置的参考电压集合称为第三参考电压集合。在第三参考电压集合中，处理器1022可以同时增加第一区域以及第二区域的参考电压。例如，在第三参考电压集合中，处 理器可以分别设置参考电压：2.549V、2.665V、3.605V、3.503V以及3.72V。然后，闪存阵列108根据设置的第三参考电压集合读取待读取的闪存页中的数据D3。并在步骤606中，处理器判断读取的数据D3是否为正确数据。如果不正确，则该方法还会进入步骤604，闪存设备100再次重新设置参考电压，例如，重新设置的参考电压可以如图9-B所示，并根据重新设置的参考电压读取数据。在本发明实施例中，如果数据不正确，可以循环执行步骤604和步骤606，直到读出正确数据，该读操作结束。
如前所述，每个区域的参考电压最多可以增加7个。本发明实施例中，处理器1022如何设置不同区域的参考电压可以如图8所示。在图8所示的增加参考电压的顺序示意中，每次都会增加第二区域的参考电压，但第一区域的参考电压并不是每次都增加。在可以增加第二区域的参考电压时，可以隔一次增加一次第一区域的参考电压。例如，第一区域的参考电压只是在第3、5、7次才增加。在第二区域的参考电压都增加完了之后，如果数据还不正确，则可以依次增加第一区域的参考电压。可以理解的是，图8所示的增加参考电压的顺序及数量仅仅只是一种示例，实际应用中，还可以以其他顺序增加第一区域的参考电压，只要保证优先增加第二区域的参考电压即可。换一种表达方式，在本发明实施例中，在增加参考电压时，只要优先增加第二区域的参考电压即可，对于第一区域的参考电压的增加方式可以有多种。根据这种方式，在重新设置参考电压的过程中，第二区域的参考电压的数量会多余第一区域的参考电压的数量。
在本发明实施例提供的数据读取方法中，考虑到不同状态之间错误的非对称性，在读取闪存设备中的数据时，并不同时在不同的相邻状态之间增加相同数量的参考电压，而是优先增加错误率较高的相邻状态之间的参考电压。从而，能够在保证读取正确数据的概率基础上尽量减少参考电压的数量，从而能够减少电压比较次数，缩短读取出正确数据的时间。并且，由于参考电压的数量较少，存储单元的电压的状态区间较少，因此传输状态信息的时间也相对较短。因此，缩短了读操作的执行时间。
图10为本发明实施例提供的又一种闪存设备的结构示意图。如图10所示，闪存设备1000包括接收模块1002、参考电压管理模块1004、读取模块1006以及校验模块1008。其中，所述接收模块1002用于接收用于读取所述闪存 设备中的目标闪存页的读请求。其中，所述目标闪存页包含有多个存储单元，每个存储单元用于存储数据。
所述参考电压管理模块1004，用于设置根据所述读请求执行的读操作所需的第一参考电压集合中的参考电压。其中，在所述第一参考电压集合中，第一区域的参考电压的数量不多于第二区域的参考电压的数量。所述第一区域的参考电压用于区分存储单元中的电压状态为第一状态还是第二状态。所述第二区域的参考电压用于区分存储单元中的电压状态为第三状态还是第四状态。所述第一状态、第二状态、第三状态和第四状态为设置的存储单元的电压状态。所述第三状态和所述第四状态之间的数据错误率高于所述第一状态和所述第二状态之间的数据错误率。
所述读取模块1004用于根据第一参考电压集合中的参考电压从所述目标闪存页中读取第一数据。
所述校验模块1008，用于对所述读取模块1004读取的所述第一数据进行校验，以确定所述第一数据是否为正确数据。具体的，所述校验模块1005可以采用ECC编码对读取的数据进行校验。在本发明实施例中，校验模块1005可以根据低密度校验码LDPC对所述第一数据进行校验以确定所述第一数据是否为正确数据。
所述参考电压管理模块1004，还用于在所述校验模块1008确定所述第一数据为错误数据时，设置第二参考电压集合中的参考电压。其中，所述第二参考电压集合在所述第一参考电压集合的基础上增加了第二区域的参考电压的数量，而没有增加第一区域的参考电压的数量。
所述读取模块1006还用于，在所述校验模块1008确定所述第一数据为错误数据时，根据所述第二参考电压集合中的参考电压从所述目标闪存页中读取数据。
可以理解的是，闪存设备1000中的各个模块分别用于执行前述各方法实施例中的各个步骤。具体对闪存设备1000中各个模块的描述可以参见前述方法实施例中各步骤的详细描述。
需要说明的是，本发明实施例中的“第一”、“第二”等表述只是用于区分不同的对象，不对本发明实施例作其它限定。
本发明实施例还提供一种数据读取方法的计算机程序产品，包括存储了程序代码的计算机可读存储介质，所述程序代码包括的指令用于执行前述任意一个方法实施例所述的方法流程。本领域普通技术人员可以理解，前述的存储介质包括：U盘、移动硬盘、磁碟、光盘、随机存储器(Random-Access Memory，RAM)、固态硬盘(Solid State Disk，SSD)或者非易失性存储器(non-volatile memory)等各种可以存储程序代码的非短暂性的(non-transitory)机器可读介质。
需要说明的是，本申请所提供的实施例仅仅是示意性的。例如，上述实施例中各部件的划分，实际实现时还可以有另外的划分方式。例如多个模块或组件可以结合或者可以集成到另一个设备中，或一些特征可以忽略，或不执行。另外，所显示或讨论的部件相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口、模块的间接耦合或通信连接，可以包括电性连接、机械连接或其它的连接形式。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。在本发明实施例、权利要求以及附图中揭示的特征可以独立存在也可以组合存在。在本发明实施例中以硬件形式描述的特征可以通过软件来执行，反之亦然。在此不做限定。

Claims (13)

  1. 一种数据读取方法，用于读取闪存设备中的数据，所述方法包括：
    接收用于读取所述闪存设备中的目标闪存页的读请求，其中，所述目标闪存页包含有多个存储单元，每个存储单元用于存储数据；
    根据第一参考电压集合中的参考电压从所述目标闪存页中读取第一数据，其中，在所述第一参考电压集合中，第一区域的参考电压的数量不多于第二区域的参考电压的数量，所述第一区域的参考电压用于区分存储单元中的电压状态为第一状态还是第二状态，所述第二区域的参考电压用于区分存储单元中的电压状态为第三状态还是第四状态，所述第一状态、第二状态、第三状态和第四状态为设置的存储单元的电压状态，所述第三状态和所述第四状态之间的数据错误率高于所述第一状态和所述第二状态之间的数据错误率；
    当所述第一数据为错误数据时，根据第二参考电压集合中的参考电压从所述目标闪存页中读取数据，其中，所述第二参考电压集合在所述第一参考电压集合的基础上增加了第二区域的参考电压的数量，而没有增加第一区域的参考电压的数量。
  2. 根据权利要求1所述的方法，其特征在于：
    在所述第二参考电压集合中，所述第二区域的参考电压的数量多于所述第一区域的参考电压的数量。
  3. 根据权利要求1或2所述的方法，其特征在于：
    所述第一区域的参考电压的数量不多于7个，所述第二区域的参考电压的数量不多于7个。
  4. 根据权利要求1-3任意一项所述的方法，其特征在于，还包括：
    根据低密度校验码LDPC对所述第一数据进行校验以确定所述第一数据是否为正确数据。
  5. 一种闪存设备，包括控制器以及和所述控制器连接的闪存芯片，其特征 在于，所述闪存芯片中包括用于存储数据的多个闪存页；
    所述控制器用于：
    接收用于读取所述闪存设备中的目标闪存页的读请求，其中，所述目标闪存页包含有多个存储单元，每个存储单元用于存储数据，所述目标闪存页为所述多个闪存页中的一个闪存页；
    根据第一参考电压集合中的参考电压从所述目标闪存页中读取第一数据，其中，在所述第一参考电压集合中，第一区域的参考电压的数量不多于第二区域的参考电压的数量，所述第一区域的参考电压用于区分存储单元中的电压状态为第一状态还是第二状态，所述第二区域的参考电压用于区分存储单元中的电压状态为第三状态还是第四状态，所述第一状态、第二状态、第三状态和第四状态为设置的存储单元的电压状态，所述第三状态和所述第四状态之间的数据错误率高于所述第一状态和所述第二状态之间的数据错误率；
    当所述第一数据为错误数据时，根据第二参考电压集合中的参考电压从所述目标闪存页中读取数据，其中，所述第二参考电压集合在所述第一参考电压集合的基础上增加了第二区域的参考电压的数量，而没有增加第一区域的参考电压的数量。
  6. 根据权利要求5所述的闪存设备，其特征在于：
    在所述第二参考电压集合中，所述第二区域的参考电压的数量多于所述第一区域的参考电压的数量。
  7. 根据权利要求5或6所述的闪存设备，其特征在于，所述控制器还用于：
    根据低密度校验码LDPC对所述第一数据进行校验以确定所述第一数据是否为正确数据。
  8. 根据权利要求5-7任意一项所述的闪存设备，其特征在于：
    所述第一区域的参考电压的数量不多于7个，所述第二区域的参考电压的数量不多于7个。
  9. 一种闪存设备，其特征在于，包括：
    接收模块，用于接收用于读取所述闪存设备中的目标闪存页的读请求，其中，所述目标闪存页包含有多个存储单元，每个存储单元用于存储数据；
    读取模块，用于根据所述第一参考电压集合中的参考电压从所述目标闪存页中读取第一数据，其中，在所述第一参考电压集合中，第一区域的参考电压的数量不多于第二区域的参考电压的数量，所述第一区域的参考电压用于区分存储单元中的电压状态为第一状态还是第二状态，所述第二区域的参考电压用于区分存储单元中的电压状态为第三状态还是第四状态，所述第一状态、第二状态、第三状态和第四状态为设置的存储单元的电压状态，所述第三状态和所述第四状态之间的数据错误率高于所述第一状态和所述第二状态之间的数据错误率；
    所述读取模块还用于，当所述第一数据为错误数据时，根据第二参考电压集合中的参考电压从所述目标闪存页中读取数据，其中，所述第二参考电压集合在所述第一参考电压集合的基础上增加了第二区域的参考电压的数量，而没有增加第一区域的参考电压的数量。
  10. 根据权利要求9所述的闪存设备，其特征在于，还包括：
    参考电压管理模块，用于设置所述第一参考电压集合中的参考电压以及所述第二参考电压集合中的参考电压；
    校验模块，用于根据低密度校验码LDPC对所述第一数据进行校验以确定所述第一数据是否为正确数据。
  11. 根据权利要求9或10所述的闪存设备，其特征在于：
    在所述第二参考电压集合中，所述第二区域的参考电压的数量多于所述第一区域的参考电压的数量。
  12. 根据权利要求9-11任意一项所述的闪存设备，其特征在于：
    所述第一区域的参考电压的数量不多于7个，所述第二区域的参考电压的数量不多于7个。
  13. 一种计算机程序产品，包括存储了程序代码的计算机可读存储介质，所述程序代码包括的指令用于执行如权利要求1-4任意一项所述的方法。
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