WO2018118084A1

WO2018118084A1 - Back-side magnetic shielding of integrated circuit devices

Info

Publication number: WO2018118084A1
Application number: PCT/US2016/068567
Authority: WO
Inventors: Aaron D. Lilak; Roksana GOLIZADEH MOJARAD; Patrick Morrow; Rishabh Mehandru
Original assignee: Intel Corporation
Priority date: 2016-12-23
Filing date: 2016-12-23
Publication date: 2018-06-28

Abstract

Integrated circuits (ICs) including a device stratum with interconnect metallization over a first side of the stratum and a magnetic shield on a second side of the stratum. The device stratum may comprise transistors that are interconnected by routing traces of the interconnect metallization. The IC may further include one or more magnetically sensitive devices, such as memory cells comprising a magnetic tunneling junction (MTJ). The second side of the device stratum may be exposed, enabling fabrication of a magnetic shield in close proximity to the magnetically sensitive devices and unrestricted by interconnect metallization over the first side of the device stratum. The magnetic shield may limit magnetic flux within the z-dimensional projection of an area within which magnetically sensitive devices are located. The magnetic shield may be made hundreds of micrometers thick and be backfilled with any known gap-fill material to impart mechanical stability to the IC.

Description

BACK-SIDE MAGNETIC SHIELDING OF INTEGRATED CIRCUIT DEVICES

BACKGROUND

Shielding integrated circuit (IC) devices from external magnetic fields is becoming increasing important and complex as the form factors of device platforms (e.g., mobile phones, wearables, etc.) continue to shrink. Magnetic field-sensitive devices, such as those employing a magnetic tunneling junction (MTJ) or the like, may also be integrated with other circuitry, such as silicon CMOS transistor-based circuitry, rendering regions of an IC more susceptible to external magnetic fields.

To date, magnetic shielding for IC devices has typically entailed structures implemented at the platform level. Alternatives integrated at the IC chip-level include a magnetic shield structure folded over an edge of a chip, a shield formed at the chip bump level, or a shield embedded within through-die vias. Efficacy and physical size of a shield structure is a function of how near the shield can be located to a magnetic field-sensitive device. A shield can be smaller and more effective the closer it is to the field-sensitive device. Magnetic shields implemented at the platform-level need to be quite large and often must be dimensioned to shield an entire packaged IC chip as it is difficult to effectively shield only a portion of an IC chip. This shielding approach therefore consumes significant spatial volume, presenting difficulty for small form-factor applications. Another difficulty is the additional bill-of-materials cost for the shielding apparatus. There is also an additional assembly cost to incorporate the shield into a given platform design.

A "u-shaped" envelope shield folded over a portion of an IC chip also poses form- factor difficulties as the shielding material makes the shielded package much thicker than the IC chip alone. In addition, this approach can complicate integration of the product if the shield interferes with electrical connections to the chip. The layout of the chip is also impacted as the magnetic field-sensitive devices need be contained within the shield envelope itself. This can necessitate a shielded region approximately as large as the semiconductor chip.

On-die shielding structures can be much smaller than the platform-level

implementations. However, when formed at the bump level the shielding structures are only on one side of the field-sensitive device(s), rendering the shielding less effective. Through- via shielding structures are better in this respect, but are difficult to incorporate within a die as they require the interconnect metal layers to be routed around the shielding material. In addition, the through-via approach presents challenges because the shield patterning processes should not damage metal routing or IC devices. As such, through-die via approaches have proven difficult to implement. BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example, and not by way of limitation, in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:

FIG. 1A, IB, 1C, and ID illustrate perspective views of back-side magnetic shielding structures, in accordance with some embodiments;

FIG. 2A and 2B are flow diagrams illustrating methods for fabricating back-side magnetic shielding structures, in accordance with some embodiments;

FIG. 3 is a perspective view of an IC structure including a magnetic field-sensitive device, in accordance with some embodiments;

FIG. 4A and 4B illustrate cross-sectional perspective views of the IC structure illustrated in FIG. 3, in accordance with some embodiments; FIG. 5 and 6 illustrate perspective views of an IC structure including a back-side magnetic shield evolving as operations in the methods shown in FIG. 2A or FIG. 2B are practiced, in accordance with some embodiments;

FIG. 7A, 7B, and 7C illustrate cross-sectional perspective views through a magnetic field-sensitive device and a magnetic field shield, in accordance with some embodiments; FIG. 8 is a flow diagram illustrating methods for fabricating back-side magnetic shielding structures, in accordance with some embodiments;

FIG. 9 is a cross-sectional perspective view through an IC structure including a magnetic field-sensitive device, in accordance with some embodiments; FIG. 10 and 11 illustrate perspective views of an IC structure evolving as operations in the methods shown in FIG. 9 are practiced, in accordance with some embodiments;

FIG. 12 is a cross-sectional perspective view through an IC structure including a magnetic field-sensitive device, in accordance with some embodiments; FIG. 13 is a schematic of a magnetic memory cell of a magnetic memory array that is shielded by a back-side magnetic shielding structure, in accordance with some embodiments;

FIG. 14 illustrates a mobile computing platform and a data server machine employing an SoC including a back-side magnetic shield, in accordance with embodiments; and

FIG. 15 is a functional block diagram of an electronic computing device, in accordance with some embodiments.

DETAILED DESCRIPTION

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material or material "on" a second material or material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies. As used throughout this description, and in the claims, a list of items joined by the term "at least one of or "one or more of can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. Described herein are integrated circuits (ICs) including a device stratum with interconnect metallization over a first (e.g., front) side of the stratum, and a magnetic shield over a second (e.g., back) side of the stratum. The device stratum may, for example, comprise a plurality of transistors, such as field effect transistors (FETs). Devices within the device stratum are at least partially interconnected by routing traces of the interconnect

metallization. The IC may further include one or more magnetically sensitive devices, such as memory cells comprising an MTJ. Such field-sensitive devices may, for example, be fabricated on, or near, the device stratum or intermingled within the interconnect

metallization layers.

During the IC chip fabrication process, the second side of the device stratum may be exposed, for example by removing an IC fabrication substrate or carrier thickness with processes such as chemical mechanical planarization (CMP). Following reveal of the back side of the device stratum, a magnetic shield may be fabricated using any suitable additive and/or subtractive processing known in the art. The back-side magnetic shield may interrupt any external magnetic field, redirecting magnetic flux away from and/or around field- sensitive devices protected by the shield. Generally, the effectiveness of a magnetic shield is a function of the proximity (e.g., z-dimension where the device stratum has an x-y dimensional area) of the shield to the region needing shielding. Placing the shield

significantly above or below a field-sensitive device reduces the shielding effectiveness and/or requires a much larger shield structure to effectively shield an IC area within a projection or shadow of the shield. Shields in accordance with some embodiments herein, while being in close proximity to the magnetically sensitive devices, can be unrestricted by interconnect metallization over the first side of the device stratum and can be large related to typical dimensions of features within the device stratum and overlying interconnect metallization. The magnetic shields may, for example, be fabricated to completely surround a specific area of the IC and limit magnetic flux within the z-dimensional projection of this area where the magnetically sensitive devices are located. The magnetic shield may be made hundreds of micrometers thick and be backfilled with any known gap-fill material to impart mechanical stability to the IC. FIG. 1A-1D illustrate perspective views of back-side magnetic shielding structures, in accordance with some embodiments. The perspective views are of a volume of an IC chip or die associated with a full thickness of the IC chip (e.g., z-dimension) and a partial area of the IC chip (e.g., x-y dimensions) within which both a magnetic field-sensitive device and a magnetic shield reside. As shown in FIG. 1A-1B, the IC structures 101, 102, 103 and 104 each include a device stratum 115. Devices, such as, but not limited to, transistors and optical devices (e.g., diodes, LEDs, waveguides, etc.) reside within device stratum 115. In some CMOS circuitry embodiments, a plurality of n-type and p-type FETs reside within device stratum 115. In some of these embodiments, the FETs employ a non-planar semiconductor body for the transistor channel (e.g., a fin such that the devices are finFETs). Device stratum 115 may be considered a plane occupying an area or footprint of the IC chip, but this plane need not be a homogenous thin film. In some embodiments, for example, device stratum 115 comprises semiconductor bodies separated from each other by surrounding dielectric. As one example, in a transistor device, such as a FET, the channel semiconductor is formed from a semiconductor body within device stratum 115. As another example, for an optical device, such as a photodiode, the drift and/or gain semiconductor is formed from a semiconductor body within the device stratum 115. Device stratum 115 may also comprise passive structures with an IC. For example, an optical waveguide may employ a semiconductor body within device stratum 115. Over (under) a first side of device stratum 115 is one or more interconnect strata 110.

Within interconnect strata 110 are traces of interconnect metallization 120 embedded within a dielectric 130. Although not depicted, interconnect strata 110 may include many (e.g., 8-10, or more) interconnect metallization levels electrically coupling various terminals of the devices within device stratum 115 together into a circuit. Interconnect metallization 120 may, for example, be primarily copper (e.g., a Cu-rich alloy), or primarily other than copper (e.g., an Al-rich alloy), or comprised of layers of differing primary materials. Dielectric 130 may be any dielectric material(s) known to be suitable as an inter-level dielectric (ILD), such as conventional dielectrics (e.g., SiO, SiN, SiON), or low-k dielectrics (e.g., SiOC, SiOCH, HSQ, or MSQ). Under (over) a second side of device stratum 115 (i.e., a side opposite interconnect strata 110), is a back-side stack 150. In the examples illustrated in FIG 1A, IB and ID, backside stack 150 includes a magnetic shield 160 embedded within a back-side dielectric 170. In the example illustrated in FIG. IC, back-side stack 150 includes magnetic shield 160, backside dielectric 170, and one or more additional levels of interconnect metallization 120.

Magnetic shield 160 may entail one or more features of material having a suitably high magnetic permeability. In exemplary embodiments, magnetic shield 160 is of a material having a high relative magnetic permeability (e.g., exceeding 50,000, advantageously exceeding 70,000, and more advantageously exceeding 80,000). Commercially available examples of such materials include Mu-metal, super Mu-metal, permalloy, supermalloy. Other commercially available examples are known by the trade names Sanbold, Sendust, M- 1040, Hipernom, HuMu-80, Co-Netic and Amumetal. The highly permeable material may be fabricated into features having any dimensions required to achieve a desired reduction in flux within a protected region of the IC structure. The field permeable features may be architected into any shape. In some embodiments, the shield structures protect a magnetic field-sensitive region of an IC that lies within a z-dimensional projection of shield the shield. The dimensions of the shield may therefore be commensurate with one or more magnetic field- sensitive device(s) fabricated in the IC that are to be protected by the shield. As such, some of the shields described herein can be considered "selective shields" because the area of the region protected by the shield is smaller than the area of the IC chip. With the footprint of a shield being less than the IC chip area, a plurality of such shields may be fabricated, each of which protects a specific region of the IC structure where magnetic field-sensitive device(s) are located.

In some embodiments, back-side dielectric 170 is planarized with shield 160. Backside dielectric 170 may be of any material(s) compatible with the aspect ratio of shield 160. Back-side dielectric 170 may be deposited before shield 160 is fabricated, in which case dielectric 170 may be any conventional or low-k dielectric material. Alternatively, back-side dielectric 170 may be deposited after shield 160 is fabricated, in which case dielectric 170 may by any known gap-fill material (e.g., conventional or low-k flowable dielectric material). In some embodiments where shield 160 is many tens to hundreds of micrometers (μιτι) in height or thickness, dielectric 170 (being of substantially the same thickness and extending over portions of the IC not occupied by shield 160) may provide mechanical stability to the IC structure. In some embodiments, backside dielectric 170 may not be deposited and the resultant shield 160 may be surrounded by air or by a packaging material that subsequently encompassed the IC. In some embodiments, as illustrated in FIG. 1 A, shield 160 includes a wall forming an enclosure having a perimeter that surrounds an interior region 180 that is backfilled with back-side dielectric 170. In some embodiments, interior region 180 may be filled with a different dielectric than is used for the region outside of the magnetic shield. Alternatively, interior region 180 may be left as an air gap or subsequently filled with a packaging material (e.g., epoxy resin overmold). As described further below, one or more magnetic field- sensitive device(s) may be located within a z-dimensional projection of interior region 180, embedded within back-side dielectric 170, embedded within device stratum 115, or located somewhere within interconnect strata 110. Effectiveness of a shield wall may improve with greater z-height/z-thickness, and smaller physical separation (in the z-dimension) from field- sensitive devices.

In some embodiments, as illustrated for IC structure 102 in FIG. IB, shield 160 includes a top cap or a solid slug having a footprint of an area at least equal to that of a magnetic field-sensitive device located within a z-dimensional projection of shield 160. Effectiveness of such a shield may improve with larger shield area in the x-y dimensions and smaller separation (in the z-dimension) from field-sensitive devices. The area of such a shield is limited only by the area of the IC in view of shield architecture being independent of interconnect metallization routed on the opposite side of device stratum 115.

In some embodiments, as illustrated for IC structure 103 in FIG. IC, shield 160 includes a plurality of structures, such as pillars, arrayed over an area of the IC. Such embodiments are well suited to shielding sensitive devices from magnetic flux substantially perpendicular to a plane defined by device stratum 115 while still allowing passage of interconnect metallization traces between adjacent pillars of shield material so that the shield can extend through back-side interconnect strata, if present. Effectiveness of such shield pillars may again improve with greater height/thickness in the z-dimension and smaller separation (in the z-dimension) from field-sensitive devices.

In some other embodiments, as illustrated for IC structure 104 in FIG. ID, shield 160 includes one or more intersecting features of magnetic permeable material to form a plurality of enclosed cells or regions 180 arrayed over an area of the IC. Such a structure may be advantageous where magnetic field-sensitive devices are arrayed over an area of the IC that is so large that a shield with a single perimeter wall would need an impractically large z- thickness to be effective. For such applications, an array of many smaller shield structures (physically independent or interconnected as for the lattice structure shown in FIG. ID) may provide a plurality of field shielded zones with one or more sensitive device located within each zone.

FIG. 2A is a flow diagram illustrating methods of fabricating back-side magnetic shielding structures, in accordance with some embodiments. Methods 201 begin at operation 205 where front-side IC structures including one or more magnetic field-sensitive devices are fabricated. Alternatively, an IC fabrication substrate including such structures is received as an input to methods 201. Any front-side fabrication process(es) known in the art may be employed to fabricate IC devices, such as FETs, and the field-sensitive devices. For example, in some embodiments, additive and/or subtractive patterning techniques are employed to fabricated finFET structures over an area of a fabrication substrate. Front-side fabrication further includes any technique known to be suitable for forming a magnetic field-sensitive device adjacent to, or over other IC devices (e.g., FETs). In some embodiments, one or more techniques known to be suitable for forming a magnetic memory array including cells with an MTJ are practiced during front-side IC fabrication. Front-side fabrication further includes any technique known to be suitable for electrically coupling with interconnect metallization the various fabricated device structures, to thereby form a circuit. For example, dual-damascene technique may be employed to form copper-based interconnect metallization levels within front-side interconnect strata over a front side of the fabricated devices. FIG. 3 is a perspective view of an IC structure 301 including a magnetic field- sensitive device region following front-side IC fabrication, in accordance with some embodiments. As shown, a plurality of non-planar semiconductor bodies (e.g., fins) 315 have been formed into a top semiconductor (e.g., silicon) portion of a IC fabrication substrate 305. For FET embodiments, gate stacks and source/drains (not depicted) are formed over and/or on semiconductor bodies 315. A gate stack may include a gate electrode over a gate dielectric on a channel region of semiconductor bodies 315. While any gate stack materials known to be suitable for semiconductor bodies 315 may be utilized, in some exemplary embodiments the gate stack includes a high-k dielectric material (with a bulk relative permittivity greater than 9) and a metal gate electrode. Exemplary high-k materials include metal oxides, such as, but not limited to AI2O3, HfC , HfAlOx. Silicates, such as, but not limited to HfSiOx, or

TaSiOx may also be suitable for some semiconductor body compositions (e.g., Si, Ge, SiGe, III-V). Source/drains may be formed on opposite ends of the channel region using any known techniques. Interconnect strata 110 are layered over semiconductor bodies 315, for example using any known deposition and patterning techniques.

FIG. 4A and 4B illustrate cross-sectional perspective views of IC structure 301, in accordance with two exemplary embodiments. The cross-sectional views are along the A-A' plane indicated by dashed line in FIG. 3. For IC structure 301A illustrated in FIG. 4A, magnetic field-sensitive device(s) 330 have been formed within interconnect strata 110, for example between two levels of metallization (e.g., between metal-2 and metal-3, between metal-3 and metal-4, etc.). In some such embodiments, at least one interconnect metallization level (e.g., metal-0) is between magnetic field-sensitive device(s) 330 and semiconductor bodies 315. As further shown in schematic form within the expanded view of FIG. 4A, magnetic field-sensitive device(s) 330 comprise an array of magnetic memory cells 335, each having an MTJ. For IC structure 301B illustrated in FIG. 4A, magnetic field-sensitive device(s) 330 have been formed before interconnect strata 110 was formed, for example before a first interconnect metallization level (e.g., metal-0) is fabricated. For such embodiments, magnetic field-sensitive device(s) 330 is directly over a portion of the semiconductor employed for bodies 315. In the example of FIG. 4B, no semiconductor bodies 315 are present under magnetic field-sensitive device(s) 330, which is indicative of the magnetic field-sensitive device(s) having been fabricated early in the IC fabrication process. For some embodiments, magnetic field-sensitive device(s) 330 within IC structure 301B also comprise an array of magnetic memory cells 335, each having an MTJ.

Returning to FIG. 2, methods 201 continue at operation 210 where the back side of an IC device stratum is revealed. To reveal the back side of the device stratum, portions of bulk semiconductor or carrier employed during front-side IC fabrication is removed, and/or polished back, and/or recess etched with a wet and/or dry etch process. Any grind, polish, and/or wet/dry etch process known to be suitable for the composition of the substrate or carrier may be employed at operation 210. For example, where the substrate or carrier is a group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning the semiconductor may be employed at operation 210. Likewise any wet etchant or plasma etch process known to be suitable for thinning the group IV semiconductor may also be employed at operation 210. In some embodiments, operation 210 includes cleaving the substrate or carrier along a fracture plane substantially parallel to the device stratum. The cleaving or fracture process may remove a substantial portion of the substrate as a bulk mass, reducing the polish or etch time needed to remove any remainder. For example, where the substrate or carrier is 400-900 μηι in thickness, 100-700 μηι may be cleaved off by practicing any blanket implant known to promote a wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the substrate or carrier where the fracture plane is desired. Following such a cleaving process, any remainder may then be polished or etched to complete removal and expose a back side of the IC device stratum.

FIG. 5 illustrates a perspective view of an IC structure 501 following back-side reveal, in accordance with some embodiments. IC structure 501 may, for example, have evolved from IC structure 301 A or 301B (FIG. 3A or 3B, respectively). Relative to FIG. 3A and 3B, IC structure 501 has been inverted for clarity of the back side of device stratum 115. As shown, with substrate 305 removed, a back side of non-planar semiconductor bodies 315 is exposed. In some exemplary embodiments where a highly selective (e.g., 200-300: 1) CMP slurry having a higher etch rate of device layer semiconductor (e.g., Si) than dielectric is employed during the reveal operation, the back-side polish may be stopped upon exposure of isolation dielectric surrounding semiconductor bodies 315. An amount of over-etch (over- polish) may be performed to reduce the height of semiconductor bodies 315.

Returning to FIG. 2A, a magnetic shield may be fabricated over the exposed back side of the device stratum at operation 230. Any material of high magnetic permeability may be deposited over the exposed back side, such as, but not limited to those exemplary materials provided elsewhere herein. Any deposition and patterning techniques known to be suitable for the particular magnetic permeable material employed for the shield may be practiced at operation 230. Methods 201 then complete at operation 250 with singulation and packaging of the shielded IC chips. In some embodiments, back-side shields fabricated at the IC chip level are supplemented at operation 250 with front-side shields fabricated at the bump-level or package level. The back-side shield may also be supplemented with one or more shields integrated at the platform level. In other embodiments, the only magnetic shielding integrated within a platform is the back-side shield fabricated at operation 230. If desired, one or more levels of back-side interconnect (e.g., as shown in FIG. IC) may be fabricated during back- side processing performed prior to die singulation. Traces formed during such back-side processing may be routed around a magnetic shield. Alternatively, traces formed during such processing may extend under, over, or pass through a wall (e.g., between adjacent pillars) of a magnetic shield.

Turning to FIG. 2B, methods 202 also include back-side reveal operation 210, magnetic shield fabrication operation 230, and IC chip packaging operation 250. Each of these operations may be substantially as described above for methods 201 in the context of FIG. 2A. However, in methods 202, magnetic field-sensitive devices are not fabricated during the front-side fabrication of IC. Instead, magnetic field-sensitive devices are fabricated at operation 220 as part of the back-side processing performed after reveal operation 210. Any of the field-sensitive devices fabricated during front-side IC fabrication in the context of methods 201 may also be fabricated during back-side processing in the context of methods 202. The examples illustrated in FIG. 3, 5, and 6 are therefore also applicable to the practice of methods 202. If desired, one or more levels of back-side interconnect (e.g., as shown in FIG. IC) may be fabricated before or after fabrication of the magnetic field-sensitive devices. Traces formed during such back-side processing may be routed around a magnetic shield. Alternatively, traces formed during such processing may extend under, over, or pass through a wall of a magnetic shield.

FIG. 7A-7C illustrate cross-sectional perspective views through a magnetic field- sensitive device and a proximal magnetic field shield, in accordance with some embodiments. Each of these illustrations are along the sectional A-A' plane illustrated in dashed line in FIG. 6. In FIG. 7A, IC structure 101A is representative of the IC structure 101 introduced in FIG. 1A that includes magnetic field-sensitive device(s) 330 within interconnect strata 110 and is therefore representative of how IC structure 301A (FIG. 4A) may further evolve as methods 201 are practiced. As shown in FIG. 7 A, magnetic shield 160 forms a perimeter surrounding an area where magnetic field-sensitive device(s) 330 is located. Magnetic shield 160 has a wall height or shield thickness in the z-dimension equal to H. As noted above, shield height H may be a function of the proximity of shield 160 to magnetic field-sensitive device(s) 330. Shield height H may, for example, range between 5 and 300 μιτι, or greater. The feature width W οΐ shield 160 may be a function of shield height H as limited by aspect ratio capability of the shield fabrication techniques. Shield feature width W may, for example, range between 2 and 30 μιτι, or larger.

In FIG. 7A-7C, the surface of magnetic field-sensitive device(s) 330 nearest to shield 160 defines a plane B that is substantially parallel to a plane of device stratum 115. As shown, shield 160 is separated from device(s) 330 by a shield separation S in the z- dimension. In FIG. 7 A and 7B, separation S varies as a function of where magnetically sensitive devices 330 are fabricated within the front-side. Separation Smay range, for example, from a few hundred nanometers (e.g., where device(s) 330 is separated from shield 160 only by device stratum 115) to tens of microns (e.g., where device(s) 330 is separated from shield 160 by multiple interconnect metallization levels). As such, IC structure 101B may have a shield of smaller shield height H than IC structure 101 A, and/or provide more effective shielding for a given shield height H. For embodiments where magnetic field- sensitive device(s) 330 are fabricated over the back side of device stratum 115, shield 160 may overlap the magnetic field-sensitive device(s) 330. For example, as shown in FIG. 7C, there is a negative separation S because plane B intersects shield 160. As such, IC structure 101C may have a shield of smaller shield height H than IC structure lOlA or lOlB, and/or provide more effective shielding for a given shield height H.

In some embodiments, a back-side magnetic shield extends through a device stratum, reducing separation between the shield and magnetic field-sensitive device(s). Such embodiments may be particularly advantageous where magnetic field-sensitive device(s) are fabricated over the front side of a device stratum. FIG. 8 is a flow diagram illustrating methods 801 for fabricating back-side magnetic shielding structures, in accordance with some embodiments. Methods 801 may be practiced to reduce z-dimensional separation of a shield from the magnetic field-sensitive device(s). Methods 801 may be practiced for IC structures that include magnetic field-sensitive device(s) over a front side and/or a back side of a device stratum.

Beginning at operation 805, IC structures are fabricated with any front-side processing of an IC fabrication substrate. Alternatively, the IC structures are received at operation 805 from an upstream fabrication process as an input to methods 801. In some embodiments, the front-side IC structures include a sacrificial material within a region of an IC that is to be subsequently occupied by a portion of the magnetic shield. FIG. 9 is a cross- sectional perspective view through an IC structure 901 including a magnetic field-sensitive device region, in accordance with some embodiments. IC structure 901 includes all the structural features described elsewhere herein in the context of IC structure 301 (FIG. 3), and more particularly IC structure 301A (FIG. 4A). In addition, IC structure 901 includes sacrificial feature 910, which in some embodiments is any material (e.g., a metal) that can be removed selectively from the surrounding semiconductor bodies 315 and/or dielectric 130. Sacrificial feature 910 may have any architecture. In the illustrated embodiment, sacrificial feature 910 extends between the bottom and top surfaces of semiconductor bodies 315 (i.e., sacrificial feature 910 has at least the z-height of semiconductor bodies 315). As further shown in FIG. 9, sacrificial feature 910 may have a greater z-height of semiconductor bodies 315 such that one or more inter-dielectric layer of interconnect strata 110 surrounds a portion of sacrificial feature 910. The z-height of sacrificial feature 910 may vary, for example as a function of the location (e.g., in the z-dimension) of magnetic field-sensitive device(s) 330. In FIG. 9, sacrificial feature 910 overlaps plane B associated with the z-position of magnetic field-sensitive device(s) 330.

Returning to FIG. 8, methods 801 continue with back-side reveal operation 210, and etching operation 820 where a conduit through the device stratum is fabricated. Back-side reveal operation 210 may be substantially as described elsewhere herein. In some embodiments, in addition to exposing the semiconductor and/or dielectric materials as described above, the back-side reveal also exposes a back side of sacrificial material deposited during front-side processing. Any selective etching process may be practiced at operation 820, such as back-side mask application, patterning, and etching of unmasked regions of the device stratum. In some embodiments where sacrificial material is exposed by the back-side reveal, operation 820 entails an unmasked etch that removes the sacrificial material selectively from the surrounding materials (e.g., semiconductor and/or dielectric) exposed by the back-side reveal. A back-side masked or unmasked etch at operation 820 may advantageously be of sufficient duration to clear through the z-thickness of the device stratum and terminate somewhere within the front-side interconnect stratum. The resulting recess or conduit through the device stratum may then be backfilled with material having high magnetic permeably during magnetic field fabrication operation 830. Any of the permeable materials described elsewhere herein may be deposited and patterned with any additive and/or subtractive technique known to be suitable for such material (s). Following operation 830, the resulting shield structure(s) will include a portion passing through the device stratum. Depending on the z-height of the shield, a portion of the shield may extend out of the conduit over the backside of the device stratum. Following shield fabrication, methods 801 complete at operation 250 where the shielded chip can be singulated and packaged, for example following any known techniques. If desired, one or more levels of back-side interconnect (e.g., as shown in FIG. 1C) may be fabricated during back-side processing performed prior to die singulation. Traces formed during such back-side processing may be routed around a magnetic shield. Alternatively, traces formed during such processing may extend under, over, or pass through a wall of a magnetic shield.

FIG. 10 illustrates a perspective view of an IC structure 1001 including a magnetic field-sensitive device following reveal operation 210. IC structure 1001 may be generated from IC structure 901, for example. As shown in FIG. 10, sacrificial feature 910 has an annular architecture, with a wall of sacrificial separating device stratum 115 into an interior region 180 that is surrounded by sacrificial feature 910, and an exterior region. FIG. 11 illustrates a perspective view of an IC structure 1101 including a magnetic field-sensitive device region following a back-side recess etch that selectively removed sacrificial feature

910. IC structure 1101 may be generated from IC structure 1001, for example. Because of the annular architecture of the sacrificial feature, recess 1110 forms an annular moat through device stratum 115. As shown in FIG. 11, recess 1110 is sufficiently deep (e.g., in the z- dimension) to expose dielectric 130. FIG. 12 is a cross-sectional perspective view through IC structure 101D including a magnetic field-sensitive device 330, in accordance with some embodiments. IC structure 101D may be generated from IC structure 1101, for example. IC structure 101D may share any of the structural and/or functional attributes described IC structure 101A (FIG. 7A). With highly permeable material backfilling a recess through device stratum 115, shield 160 includes a portion 160B that extends (e.g., in the z-dimension) over a front side of device stratum 115 as well as a portion 160A that extends (e.g., in the z- dimension) over a back side of device stratum 115. In the illustrated embodiment, shield portion 160B overlaps plane B associated with magnetic field-sensitive device(s) 330, such that shield separation S is negative. In some embodiments, the shield is contained completely within the moat formed within the front-side of the die and the height of region 160A zero. Alternatively, the height of region 160B may be less than the depth of the moat formed within the front-side of the die.

FIG. 13 is a schematic of a magnetic memory cell 1301 of a memory array that is shielded by a back-side magnetic shielding structure, in accordance with some embodiments. FIG. 13 is a schematic of a STTM bit cell, which includes a spin transfer torque element 1310, in accordance with one exemplary embodiment of a magnetic memory cell. Spin transfer torque element 1310 includes a free magnetic material 1355. Element 1310 further includes first metallization 1307 proximate to a fixed magnetic material 1320, a tunneling layer 1330 disposed between free magnetic material 1355 and fixed magnetic material 1320, and a second metallization 1380 proximate to free magnetic material 1355. Second metallization 1380 is electrically coupled to a first metal interconnect 1392 (e.g., bit line). First metallization 1307 is electrically connected to a second metal interconnect 1391 (e.g., source line) through a transistor 1315. The transistor 1315 is further connected to a third metal interconnect 1393 (e.g., word line) in any manner conventional in the art. In SHE implementations second metallization 1380 is further coupled to a fourth metal interconnect 1394 (e.g., maintained at a reference potential relative to first metal interconnect 1392). The spin transfer torque memory bit cell may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as understood by those skilled in the art of solid state non-volatile memory devices. A plurality of the spin transfer torque memory bit cells may be operably connected to one another to form a memory array (not shown), wherein the memory array can be incorporated into a nonvolatile memory device that is shielded from external magnetic fields, at least in part, by a back-side magnetic shield, for example having one more of the features or attributes described elsewhere herein.

In some embodiments, transistor 1315 is a transistor located an IC device stratum, for example as described elsewhere herein. In some further embodiments, magnetic memory cell 1301 is located over a front side, or a back side, of the device stratum, for example as described elsewhere herein. In some further embodiments, one or more of metal

interconnects 1391, 1392, or 1393 electrically couples magnetic memory cell 1301 to CMOS circuitry located within an IC device stratum, for example as described elsewhere herein. One or more of metal interconnects 1391, 1392, or 1393 may be located within one or more levels of interconnect strata over a front side of an IC device stratum, for example as described elsewhere herein. One or more of metal interconnects 1391, 1392, or 1393 may be alternatively located within one or more levels of interconnect strata over a back side of an IC device stratum, for example as described elsewhere herein.

FIG. 14 illustrates a mobile computing platform and a data server machine employing an SoC including one or more magnetic field-sensitive devices and one or more back-side magnetic shields, for example as described elsewhere herein. The server machine 1406 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged monolithic SoC 1450. The mobile computing platform 1405 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1405 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 1410, and a battery 1415.

Either disposed within the integrated system 1410 illustrated in the expanded view 1420, or as a stand-alone packaged chip within the server machine 1406, monolithic SoC 1450 includes a memory block (e.g., RAM), a processor block (e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like) including one or more magnetic field-sensitive devices (e.g., magnetic memory cells) and one or more back-side magnetic shields, for example as described elsewhere herein. The monolithic SoC 1450 may be further coupled to a board, a substrate, or an interposer 1460 along with, one or more of a power management integrated circuit (PMIC) 140, RF (wireless) integrated circuit (RFIC) 1425 including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further comprises a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller 1435.

Functionally, PMIC 1430 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 1415 and with an output providing a current supply to other functional modules. As further illustrated, in the exemplary embodiment, RFIC 1425 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT,

Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 4G+, and beyond. In alternative implementations, each of these board-level modules may be integrated onto separate ICs or integrated into monolithic SoC 1450.

FIG. 15 is a functional block diagram of an electronic computing device, in accordance with some embodiments. Computing device 1500 may be found inside platform 1405 or server machine 1406, for example. Device 1500 further includes a motherboard 1502 hosting a number of components, such as, but not limited to, a processor 1504 (e.g., an applications processor), which may further incorporate at least one oxide semiconductor TFTs covered with a passivation dielectric, for example as described elsewhere herein. Processor 1504 may be physically and/or electrically coupled to motherboard 1502. In some examples, processor 1504 includes an integrated circuit die packaged within the processor 1504. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips 1506 may also be physically and/or electrically coupled to the motherboard 1502. In further implementations, communication chips 1506 may be part of processor 1504. Depending on its applications, computing device 1500 may include other components that may or may not be physically and electrically coupled to motherboard 1502. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. Communication chips 1506 may enable wireless communications for the transfer of data to and from the computing device 1500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 906 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 900 may include a plurality of communication chips 906. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other

implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.

It will be recognized that principles of the disclosure are not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below. In one or more first examples, an integrated circuit (IC) comprises a plurality of transistors within a device stratum of the IC, one or more interconnect levels over a first side of the device stratum and electrically coupled to one or more of the transistors, and a magnetic shield comprising a material having a relative magnetic permeability of at least 50,000. At least a portion of the shield is over a second side of the device stratum opposite the interconnect levels. The IC further comprises one or more magnetic field-sensitive devices coupled to one or more of the transistors.

In one or more second examples, for the first examples the one or more magnetic field-sensitive devices comprise an array of magnetic memory cells.

In one or more third examples, for any of the first or second examples the shield comprises a feature having a width of 2-30 μιτι in a direction substantially parallel to the device stratum, and a height of 5-300 μιτι in a direction substantially perpendicular to the device stratum.

In one or more fourth examples, for any of the first, second, or third examples the shield comprises an annulus of the permeable material. In one or more fifth examples, for any of the first, second, third, or fourth examples the one or more magnetic field-sensitive devices comprise an array of magnetic memory cells having magnetic anisotropy substantially perpendicular to the device stratum, and the shield defines a perimeter surrounding an area of the IC occupied by the magnetic field-sensitive devices. In one or more sixth examples, for any of the first, second, third, fourth, or fifth examples the one or more magnetic field-sensitive devices are over the first side of the device stratum.

In one or more seventh examples, for any of the first, second, third, fourth, fifth, or sixth examples at least a portion of the magnetic shield extends through the device stratum.

In one or more eighth examples, for any of the first, second, third, fourth, fifth, sixth, or seventh examples the magnetic shield is one of a plurality of shields in the IC. Each of the shields occupies an annular conduit passing through the device stratum and surrounding an area of the IC that is underlying the magnetic field-sensitive devices. In one or more ninth examples, for any of the first, second, third, fourth, fifth, sixth, seventh, or eighth examples the one or more magnetic field-sensitive devices are over the second side of the device stratum. At least a portion of the magnetic shield is adjacent to the magnetic field-sensitive devices.

In one or more tenth examples, for any of the first, second, third, fourth, fifth, sixth, seventh, eighth, or ninth examples the IC further comprises one or more second interconnect levels over the second side of the device stratum and electrically coupled to one or more of the transistors or one or more of the magnetic field-sensitive devices. A trace of the second interconnect strata is adjacent to the shield or extends between portions of the shield.

In one or more eleventh examples, an integrated circuit (IC) comprises a plurality of n-type fin field effect transistors (finFETs) and p-type finFETs within a device stratum of the IC. The IC comprises one or more interconnect levels over a first side of the device stratum and electrically coupled to at least some of the finFETs. The IC comprises a magnetic shield comprising a material having a relative magnetic permeability of at least 50,000. At least a portion of the shield is over a second side of the device stratum opposite the interconnect levels. The IC comprises a magnetic memory array within an area of the IC protected by the magnetic shield, wherein cells of the array are coupled to one or more of the finFETs.

In one or more twelfth examples, for any of the eleventh examples the magnetic memory array is over the first side of the device stratum, an individual cell of the array comprises a magnetic tunneling junction (MTJ). The shield comprises a continuous wall surrounding the protected area of the IC, the wall having a width of 2-30 μιτι in a direction substantially parallel to the device stratum and a height of 5-300 μηι in a direction substantially perpendicular to the device stratum.

In one or more thirteenth examples, for any of the eleventh or twelfth examples at least a portion of the magnetic shield extends through the device stratum, and is adjacent to one or more of the finFETs.

In one or more fourteenth examples, a method of fabricating an integrated circuit (IC) comprises forming a plurality of transistors within a device stratum. The method comprises forming one or more interconnect levels over a first side of the device stratum and electrically coupled to one or more of the transistors. The method comprises exposing a second side of the device stratum opposite the interconnect levels. The method comprises forming a magnetic shield over the exposed second side of the device stratum, the shield comprising a material having a relative magnetic permeability of at least 50,000.

In one or more fifteenth examples, for any of the fourteenth examples the method further comprises forming one or more magnetically sensitive devices over the first side of the device stratum.

In one or more sixteenth examples, for any of the fourteenth or fifteenth examples forming the magnetically sensitive devices further comprises fabricating a magnetic memory cell array.

In one or more seventeenth examples, for any of the fourteenth, fifteenth, or sixteenth examples forming the magnetic shield further comprises etching an annular moat through the device stratum from the second side toward the first side, the moat surrounding an area of the IC where one or more magnetically sensitive devices are located. Forming the magnetic shield further comprises depositing the magnetic shield material into the moat.

In one or more eighteenth examples, for any of the fourteenth, fifteenth, sixteenth, or seventeenth examples the method further comprises depositing a sacrificial material into regions of the device stratum prior to forming the interconnect levels over the first side of the device stratum. Exposing the second side of the device stratum exposes the sacrificial material. Etching the moat further comprises removing the sacrificial material selectively from one or more surrounding materials. In one or more nineteenth examples, for any of the fourteenth, fifteenth, sixteenth, seventeenth, or eighteenth examples the method further comprises forming one or more magnetically sensitive devices over the second side of the device stratum after exposing the second side of the device stratum and prior to forming the magnetic shield. In one or more twentieth examples, for any of the fourteenth, fifteenth, sixteenth, seventeenth, eighteenth, or nineteenth examples forming the shield further comprises additively or subtractively defining a continuous wall of shield material surrounding a protected area of the IC where one or more magnetically sensitive devices are located. The wall has a width of 2-30 μιτι in a direction substantially parallel to the device stratum, and a height 5-300 μιτι in a direction substantially perpendicular to the device stratum.

However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMS What is claimed is:

1. An integrated circuit (IC), comprising:

a plurality of transistors within a device stratum of the IC;

one or more interconnect levels over a first side of the device stratum and electrically coupled to one or more of the transistors;

a magnetic shield comprising a material having a relative magnetic permeability of at least

50,000, wherein at least a portion of the shield is over a second side of the device stratum opposite the interconnect levels; and

one or more magnetic field-sensitive devices.

2. The IC of claim 1, wherein the one or more magnetic field-sensitive devices comprise an array of magnetic memory cells.

3. The IC of claim 1, wherein the shield comprises a feature having a width of 2-30 μιτι in a direction substantially parallel to the device stratum and a height of 5-300 μιτι in a direction substantially perpendicular to the device stratum.

4. The IC of claim 3, wherein the shield comprises an annulus of the permeable material.

5. The IC of claim 3, wherein:

the one or more magnetic field-sensitive devices comprise an array of magnetic memory cells having magnetic anisotropy substantially perpendicular to the device stratum; and the shield defines a perimeter surrounding an area of the IC occupied by the magnetic field- sensitive devices.

6. The IC of claim 1, wherein the one or more magnetic field-sensitive devices are over the first side of the device stratum.

7. The IC of claim 6, wherein at least a portion of the magnetic shield extends through the device stratum.

8. The IC of claim 7, wherein:

the magnetic shield is one of a plurality of shields in the IC;

each of the shields occupies an annular conduit passing through the device stratum and

surrounding an area of the IC that is underlying the magnetic field-sensitive devices.

9. The IC of claim 1, wherein:

the one or more magnetic field-sensitive devices are over the second side of the device

stratum; and

at least a portion of the magnetic shield is adjacent to the magnetic field-sensitive devices.

10. The IC of claim 1, further comprising one or more second interconnect levels over the second side of the device stratum and electrically coupled to one or more of the transistors or one or more of the magnetic field-sensitive devices; and

wherein a trace of the second interconnect strata is adjacent to the shield or extends between portions of the shield.

11. An integrated circuit (IC), comprising:

a plurality of n-type fin field effect transistors (finFETs) and p-type finFETs within a device stratum of the IC;

one or more interconnect levels over a first side of the device stratum and electrically coupled to at least some of the finFETs;

a magnetic memory array within an area of the IC protected by the magnetic shield, wherein cells of the array coupled to one or more of the finFETs.

12. The IC of claim 11, wherein:

the magnetic memory array is over the first side of the device stratum;

an individual cell of the array comprises a magnetic tunneling junction (MTJ); and the shield comprises a continuous wall surrounding the protected area of the IC, the wall having a width of 2-30 μιτι in a direction substantially parallel to the device stratum and a height of 5-300 μιτι in a direction substantially perpendicular to the device stratum.

13. The IC of claim 12, wherein:

at least a portion of the magnetic shield extends through the device stratum, and is adjacent to one or more of the finFETs.

14. A method of fabricating an integrated circuit (IC), the method comprising:

forming a plurality of transistors within a device stratum;

forming one or more interconnect levels over a first side of the device stratum and electrically coupled to one or more of the transistors;

exposing a second side of the device stratum opposite the interconnect levels; and forming a magnetic shield over the exposed second side of the device stratum, the shield comprising a material having a relative magnetic permeability of at least 50,000.

15. The method of claim 14, further comprising forming one or more magnetically sensitive devices over the first side of the device stratum.

16. The method of claim 15, wherein forming the magnetically sensitive devices further comprises fabricating a magnetic memory cell array.

17. The method of claim 14, wherein forming the magnetic shield further comprises:

etching an annular moat through the device stratum from the second side toward the first side, the moat surrounding an area of the IC where one or more magnetically sensitive devices are located; and

depositing the magnetic shield material into the moat.

18. The method of claim 17, further comprising depositing a sacrificial material into regions of the device stratum prior to forming the interconnect levels over the first side of the device stratum; and

wherein:

exposing the second side of the device stratum exposes the sacrificial material; and etching the moat further comprises removing the sacrificial material selectively from one or more surrounding materials.

19. The method of claim 14, further comprising forming one or more magnetically sensitive devices over the second side of the device stratum after exposing the second side of the device stratum and prior to forming the magnetic shield.

20. The method of claim 14, wherein forming the shield further comprises:

additively or subtractively defining a continuous wall of shield material surrounding a

protected area of the IC where one or more magnetically sensitive devices are located, the wall having a width of 2-30 μιτι in a direction substantially parallel to the device stratum and a height of 5-300 μιτι in a direction substantially perpendicular to the device stratum.