WO2018113464A1 - Puce d'alimentation électrique, alimentation électrique et procédé de fourniture d'énergie électrique - Google Patents

Puce d'alimentation électrique, alimentation électrique et procédé de fourniture d'énergie électrique Download PDF

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WO2018113464A1
WO2018113464A1 PCT/CN2017/111658 CN2017111658W WO2018113464A1 WO 2018113464 A1 WO2018113464 A1 WO 2018113464A1 CN 2017111658 W CN2017111658 W CN 2017111658W WO 2018113464 A1 WO2018113464 A1 WO 2018113464A1
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WIPO (PCT)
Prior art keywords
power
chip
voltage
control signal
signal
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PCT/CN2017/111658
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English (en)
Chinese (zh)
Inventor
付玉堂
段向阳
封葳
班卫全
王玺
王文静
王雪松
赵金栓
刘亮
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中兴通讯股份有限公司
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Publication of WO2018113464A1 publication Critical patent/WO2018113464A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

Definitions

  • the present disclosure relates to the field of power supplies, and in particular, to a power chip, a power source, and a power supply method.
  • power supply design is required in the circuit board design of many devices such as communication electronic equipment and information technology (IT) servers, and the power supply to be designed is often required to have large power requirements and various types of voltages.
  • the commonly used power supply design is divided into independent power supply design and on-board power supply design.
  • a related power supply design is introduced by Infineon and Texas Instruments (TI) chip vendors based on the System Management Bus (SMBus) through the CPU.
  • SMBs System Management Bus
  • the square wave that outputs different duty cycles is controlled to drive a voltage set by a metal oxide semiconductor (MOS) tube.
  • MOS metal oxide semiconductor
  • the design scheme can only output one voltage value for a period of time, and the power-on timing needs to be controlled by the CPU according to the power requirement of the target chip. Therefore, it is unavoidable that the voltage required by the target chip is large, the difference is large, and The electrical timing is different and the circuit design is cumbersome.
  • the embodiment of the present disclosure provides a power chip, a power supply, and a power supply method, which can avoid the problem that the circuit design is complicated due to various types of voltages required by the target chip, large differences, and different power-on timings, and is convenient for subsequent Circuit debugging and maintenance.
  • a power chip includes a power chip body and M power bus interfaces disposed on the power chip body; wherein each of the power bus interfaces supports S types of power buses, and M and S are positive integers;
  • the power chip is configured to output a first control signal, wherein the first control signal comprises a voltage control signal.
  • the first control signal further includes a timing control signal.
  • the power chip as described above is further configured to acquire a voltage feedback signal and output a second control signal according to the voltage feedback signal; wherein the second control signal comprises a voltage adjustment signal.
  • each of the power bus interfaces is connected to at least one power conversion unit by any one of the S types of power buses;
  • the power chip is configured to output a first control signal to the power conversion unit.
  • the power chip as described above is configured to acquire a voltage feedback signal output by the power conversion unit, and output a second control signal to the power conversion unit according to the voltage feedback signal.
  • the power chip body includes:
  • micro control unit MCU and a signal output unit, the MCU being connected to the signal output unit;
  • the MCU is configured to acquire a voltage value of a voltage required by the power bus according to a type of a power bus, and output a voltage control signal to the signal output unit;
  • the signal output unit is configured to output a first control signal according to the voltage control signal.
  • the MCU is further configured to acquire a power-on sequence of a voltage required by the power bus according to a type of the power bus, and output a timing control signal to the signal output unit;
  • the signal output unit is further configured to output a first control signal according to the voltage control signal and the timing control signal.
  • the power chip body further includes:
  • a power monitoring unit wherein the power monitoring unit is connected to the MCU;
  • the power monitoring unit is configured to acquire a voltage feedback signal, obtain a feedback voltage value according to the voltage feedback signal, and output the feedback voltage value to the MCU;
  • the MCU is further configured to compare the feedback voltage value with a voltage value of a voltage required by the power bus to obtain a voltage adjustment signal and output the voltage adjustment signal to the signal output unit;
  • the signal output unit is further configured to output the second control signal according to the voltage adjustment signal.
  • the power supply monitoring unit comprises a resistor divider network unit and an analog to digital conversion AD sampling unit;
  • the resistor divider network unit is connected to the AD sampling unit;
  • the resistor divider network unit is configured to acquire a voltage feedback signal, and perform a voltage division process on the first feedback voltage value corresponding to the voltage feedback signal to obtain a second feedback voltage value;
  • the AD sampling unit is configured to sample the second feedback voltage value to obtain the feedback voltage value and output to the MCU.
  • the M power bus interfaces are configured through an IO pin of the power chip or configured through an I2C interface.
  • each of the M power bus interfaces is configured to support a power bus interface of one of the S types of power buses.
  • the power chip further includes a power conversion unit, the power conversion unit being integrated in the power chip, and when the power chip is used, the power conversion unit passes through S types of power buses Any one of them is connected to a target chip supporting a corresponding type of power bus;
  • the power conversion unit is configured to provide power to the target chip according to the first control signal.
  • the power conversion unit is further configured to acquire the voltage feedback signal output by the target chip, and provide power to the target chip according to the second control signal.
  • a power supply comprising a power chip and N power conversion units
  • the power chip includes a power chip body and M power bus interfaces disposed on the power chip body; each of the M power bus interfaces supports S types of power buses, and passes through the S Any of the M types of power buses connected to the N power conversion units; when the power source is used, the N power conversion units pass any of the S types of power buses and support The target chip of the corresponding type of power bus is connected; N, M, and S are positive integers;
  • the power chip is configured to output a first control signal to the N power conversion units; wherein the first control signal includes a voltage control signal;
  • the power conversion unit is configured to output power to the target chip according to the first control signal.
  • the first control signal further comprising a timing control signal.
  • the power supply chip is further configured to acquire a voltage feedback signal output by the N power conversion units, and output a second control signal to the N power conversion units according to the voltage feedback signal;
  • the second control signal includes a voltage adjustment signal;
  • the power conversion unit is further configured to acquire a voltage feedback signal output by the target chip and output the voltage feedback signal to the power chip; and output power to the target chip according to the second control signal.
  • the N power conversion units are connected to a target chip supporting a corresponding type of power bus through any one of the S types of power buses, including:
  • the power conversion unit includes: a metal oxide semiconductor MOS transistor unit and an inductance unit;
  • the MOS tube unit is configured to control the power supply to charge the inductive unit according to the first control signal
  • the inductance unit is configured to output electrical energy to the target chip according to the first control signal.
  • the MOS transistor unit is further configured to control the power supply to charge the inductive unit according to the second control signal;
  • the inductor unit is further configured to acquire a voltage feedback signal output by the target chip and output the voltage feedback signal to the power chip; and output power to the target chip according to the second control signal.
  • a method of providing electrical energy comprising:
  • the power chip acquires a voltage value of a voltage required by the power bus according to a type of the power bus, and obtains a voltage control signal;
  • the power chip outputs a first control signal according to the voltage control signal.
  • the method as described above further includes:
  • the power chip acquires a power-on sequence of a voltage required by the power bus according to a type of the power bus, and obtains a timing control signal;
  • the power chip outputs the first control signal according to the voltage control signal, including:
  • the power chip outputs the first control signal according to the voltage control signal and the timing control signal.
  • the method as described above further includes:
  • the power chip acquires a voltage feedback signal
  • the power chip outputs a second control signal according to the voltage feedback signal, wherein the second control signal includes a voltage adjustment signal.
  • the power chip outputs a second control signal according to the voltage feedback signal, including:
  • the power chip acquires a feedback voltage value according to the voltage feedback signal
  • the power chip compares the feedback voltage value with a voltage value of a voltage required by the power bus to obtain a voltage adjustment signal
  • the power chip outputs the second control signal according to the voltage adjustment signal.
  • the obtaining, by the power chip, the feedback voltage value according to the voltage feedback signal includes:
  • the power chip performs a voltage division process on the first feedback voltage value corresponding to the voltage feedback signal to obtain a second feedback voltage value
  • the power chip samples the second feedback voltage value to obtain the feedback voltage value.
  • the power chip provided by the embodiment of the present disclosure includes a chip body and M power bus interfaces disposed on the power chip body; wherein each power bus interface supports S types of power buses, M and S are positive integers;
  • the chip is configured to output a first control signal including a voltage control signal.
  • the power chip scheme provided by some embodiments of the present disclosure avoids the problem that the circuit design is complicated due to various types of voltages required by the target chip, large differences, and different power-on timings, and facilitates subsequent circuit debugging and maintain.
  • FIG. 1 is a schematic structural diagram of a power chip according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a power chip connected to a power conversion unit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a power chip according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another power supply chip according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a power monitoring unit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a power supply according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another power supply according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a power source and a target chip connected according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of another power source connected to a target chip according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of still another connection between a power source and a target chip according to an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of still another connection between a power source and a target chip according to an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram of a power conversion unit according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of still another connection between a power source and a target chip according to an embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram of another power source connected to a target chip according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic flowchart diagram of a method for providing power according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic flowchart diagram of another power supply method according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic flowchart diagram of still another method for providing power according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic flowchart diagram of still another method for providing power according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic flow chart of an embodiment of a power supply working method according to the present disclosure.
  • FIG. 1 is a schematic structural diagram of a power supply chip according to an embodiment of the present disclosure.
  • the power supply chip provided in this embodiment includes a power chip body and M power interfaces disposed on the power chip body; Each power interface supports S types of power buses, and M and S are positive integers.
  • the power chip is configured to output a first control signal, wherein the first control signal comprises a voltage control signal.
  • the voltage control signal carries the voltage value information of the output voltage, and the voltage value of the output voltage may be one or more.
  • each power bus interface can support S types of power bus, that is, each power bus interface can support all types of power bus, but each A power bus interface can only be connected to one type of power bus, ie each power bus interface can be configured as a separate power bus.
  • the M power bus interfaces need to be configured as a power bus interface corresponding to the corresponding type of power bus.
  • the M bus interfaces can pass through the power chip.
  • the IO pins are configured or configured through an I2C interface, or through a Serial Peripheral Interface (SPI) or a Universal Asynchronous Receiver/Transmitter (UART) communication interface.
  • the registers are configured.
  • the I2C interface, the SPI, and the UART communication interface are all media for configuring the bus interface.
  • the media used in the present disclosure for configuring the bus interface include, but are not limited to, the above interfaces.
  • the bus type power chip can be designed in multiple versions, one of which is a simplified version in which each of the M power bus interfaces is configured to support S types of power supplies.
  • the power bus interface of one type of power bus in the bus that is, the power bus interface on the power chip is directly set to support a power bus interface corresponding to a certain type of power bus, and only needs to pass through the power bus and the corresponding target when using The chip can be connected.
  • the power chip provided in this embodiment includes a chip body and M power bus interfaces disposed on the power chip body; wherein each power bus interface supports S types of power buses; and the power chip is configured to output a voltage control signal.
  • a control signal thereby implementing a plurality of power supply schemes, avoids the cumbersome circuit design caused by the variety of voltages required by the target chip, large differences, and different power-on timings.
  • the first control signal further includes a timing control signal.
  • timing control signal carries the voltage of the output voltage of the power bus. Order information.
  • the power chip can complete the voltage timing control through internal processing, so that only the first control signal including the voltage control signal is output, or the internal processing is not performed, but the voltage timing control and the voltage control are all given by Other devices are implemented.
  • the specific implementation process may output a first control signal including a voltage control signal and a timing control signal as described in this embodiment.
  • the power chip is further configured to acquire a voltage feedback signal, and output a second control signal according to the voltage feedback signal, wherein the second control signal includes a voltage adjustment signal.
  • the actual voltage value of the output power may have a certain negative deviation from the voltage value required by the power bus, and according to the voltage feedback signal, the target chip may receive the output power.
  • the actual voltage value outputs a second control signal including the voltage adjustment signal according to the voltage feedback signal, and further adjusts the voltage value of the output power according to the second control signal to reach a voltage value required by the power bus.
  • the power chip provided in this embodiment includes a chip body and M power bus interfaces disposed on the power chip body; wherein each power bus interface supports S types of power bus; the power chip is set to output including voltage control signals and timing
  • the first control signal of the control signal is further configured to acquire a voltage feedback signal, and output a second control signal including the voltage adjustment signal according to the voltage feedback signal, thereby implementing a plurality of power supply schemes more accurately, and avoiding a voltage required by the target chip
  • FIG. 2 is a schematic structural diagram of a power chip connected to a power conversion unit according to an embodiment of the present disclosure. As shown in FIG. 2, when the power chip is used, each power bus interface is connected to at least one power conversion unit by any one of S types of power buses.
  • the power chip is configured to output a first control signal to the power conversion unit.
  • the power chip needs to be connected to at least one power conversion unit through a power bus, and at least one power conversion unit is connected to a target chip through a power bus, and the power chip is combined with the power conversion unit to implement the target chip.
  • the number of connected power conversion units depends on the number of types of voltages required by the target chip connected to the power conversion unit, and the number of connected target chips may be one target chip or total power consumption. Multiple target chips that do not exceed the maximum value of the power chip.
  • the first control signal may include a voltage control signal, and may further include a voltage control signal and a timing control signal.
  • the power chip provided in this embodiment includes a chip body and M power bus interfaces disposed on the power chip body; wherein each power bus interface supports S types of power buses, and any of the S types of power buses One is connected to at least one power conversion unit; the power chip outputs a first control signal to the power conversion unit; thereby implementing a plurality of power supply schemes, thereby avoiding various types of voltages required by the target chip, large differences, and different power-on timings.
  • the problem of cumbersome circuit design is brought about.
  • the power chip is configured to obtain a voltage feedback signal output by the power conversion unit, and output a second control signal to the power conversion unit according to the voltage feedback signal.
  • the power chip provided in this embodiment includes a chip body and M power bus interfaces disposed on the power chip body; wherein each power bus interface supports S types of power buses, and any of the S types of power buses One is connected to the at least one power conversion unit; the power chip outputs a first control signal to the power conversion unit, obtains a voltage feedback signal output by the power conversion unit, and outputs a second control signal including the voltage adjustment signal to the power conversion unit according to the voltage feedback signal. Therefore, more precise implementation of a variety of power supply schemes, avoiding the cumbersome circuit design problems caused by the variety of voltages required by the target chip, large differences, and different power-on timings, and facilitating subsequent circuit testing and maintenance .
  • FIG. 3 is a schematic structural diagram of a power chip according to an embodiment of the present disclosure.
  • the power chip body provided in this embodiment includes:
  • a Microcontroller Unit (MCU) and a signal output unit, the MCU is connected to the signal output unit.
  • the MCU is configured to obtain a voltage value of a voltage required by the power bus according to the type of the power bus, and output a voltage control signal to the signal output unit.
  • the signal output unit is configured to output the first control signal according to the voltage control signal.
  • the signal output unit integrates the voltage control signals to form a first control signal and outputs.
  • the power chip provided in this embodiment provides M bus interfaces on the power chip body, and each bus interface supports S types of power buses; the MCU of the power chip obtains a voltage control signal according to the type of the power bus, and the signal output of the power chip The unit outputs the first control signal according to the voltage control signal, so that the power of the multi-type target chip can be supplied according to the voltage value and the power-on timing requirement of the multi-type target chip, thereby avoiding the large variety and large difference of the voltage required by the target chip.
  • the power-up sequence is different, which brings cumbersome circuit design and facilitates subsequent circuit testing and maintenance.
  • the MCU is further configured to obtain a power-on sequence of a voltage required by the power bus according to the type of the power bus, and output a timing control signal to the signal output unit.
  • the signal output unit is further configured to output the first control signal according to the voltage control signal and the timing control signal.
  • the signal output unit integrates the voltage control signal and the timing control signal to form a first control signal and outputs the same.
  • the power chip provided in this embodiment provides M bus interfaces on the power chip body, and each bus interface supports S types of power buses; the MCU of the power chip obtains voltage control signals and timing control signals according to the type of the power bus, and the power supply.
  • the signal output unit of the chip outputs the first control signal according to the voltage control signal and the timing control signal, so that the power value of the multi-type target chip can be supplied according to the voltage value and the power-on timing requirement of the multi-type target chip, thereby avoiding the target chip.
  • FIG. 4 is a schematic structural diagram of another power supply chip according to an embodiment of the present disclosure.
  • the power chip body provided in this embodiment further includes:
  • the power monitoring unit the power monitoring unit is connected to the MCU, and the power monitoring unit is configured to obtain a voltage feedback signal, obtain a feedback voltage value according to the voltage feedback signal, and output feedback to the MCU. Voltage value.
  • the MCU is further configured to compare the feedback voltage value with the voltage value of the voltage required by the power bus to obtain a voltage adjustment signal and output a voltage adjustment signal to the signal output unit.
  • the signal output unit is further configured to output a second control signal to the power conversion unit according to the voltage adjustment signal.
  • the target chip when the power conversion unit supplies power to the target chip according to the first control signal, the target chip returns the voltage feedback signal to the power monitoring unit through the power conversion unit, so that the power chip can calculate the voltage value of the voltage required by the target chip. Make precise adjustments.
  • the voltage values of the voltages required for different types of power buss are different. Assuming that the type A of the power bus requires three voltages, the voltage values are 1.8V, 2.5V, and 3.3V, respectively, then the MCU will feedback the voltage value (this The feedback voltage value is three voltage values close to 1.8V, 2.5V and 3.3V. It is compared with 1.8V, 2.5V and 3.3V respectively, and the voltage adjustment signal is obtained and output to the signal output unit; assuming bus type B requires 2 The voltage and voltage values are 2.0V and 2.8V respectively, then the MCU compares the feedback voltage value (the feedback voltage value is close to 2.0V and 2.8V) and compares it with 2.0V and 2.8V to obtain the voltage. Adjust the signal and output to the signal output unit.
  • the signal output unit integrates the voltage adjustment signal to form a second control signal and outputs it.
  • the power chip provided in this embodiment adds a power monitoring unit based on the power chip provided in the foregoing embodiment, so that the power chip can provide power to the target chip with a precise voltage value, thereby avoiding various types of voltages required by the target chip.
  • the problems of large circuit design and complicated power-on sequence are complicated, and the subsequent circuit debugging and maintenance are convenient.
  • FIG. 5 is a schematic structural diagram of a power monitoring unit according to an embodiment of the present disclosure.
  • the power monitoring unit provided in this embodiment includes a resistor divider network unit and an analog-to-digital converter (AD) sampling unit; the resistor divider network unit is connected to the AD sampling unit.
  • AD analog-to-digital converter
  • a resistor divider network unit configured to acquire a voltage feedback signal and to apply a voltage feedback signal Performing a voltage division process on the corresponding first feedback voltage value to obtain a second feedback voltage value
  • the AD sampling unit is configured to sample the second feedback voltage value to obtain a feedback voltage value and output to the MCU.
  • the power chip provided in this embodiment adds a power monitoring unit, so that the power chip can provide power to the target chip with a precise voltage value, thereby avoiding that the target chip requires a variety of voltages, large differences, and different power-on timings.
  • the circuit design is cumbersome and convenient for subsequent circuit debugging and maintenance.
  • the power chip provided in this embodiment further includes a power conversion unit, and the power conversion unit is integrated in the power chip.
  • the power conversion unit passes through any one of the S types of power buses and supports the corresponding type.
  • the target chip connection of the power bus
  • the power conversion unit is configured to supply power to the target chip according to the first control signal.
  • the power conversion unit can also be integrated in the power chip to realize the integration of the voltage control function and the power conversion function.
  • the power chip provided in this embodiment includes a chip body and M power bus interfaces disposed on the power chip body; wherein each power bus interface supports S types of power buses, and the power chip further includes a power conversion unit and a power conversion unit.
  • the power conversion unit is connected to the target chip supporting the corresponding type of power bus through any one of the S types of power buses, and supplies power to the target chip according to the first control signal. Therefore, a plurality of power supply schemes are realized, and the problem that the circuit design is complicated due to various types of voltages required by the target chip, large differences, and different power-on timings are avoided.
  • the power conversion unit is further configured to acquire a voltage feedback signal output by the target chip, and provide power to the target chip according to the second control signal.
  • the power chip provided in this embodiment includes a chip body and M power bus interfaces disposed on the power chip body; wherein each power bus interface supports S types of power buses, and the power chip further includes a power conversion unit and a power conversion unit. Integrated in the power chip, when the power chip is used, the power conversion unit is connected to the target chip supporting the corresponding type of power bus through any one of the S types of power buses, and is the target chip according to the first control signal.
  • FIG. 6 is a schematic structural diagram of a power supply according to an embodiment of the present disclosure. As shown in FIG. 6, the power supply provided in this embodiment includes: a power chip and N power conversion units.
  • the power chip includes a power chip body and M power bus interfaces disposed on the power chip body; each of the M power bus interfaces supports S types of power buses, and adopts any M types of the S types.
  • the type of power bus is connected to the N power conversion units; when the power source is used, the N power conversion units are connected to the target chip supporting the corresponding type of power bus through any of the M types of power buses of the S types (in the figure The first type of target chip, the second type of target chip...
  • the Mth type target chip represents a target chip supporting different types of power buses; N, M, and S are positive integers.
  • a power chip configured to output a first control signal to the N power conversion units; wherein the first control signal includes a timing control signal;
  • the power conversion unit is configured to output power to the target chip according to the first control signal.
  • the power supply provided in this embodiment includes a power chip and N power conversion units.
  • the power chip outputs a first control signal including a voltage control signal to the power conversion unit, and the power conversion unit outputs power to the target chip according to the first control signal, thereby avoiding Due to the variety of voltages required by the target chip, large differences, and different power-up timings, the circuit design is cumbersome, and the subsequent circuit debugging and maintenance is facilitated.
  • the first control signal further includes a timing control signal.
  • the power supply provided in this embodiment includes a power chip and N power conversion units.
  • the power chip outputs a first control signal including a voltage control signal and a timing control signal to the power conversion unit, and the power conversion unit outputs the target control chip according to the first control signal.
  • the electric energy avoids the problem that the circuit design is complicated due to various types of voltages required by the target chip, large differences, and different power-on timings, and facilitates subsequent circuit debugging and maintenance.
  • FIG. 7 is a schematic structural diagram of another power supply according to an embodiment of the present disclosure.
  • the power chip is also set to acquire N power conversion unit outputs.
  • the voltage feedback signal outputs a second control signal to the N power conversion units according to the voltage feedback signal, wherein the second control signal includes a voltage adjustment signal.
  • the power conversion unit is further configured to acquire a voltage feedback signal output by the target chip and output the signal to the power chip; and output power to the target chip according to the second control signal.
  • the power supply provided in this embodiment is based on the foregoing embodiment, the power chip acquires the voltage feedback signal of the power conversion unit, outputs a second control signal including the voltage adjustment signal according to the voltage feedback signal, and the power conversion unit targets the target according to the second control signal.
  • the output power of the chip enables the power chip to supply power to the target chip with a precise voltage value, thereby avoiding the cumbersome circuit design caused by the variety of voltages required by the target chip, large differences, and different power-on timings. And facilitate subsequent circuit debugging and maintenance.
  • the type of the power bus is divided according to the voltage type, power consumption, and power-on timing required by the target chip. Therefore, power can be supplied to a type of target chip through one type of power bus, if one type is passed.
  • the power bus supplies power to a type of target chip.
  • the voltage type, power consumption, and power-on timing required for such a target chip are the same.
  • the number of target chips of one type may be a target chip or a total Multiple target chips that consume no more than the maximum power chip.
  • FIG. 8 is a schematic structural diagram of a connection between a power source and a target chip according to an embodiment of the present disclosure. As shown in FIG. 8, the power supply is connected to the target chip through the power bus to supply power to the target chip.
  • FIG. 8 is a schematic structural diagram of a connection between a power source and a target chip according to an embodiment of the present disclosure. As shown in FIG. 8, the power supply is connected to the target chip through the power bus to supply power to the target chip.
  • FIG. 9 is a schematic structural diagram of another power source and a target chip connected according to an embodiment of the present disclosure.
  • the N power conversion units pass any of the S types.
  • a type of power bus is connected to a target chip that supports a corresponding type of power bus, including:
  • the N 1 power conversion unit is connected to the target chip (the first type of target chip) supporting the first type of power bus through the first type of power bus; wherein the first type of power supply
  • the bus is any one of the S types of power buses, and N 1 is equal to the number of voltage values of the voltage required by the first type of power bus;
  • N 2 power conversion units are connected to a target chip (second type target chip) supporting a second type of power bus through a second type of power bus; wherein the second type of power bus is a type S power supply Any one of the buses, N 2 is equal to the number of voltage values of the voltage required by the second type of power bus;
  • the N M power conversion units are connected to the target chip (the M-type target chip) supporting the M-type power bus through the M-type power bus; wherein the M-type power bus is S Any of the types of power buses, N M is equal to the number of types of voltage values required for the power supply bus of the Mth type.
  • the power supply provided by the embodiment provides power to the target chip supporting the corresponding type of power bus through various types of power buses, thereby avoiding the fact that the target chip requires a variety of voltages, large differences, and different power-on timings.
  • the circuit design is cumbersome and convenient for subsequent circuit debugging and maintenance.
  • FIG. 10 is a schematic structural diagram of still another connection between a power source and a target chip according to an embodiment of the present disclosure.
  • the power supply includes a power chip and N power conversion units, and the power chip supplies power to the N target chips through a power bus.
  • FIG. 11 is a schematic structural diagram of still another connection between a power source and a target chip according to an embodiment of the present disclosure.
  • the power supply includes a power chip and N power conversion units.
  • the power chip supplies power to a type of target chip through a first type of power bus, and the power chip passes another type of power bus to another type of target chip. Power, ..., the power chip supplies power to another type of target chip through the M-type power bus.
  • FIG. 12 is a schematic structural diagram of a power conversion unit according to an embodiment of the present disclosure.
  • the power conversion unit includes: a metal oxide semiconductor (MOS) tube unit and an inductor unit;
  • MOS metal oxide semiconductor
  • the MOS tube unit is configured to control the power supply to charge the inductance unit according to the first control signal.
  • the inductance unit is configured to output electrical energy to the target chip according to the first control signal.
  • MOS tube unit is further configured to control the power supply to charge the inductance unit according to the second control signal.
  • the inductor unit is further configured to acquire a voltage feedback signal output by the target chip and output a voltage feedback signal to the power chip; and output power to the target chip according to the second control signal.
  • the power supply is the original source of the electric energy, and the power supply may be other devices or devices capable of providing electric energy, which is not limited in the disclosure.
  • the power supply process of the MOS tube unit and the inductor unit to the target chip is: when the voltage supplied to the target chip (the voltage at this time is the rated voltage required by the target chip) is lowered, then the MOS tube The switching action of the unit comes into effect, the power supply charges the inductor unit and reaches the rated voltage required by the target chip; when the voltage supplied to the target chip rises, the power supply is disconnected by the switching action of the MOS tube unit, and the inductor unit is released.
  • the inductance unit becomes a "power supply" and continues to supply power to the target chip; as the stored energy on the inductor unit is continuously consumed, the voltage supplied to the target chip begins to gradually decrease, and the power supply passes through the MOS.
  • the switching action of the tube unit begins to charge the inductor unit, so that the cycle is continuously charged and discharged, thereby forming a stable voltage to power the target chip.
  • FIG. 13 is a schematic structural diagram of another power supply connected to the target chip according to an embodiment of the present disclosure. Assuming M is equal to 2, the target chip can be divided into two categories according to the required voltage type, power consumption and power-on timing, which are recorded as the first type target chip and the second type target chip, and the first type target chip passes the first type.
  • the power bus is connected to one of the power supplies, and the second type of target chip is connected to the other interface of the power supply via the second type of power bus.
  • the first type of power bus also needs the voltage values of the three voltages and the same power-on sequence.
  • the first type of power bus requires three power conversion units; assuming that the voltage required for the second type of target chip is 2.0V, 1.5V, and the power-up sequence is 1.5V to 2.0V, then the second type The power bus also requires the voltage values of the two voltages and the same power-on sequence; correspondingly, the second type of power bus requires two power conversion units. As shown in Figure 13, the power chip obtains the voltage required for the first type of power bus according to the first type of power bus.
  • the voltage value is 3.3V, 1.8V, 1.2V
  • the power-up timing is 1.2V to 1.8V.
  • Up to 3.3V outputting a first control signal including a voltage control signal and a timing control signal to the corresponding three power conversion units, and the corresponding three power conversion units output power to the first type of target chip according to the first control signal, specifically
  • the three power conversion units respectively undertake three different step-down tasks according to the voltage control signal, and the voltages are respectively reduced to 3.3V, 1.8V, and 1.2V, and then the voltage after the step-down is completed according to the timing control signal is 1.2V.
  • the corresponding three power conversion units obtain the feedback signal of the first type of target chip output and feedback signal Output to the power chip, the power chip outputs a second control signal including a voltage adjustment signal to the corresponding three power conversion units through a series of processing and control, and corresponding three power conversions
  • the element adjusts the output voltage according to the second control signal, and adjusts and compensates the voltage value of the output voltage that does not reach 3.3V, 1.8V, and 1.2V, thereby more accurately supplying power to the first type of target chip;
  • the process of outputting power to the second type of target chip by the chip is similar to the above process, and will not be described herein.
  • the power supply provided in this embodiment includes a power chip and N power conversion units.
  • the power chip outputs a first control signal including a voltage control signal and a timing control signal to the power conversion unit, and the power conversion unit outputs the target control chip according to the first control signal.
  • the power source chip obtains the voltage feedback signal of the power conversion unit, and outputs a second control signal including the voltage adjustment signal according to the voltage feedback signal, and the power conversion unit outputs the power to the target chip according to the second control signal, so that the accurate voltage value can be obtained.
  • the target chip provides voltage, avoids the cumbersome circuit design caused by the variety of voltages required by the target chip, large differences, and different power-on timings, and facilitates subsequent circuit debugging and maintenance.
  • FIG. 14 is a schematic structural diagram of still another connection between a power source and a target chip according to an embodiment of the present disclosure.
  • the power supply includes a power chip and a power conversion unit.
  • the power chip includes a power monitoring unit, an MCU control unit, a signal output unit, a power conversion unit including a MOS tube unit and an inductor unit, and a power bus interface is disposed on the power chip. Connect the power bus at the power bus interface.
  • the MOS tube unit and the inductor unit supply power to the target chip according to the control signal.
  • the inductor unit receives the voltage feedback signal sent by the target chip and sends the voltage feedback signal to the power source detecting unit in the power chip, and the power detecting unit performs preliminary on the voltage feedback signal. After processing, it is sent to the MCU unit for processing again. After the MCU unit processes the voltage feedback signal again, it sends it to the signal output unit, and the signal output unit outputs another control signal.
  • the MOS tube unit and the inductor unit are based on the new control signal.
  • the target chip is powered.
  • FIG. 15 is a schematic flowchart diagram of a method for providing power according to an embodiment of the present disclosure. As shown in FIG. 15, the method provided in this embodiment includes:
  • Step 101 The power chip acquires a voltage value of a voltage required by the power bus according to the type of the power bus, and obtains a voltage control signal.
  • Step 102 The power chip outputs a first control signal according to the voltage control signal.
  • the power chip acquires voltage values of different voltages according to the type of the power bus, obtains a voltage control signal, and outputs a first control signal according to the obtained voltage control signal, thereby satisfying the power supply for the plurality of target chips. the goal of.
  • FIG. 16 is a schematic flowchart diagram of another power supply method according to an embodiment of the present disclosure. As shown in FIG. 16, the method provided in this embodiment includes:
  • Step 201 The power chip acquires a voltage value of a voltage required by the power bus according to a type of the power bus, and obtains a voltage control signal.
  • Step 202 The power chip acquires a power-on sequence of a voltage required by the power bus according to the type of the power bus, and obtains a timing control signal.
  • Step 203 The power chip outputs the first control signal according to the voltage control signal and the timing control signal.
  • the power chip obtains a voltage control signal according to the type of the power bus, and obtains a voltage control signal according to the type of the power bus, and obtains a timing control signal according to the power supply timing of the power bus.
  • the voltage control signal and the timing control signal output the first control signal; thereby satisfying the purpose of supplying power to a plurality of target chips.
  • FIG. 17 is a schematic flowchart diagram of still another method for providing power according to an embodiment of the present disclosure. As shown in FIG. 17, the method provided in this embodiment includes:
  • Step 301 The power chip acquires a voltage feedback signal.
  • Step 302 The power chip acquires a feedback voltage value according to the voltage feedback signal.
  • Step 303 The power chip compares the feedback voltage value with the voltage value of the voltage required by the power bus to obtain a voltage adjustment signal.
  • Step 304 The power chip outputs a second control signal according to the voltage adjustment signal.
  • the power chip acquires a voltage feedback signal, obtains a feedback voltage value according to the voltage feedback signal, compares the feedback voltage value with a voltage value of a voltage required by the power bus, obtains a voltage adjustment signal, and adjusts according to the voltage.
  • the signal outputs a second control signal; thereby better satisfying the design requirements of different distribution of the target chip, voltage type, current size and power-on timing, and facilitating subsequent commissioning and maintenance.
  • FIG. 18 is a schematic flowchart diagram of still another method for providing power according to an embodiment of the present disclosure. As shown in FIG. 18, the method provided in this embodiment includes:
  • Step 401 The power chip acquires a voltage value of a voltage required by the power bus according to a type of the power bus, and outputs a voltage control signal; acquires a power-on sequence of a voltage required by the power bus according to a type of the power bus, and outputs a timing control signal.
  • Step 402 The power chip outputs the first control signal according to the voltage control signal and the timing control signal.
  • Step 403 The power chip acquires a voltage feedback signal.
  • Step 404 The power chip performs voltage division processing on the first feedback voltage value corresponding to the voltage feedback signal to obtain a second feedback voltage value.
  • Step 405 The power chip samples the second feedback voltage value to obtain a feedback voltage value.
  • Step 406 The power chip compares the feedback voltage value with the voltage value of the voltage required by the power bus to obtain a voltage adjustment signal.
  • Step 407 The power chip outputs a second control signal according to the voltage adjustment signal.
  • the power chip acquires voltage values of different voltages according to the type of the power bus, and outputs a voltage control signal; acquires power-on timings of different voltages according to the type of the power bus, and outputs a timing control signal; according to the voltage control signal And the timing control signal outputs a first control signal; and obtains a voltage feedback signal of the power conversion unit, thereby obtaining a voltage adjustment signal, and outputting a second control signal including the voltage adjustment signal; thereby better satisfying the dispersion of the target chip due to voltage
  • the design requirements vary in type, current size, and power-up timing, and facilitate subsequent commissioning and maintenance.
  • FIG. 19 is a schematic flow chart of an embodiment of a power supply working method according to the present disclosure. As shown in FIG. 19, first, the power supply is powered on, and then the configuration of the external pin is read or the internal register is checked to determine the type configuration of the power bus, and then the power monitoring unit in the power supply monitors whether the output voltage of the power conversion unit conforms to the target chip. It is required and whether the output is normal. If it is normal, the target chip is normally powered. If it is not normal, it will alarm and stop supplying power.
  • the power supply working method provided in this embodiment detects whether the output voltage meets the requirements of the target chip before the target chip, thereby implementing power supply to the target chip under the requirement of meeting the required voltage of the target chip.
  • Embodiments of the present disclosure also provide a storage medium.
  • the foregoing storage medium may be configured to store program code for performing the following steps:
  • the power chip obtains a voltage value of a voltage required by the power bus according to the type of the power bus, and obtains a voltage control signal.
  • the power chip outputs a first control signal according to the voltage control signal.
  • the above storage medium may be further configured to store program code for performing the following steps:
  • the power chip acquires the voltage value of the voltage required by the power bus according to the type of the power bus. A voltage control signal is obtained.
  • the power chip acquires a power-on sequence of a voltage required by the power bus according to the type of the power bus, and obtains a timing control signal.
  • the power chip outputs the first control signal according to the voltage control signal and the timing control signal.
  • the above storage medium may be further configured to store program code for performing the following steps:
  • the power chip acquires a voltage feedback signal.
  • the power chip acquires a feedback voltage value according to the voltage feedback signal.
  • the power chip compares the feedback voltage value with a voltage value of a voltage required by the power bus to obtain a voltage adjustment signal.
  • the power chip outputs a second control signal according to the voltage adjustment signal.
  • the above storage medium may be configured to store program code for performing the following steps:
  • the power chip performs voltage division processing on the first feedback voltage value corresponding to the voltage feedback signal to obtain a second feedback voltage value.
  • the power chip samples the second feedback voltage value to obtain a feedback voltage value.
  • the foregoing storage medium may include, but is not limited to, a USB flash drive, a Read-Only Memory (ROM), a Random Access Memory (RAM), and a mobile device.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • a variety of codes that can store programs such as hard disks, disks, or optical disks.
  • embodiments of the present disclosure can be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware aspects. Moreover, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the present disclosure refers to methods, devices (systems), and computer programs in accordance with embodiments of the present disclosure.
  • the flow chart and/or block diagram of the product is described. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG.
  • These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the power chip provided by the embodiment of the present disclosure includes a chip body and M power bus interfaces disposed on the power chip body; wherein each power bus interface supports S types of power buses, M and S are positive integers;
  • the chip is configured to output a first control signal including a voltage control signal; thereby avoiding the problem that the circuit design is complicated due to various types of voltages required by the target chip, large differences, and different power-on timings, and is convenient for subsequent Circuit debugging and maintenance.

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  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

La présente invention concerne une puce d'alimentation électrique, une alimentation électrique et un procédé de fourniture d'énergie électrique. La puce d'alimentation électrique comprend un corps de puce et M interfaces de bus disposées sur le corps de puce d'alimentation électrique, chaque interface de bus d'alimentation électrique prenant en charge S types de bus d'alimentation électrique, et M et S étant tous les deux des nombres entiers positifs. La puce d'alimentation électrique est configurée pour émettre un premier signal de commande comprenant un signal de commande de tension.
PCT/CN2017/111658 2016-12-20 2017-11-17 Puce d'alimentation électrique, alimentation électrique et procédé de fourniture d'énergie électrique WO2018113464A1 (fr)

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Publication number Priority date Publication date Assignee Title
CN109582115B (zh) * 2018-11-01 2022-04-26 超越科技股份有限公司 基于cpld保障服务器电源系统稳定性的装置及方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020001213A1 (en) * 1999-05-24 2002-01-03 Philips Electronics North America Corporation Integrated circuit (ic) switching power converter
CN101039067A (zh) * 2006-03-17 2007-09-19 富士通株式会社 电源控制电路、电源及其控制方法
US20100072963A1 (en) * 2008-09-22 2010-03-25 Richtek Technology Corporation Power management chip with dual function pin
CN102158082A (zh) * 2011-04-12 2011-08-17 杭州矽力杰半导体技术有限公司 一种具有多路输出的电源管理系统
CN102349224A (zh) * 2009-03-13 2012-02-08 罗姆股份有限公司 多输出电源装置及使用了它的电气设备

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101198214A (zh) * 2006-12-07 2008-06-11 黑龙江大学 带扩展接口的基本系统印刷电路板
CN100546161C (zh) * 2007-06-05 2009-09-30 江苏万工科技集团有限公司 电源控制装置
CN103107693A (zh) * 2011-11-14 2013-05-15 鸿富锦精密工业（深圳）有限公司 测试电源装置
US8894419B1 (en) * 2012-08-14 2014-11-25 Bby Solutions, Inc. Magnetically connected universal computer power adapter
CN103488273B (zh) * 2013-09-12 2016-03-23 江苏中科梦兰电子科技有限公司 一种通过gpio控制龙芯3b1500核心电压的供电电路
CN104917014A (zh) * 2014-03-13 2015-09-16 苏州普福斯信息科技有限公司 一种三合一转接器及其控制系统
CN104615063A (zh) * 2014-12-29 2015-05-13 浪潮电子信息产业股份有限公司 电源管理系统及方法
CN104617771A (zh) * 2015-03-09 2015-05-13 王锴 开关电源转换器系统及其控制方法
CN204462740U (zh) * 2015-03-11 2015-07-08 湖南省交通科学研究院 基于传感器监测系统的电源管理装置
CN105045366B (zh) * 2015-07-01 2019-01-15 湖南汽车工程职业学院 一种处理器多电源管理控制装置、系统及方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020001213A1 (en) * 1999-05-24 2002-01-03 Philips Electronics North America Corporation Integrated circuit (ic) switching power converter
CN101039067A (zh) * 2006-03-17 2007-09-19 富士通株式会社 电源控制电路、电源及其控制方法
US20100072963A1 (en) * 2008-09-22 2010-03-25 Richtek Technology Corporation Power management chip with dual function pin
CN102349224A (zh) * 2009-03-13 2012-02-08 罗姆股份有限公司 多输出电源装置及使用了它的电气设备
CN102158082A (zh) * 2011-04-12 2011-08-17 杭州矽力杰半导体技术有限公司 一种具有多路输出的电源管理系统

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