WO2018111277A1 - P-dopant precursors for iii-v semiconductor devices - Google Patents

P-dopant precursors for iii-v semiconductor devices Download PDF

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Publication number
WO2018111277A1
WO2018111277A1 PCT/US2016/066927 US2016066927W WO2018111277A1 WO 2018111277 A1 WO2018111277 A1 WO 2018111277A1 US 2016066927 W US2016066927 W US 2016066927W WO 2018111277 A1 WO2018111277 A1 WO 2018111277A1
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Prior art keywords
stabilized
mocvd
eta
group
semiconductor region
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PCT/US2016/066927
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French (fr)
Inventor
Patricio E. Romero
Scott B. Clendenning
Matthew V. Metz
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Intel Corporation
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Priority to PCT/US2016/066927 priority Critical patent/WO2018111277A1/en
Publication of WO2018111277A1 publication Critical patent/WO2018111277A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures

Definitions

  • TFET tunnel field effect transistor
  • An essential feature of a TFET is the inclusion of a highly p- doped source region. Placing free p-dopant atoms in a thin film layer growth, however, can lead to undesirable diffusion as the p-dopant atoms are not tightly bound within the crystal lattice.
  • FIG. 1 illustrates a cross-sectional view of an example semiconductor device, according to some embodiments
  • Fig. 2 illustrates an atomic composition of an example p-type III-V semiconductor region, according to some embodiments
  • FIG. 3 illustrates an atomic composition of an example p-type III-V semiconductor region, according to some embodiments
  • FIG. 4 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments
  • FIG. 5 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments
  • FIG. 6 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments
  • FIG. 7 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments.
  • Fig, 8 illustrates a diagram of an example semiconductor manufacturing equipment, according to some embodiments.
  • Figs. 9A-9H illustrate example p-dopant precursor molecules for III-V semiconductor devices, according to some embodiments
  • Fig. 10 illustrates a flowchart of a method of forming a semiconductor device, in accordance with some embodiments
  • Fig. 11 illustrates a smart device or a computer system or a SoC (System-on-
  • Chip which includes a semiconductor device, according to some embodiments.
  • P-dopant precursors for III-V semiconductor devices are generally presented.
  • embodiments of the present invention enable highly doped p-type III-V semiconductor regions that previously may have been more difficult or impossible to achieve due to diffusion of p-dopant atoms that are not tightly bound within the crystal lattice.
  • highly doped regions may enable steeper junctions with lower switching voltages and lower leakage currents.
  • connection means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.
  • coupled means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
  • circuit or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
  • signal may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.
  • the meaning of "a,” “an,” and “the” include plural references.
  • the meaning of "in” includes “in” and "on.”
  • phrases “A and/or B” and “A or B” mean (A), (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • the terms “left,” “right/' “front,' ' “hack,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.
  • Fig. 1 illustrates a cross-sectional view of an example semiconductor device, according to some embodiments.
  • device 100 includes substrate 102, p-type source 104, n-type drain 106, gate 108, gate oxide 110 and intrinsic channel 112.
  • TFET tunnel FET
  • TFET tunnel FET
  • other types of semiconductor devices can benefit from teachings of the present invention as well, including, but not limited to, diodes, transistors, solar cells, and sensors.
  • P-type source 104 can be formed from a MOCVD thin film epitaxial growth using precursor molecules described in more detail hereinafter. While shown as being a recessed region, p-type source 104 can be a raised source, a fin, or any other configuration.
  • Fig. 2 illustrates an atomic composition of an example p-type III-V semiconductor region, according to some embodiments.
  • p-type lattice 200 includes group 13 atoms 202, group 15 atoms 204, single bonds 206, dopants 208 and holes 210.
  • p-type lattice 200 represents the product of a metalorganic chemical vapor deposition (MOCVD) wherein precursor molecules with appropriate thermal stability and volatility have been suitably diffused prior to dissociation of molecular components such that dopants 208 are substantially uniformly present in p-type lattice 200.
  • MOCVD metalorganic chemical vapor deposition
  • dopants 208 are present in p-type lattice 200 at a concentration of about 5 x 10 19 atoms»cm "3 .
  • dopants 208 may replace some group 13 atoms 202 in p-type lattice 200. Where dopants 208 are atoms with two valence electrons, such as Zn or Mg, for example, instead of the three valence electrons of the replaced group 13 atom 202, this leads to the presence of holes 210.
  • Fig. 3 illustrates an atomic composition of an example p-type III-V semiconductor region, according to some embodiments.
  • p-type lattice 300 includes group 13 atoms 302, group 15 atoms 304, single bonds 306, dopants 308 and holes
  • p-type lattice 300 represents the product of a metalorganic chemical vapor deposition (MOCVD) including precursor molecules with dopants 308 prebound to group 13 atoms 302 such that dopants 308 are substantially uniformly present in p-type lattice 300.
  • MOCVD metalorganic chemical vapor deposition
  • dopants 308 are present in p- type lattice 300 at a concentration of about 5 x 10 19 atoms»cm "3 .
  • dopants 308 may replace some group 15 atoms 304 in p-type lattice 300. Where dopants 308 are atoms with four valence electrons, such as C, for example, instead of the five valence electrons of the replaced group 15 atom 304, this leads to the presence of holes 310.
  • Fig. 4 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments.
  • assembly 400 includes semiconductor substrate 102 and substrate surface 402.
  • substrate 102 comprises at least one layer of undoped
  • III-V semiconductor such as GaAs, InGaAs, BP, AlSb, etc.
  • Substrate 102 may be composed of one or more III-V semiconductor material layers on top of another semiconductor material such as silicon.
  • Fig. 5 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments.
  • assembly 500 includes substrate 102, substrate surface 402, and recessed surface 502.
  • Recessed surface 502 may be created below substrate surface 402 by removing material from substrate 102 by various means, including chemical, mechanical or laser.
  • Fig. 6 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments.
  • assembly 600 includes substrate 102, recessed surface 502 and mask 602.
  • Mask 602 may be formed on select surfaces of substrate 102 to prevent
  • recessed surface 502 may be made by first depositing a blanket layer of hard mask material (such as but not limited to a silicon oxide, silicon nitride, silicon carbide or metal nitride such as titanium nitride or tantalum nitride) 602 followed by a photoresist layer, lithographic definition of areas of photoresist to remove and the wet chemical and/or plasma etching of exposed mask regions. Selective removal of the photoresist by chemical and/or plasma etching may then allow for the patterning of the underlying III-V layer using the mask 602. Mask 602 may subsequently be removed during a later step using wet chemical or plasma etching or chemical mechanical polishing.
  • hard mask material such as but not limited to a silicon oxide, silicon nitride, silicon carbide or metal nitride such as titanium nitride or tantalum nitride
  • Fig. 7 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments.
  • assembly 700 includes substrate 102, p-fype II1-V semiconductor region 104, substrate surface 402, and mask 602.
  • P-type III-V semiconductor region 104 may be an epitaxially grown MOCVD thin film layer resulting from the reaction of precursor molecules described in reference to Figs. 9A-9H,
  • Fig. 8 illustrates a diagram of an example semiconductor manufacturing equipment, according to some embodiments.
  • equipment 800 includes chamber 802, substrate 102, pedestal 804, temperature control 806, pressure control 808, precursor control 810 and byproduct control 812.
  • chamber 802 contains the reactions of MOCVD and is made of material that does not react with the chemicals being used. In some embodiments, chamber 802 must withstand high temperatures.
  • Pedestal 804 may be present to support substrate 102.
  • pedestal 804 is a source of heat energy in chamber 802.
  • Temperature control 806 may control the temperature within chamber 802. In some embodiments, temperature control 806 may control air temperature within chamber 802 and'Or heat energy provided to pedestal 804. In some embodiments, temperature control 806 may provide a temperature in chamber 802 of between about 350 and 1300 degrees Celsius during a MOCVD process.
  • Pressure control 808 may control the pressure within chamber 802. In some embodiments, pressure control 808 may pro vide a pressure in chamber 802 of between about 100 and 700 Torr during a MOCVD process.
  • Precursor control 810 may introduce precursor molecules proximate to a surface of substrate 102, In some embodiments, precursor control 810 may introduce one or more precursors discussed in reference to Figs. 9A-9H.
  • Byproduct control 812 may contain MOCVD reaction byproducts. In some embodiments, byproduct control 812 may contain hydrocarbon and organo-amine reaction byproducts.
  • Figs. 9A-9H illustrate example p-dopant precursor molecules for III-V semiconductor devices, according to some embodiments.
  • Fig. 9A depicts precursor molecule 902, which may represent magnesium
  • molecule 902 may be able to provide magnesium atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process,
  • Fig. 93B depicts precursor molecule 904, which may represent an amine stabilized dialkylmagnesium, where M is Mg.
  • molecule 904 may be able to provide magnesium atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process.
  • Precursor molecule 904 may represent an amine stabilized dialkylzinc, where M is Zn.
  • molecule 904 may be able to provide zinc atoms as p- dopants in a III-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process.
  • Fig. 9C depicts precursor molecule 906, which may represent a phosphine stabilized diethylmagesium, where M is Mg and L is a phosphine.
  • molecule 906 may be able to provide magnesium atoms as p-dopants in a TTT-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process.
  • Precursor molecule 906 may represent a carbene stabilized diethylmagesium, where M is Mg and L is a carbene.
  • molecule 906 may be able to provide magnesium atoms as p-dopants in a III-V
  • Precursor molecule 906 may represent a phosphine stabilized diethylzinc, where M is Zn and L is a phosphine. As such, molecule 906 may be able to provide zinc atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process. Precursor molecule 906 may represent a carbene stabilized diethylzinc, where M is Zn and L is a carbene.
  • molecule 906 may be able to provide zinc atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process. While reference may be made to "a phosphine" and "a carbene,” it should be noted that any type of phosphine or carbene may be suitable for these embodiments.
  • a phosphine may include phosphine or also include trialkylphosphines such as trimethylphosphine and triethylphospine, among others.
  • Fig. 9D depicts precursor molecule 908, which may represent an N- heterocyclic carbene trimethylgallium adduct where R is H or an alkyl or aryl group. As such, molecule 908 may be able to provide carbon atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 300, as part of a MOCVD process.
  • Fig. 9E depicts precursor molecule 910, which may represent eta-5 pentamethylcyclopentadienylgallium. As such, molecule 910 may be able to provide carbon atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 300, as part of a MOCVD process.
  • Fig. 9F depicts precursor molecule 912, which may represent an eta-1 cyclopentadienyldimethylgallium trialkylarsine adduct where R is H or an alkyl or aryl group.
  • molecule 912 may be able to provide carbon atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 300, as part of a MOCVD process.
  • Fig. 9G depicts precursor molecule 914, which may represent a tris eta-1 cyclopentadienylgallium trialkylarsine adduct where R is H or an alkyl or aryl group.
  • molecule 914 may be able to provide carbon atoms as p-dopants in a III-V
  • semiconductor lattice for example p-type lattice 300, as part of a MOCVD process.
  • Fig. 9H depicts precursor molecule 916, which may represent tris eta-1 cyclopentadienylgallium where R is H or an alkyl or aryl group.
  • molecule 916 may be able to provide carbon atoms as p-dopants in a III-V semiconductor lattice, for example p- type lattice 300, as part of a MOCVD process.
  • Fig. 10 illustrates a flowchart of a method of forming a semiconductor device, in accordance with some embodiments.
  • the blocks in the flowchart with reference to Fig. 10 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 10 are optional in accordance with certain embodiments.
  • the numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.
  • Method 1000 begins with receiving (1002) a semiconductor substrate 102.
  • semiconductor substrate 102 comprises III-V semiconductor material, such as GaAs.
  • material is removed (1004) from substrate surface 402 to create a recessed surface 502, as necessary.
  • protective mask 602 is formed (1006) on portions of substrate 102 to prevent MOCVD growth.
  • precursor molecules such as one or more of 902-916 are introduced (1008) proximate to a surface of substrate 102, for example recessed surface 502 in chamber 802, by precursor control 810.
  • the method continues with controlling (1010) temperature and pressure in chamber 802, for example by temperature control 806 and pressure control 808, respectively, to facilitate MOCVD reactions leading to epitaxial growth of p-type III-V semiconductor region 104.
  • a temperature may be provided in chamber 802 of between about 350 and 1300 degrees Celsius.
  • a pressure may be provided in chamber 802 of between about 100 and 700 Torr.
  • MOCVD reaction byproducts are contained (1012), for example by byproduct control 812.
  • additional regions are created (1014) to form the semiconductor device.
  • n-type drain 106, gate 108 and gate oxide 110 are formed to create device 100.
  • Fig. 11 illustrates a smart device or a computer system or a SoC (System-on-
  • computing device 1100 which includes a semiconductor device, according to some embodiments.
  • computing device 1100 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1100.
  • one or more components of computing device 1100 for example processor 1110 and/or memory subsystem 1160, include devices having p-type III-V semiconductor regions as described above.
  • the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals.
  • the transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices.
  • MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here.
  • a TFET device on the other hand, has asymmetric Source and Drain terminals.
  • Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, etc. may be used without departing from the scope of the disclosure.
  • computing device 1100 includes a first processor 1110.
  • the various embodiments of the present disclosure may also comprise a network interface within 1 170 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.
  • a network interface within 1 170 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.
  • processor 1 110 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means.
  • the processing operations performed by processor 1 1 10 include the execution of an operating platform or operating system on which applications and/or device functions are executed.
  • the processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1 100 to another device.
  • the processing operations may also include operations related to audio I/O and/or display I/O.
  • computing device 1100 includes audio subsystem 1 120, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1100, or connected to the computing device 1 100. In one embodiment, a user interacts with the computing device 1100 by providing audio commands that are received and processed by processor 1 1 10.
  • audio subsystem 1 120 represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1100, or connected to the computing device 1 100. In one embodiment, a user interacts with the computing device 1100 by providing audio commands that are received and processed by processor 1 1 10.
  • Display subsystem 1 130 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1 100.
  • Display subsystem 1 130 includes display interface 1132, which includes the particular screen or hardware device used to provide a display to a user.
  • display interface 1132 includes logic separate from processor 11 10 to perform at least some processing related to the display.
  • display subsystem 1 130 includes a touch screen (or touch pad) device that provides both output and input to a user.
  • I/O controller 1140 represents hardware devices and software components related to interaction with a user.
  • I/O controller 1 140 is operable to manage hardware that is part of audio subsystem 1120 and/or display subsystem 1 130.
  • I/O controller 1140 illustrates a connection point for additional devices that connect to computing device 1100 through which a user might interact with the system.
  • devices that can be attached to the computing device 1100 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
  • I/O controller 1140 can interact with audio subsystem
  • display subsystem 1130 For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1100. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1130 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1140. There can also be additional buttons or switches on the computing device 1100 to provide I/O functions managed by I/O controller 1140.
  • I/O controller 1140 manages devices such as
  • the input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
  • computing device 1100 includes power management 1150 that manages battery power usage, charging of the battery, and features related to power saving operation.
  • Memory subsystem 1160 includes memory devices for storing information in computing device 1100. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1160 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1100.
  • the machine-readable medium may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions.
  • a computer program e.g., BIOS
  • BIOS BIOS
  • a remote computer e.g., a server
  • a requesting computer e.g., a client
  • a communication link e.g., a modem or network connection
  • Connectivity 1170 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1100 to communicate with external devices.
  • the computing device 1100 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.
  • Connectivity 1170 can include multiple different types of connectivity.
  • the computing device 1100 is illustrated with cellular connectivity 1172 and wireless connectivity 1174.
  • Cellular connectivity 1172 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards.
  • Wireless connectivity (or wireless interface) 1174 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.
  • Peripheral connections 1180 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1100 could both be a peripheral device ("to" 1182) to other computing devices, as well as have peripheral devices ("from” 1184) connected to it.
  • the computing device 1100 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1100. Additionally, a docking connector can allow computing device 1100 to connect to certain peripherals that allow the computing device 1100 to control content output, for example, to audiovisual or other systems.
  • the computing device 1100 can make peripheral connections 1680 via common or standards-based connectors.
  • Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.
  • USB Universal Serial Bus
  • MDP MiniDisplayPort
  • HDMI High Definition Multimedia Interface
  • Firewire or other types.
  • an apparatus comprising: a substrate comprising III-V semiconductor material; and a p-type III-V semiconductor region on the substrate, wherein the p-type III-V semiconductor region comprises p-dopant atoms substantially uniformly present in a crystal lattice at a concentration of about 5 x 10 19 atoms»cm "3 , and wherein the p- dopant atoms comprises one or more atoms chosen from the group consisting of: magnesium, zinc, and carbon.
  • the p-dopant atoms comprise magnesium
  • the p-type semiconductor region comprises a metalorganic chemical vapour deposition (MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: magnesium ⁇ , ⁇ -dimethylaminodiboronate, an amine stabilized dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
  • MOCVD metalorganic chemical vapour deposition
  • the p-dopant atoms comprise zinc
  • the p- type semiconductor region comprises a metalorganic chemical vapour deposition (MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc.
  • MOCVD metalorganic chemical vapour deposition
  • the p-dopant atoms comprise carbon, and wherein the p-type semiconductor region comprises a metalorganic chemical vapour deposition
  • MOCVD metal-organic chemical vapor deposition
  • the III-V semiconductor material comprises GaAs.
  • the p-type III-V semiconductor region comprises a source region of a tunnel field effect transistor (TFET).
  • TFET tunnel field effect transistor
  • a method comprising: introducing precursor molecules proximate to a substrate surface; and growing a p-type III-V semiconductor region through chemical reaction of the precursor molecules, wherein the p-type III-V
  • semiconductor region comprises p-dopant atoms substantially uniformly present in a crystal lattice at a concentration of about 5 x 10 19 atoms»cm "3 .
  • a precursor molecule is chosen from the group consisting of: magnesium N,N-dimethylaminodiboronate, an amine stabilized dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
  • a precursor molecule is chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc.
  • a precursor molecule is chosen from the group consisting of: an N-heterocyclic carbene trimethylgallium adduct, eta-5 pentamethylcyclopentadienylgallium, an eta-1 cyclopentadienyldimethylgallium
  • trialkylarsine adduct a tris eta-1 cyclopentadienylgallium trialkylarsine adduct, and tris eta-1 cyclopentadienylgallium.
  • a method comprising: performing a metalorganic chemical vapour deposition (MOCVD) to form a p-type III-V semiconductor region on a substrate surface, wherein performing the MOCVD comprises reacting a precursor molecule comprising magnesium or zinc, wherein the precursor molecule has a thermal stability and a volatility to allow suitable diffusion prior to dissociation of molecular components during the MOCVD process.
  • MOCVD metalorganic chemical vapour deposition
  • the precursor molecule is chosen from the group consisting of: magnesium N,N-dimethylaminodiboronate, an amine stabilized
  • dialkylmagnesium dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
  • the precursor molecule is chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc.
  • providing a temperature of about 350 to 1300 degrees C. removing semiconductor material from a substrate surface and forming the p-type III-V semiconductor region in a recessed area.
  • a method comprising: performing a metalorganic chemical vapour deposition (MOCVD) to form a p-type III-V semiconductor region on a substrate surface, wherein performing the MOCVD comprises reacting a precursor molecule comprising carbon bonded to a group 13 element.
  • MOCVD metalorganic chemical vapour deposition
  • a precursor is chosen from the group consisting of: an
  • N-heterocyclic carbene trimethylgallium adduct, eta-5 pentamethylcyclopentadienylgallium, an eta-1 cyclopentadienyldimethylgallium trialkylarsine adduct, a tris eta-1 cyclopentadienylgallium trialkylarsine adduct, and tris eta-1 cyclopentadienylgallium.
  • a pressure of about 100 to 700 Torr is provided.
  • a system comprising: a display subsystem; a wireless communication interface; and an integrated circuit device, the integrated circuit device comprising: a substrate comprising III-V semiconductor material; and a p-type III-V semiconductor region on the substrate, wherein the p-type III-V semiconductor region comprises p-dopant atoms substantially uniformly present in a crystal lattice at a
  • the p-dopant atoms comprises one or more atoms chosen from the group consisting of: magnesium, zinc, and carbon.
  • the p-dopant atoms comprise magnesium, and wherein the p-type semiconductor region comprises a metalorganic chemical vapour deposition
  • MOCVD metal-organic chemical vapor deposition
  • the p-dopant atoms comprise zinc
  • the p- type semiconductor region comprises a metalorganic chemical vapour deposition (MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc.
  • MOCVD metalorganic chemical vapour deposition
  • the p-dopant atoms comprise carbon, and wherein the p-type semiconductor region comprises a metalorganic chemical vapour deposition
  • MOCVD metal-organic chemical vapor deposition
  • the III-V semiconductor material comprises GaAs.
  • the p-type III-V semiconductor region comprises a source region of a tunnel field effect transistor (TFET).
  • TFET tunnel field effect transistor
  • reaction chamber for performing metalorganic chemical vapour deposition comprising: means for introducing precursor molecules proximate to a substrate surface; and means for growing a p-type III-V
  • the p- type III-V semiconductor region comprises p-dopant atoms substantially uniformly present in a crystal lattice at a concentration of about 5 x 10 19 atoms»cm "3 .
  • the means for introducing precursor molecules comprises means for introducing a precursor molecule chosen from the group consisting of: magnesium N,N-dimethylaminodiboronate, an amine stabilized dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
  • the means for introducing precursor molecules comprises means for introducing a precursor molecule chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc.
  • the means for introducing precursor molecules comprises means for introducing a precursor molecule chosen from the group consisting of: an N-heterocyclic carbene trimethylgallium adduct, eta-5
  • means are further provided to provide a pressure of about 100 to 700 Torr. In some embodiments, means are further provided to provide a temperature of about 350 to 1300 degrees C.

Abstract

Apparatus and methods are provided which utilize p-dopant precursors to form highly doped p-type III-V semiconductor regions. In some embodiments, performing metalorganic chemical vapor deposition (MOCVD) comprises reacting a precursor molecule comprising carbon bonded to a group 13 element. In some embodiments, performing the MOCVD comprises reacting a precursor molecule comprising magnesium or zinc, wherein the precursor molecule has a thermal stability and a volatility to allow suitable diffusion prior to dissociation of molecular components during the MOCVD process. Other embodiments are also disclosed and claimed.

Description

P-DoPANT PRECURSORS FOR III- V SEMICONDUCTOR DEVICES
BACKGROUND
[0001] As semiconductor devices, such as transistors, have continued to get smaller, power savings has become increasingly important. One idea for low power switching is the tunnel field effect transistor (TFET), which has the potential for steep junctions of less than 60mV per decade of current. An essential feature of a TFET is the inclusion of a highly p- doped source region. Placing free p-dopant atoms in a thin film layer growth, however, can lead to undesirable diffusion as the p-dopant atoms are not tightly bound within the crystal lattice.
BRIEF DESCRIPTION OF THE DRAWINGS
[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.
[0003] Fig. 1 illustrates a cross-sectional view of an example semiconductor device, according to some embodiments,
[0004] Fig. 2 illustrates an atomic composition of an example p-type III-V semiconductor region, according to some embodiments,
[0005] Fig. 3 illustrates an atomic composition of an example p-type III-V semiconductor region, according to some embodiments,
[0006] Fig. 4 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments,
[0007] Fig. 5 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments,
[0008] Fig. 6 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments,
[0009] Fig. 7 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments,
[0010] Fig, 8 illustrates a diagram of an example semiconductor manufacturing equipment, according to some embodiments,
[0011] Figs. 9A-9H illustrate example p-dopant precursor molecules for III-V semiconductor devices, according to some embodiments, [0012] Fig. 10 illustrates a flowchart of a method of forming a semiconductor device, in accordance with some embodiments, and
[0013] Fig. 11 illustrates a smart device or a computer system or a SoC (System-on-
Chip) which includes a semiconductor device, according to some embodiments.
DETAILED DESCRIPTION
[0014] P-dopant precursors for III-V semiconductor devices are generally presented.
In this regard, embodiments of the present invention enable highly doped p-type III-V semiconductor regions that previously may have been more difficult or impossible to achieve due to diffusion of p-dopant atoms that are not tightly bound within the crystal lattice. One skilled in the art would appreciate that these highly doped regions may enable steeper junctions with lower switching voltages and lower leakage currents.
[0015] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.
[0016] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."
[0017] Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
[0018] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms "left," "right/' "front,'' "hack," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.
[0019] Fig. 1 illustrates a cross-sectional view of an example semiconductor device, according to some embodiments. As shown, device 100 includes substrate 102, p-type source 104, n-type drain 106, gate 108, gate oxide 110 and intrinsic channel 112. While a tunnel FET (TFET) such as device 100 can benefit from a highly doped p-type III-V semiconductor region, for example p-type source 104, as described in more detail hereinafter, other types of semiconductor devices can benefit from teachings of the present invention as well, including, but not limited to, diodes, transistors, solar cells, and sensors.
[0020] P-type source 104 can be formed from a MOCVD thin film epitaxial growth using precursor molecules described in more detail hereinafter. While shown as being a recessed region, p-type source 104 can be a raised source, a fin, or any other configuration.
[0021] Fig. 2 illustrates an atomic composition of an example p-type III-V semiconductor region, according to some embodiments. As shown, p-type lattice 200 includes group 13 atoms 202, group 15 atoms 204, single bonds 206, dopants 208 and holes 210.
[0022] While not drawn to scale, p-type lattice 200 represents the product of a metalorganic chemical vapor deposition (MOCVD) wherein precursor molecules with appropriate thermal stability and volatility have been suitably diffused prior to dissociation of molecular components such that dopants 208 are substantially uniformly present in p-type lattice 200. In some embodiments, dopants 208 are present in p-type lattice 200 at a concentration of about 5 x 1019 atoms»cm"3.
[0023] While group 13 atoms 202, such as Ga, and group 15 atoms 204, such as As, generally share two valence electrons as single bonds 206, dopants 208 may replace some group 13 atoms 202 in p-type lattice 200. Where dopants 208 are atoms with two valence electrons, such as Zn or Mg, for example, instead of the three valence electrons of the replaced group 13 atom 202, this leads to the presence of holes 210.
[0024] Fig. 3 illustrates an atomic composition of an example p-type III-V semiconductor region, according to some embodiments. As shown, p-type lattice 300 includes group 13 atoms 302, group 15 atoms 304, single bonds 306, dopants 308 and holes [0025] While not drawn to scale, p-type lattice 300 represents the product of a metalorganic chemical vapor deposition (MOCVD) including precursor molecules with dopants 308 prebound to group 13 atoms 302 such that dopants 308 are substantially uniformly present in p-type lattice 300. In some embodiments, dopants 308 are present in p- type lattice 300 at a concentration of about 5 x 1019 atoms»cm"3.
[0026] While group 13 atoms 302, such as Ga, and group 15 atoms 304, such as As, generally share two valence electrons as single bonds 306, dopants 308 may replace some group 15 atoms 304 in p-type lattice 300. Where dopants 308 are atoms with four valence electrons, such as C, for example, instead of the five valence electrons of the replaced group 15 atom 304, this leads to the presence of holes 310.
[0027] Fig. 4 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments. As shown, assembly 400 includes semiconductor substrate 102 and substrate surface 402.
[0028] In some embodiments, substrate 102 comprises at least one layer of undoped
III-V semiconductor, such as GaAs, InGaAs, BP, AlSb, etc. Substrate 102 may be composed of one or more III-V semiconductor material layers on top of another semiconductor material such as silicon.
[0029] Fig. 5 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments. As shown, assembly 500 includes substrate 102, substrate surface 402, and recessed surface 502.
[0030] Recessed surface 502 may be created below substrate surface 402 by removing material from substrate 102 by various means, including chemical, mechanical or laser.
[0031] Fig. 6 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments. As shown, assembly 600 includes substrate 102, recessed surface 502 and mask 602.
[0032] Mask 602 may be formed on select surfaces of substrate 102 to prevent
MOCVD thin film growth. While in some embodiments, selective growth of the mask 602 may occur after formation of recessed surface 502, in other embodiments different process steps may be utilized. For example, recessed surface 502 may be made by first depositing a blanket layer of hard mask material (such as but not limited to a silicon oxide, silicon nitride, silicon carbide or metal nitride such as titanium nitride or tantalum nitride) 602 followed by a photoresist layer, lithographic definition of areas of photoresist to remove and the wet chemical and/or plasma etching of exposed mask regions. Selective removal of the photoresist by chemical and/or plasma etching may then allow for the patterning of the underlying III-V layer using the mask 602. Mask 602 may subsequently be removed during a later step using wet chemical or plasma etching or chemical mechanical polishing.
[0033] Fig. 7 illustrates a cross-sectional view of a manufacturing step of a semiconductor device, according to some embodiments. As shown, assembly 700 includes substrate 102, p-fype II1-V semiconductor region 104, substrate surface 402, and mask 602.
[0034] P-type III-V semiconductor region 104 may be an epitaxially grown MOCVD thin film layer resulting from the reaction of precursor molecules described in reference to Figs. 9A-9H,
[0035] Fig. 8 illustrates a diagram of an example semiconductor manufacturing equipment, according to some embodiments. As shown, equipment 800 includes chamber 802, substrate 102, pedestal 804, temperature control 806, pressure control 808, precursor control 810 and byproduct control 812.
[0036] In some embodiments, chamber 802 contains the reactions of MOCVD and is made of material that does not react with the chemicals being used. In some embodiments, chamber 802 must withstand high temperatures.
[0037] Pedestal 804 may be present to support substrate 102. In some embodiments, pedestal 804 is a source of heat energy in chamber 802.
[0038] Temperature control 806 may control the temperature within chamber 802. In some embodiments, temperature control 806 may control air temperature within chamber 802 and'Or heat energy provided to pedestal 804. In some embodiments, temperature control 806 may provide a temperature in chamber 802 of between about 350 and 1300 degrees Celsius during a MOCVD process.
[0039] Pressure control 808 may control the pressure within chamber 802. In some embodiments, pressure control 808 may pro vide a pressure in chamber 802 of between about 100 and 700 Torr during a MOCVD process.
[0040] Precursor control 810 may introduce precursor molecules proximate to a surface of substrate 102, In some embodiments, precursor control 810 may introduce one or more precursors discussed in reference to Figs. 9A-9H.
[0041] Byproduct control 812 may contain MOCVD reaction byproducts. In some embodiments, byproduct control 812 may contain hydrocarbon and organo-amine reaction byproducts. [0042] Figs. 9A-9H illustrate example p-dopant precursor molecules for III-V semiconductor devices, according to some embodiments.
[0043] Fig. 9A depicts precursor molecule 902, which may represent magnesium
Ν,Ν-dimethylaminodiboronate. As such, molecule 902 may be able to provide magnesium atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process,
[0044] Fig. 93B depicts precursor molecule 904, which may represent an amine stabilized dialkylmagnesium, where M is Mg. As such, molecule 904 may be able to provide magnesium atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process. Precursor molecule 904 may represent an amine stabilized dialkylzinc, where M is Zn. As such, molecule 904 may be able to provide zinc atoms as p- dopants in a III-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process.
[0045] Fig. 9C depicts precursor molecule 906, which may represent a phosphine stabilized diethylmagesium, where M is Mg and L is a phosphine. As such, molecule 906 may be able to provide magnesium atoms as p-dopants in a TTT-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process. Precursor molecule 906 may represent a carbene stabilized diethylmagesium, where M is Mg and L is a carbene. As such, molecule 906 may be able to provide magnesium atoms as p-dopants in a III-V
semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process. Precursor molecule 906 may represent a phosphine stabilized diethylzinc, where M is Zn and L is a phosphine. As such, molecule 906 may be able to provide zinc atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process. Precursor molecule 906 may represent a carbene stabilized diethylzinc, where M is Zn and L is a carbene. As such, molecule 906 may be able to provide zinc atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 200, as part of a MOCVD process. While reference may be made to "a phosphine" and "a carbene," it should be noted that any type of phosphine or carbene may be suitable for these embodiments. For example, a phosphine may include phosphine or also include trialkylphosphines such as trimethylphosphine and triethylphospine, among others.
[0046] Fig. 9D depicts precursor molecule 908, which may represent an N- heterocyclic carbene trimethylgallium adduct where R is H or an alkyl or aryl group. As such, molecule 908 may be able to provide carbon atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 300, as part of a MOCVD process. [0047] Fig. 9E depicts precursor molecule 910, which may represent eta-5 pentamethylcyclopentadienylgallium. As such, molecule 910 may be able to provide carbon atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 300, as part of a MOCVD process.
[0048] Fig. 9F depicts precursor molecule 912, which may represent an eta-1 cyclopentadienyldimethylgallium trialkylarsine adduct where R is H or an alkyl or aryl group. As such, molecule 912 may be able to provide carbon atoms as p-dopants in a III-V semiconductor lattice, for example p-type lattice 300, as part of a MOCVD process.
[0049] Fig. 9G depicts precursor molecule 914, which may represent a tris eta-1 cyclopentadienylgallium trialkylarsine adduct where R is H or an alkyl or aryl group. As such, molecule 914 may be able to provide carbon atoms as p-dopants in a III-V
semiconductor lattice, for example p-type lattice 300, as part of a MOCVD process.
[0050] Fig. 9H depicts precursor molecule 916, which may represent tris eta-1 cyclopentadienylgallium where R is H or an alkyl or aryl group. As such, molecule 916 may be able to provide carbon atoms as p-dopants in a III-V semiconductor lattice, for example p- type lattice 300, as part of a MOCVD process.
[0051] Fig. 10 illustrates a flowchart of a method of forming a semiconductor device, in accordance with some embodiments. Although the blocks in the flowchart with reference to Fig. 10 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 10 are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.
[0052] Method 1000 begins with receiving (1002) a semiconductor substrate 102. In some embodiments, semiconductor substrate 102 comprises III-V semiconductor material, such as GaAs. Next, material is removed (1004) from substrate surface 402 to create a recessed surface 502, as necessary.
[0053] Then, protective mask 602 is formed (1006) on portions of substrate 102 to prevent MOCVD growth. Next, precursor molecules, such as one or more of 902-916 are introduced (1008) proximate to a surface of substrate 102, for example recessed surface 502 in chamber 802, by precursor control 810. [0054] The method continues with controlling (1010) temperature and pressure in chamber 802, for example by temperature control 806 and pressure control 808, respectively, to facilitate MOCVD reactions leading to epitaxial growth of p-type III-V semiconductor region 104. In some embodiments, a temperature may be provided in chamber 802 of between about 350 and 1300 degrees Celsius. In some embodiments, a pressure may be provided in chamber 802 of between about 100 and 700 Torr. Next, one or more MOCVD reaction byproducts are contained (1012), for example by byproduct control 812. Finally, to the extent they are necessary, additional regions are created (1014) to form the semiconductor device. In some embodiments, n-type drain 106, gate 108 and gate oxide 110 are formed to create device 100.
[0055] Fig. 11 illustrates a smart device or a computer system or a SoC (System-on-
Chip) 1100 which includes a semiconductor device, according to some embodiments. In some embodiments, computing device 1100 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1100. In some embodiments, one or more components of computing device 1100, for example processor 1110 and/or memory subsystem 1160, include devices having p-type III-V semiconductor regions as described above.
[0056] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.
[0057] In some embodiments, computing device 1100 includes a first processor 1110.
The various embodiments of the present disclosure may also comprise a network interface within 1 170 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.
[0058] In one embodiment, processor 1 110 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1 1 10 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1 100 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.
[0059] In one embodiment, computing device 1100 includes audio subsystem 1 120, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1100, or connected to the computing device 1 100. In one embodiment, a user interacts with the computing device 1100 by providing audio commands that are received and processed by processor 1 1 10.
[0060] Display subsystem 1 130 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1 100. Display subsystem 1 130 includes display interface 1132, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1132 includes logic separate from processor 11 10 to perform at least some processing related to the display. In one embodiment, display subsystem 1 130 includes a touch screen (or touch pad) device that provides both output and input to a user.
[0061] I/O controller 1140 represents hardware devices and software components related to interaction with a user. I/O controller 1 140 is operable to manage hardware that is part of audio subsystem 1120 and/or display subsystem 1 130. Additionally, I/O controller 1140 illustrates a connection point for additional devices that connect to computing device 1100 through which a user might interact with the system. For example, devices that can be attached to the computing device 1100 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
[0062] As mentioned above, I/O controller 1140 can interact with audio subsystem
1120 and/or display subsystem 1130. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1100. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1130 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1140. There can also be additional buttons or switches on the computing device 1100 to provide I/O functions managed by I/O controller 1140.
[0063] In one embodiment, I/O controller 1140 manages devices such as
accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1100. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
[0064] In one embodiment, computing device 1100 includes power management 1150 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1160 includes memory devices for storing information in computing device 1100. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1160 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1100.
[0065] Elements of embodiments are also provided as a machine-readable medium
(e.g., memory 1160) for storing the computer-executable instructions. The machine-readable medium (e.g., memory 1160) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection). [0066] Connectivity 1170 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1100 to communicate with external devices. The computing device 1100 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.
[0067] Connectivity 1170 can include multiple different types of connectivity. To generalize, the computing device 1100 is illustrated with cellular connectivity 1172 and wireless connectivity 1174. Cellular connectivity 1172 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1174 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.
[0068] Peripheral connections 1180 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1100 could both be a peripheral device ("to" 1182) to other computing devices, as well as have peripheral devices ("from" 1184) connected to it. The computing device 1100 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1100. Additionally, a docking connector can allow computing device 1100 to connect to certain peripherals that allow the computing device 1100 to control content output, for example, to audiovisual or other systems.
[0069] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1100 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.
[0070] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.
[0071] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive
[0072] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.
[0073] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.
[0074] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process. [0075] For example, an apparatus is provided comprising: a substrate comprising III-V semiconductor material; and a p-type III-V semiconductor region on the substrate, wherein the p-type III-V semiconductor region comprises p-dopant atoms substantially uniformly present in a crystal lattice at a concentration of about 5 x 1019 atoms»cm"3, and wherein the p- dopant atoms comprises one or more atoms chosen from the group consisting of: magnesium, zinc, and carbon.
[0076] In some embodiments, the p-dopant atoms comprise magnesium, and wherein the p-type semiconductor region comprises a metalorganic chemical vapour deposition (MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: magnesium Ν,Ν-dimethylaminodiboronate, an amine stabilized dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
[0077] In some embodiments, the p-dopant atoms comprise zinc, and wherein the p- type semiconductor region comprises a metalorganic chemical vapour deposition (MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc.
[0078] In some embodiments, the p-dopant atoms comprise carbon, and wherein the p-type semiconductor region comprises a metalorganic chemical vapour deposition
(MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: an N-heterocyclic carbene trimethylgallium adduct, eta-5
pentamethylcyclopentadienylgallium, an eta-1 cyclopentadienyldimethylgallium
trialkylarsine adduct, a tris eta-1 cyclopentadienylgallium trialkylarsine adduct, and tris eta-1 cyclopentadienylgallium. In some embodiments, the III-V semiconductor material comprises GaAs. In some embodiments, the p-type III-V semiconductor region comprises a source region of a tunnel field effect transistor (TFET).
[0079] In another example, a method is provided comprising: introducing precursor molecules proximate to a substrate surface; and growing a p-type III-V semiconductor region through chemical reaction of the precursor molecules, wherein the p-type III-V
semiconductor region comprises p-dopant atoms substantially uniformly present in a crystal lattice at a concentration of about 5 x 1019 atoms»cm"3.
[0080] In some embodiments, a precursor molecule is chosen from the group consisting of: magnesium N,N-dimethylaminodiboronate, an amine stabilized dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
[0081] In some embodiments, a precursor molecule is chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc. In some embodiments, a precursor molecule is chosen from the group consisting of: an N-heterocyclic carbene trimethylgallium adduct, eta-5 pentamethylcyclopentadienylgallium, an eta-1 cyclopentadienyldimethylgallium
trialkylarsine adduct, a tris eta-1 cyclopentadienylgallium trialkylarsine adduct, and tris eta-1 cyclopentadienylgallium.
[0082] In another example, a method is provided comprising: performing a metalorganic chemical vapour deposition (MOCVD) to form a p-type III-V semiconductor region on a substrate surface, wherein performing the MOCVD comprises reacting a precursor molecule comprising magnesium or zinc, wherein the precursor molecule has a thermal stability and a volatility to allow suitable diffusion prior to dissociation of molecular components during the MOCVD process.
[0083] In some embodiments, the precursor molecule is chosen from the group consisting of: magnesium N,N-dimethylaminodiboronate, an amine stabilized
dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
[0084] In some embodiments, the precursor molecule is chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc. In some embodiments, providing a temperature of about 350 to 1300 degrees C. In some embodiments, removing semiconductor material from a substrate surface and forming the p-type III-V semiconductor region in a recessed area. In some embodiments, forming a mask material on portions of the substrate surface to prevent MOCVD.
[0085] In another example, a method is provided comprising: performing a metalorganic chemical vapour deposition (MOCVD) to form a p-type III-V semiconductor region on a substrate surface, wherein performing the MOCVD comprises reacting a precursor molecule comprising carbon bonded to a group 13 element.
[0086] In some embodiments, a precursor is chosen from the group consisting of: an
N-heterocyclic carbene trimethylgallium adduct, eta-5 pentamethylcyclopentadienylgallium, an eta-1 cyclopentadienyldimethylgallium trialkylarsine adduct, a tris eta-1 cyclopentadienylgallium trialkylarsine adduct, and tris eta-1 cyclopentadienylgallium. In some embodiments, a pressure of about 100 to 700 Torr is provided.
[0087] In another example a system is provided comprising: a display subsystem; a wireless communication interface; and an integrated circuit device, the integrated circuit device comprising: a substrate comprising III-V semiconductor material; and a p-type III-V semiconductor region on the substrate, wherein the p-type III-V semiconductor region comprises p-dopant atoms substantially uniformly present in a crystal lattice at a
concentration of about 5 x 1019 atoms»cm"3, and wherein the p-dopant atoms comprises one or more atoms chosen from the group consisting of: magnesium, zinc, and carbon.
[0088] In some embodiments, the p-dopant atoms comprise magnesium, and wherein the p-type semiconductor region comprises a metalorganic chemical vapour deposition
(MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: magnesium Ν,Ν-dimethylaminodiboronate, an amine stabilized dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
[0089] In some embodiments, the p-dopant atoms comprise zinc, and wherein the p- type semiconductor region comprises a metalorganic chemical vapour deposition (MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc.
[0090] In some embodiments, the p-dopant atoms comprise carbon, and wherein the p-type semiconductor region comprises a metalorganic chemical vapour deposition
(MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: an N-heterocyclic carbene trimethylgallium adduct, eta-5
pentamethylcyclopentadienylgallium, an eta-1 cyclopentadienyldimethylgallium
trialkylarsine adduct, a tris eta-1 cyclopentadienylgallium trialkylarsine adduct, and tris eta-1 cyclopentadienylgallium. In some embodiments, the III-V semiconductor material comprises GaAs. In some embodiments, the p-type III-V semiconductor region comprises a source region of a tunnel field effect transistor (TFET).
[0091] In another example, reaction chamber for performing metalorganic chemical vapour deposition (MOCVD) is provided comprising: means for introducing precursor molecules proximate to a substrate surface; and means for growing a p-type III-V
semiconductor region through chemical reaction of the precursor molecules, wherein the p- type III-V semiconductor region comprises p-dopant atoms substantially uniformly present in a crystal lattice at a concentration of about 5 x 1019 atoms»cm"3.
[0092] In some embodiments, the means for introducing precursor molecules comprises means for introducing a precursor molecule chosen from the group consisting of: magnesium N,N-dimethylaminodiboronate, an amine stabilized dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
[0093] In some embodiments, the means for introducing precursor molecules comprises means for introducing a precursor molecule chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc.
[0094] In some embodiments, the means for introducing precursor molecules comprises means for introducing a precursor molecule chosen from the group consisting of: an N-heterocyclic carbene trimethylgallium adduct, eta-5
pentamethylcyclopentadienylgallium, an eta-1 cyclopentadienyldimethylgallium
trialkylarsine adduct, a tris eta-1 cyclopentadienylgallium trialkylarsine adduct, and tris eta-1 cyclopentadienylgallium. In some embodiments, means are further provided to provide a pressure of about 100 to 700 Torr. In some embodiments, means are further provided to provide a temperature of about 350 to 1300 degrees C.
[0095] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:
1. An apparatus comprising:
a substrate comprising III-V semiconductor material; and
a p-type III-V semiconductor region on the substrate, wherein the p-t pe III-V semiconductor region comprises p-dopant atoms substantially uniformly present in a crystal lattice at a concentration of about 5 x 1019 atoms»cm"3, and wherein the p-dopant atoms comprises one or more atoms chosen from the group consisting of: magnesium, zinc, and carbon.
2. The apparatus of claim 1 , wherein the p-dopant atoms comprise magnesium, and wherein the p-type semiconductor region comprises a metalorganic chemical vapor deposition (MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: magnesium Ν,Ν-dimethylaminodiboronate, an amine stabilized dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
3. The apparatus of claim 1 , wherein the p-dopant atoms comprise zinc, and wherein the p- type semiconductor region comprises a metalorganic chemical vapor deposition
(MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc.
4. The apparatus of claim 1 , wherein the p-dopant atoms comprise carbon, and wherein the p-type semiconductor region comprises a metalorganic chemical vapor deposition (MOCVD) thin film formed in a reaction with a precursor chosen from the group consisting of: an N-heterocyclic carbene trimethylgallium adduct, eta-5
pentamethylcyclopentadienylgallium, an eta-1 cyclopentadienyldimethylgallium trialkylarsine adduct, a tris eta-1 cyclopentadienylgallium trialkylarsine adduct, and tris eta-1 cyclopentadienylgallium.
5. The apparatus according to any one of claims 1 to 4, wherein the III-V semiconductor material comprises GaAs.
6. The apparatus according to any one of claims 1 to 4, wherein the p-type III-V
semiconductor region comprises a source region of a tunnel field effect transistor (TFET).
7. A method comprising:
introducing precursor molecules proximate to a substrate surface; and
growing a p-type III-V semiconductor region through chemical reaction of the precursor molecules, wherein the p-type III-V semiconductor region comprises p-dopant atoms substantially uniformly present in a crystal lattice at a concentration of about 5 x 1019 atoms»cm"3.
8. The method of claim 7, further comprising a precursor molecule is chosen from the group consisting of: magnesium Ν,Ν-dimethylaminodiboronate, an amine stabilized
dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
9. The method of claim 7, further comprising a precursor molecule is chosen from the group consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc.
10. The method of claim 7, further comprising a precursor molecule is chosen from the group consisting of: an N-heterocyclic carbene trimethylgallium adduct, eta-5
pentamethylcyclopentadienylgallium, an eta-1 cyclopentadienyldimethylgallium trialkylarsine adduct, a tris eta-1 cyclopentadienylgallium trialkylarsine adduct, and tris eta-1 cyclopentadienylgallium.
11. The method according to any one of claims 7 to 10, further comprising providing a
pressure of about 100 to 700 Torr.
12. The method according to any one of claims 7 to 10, further comprising providing a
temperature of about 350 to 1300 degrees C.
13. A method comprising:
performing a metalorganic chemical vapor deposition (MOCVD) to form a p-type III-V semiconductor region on a substrate surface, wherein performing the MOCVD comprises reacting a precursor molecule comprising magnesium or zinc, wherein the precursor molecule has a thermal stability and a volatility to allow suitable diffusion prior to dissociation of molecular components during the MOCVD process.
14. The method of claim 13, wherein the precursor molecule is chosen from the group
consisting of: magnesium Ν,Ν-dimethylaminodiboronate, an amine stabilized dialkylmagnesium, a phosphine stabilized diethylmagesium, and a carbene stabilized diethylmagesium.
15. The method of claim 13, wherein the precursor molecule is chosen from the group
consisting of: an amine stabilized dialkylzinc, a phosphine stabilized diethylzinc, and a carbene stabilized diethylzinc.
16. The method of claim 13, further comprising providing a temperature of about 350 to 1300 degrees C.
17. The method of any of claims 13 to 16, further comprising removing semiconductor
material from a substrate surface and forming the p-type III-V semiconductor region in a recessed area.
18. The method of any of claims 13 to 16, further comprising forming a mask material on portions of the substrate surface to prevent MOCVD.
19. A method comprising:
performing a metalorganic chemical vapor deposition (MOCVD) to form a p-type III- V semiconductor region on a substrate surface, wherein performing the MOCVD comprises reacting a precursor molecule comprising carbon bonded to a group 13 element.
20. The method of claim 19, a precursor chosen from the group consisting of: an N- heterocyclic carbene trimethylgallium adduct, eta-5 pentamethylcyclopentadienylgallium, an eta-1 cyclopentadienyldimethylgallium trialkylarsine adduct, a tris eta-1
cyclopentadienylgallium trialkylarsine adduct, and tris eta-1 cyclopentadienylgallium.
21. The method of claim 19, further comprising providing a pressure of about 100 to 700 Torr.
22. The method of claim 21, further comprising providing a temperature of about 350 to 1300 degrees C.
23. The method of any of claims 19 to 22, further comprising containing MOCVD
byproducts.
24. The method of claim 23, wherein the byproducts comprise hydrocarbons or organo- amines.
25. The method of any of claims 19 to 22, further comprising forming an n-type III-V
semiconductor region on the substrate surface.
PCT/US2016/066927 2016-12-15 2016-12-15 P-dopant precursors for iii-v semiconductor devices WO2018111277A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6099903A (en) * 1999-05-19 2000-08-08 Research Foundation Of State University Of New York MOCVD processes using precursors based on organometalloid ligands
KR20080006745A (en) * 2006-07-13 2008-01-17 삼성전자주식회사 Nitride-based semiconducter light emitting device and method of manufacturing the same
KR20150108779A (en) * 2014-03-18 2015-09-30 주식회사 유진테크 머티리얼즈 Organo germanium compounds and method of depositing thin film using them as precursors
US20160071968A1 (en) * 2014-09-08 2016-03-10 International Business Machines Corporation Low external resistance channels in iii-v semiconductor devices
US20160343860A1 (en) * 2014-06-23 2016-11-24 International Business Machines Corporation Silicon-containing, tunneling field-effect transistor including iii-n source

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6099903A (en) * 1999-05-19 2000-08-08 Research Foundation Of State University Of New York MOCVD processes using precursors based on organometalloid ligands
KR20080006745A (en) * 2006-07-13 2008-01-17 삼성전자주식회사 Nitride-based semiconducter light emitting device and method of manufacturing the same
KR20150108779A (en) * 2014-03-18 2015-09-30 주식회사 유진테크 머티리얼즈 Organo germanium compounds and method of depositing thin film using them as precursors
US20160343860A1 (en) * 2014-06-23 2016-11-24 International Business Machines Corporation Silicon-containing, tunneling field-effect transistor including iii-n source
US20160071968A1 (en) * 2014-09-08 2016-03-10 International Business Machines Corporation Low external resistance channels in iii-v semiconductor devices

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