WO2018109930A1 - Doherty amplifier - Google Patents

Doherty amplifier Download PDF

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WO2018109930A1
WO2018109930A1 PCT/JP2016/087584 JP2016087584W WO2018109930A1 WO 2018109930 A1 WO2018109930 A1 WO 2018109930A1 JP 2016087584 W JP2016087584 W JP 2016087584W WO 2018109930 A1 WO2018109930 A1 WO 2018109930A1
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Prior art keywords
terminal
circuit
transmission line
harmonic
amplifier
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PCT/JP2016/087584
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French (fr)
Japanese (ja)
Inventor
末松　憲治
亀田　卓
高木　直
一真 寺嶋
藤井　憲一
坪内　和夫
Original Assignee
株式会社Ｗａｖｅ Ｔｅｃｈｎｏｌｏｇｙ
国立大学法人東北大学
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Priority to PCT/JP2016/087584 priority Critical patent/WO2018109930A1/en
Priority to JP2018556148A priority patent/JP6736024B2/en
Publication of WO2018109930A1 publication Critical patent/WO2018109930A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/534—Transformer coupled at the input of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/537—A transformer being used as coupling element between two amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/541—Transformer coupled at the output of an amplifier

Definitions

  • the present invention relates to a Doherty amplifier that is used in a wireless communication transmitter and has high saturation output power performance and good power efficiency performance during linear operation.
  • a communication signal for high-speed wireless communication has a large PAPR (Peak to Average Power Ratio), and a power amplifier used in the transmitter operates with an average power smaller than a saturated output power. Therefore, in order to suppress the power consumption of the transmitter, a power amplifier with high efficiency in average power is required.
  • a Doherty amplifier proposed by Doherty is prominent (see Non-Patent Document 1, for example).
  • the output power of the power amplifier increases, the size of the transistor used for it increases, and the output impedance of the transistor decreases. Therefore, in a power amplifier having a large output power, the transistor matching circuit requires a high impedance conversion ratio, which causes problems such as narrow band performance and increased matching circuit loss. For this reason, a high-performance Doherty amplifier is desired that has less problems such as narrow band performance and increased matching circuit loss even during high power operation.
  • it is known to apply a balun to a power amplifier see, for example, Patent Document 1).
  • the Doherty amplifier is configured by combining a carrier amplifier 100 that operates in a class AB to a class B and a peak amplifier 101 that operates in a class C, thereby obtaining high performance even during linear operation with a low signal level.
  • a parallel load connection type shown in FIG. 18 and a series load connection type configured in combination with the baluns 102 and 103 shown in FIG. 19 or FIG. 20 have been proposed.
  • a divider 206 is provided on the input side, and ⁇ / 4 lines 20a and 20b and a phase adjustment line 105 are provided on the line.
  • the parallel load connection type configuration generally has a larger impedance conversion ratio when performing output matching of the carrier amplifier 100 and the peak amplifier 101 than the series load connection type configuration, resulting in the configuration of the output matching circuit.
  • problems such as narrow band performance and increased loss of the matching circuit.
  • a series load connection configuration in which the impedance conversion ratio of the matching circuit is smaller than this can be used.
  • Doherty proposed a series load connection type Doherty amplifier configured as shown in FIG.
  • the transistor of the peak amplifier 101 (at that time a vacuum tube) operates on the assumption that the output impedance during linear operation is short-circuited.
  • the transistor of the actual peak amplifier 101 does not short-circuit the output impedance during linear operation, but rather is open. Therefore, this problem can be solved by loading an impedance conversion circuit 104 that converts an open circuit into a short circuit on the output side of the peak amplifier 101 during linear operation as shown in FIG.
  • the phase adjustment line 105 is provided on the input side of the carrier amplifier 100 in accordance with the provision of the impedance conversion circuit 104.
  • the impedance conversion circuit 104 provided on the output side of the peak amplifier 101 is provided so that the impedance condition for expecting the output load side from the carrier amplifier 100 is optimal during linear operation and saturation operation. It is necessary to realize it. For this reason, it is not direct to realize the optimum load impedance condition for the carrier amplifier 100. As a result, there is a problem that it is difficult to obtain the optimum impedance condition.
  • the present invention has been made to solve the above-described problems, and an object thereof is to provide a Doherty amplifier capable of realizing good power efficiency even during linear operation.
  • the present invention provides a Doherty amplifier that distributes an input signal to a first input signal and a second input signal having a phase difference from each other, a carrier amplifier that amplifies the first input signal, and a second input signal.
  • a peak amplifier whose output impedance is open at the time of a small signal operation which is a linear operation, an impedance conversion circuit connected to the output side of the carrier amplifier, and a first amplifier which is amplified by the carrier amplifier and output through the impedance conversion circuit
  • a synthesis circuit composed of a balun for synthesizing one output signal and a second output signal amplified and output by a peak amplifier, and the carrier amplifier is connected to one balanced terminal of the synthesis circuit via an impedance conversion circuit
  • the peak amplifier is connected to the other balanced terminal of the synthesis circuit. Output signal is output.
  • the present invention it is possible to provide a Doherty amplifier capable of realizing good power efficiency even during a linear operation, and thereby it is possible to reduce the power consumption of the wireless transmitter.
  • FIG. 1 is a circuit diagram showing a configuration of a Doherty amplifier according to Embodiment 1 of the present invention.
  • the Doherty amplifier includes a distribution circuit 202 distributes the input signal S1 to the first input signal S2 and the second input signal S3 having a proper phase difference theta d each other, a carrier amplifier 100 for amplifying the first input signal S2, The second input signal S3 is amplified, and a peak amplifier 101 whose output impedance is opened during the small signal operation, an impedance conversion circuit 201 connected to the output side of the carrier amplifier 100, and an impedance conversion amplified by the carrier amplifier 100.
  • the synthesis circuit 200 is configured to synthesize the first output signal S4 output via the circuit 201 and the second output signal S5 amplified and output by the peak amplifier 101.
  • FIG. 2 is a circuit diagram showing a detailed configuration of the synthesis circuit 200 according to the first embodiment.
  • the synthesis circuit 200 is configured using the first coupled transmission line 300 and the second coupled transmission line 310 having a length of 1 ⁇ 4 wavelength with respect to the fundamental frequency f 0 and having the same performance. It is a balun.
  • the first coupled transmission line 300 includes a first transmission line 301 and a second transmission line 302 that are arranged close to each other in parallel.
  • the first transmission line 301 has a first terminal p1 and a second terminal p2, and the second transmission line 302 faces the first terminal p1 and faces the fourth terminal p4 and the second terminal p2, and third.
  • a terminal p3 is provided.
  • the second coupled transmission line 310 includes a third transmission line 311 and a fourth transmission line 312 that are arranged close to each other in parallel.
  • the third transmission line 311 has a fifth terminal p5 and a sixth terminal p6, and the fourth transmission line 312 faces the fifth terminal p5 and faces the eighth terminal p8 and the sixth terminal p6.
  • a terminal p7 is provided.
  • the second terminal p2, the fifth terminal p5, and the sixth terminal p6 are short-circuited to the ground, and the fourth terminal p4 and the seventh terminal p7 are connected to each other.
  • the first terminal p1 forms an unbalanced terminal T1 with the ground, and the third terminal p3 and the eighth terminal p8 form balanced terminals T2 and T3 that are in opposite phases to each other.
  • An example of such a balun is disclosed in Patent Document 1.
  • the output side of the carrier amplifier 100 is connected to one balanced terminal T2 of the synthesis circuit 200 via the impedance conversion circuit 201, and the output side of the peak amplifier 101 is connected to the other balanced terminal T3 of the synthesis circuit 200. .
  • a combined output signal of the first output signal S4 and the second output signal S5 combined by the combining circuit 200 is output from the unbalanced terminal T1.
  • the even-mode characteristic impedance Z oe and the odd-mode characteristic impedance Z oo of the first coupled transmission line 300 and the second coupled transmission line 310 are the same as the output load connected to the unbalanced terminal T1.
  • the impedance Z s and the impedance Z L of the load connected to the balanced terminals T2 and T3 are designed in advance so as to satisfy the relational expression of the following expression (1).
  • the carrier amplifier 100 and the peak amplifier 101 operate in the same manner as a normal push-pull amplifier, and the balanced terminal T2 and the balanced terminal T3 operate as balanced terminals that operate in opposite phases.
  • the impedances Z 2 and Z 3 for which the combined circuit 200 is expected from the balanced terminal T2 and the balanced terminal T3 during the saturation operation are given by the following equation (2) at the time of matching.
  • the impedance Z 2 at the time of linear operation is given by the following equation (4) from the equations (1) to (3).
  • the amplifier in high efficiency as the value of the load impedance Z 1 looking into the load side from the transistor is increased, conversely, as the output power value of the load impedance Z 1 becomes small becomes high.
  • the load impedance Z 1 is increased during linear operation where high efficiency is desired, and the load impedance is controlled according to the power level so that the value of load impedance Z 1 is decreased during saturation operation where large output power is desired.
  • an impedance conversion circuit 201 is provided between the carrier amplifier 100 and the synthesis circuit 200.
  • Such impedance conversion can be realized by using a transmission line or a circuit in which an inductor L and a capacitor C are combined.
  • phase difference theta d between first input signal S2 and the second input signal S3 is provided at the fundamental frequency f 0 so as to satisfy the following equation (5).
  • FIG. 4 to 6 show various configuration examples of the distribution circuit 202.
  • FIG. The distribution circuit shown in FIG. 4 is configured by combining a balun 400 that performs antiphase distribution and a phase adjustment line 401.
  • the distribution circuit shown in FIG. 5 is configured by combining an in-phase distributor 402 such as a Wilson coupler and a phase adjustment line 403.
  • the distribution circuit shown in FIG. 6 is configured using a 90 ° hybrid circuit 404.
  • FIG. 7 shows the drain efficiency with respect to the back-off amount from the saturated output power of the Doherty amplifier according to the first embodiment of the present invention. For the above reasons, the efficiency is high even during linear operation as shown in FIG. Operates as a Doherty amplifier.
  • the series load connection type Doherty amplifier according to the first embodiment of the present invention shown in FIG. 1 differs from the conventional series load connection type Doherty amplifier shown in FIG.
  • the impedance conversion circuit 201 is provided on the output side of the carrier amplifier 100, the optimum impedance condition for expecting the load side from the carrier amplifier 100 during linear operation and saturation operation can be directly and easily controlled. Is possible.
  • the optimum load impedance condition for the linear operation and the saturation operation for the carrier amplifier is directly determined using the impedance conversion circuit provided on the output side of the carrier amplifier.
  • a Doherty amplifier that can be controlled. This makes it possible to easily realize the optimum load impedance condition corresponding to the operation level for the carrier amplifier.
  • FIG. FIG. 8 is a circuit diagram showing the configuration of the Doherty amplifier according to the second embodiment of the present invention.
  • the basic configuration is the same as that of the Doherty amplifier according to the first embodiment shown in FIG. It is. Therefore, the same reference numerals as those in the circuit diagram shown in FIG.
  • FIG. 9 is a circuit diagram showing a detailed configuration of the synthesis circuit 210 used in the second embodiment.
  • the combining circuit 210 shown in FIG. 9 is configured using a coupled transmission line 320 having a length of 1 ⁇ 4 wavelength with respect to the fundamental frequency f 0 and a transmission line 330 having a length of 1 ⁇ 4 wavelength.
  • the coupled transmission line 320 includes a first transmission line 321 and a second transmission line 322 that are arranged close to each other in parallel.
  • the first transmission line 321 has a first terminal p1 and a second terminal p2, and the second transmission line 322 is a fourth terminal p4 facing the first terminal p1 and a third terminal p3 facing the second terminal p2.
  • the transmission line 330 having a length of 1 ⁇ 4 wavelength has an eighth terminal p8 and a seventh terminal p7.
  • the synthesis circuit 210 is configured without using the second coupled transmission line 310 in the synthesis circuit 200 shown in FIG.
  • the second terminal p2 is shorted to ground.
  • the fourth terminal p4 and the seventh terminal p7 are connected to each other.
  • the first terminal p1 forms an unbalanced terminal T1 with the ground, and the third terminal p3 and the eighth terminal p8 form balanced terminals T2 and T3 that are in opposite phases to each other.
  • the balun used in the Doherty amplifier combining circuit 210 of the second embodiment shown in FIG. 9 has characteristics equivalent to the balun used in the Doherty amplifier combining circuit 200 of the first embodiment shown in FIG.
  • the Doherty amplifier according to the second embodiment operates in the same manner as the Doherty amplifier according to the first embodiment.
  • FIG. Figure 10 is a circuit diagram showing the configuration of a Doherty amplifier according to a third embodiment of the present invention, instead of the impedance conversion circuit 201 of FIG. 1 showing the first embodiment, the fundamental wave frequency f 0 1 / A quarter wavelength transmission line 203 having a length of 4 wavelengths is used.
  • the same reference numerals as those in the circuit diagrams of the Doherty amplifiers of Embodiments 1 and 2 indicate the same or corresponding parts, and the description thereof is omitted.
  • the synthesis circuit 200 may be configured using the synthesis circuit 210 shown in FIG. 9 as in the second embodiment.
  • FIG. FIG. 11 is a circuit diagram of the Doherty amplifier according to the fourth embodiment of the present invention
  • FIGS. 12 and 13 are circuit diagrams showing a detailed configuration of the synthesis circuit 220 used in the fourth embodiment.
  • the synthesis circuit 220 illustrated in FIG. 13 illustrates another example configured without using the second coupled transmission line 310 in FIG. 12. Note that the same reference numerals as those in the circuit diagrams of the Doherty amplifiers of Embodiments 1 to 3 indicate the same or corresponding parts, and a description thereof will be omitted.
  • the combining circuit 220 in FIG. 12 is secondary to the ninth terminal p9 between the fourth terminal p4 and the seventh terminal p7 connected to each other.
  • a second harmonic injection extraction circuit 340 having an injection extraction terminal T4 for injecting or extracting harmonics is provided.
  • the second-order harmonic injection extraction circuit 340 connects the transmission lines 341 and 342 having a quarter wavelength with respect to the fundamental frequency f 0 in series, and the second order is connected to the connection point connected in series.
  • An injection extraction terminal T4 for injecting or extracting harmonics may be provided, and the other end of the transmission line 341 may be an open end.
  • the combining circuit 220 in FIG. 13 is secondary to the ninth terminal p9 between the fourth terminal p4 and the seventh terminal p7 connected to each other.
  • a second harmonic injection extraction circuit 340 having an injection extraction terminal T4 for injecting or extracting harmonics is provided, and has characteristics equivalent to those of the synthesis circuit 220 of FIG.
  • the same effects as in the first to third embodiments can be obtained.
  • FIG. FIG. 14 is a circuit diagram showing a configuration of the Doherty amplifier according to the fifth embodiment of the present invention
  • FIG. 15 is a circuit diagram showing a detailed configuration of the distribution circuit 204 used in the fifth embodiment.
  • the same reference numerals as those in the circuit diagrams of the Doherty amplifiers of Embodiments 1 to 4 indicate the same or corresponding parts, and the description thereof is omitted.
  • the synthesis circuit 200 may be configured using the synthesis circuit 210 as in the second embodiment.
  • the distribution circuit 204 includes a balun 400, a second harmonic injection extraction circuit 405 having an injection extraction terminal T5 for injecting or extracting the second harmonic, and a phase adjustment line 401.
  • the second harmonic injection extraction circuit 405 enables the injection extraction of the second harmonic without affecting the fundamental wave. As a result, the optimum circuit condition for the second harmonic frequency can be easily obtained. Can be realized.
  • the same effects as in the first to third embodiments can be obtained.
  • FIG. FIG. 16 is a circuit diagram of a Doherty amplifier according to the sixth embodiment of the present invention. Note that the same reference numerals as those in the circuit diagrams of the Doherty amplifiers of Embodiments 1 to 5 denote the same or corresponding parts, and a description thereof will be omitted. Further, the synthesis circuit 220 may be configured using either the synthesis circuit 220 shown in FIG. 12 or the synthesis circuit 220 shown in FIG. 13 as in the fourth embodiment.
  • the distribution circuit 204 includes a balun 400 and a second harmonic injection extraction circuit 405 having an injection extraction terminal T5 for injecting or extracting the second harmonic, and a phase adjustment line. 401.
  • the second harmonic injection extraction circuit 405 enables the injection extraction of the second harmonic without affecting the fundamental wave. As a result, the optimum circuit condition for the second harmonic frequency can be easily obtained. Can be realized.
  • the same effects as in the first to fifth embodiments can be obtained.
  • FIG. 17 is a circuit diagram showing a configuration of a Doherty amplifier according to the seventh embodiment of the present invention.
  • the combining circuit 220 shown in Embodiment 4 is used as the combining circuit, and the distribution circuit 204 shown in Embodiment 5 is used as the distribution circuit.
  • the combining circuit 220 may be configured using either the combining circuit 220 shown in FIG. 12 or the combining circuit 220 shown in FIG. 13 as in the fourth embodiment.
  • the amplitude and phase of the second harmonic are adjusted between the injection extraction terminal T4 for injecting or extracting the second harmonic of the synthesis circuit 220 and the injection extraction terminal T5 for injecting or extracting the second harmonic of the distribution circuit 204.
  • the second harmonic amplitude / phase adjustment circuit 205 is loaded.
  • the secondary harmonic generated at the output side of the Doherty amplifier is fed back to the input side with an appropriate amplitude and phase, or the secondary harmonic generated at the input side of the Doherty amplifier. It is possible to feed forward the second harmonic that injects the harmonic with an appropriate amplitude and phase to the output side, thereby enabling higher efficiency and lower distortion of the Doherty amplifier.
  • the same effects as in the first to sixth embodiments can be obtained.
  • the present invention can be freely combined with each other within the scope of the present invention, or can be appropriately modified or omitted.

Abstract

[Problem] To obtain a Doherty amplifier having a high saturation output power performance and further having a good power-efficiency performance during a linear operation. [Solution] In a Doherty amplifier of series load connection type configured by use of a balun, a carrier amplifier 100 is connected to one balanced terminal T2 of a combination circuit 200 via an impedance conversion circuit 201, a peak amplifier 101 is connected to the other balanced terminal T3 of the combination circuit 200, and a combined output signal is outputted from an unbalanced terminal T1 of the combination circuit 200.

Description

ドハティ増幅器Doherty amplifier
　本発明は、無線通信の送信機に用いられ、高い飽和出力電力性能を有するとともに、線形動作時に良好な電力効率性能を有するドハティ増幅器に関する。 The present invention relates to a Doherty amplifier that is used in a wireless communication transmitter and has high saturation output power performance and good power efficiency performance during linear operation.
　高速な無線通信の通信信号は、ＰＡＰＲ（Peak　to　Average　Power　Ratio　:　ピーク対平均電力比）が大きく、送信機に用いる電力増幅器は飽和出力電力より小さい平均電力で動作する。したがって、送信機の消費電力を抑えるためには平均電力における効率が高い電力増幅器が必要である。そのような電力増幅器としてドハティが提案したドハティ増幅器が有力である（例えば、非特許文献１参照）。
　電力増幅器の出力電力が大きくなると、それに用いるトランジスタのサイズが大きくなり、トランジスタの出力インピーダンスが小さくなる。したがって、出力電力が大きな電力増幅器では、トランジスタの整合回路は高いインピーダンス変換比が必要となるため、狭帯域性能となることや整合回路の損失が増大するなどの課題がある。このため、大電力動作時にも狭帯域性能となることや整合回路の損失が増大するなどの問題が小さい、高性能なドハティ増幅器が望まれる。
　また、電力増幅器にバランを適用することが知られている（例えば、特許文献１参照）。 A communication signal for high-speed wireless communication has a large PAPR (Peak to Average Power Ratio), and a power amplifier used in the transmitter operates with an average power smaller than a saturated output power. Therefore, in order to suppress the power consumption of the transmitter, a power amplifier with high efficiency in average power is required. As such a power amplifier, a Doherty amplifier proposed by Doherty is prominent (see Non-Patent Document 1, for example).
When the output power of the power amplifier increases, the size of the transistor used for it increases, and the output impedance of the transistor decreases. Therefore, in a power amplifier having a large output power, the transistor matching circuit requires a high impedance conversion ratio, which causes problems such as narrow band performance and increased matching circuit loss. For this reason, a high-performance Doherty amplifier is desired that has less problems such as narrow band performance and increased matching circuit loss even during high power operation.
In addition, it is known to apply a balun to a power amplifier (see, for example, Patent Document 1).
特許第５８２９８８５号公報Japanese Patent No. 5829985
　図１８～図２０は、ドハティが提案した従来のドハティ増幅器の回路図を示す（例えば、非特許文献１参照）。ドハティ増幅器は、ＡＢ～Ｂ級動作するキャリア増幅器１００とＣ級動作するピーク増幅器１０１とを組み合わせて構成することにより、信号レベルの低い線形動作時にも高効率な性能を得るものである。このドハティ増幅器には、図１８に示す並列負荷接続形と図１９または図２０に示すバラン１０２、１０３と組み合わせて構成される直列負荷接続形の２つの構成が提案されている。なお、図１８に示すドハティ増幅器の回路においては、入力側に分配器２０６が設けられており、また線路には、λ／４線路２０ａ、２０ｂ並びに位相調整線路１０５が設けられている。 18 to 20 show circuit diagrams of conventional Doherty amplifiers proposed by Doherty (see Non-Patent Document 1, for example). The Doherty amplifier is configured by combining a carrier amplifier 100 that operates in a class AB to a class B and a peak amplifier 101 that operates in a class C, thereby obtaining high performance even during linear operation with a low signal level. For this Doherty amplifier, two configurations of a parallel load connection type shown in FIG. 18 and a series load connection type configured in combination with the baluns 102 and 103 shown in FIG. 19 or FIG. 20 have been proposed. In the Doherty amplifier circuit shown in FIG. 18, a divider 206 is provided on the input side, and λ / 4 lines 20a and 20b and a phase adjustment line 105 are provided on the line.
　ここで，並列負荷接続形の構成は，一般に，直列負荷接続形の構成に比べ，キャリア増幅器１００やピーク増幅器１０１の出力整合を行う際のインピーダンス変換比が大きくなり、その結果出力整合回路の構成が難しくなり、狭帯域性能となることや整合回路の損失が増大するなどの課題がある。 Here, the parallel load connection type configuration generally has a larger impedance conversion ratio when performing output matching of the carrier amplifier 100 and the peak amplifier 101 than the series load connection type configuration, resulting in the configuration of the output matching circuit. However, there are problems such as narrow band performance and increased loss of the matching circuit.
　並列負荷接続形の構成におけるこの課題を解決するために、整合回路のインピーダンス変換比がこれに比べて小さくなる直列負荷接続形の構成を用いることができる。ドハティは初め、図１９に示すように構成された直列負荷接続形のドハティ増幅器を提案した。図１９の直列負荷接続形の回路構成では、ピーク増幅器１０１のトランジスタ（当時は真空管）は、線形動作時の出力インピーダンスが短絡となることを前提として動作するものである。しかしながら、実際のピーク増幅器１０１のトランジスタは、線形動作時の出力インピーダンスが短絡とならず、むしろ開放となる。そこで、図２０のように線形動作時のピーク増幅器１０１の出力側に開放を短絡に変換するインピーダンス変換回路１０４を装荷する構成とすることで、この問題を解決できるとしている。なお、図２０の構成では、インピーダンス変換回路１０４を設けたことに伴い，キャリア増幅器１００の入力側に位相調整線路１０５が設けられている。 In order to solve this problem in the parallel load connection configuration, a series load connection configuration in which the impedance conversion ratio of the matching circuit is smaller than this can be used. First, Doherty proposed a series load connection type Doherty amplifier configured as shown in FIG. In the series load connection type circuit configuration of FIG. 19, the transistor of the peak amplifier 101 (at that time a vacuum tube) operates on the assumption that the output impedance during linear operation is short-circuited. However, the transistor of the actual peak amplifier 101 does not short-circuit the output impedance during linear operation, but rather is open. Therefore, this problem can be solved by loading an impedance conversion circuit 104 that converts an open circuit into a short circuit on the output side of the peak amplifier 101 during linear operation as shown in FIG. In the configuration of FIG. 20, the phase adjustment line 105 is provided on the input side of the carrier amplifier 100 in accordance with the provision of the impedance conversion circuit 104.
　しかし，図２０の構成では，キャリア増幅器１００から出力負荷側を見込むインピーダンス条件が線形動作時と飽和動作時に最適となるようにするのに、ピーク増幅器１０１の出力側に設けたインピーダンス変換回路１０４を用いて実現する必要がある。このため、キャリア増幅器１００に対する最適な負荷インピーダンス条件を実現するのに直接的でなく、この結果、最適なインピーダンス条件を得ることが難しくなる問題がある。 However, in the configuration of FIG. 20, the impedance conversion circuit 104 provided on the output side of the peak amplifier 101 is provided so that the impedance condition for expecting the output load side from the carrier amplifier 100 is optimal during linear operation and saturation operation. It is necessary to realize it. For this reason, it is not direct to realize the optimum load impedance condition for the carrier amplifier 100. As a result, there is a problem that it is difficult to obtain the optimum impedance condition.
　本発明は上述のような課題を解決するためになされたもので、線形動作時にも良好な電力効率を実現できるドハティ増幅器を提供することを目的とする。 The present invention has been made to solve the above-described problems, and an object thereof is to provide a Doherty amplifier capable of realizing good power efficiency even during linear operation.
　本発明は、ドハティ増幅器において、入力信号を互いに位相差を有する第１入力信号および第２入力信号に分配する分配回路と、第１入力信号を増幅するキャリア増幅器と、第２入力信号を増幅するとともに線形動作となる小信号動作時においては出力インピーダンスが開放となるピーク増幅器と、キャリア増幅器の出力側に接続されたインピーダンス変換回路と、キャリア増幅器で増幅されインピーダンス変換回路を介して出力される第１出力信号とピーク増幅器で増幅され出力される第２出力信号とを合成する、バランで構成される合成回路とを備え、キャリア増幅器はインピーダンス変換回路を介して合成回路の一方の平衡端子に接続され、ピーク増幅器は合成回路の他方の平衡端子に接続されており、合成回路の不平衡端子から合成された出力信号が出力される。 The present invention provides a Doherty amplifier that distributes an input signal to a first input signal and a second input signal having a phase difference from each other, a carrier amplifier that amplifies the first input signal, and a second input signal. In addition, a peak amplifier whose output impedance is open at the time of a small signal operation which is a linear operation, an impedance conversion circuit connected to the output side of the carrier amplifier, and a first amplifier which is amplified by the carrier amplifier and output through the impedance conversion circuit A synthesis circuit composed of a balun for synthesizing one output signal and a second output signal amplified and output by a peak amplifier, and the carrier amplifier is connected to one balanced terminal of the synthesis circuit via an impedance conversion circuit The peak amplifier is connected to the other balanced terminal of the synthesis circuit. Output signal is output.
　本発明によれば、線形動作時にも良好な電力効率を実現できるドハティ増幅器を提供でき、これにより無線送信機の低消費電力化が可能となる。 According to the present invention, it is possible to provide a Doherty amplifier capable of realizing good power efficiency even during a linear operation, and thereby it is possible to reduce the power consumption of the wireless transmitter.
本発明の実施の形態１におけるドハティ増幅器を示す回路図である。It is a circuit diagram which shows the Doherty amplifier in Embodiment 1 of this invention. 本発明の実施の形態１におけるドハティ増幅器の合成回路を示す回路図である。It is a circuit diagram which shows the synthetic | combination circuit of the Doherty amplifier in Embodiment 1 of this invention. 本発明の実施の形態１におけるドハティ増幅器の合成回路の動作を説明するための回路図である。It is a circuit diagram for demonstrating operation | movement of the synthetic | combination circuit of the Doherty amplifier in Embodiment 1 of this invention. 本発明の実施の形態１におけるドハティ増幅器に用いる分配回路を示す回路図である。It is a circuit diagram which shows the distribution circuit used for the Doherty amplifier in Embodiment 1 of this invention. 本発明の実施の形態１におけるドハティ増幅器に用いる分配回路の他の例を示す回路図である。It is a circuit diagram which shows the other example of the distribution circuit used for the Doherty amplifier in Embodiment 1 of this invention. 本発明の実施の形態１におけるドハティ増幅器に用いる分配回路の他の例を示す回路図である。It is a circuit diagram which shows the other example of the distribution circuit used for the Doherty amplifier in Embodiment 1 of this invention. 本発明の実施の形態１におけるドハティ増幅器の飽和出力電圧からのバックオフ量に対するドレイン効率特性示す図である。It is a figure which shows the drain efficiency characteristic with respect to the back-off amount from the saturation output voltage of the Doherty amplifier in Embodiment 1 of this invention. 本発明の実施の形態２におけるドハティ増幅器を示す回路図である。It is a circuit diagram which shows the Doherty amplifier in Embodiment 2 of this invention. 本発明の実施の形態２におけるドハティ増幅器の合成回路を示す回路図である。It is a circuit diagram which shows the synthetic | combination circuit of the Doherty amplifier in Embodiment 2 of this invention. 本発明の実施の形態３におけるドハティ増幅器を示す回路図である。It is a circuit diagram which shows the Doherty amplifier in Embodiment 3 of this invention. 本発明の実施の形態４におけるドハティ増幅器を示す回路図である。It is a circuit diagram which shows the Doherty amplifier in Embodiment 4 of this invention. 本発明の実施の形態４におけるドハティ増幅器の合成回路を示す回路図である。It is a circuit diagram which shows the synthetic | combination circuit of the Doherty amplifier in Embodiment 4 of this invention. 本発明の実施の形態４におけるドハティ増幅器に用いる合成回路の他の例を示す回路図である。It is a circuit diagram which shows the other example of the synthetic | combination circuit used for the Doherty amplifier in Embodiment 4 of this invention. 本発明の実施の形態５におけるドハティ増幅器を示す回路図である。It is a circuit diagram which shows the Doherty amplifier in Embodiment 5 of this invention. 本発明の実施の形態５におけるドハティ増幅器に用いる分配回路を示す回路図である。It is a circuit diagram which shows the distribution circuit used for the Doherty amplifier in Embodiment 5 of this invention. 本発明の実施の形態６におけるドハティ増幅器を示す回路図である。It is a circuit diagram which shows the Doherty amplifier in Embodiment 6 of this invention. 本発明の実施の形態７におけるドハティ増幅器を示す回路図である。It is a circuit diagram which shows the Doherty amplifier in Embodiment 7 of this invention. 従来のドハティ増幅器を示す回路図である。It is a circuit diagram which shows the conventional Doherty amplifier. 従来のドハティ増幅器の他の例を示す回路図である。It is a circuit diagram which shows the other example of the conventional Doherty amplifier. 従来のドハティ増幅器の他の例を示す回路図である。It is a circuit diagram which shows the other example of the conventional Doherty amplifier.
　以下、本発明の実施の形態につき、図面を参照して詳述する。なお、各図中、同一符号は、同一または相当部分を示すものとする。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same code | symbol shall show the same or an equivalent part.
実施の形態１．
　図１は、本発明の実施の形態１におけるドハティ増幅器の構成を示す回路図である。このドハティ増幅器は、入力信号Ｓ１を互いに適切な位相差θｄを有する第１入力信号Ｓ２および第２入力信号Ｓ３に分配する分配回路２０２と、第１入力信号Ｓ２を増幅するキャリア増幅器１００と、第２入力信号Ｓ３を増幅するとともに小信号動作時においては出力インピーダンスが開放となるピーク増幅器１０１と、キャリア増幅器１００の出力側に接続されるインピーダンス変換回路２０１と、キャリア増幅器１００で増幅されインピーダンス変換回路２０１を介して出力される第１出力信号Ｓ４とピーク増幅器１０１で増幅され出力される第２出力信号Ｓ５とを合成する合成回路２００で構成されている。 Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a configuration of a Doherty amplifier according to Embodiment 1 of the present invention. The Doherty amplifier includes a distribution circuit 202 distributes the input signal S1 to the first input signal S2 and the second input signal S3 having a proper phase difference theta d each other, a carrier amplifier 100 for amplifying the first input signal S2, The second input signal S3 is amplified, and a peak amplifier 101 whose output impedance is opened during the small signal operation, an impedance conversion circuit 201 connected to the output side of the carrier amplifier 100, and an impedance conversion amplified by the carrier amplifier 100. The synthesis circuit 200 is configured to synthesize the first output signal S4 output via the circuit 201 and the second output signal S5 amplified and output by the peak amplifier 101.
　図２は実施の形態１の合成回路２００の詳細構成を示す回路図である。この合成回路２００は、基本波周波数ｆ０に対して１／４波長の長さを有し、性能が同等である、第１結合伝送線路３００および第２結合伝送線路３１０を用いて構成されたバランである。第１結合伝送線路３００は、互いに平行に近接して配置された第１伝送線路３０１および第２伝送線路３０２で構成されている。第１伝送線路３０１は、第１端子ｐ１および第２端子ｐ２を有し、第２伝送線路３０２は、第１端子ｐ１に対向して第４端子ｐ４および第２端子ｐ２に対向して第３端子ｐ３を有している。第２結合伝送線路３１０は、互いに平行に近接して配置された第３伝送線路３１１および第４伝送線路３１２で構成されている。第３伝送線路３１１は、第５端子ｐ５および第６端子ｐ６を有し、第４伝送線路３１２は、第５端子ｐ５に対向して第８端子ｐ８および第６端子ｐ６に対向して第７端子ｐ７を有している。第２端子ｐ２と第５端子ｐ５と第６端子ｐ６はグランドに短絡され、第４端子ｐ４と第７端子ｐ７は互いに接続されている。第１端子ｐ１はグランドとの間に不平衡端子Ｔ１を成し、第３端子ｐ３と第８端子ｐ８はそれぞれ、互いに逆相となる平衡端子Ｔ２、Ｔ３を成している。このようなバランに相当するものとしては、例えば特許文献１記載のものがある。 FIG. 2 is a circuit diagram showing a detailed configuration of the synthesis circuit 200 according to the first embodiment. The synthesis circuit 200 is configured using the first coupled transmission line 300 and the second coupled transmission line 310 having a length of ¼ wavelength with respect to the fundamental frequency f 0 and having the same performance. It is a balun. The first coupled transmission line 300 includes a first transmission line 301 and a second transmission line 302 that are arranged close to each other in parallel. The first transmission line 301 has a first terminal p1 and a second terminal p2, and the second transmission line 302 faces the first terminal p1 and faces the fourth terminal p4 and the second terminal p2, and third. A terminal p3 is provided. The second coupled transmission line 310 includes a third transmission line 311 and a fourth transmission line 312 that are arranged close to each other in parallel. The third transmission line 311 has a fifth terminal p5 and a sixth terminal p6, and the fourth transmission line 312 faces the fifth terminal p5 and faces the eighth terminal p8 and the sixth terminal p6. A terminal p7 is provided. The second terminal p2, the fifth terminal p5, and the sixth terminal p6 are short-circuited to the ground, and the fourth terminal p4 and the seventh terminal p7 are connected to each other. The first terminal p1 forms an unbalanced terminal T1 with the ground, and the third terminal p3 and the eighth terminal p8 form balanced terminals T2 and T3 that are in opposite phases to each other. An example of such a balun is disclosed in Patent Document 1.
　キャリア増幅器１００の出力側はインピーダンス変換回路２０１を介して合成回路２００の一方の平衡端子Ｔ２に接続され、ピーク増幅器１０１の出力側は合成回路２００の他の一方の平衡端子Ｔ３に接続されている。合成回路２００で合成された第１出力信号Ｓ４と第２出力信号Ｓ５の合成出力信号は不平衡端子Ｔ１から出力される。 The output side of the carrier amplifier 100 is connected to one balanced terminal T2 of the synthesis circuit 200 via the impedance conversion circuit 201, and the output side of the peak amplifier 101 is connected to the other balanced terminal T3 of the synthesis circuit 200. . A combined output signal of the first output signal S4 and the second output signal S5 combined by the combining circuit 200 is output from the unbalanced terminal T1.
　次に動作を説明する。
　図２に示した合成回路２００は、第１結合伝送線路３００および第２結合伝送線路３１０の偶モード特性インピーダンスＺｏｅおよび奇モード特性インピーダンスＺｏｏは、不平衡端子Ｔ１に接続される出力負荷のインピーダンスＺｓならびに、平衡端子Ｔ２およびＴ３に接続される負荷のインピーダンスＺＬに対して次式（１）の関係式を満足するようにあらかじめ設計されている。
　なお、以下では、説明をわかりやすくするため、負荷のインピーダンスＺｓ、ＺＬは実数であるとし、さらに、ＺＬ＝Ｒであるとする。 Next, the operation will be described.
In the synthesis circuit 200 shown in FIG. 2, the even-mode characteristic impedance Z oe and the odd-mode characteristic impedance Z oo of the first coupled transmission line 300 and the second coupled transmission line 310 are the same as the output load connected to the unbalanced terminal T1. The impedance Z s and the impedance Z L of the load connected to the balanced terminals T2 and T3 are designed in advance so as to satisfy the relational expression of the following expression (1).
In the following description, it is assumed that the load impedances Z s and Z L are real numbers, and further, Z L = R for easy understanding.
Figure JPOXMLDOC01-appb-M000001
 　
Figure JPOXMLDOC01-appb-M000001
 　
　飽和動作（大信号動作）時には、キャリア増幅器１００とピーク増幅器１０１は通常のプッシュプル増幅器と同様の動作をし、平衡端子Ｔ２と平衡端子Ｔ３は互いに逆相で動作する平衡端子として動作する。この結果、飽和動作時に平衡端子Ｔ２と平衡端子Ｔ３から合成回路２００を見込んだインピーダンスＺ２、Ｚ３は、整合時に次式（２）で与えられる。 During the saturation operation (large signal operation), the carrier amplifier 100 and the peak amplifier 101 operate in the same manner as a normal push-pull amplifier, and the balanced terminal T2 and the balanced terminal T3 operate as balanced terminals that operate in opposite phases. As a result, the impedances Z 2 and Z 3 for which the combined circuit 200 is expected from the balanced terminal T2 and the balanced terminal T3 during the saturation operation are given by the following equation (2) at the time of matching.
Figure JPOXMLDOC01-appb-M000002
 　
Figure JPOXMLDOC01-appb-M000002
 　
　次に、図３のように一方の平衡端子Ｔ３を開放とした場合（これは、ピーク増幅器１０１の出力インピーダンスＺｏｕｔが線形動作となる小信号動作時に開放となることに対応する）、他の一方の平衡端子Ｔ２から合成回路２００を見込んだインピーダンスＺ２に対して次式（３）の関係式が成り立つ。 Then, when the open one balanced terminal T3 as shown in FIG. 3 (this corresponds to the output impedance Z out of the peak amplifier 101 is opened to the small signal operation as a linear operation), the other the following relational expression (3) holds from one balanced terminal T2 with respect to the impedance Z 2 in anticipation of the combining circuit 200.
Figure JPOXMLDOC01-appb-M000003
 　
Figure JPOXMLDOC01-appb-M000003
 　
　したがって、線形動作（小信号動作）時のインピーダンスＺ２は、式（１）～式（３）より、次式（４）で与えられる。 Therefore, the impedance Z 2 at the time of linear operation (small signal operation) is given by the following equation (4) from the equations (1) to (3).
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000004
　以上より、平衡端子Ｔ３を開放として、平衡端子Ｔ２から合成回路２００を見込んだインピーダンスＺ２は、平衡端子Ｔ２と平衡端子Ｔ３が互いに逆相で動作する平衡端子として動作する場合の、平衡端子Ｔ２から合成回路２００を見込んだインピーダンスＺ２の１／２倍となる。したがって、図１に示した本発明のドハティ増幅器は、合成回路２００のバランを用いることによって、ピーク増幅器１０１の出力インピーダンスＺｏｕｔが開放となる線形動作時には、キャリア増幅器１００側から合成回路２００側を見込んだインピーダンスＺ２はＺ２＝Ｒ／２となり、キャリア増幅器１００とピーク増幅器１０１とが平衡動作する飽和動作時には、インピーダンスＺ２、Ｚ３は、Ｚ２＝Ｚ３＝Ｒとなる。 From the above, as an open balanced terminal T3, the impedance Z 2 in anticipation of the combining circuit 200 from the balanced terminal T2, when operating as a balanced terminal balanced terminal T2 and the balanced terminal T3 is operated in opposite phases, balanced terminal T2 It becomes 1/2 times the impedance Z 2 in anticipation of the combining circuit 200 from. Therefore, the Doherty amplifier of the present invention shown in FIG. 1 uses the balun of the synthesis circuit 200 to change the synthesis circuit 200 side from the carrier amplifier 100 side during linear operation in which the output impedance Zout of the peak amplifier 101 is open. I expected but the impedance Z 2 is Z 2 = R / 2, and the at the time of saturation operation the carrier amplifier 100 and peak amplifier 101 operates equilibrium impedance Z 2, Z 3 becomes Z 2 = Z 3 = R.
　一般に、増幅器ではトランジスタから負荷側を見込む負荷インピーダンスＺ１の値が大きくなるほど効率は高くなり、逆に、負荷インピーダンスＺ１の値が小さくなるほど出力電力は高くなる。このため、高い効率が望まれる線形動作時には負荷インピーダンスＺ１の値が大きくなり、大きな出力電力が望まれる飽和動作時には負荷インピーダンスＺ１の値が小さくなるように電力レベルに応じて負荷インピーダンスを制御する必要がある。このようなインピーダンス条件を実現するため、キャリア増幅器１００と合成回路２００の間にインピーダンス変換回路２０１が設けられる。 In general, the amplifier in high efficiency as the value of the load impedance Z 1 looking into the load side from the transistor is increased, conversely, as the output power value of the load impedance Z 1 becomes small becomes high. For this reason, the load impedance Z 1 is increased during linear operation where high efficiency is desired, and the load impedance is controlled according to the power level so that the value of load impedance Z 1 is decreased during saturation operation where large output power is desired. There is a need to. In order to realize such an impedance condition, an impedance conversion circuit 201 is provided between the carrier amplifier 100 and the synthesis circuit 200.
　ここでは、インピーダンス変換回路２０１により、キャリア増幅器１００から負荷側を見込む負荷インピーダンスＺ１が、線形動作時にはＺ１＝２Ｒに、さらに、飽和動作時にはＺ１＝Ｒにインピーダンス変換される。このようなインピーダンス変換は伝送線路やインダクタＬとキャパシタＣを組み合わせた回路を用いることで実現可能である。 Here, the impedance conversion circuit 201, a load impedance Z 1 of the carrier amplifier 100 allow for load side, at the time of linear operation to Z 1 = 2R, furthermore, at the time of saturation operation is impedance converted into Z 1 = R. Such impedance conversion can be realized by using a transmission line or a circuit in which an inductor L and a capacitor C are combined.
　なお、インピーダンス変換回路２０１による位相遅延θｔを含んで、第１出力信号Ｓ４と第２出力信号Ｓ５とが平衡端子Ｔ２と平衡端子Ｔ３で逆位相となるようにするため、分配回路２０２からの第１入力信号Ｓ２と第２入力信号Ｓ３との間の位相差θｄは基本波周波数ｆ０において次式（５）を満足するように与えられる。 In addition, in order to make the first output signal S4 and the second output signal S5 have opposite phases at the balanced terminal T2 and the balanced terminal T3, including the phase delay θ t by the impedance conversion circuit 201, phase difference theta d between first input signal S2 and the second input signal S3 is provided at the fundamental frequency f 0 so as to satisfy the following equation (5).
Figure JPOXMLDOC01-appb-M000005
 　
Figure JPOXMLDOC01-appb-M000005
 　
　図４～図６に分配回路２０２の種々の構成例を示している。図４に示す分配回路は、逆相分配するバラン４００と位相調整線路４０１とを組み合わせて構成するものである。図５に示す分配回路は、ウイルソンカプラなどの同相分配器４０２と位相調整線路４０３とを組み合わせて構成するものである。図６に示す分配回路は、９０°ハイブリッド回路４０４を用いて構成するものである。 4 to 6 show various configuration examples of the distribution circuit 202. FIG. The distribution circuit shown in FIG. 4 is configured by combining a balun 400 that performs antiphase distribution and a phase adjustment line 401. The distribution circuit shown in FIG. 5 is configured by combining an in-phase distributor 402 such as a Wilson coupler and a phase adjustment line 403. The distribution circuit shown in FIG. 6 is configured using a 90 ° hybrid circuit 404.
　一方、キャリア増幅器１００とピーク増幅器１０１の最大電圧振幅をＶｍａｘとすると、飽和動作時のキャリア増幅器１００とピーク増幅器１０１の出力電力はそれぞれ、Ｖｍａｘ ２／Ｒとなり、合成回路２００で合成された最大出力電力はＰｓａｔ＝Ｖｍａｘ ２／Ｒ＋Ｖｍａｘ ２／Ｒ＝２Ｖｍａｘ ２／Ｒとなる。一方、キャリア増幅器１００のみが動作している線形動作時の出力電力（出力電力の最大値）はＰｏｕｔ＝Ｖｍａｘ ２／（２Ｒ）となり、飽和動作時の出力電力Ｐｓａｔの１／４倍（－６ｄＢ）となる。 On the other hand, when the maximum voltage amplitude of the carrier amplifier 100 and peak amplifier 101 and V max, respectively the output power of the carrier amplifier 100 and peak amplifier 101 at saturation operation, V max 2 / R, and the synthesized in the synthesizing circuit 200 The maximum output power is P sat = V max 2 / R + V max 2 / R = 2 V max 2 / R. On the other hand, the output power (maximum value of output power) at the time of linear operation in which only the carrier amplifier 100 is operating is P out = V max 2 / (2R), which is ¼ times the output power P sat at the time of saturation operation. (−6 dB).
　図７は本発明の実施の形態１によるドハティ増幅器の飽和出力電力からのバックオフ量に対するドレイン効率を示しており、以上の理由により、図７のように線形動作時にも高効率な性能となるドハティ増幅器として動作する。 FIG. 7 shows the drain efficiency with respect to the back-off amount from the saturated output power of the Doherty amplifier according to the first embodiment of the present invention. For the above reasons, the efficiency is high even during linear operation as shown in FIG. Operates as a Doherty amplifier.
　以上から、図１に示す本発明の実施の形態１の直列負荷接続形のドハティ増幅器では、図２０に示す従来の直列負荷接続形のドハティ増幅器と異なり、線形動作時に合成回路２００からピーク増幅器１０１側を見込んだインピーダンスは開放（Ｚｏｕｔ＝∞）であるが、これを短絡に変換させるインピーダンス変換回路はピーク増幅器１０１側には不要である。一方、キャリア増幅器１００の出力側にインピーダンス変換回路２０１を設ける構成であるので、線形動作時と飽和動作時のキャリア増幅器１００から負荷側を見込む最適なインピーダンス条件を直接的に容易に制御することが可能である。 From the above, the series load connection type Doherty amplifier according to the first embodiment of the present invention shown in FIG. 1 differs from the conventional series load connection type Doherty amplifier shown in FIG. The impedance in consideration of the side is open (Z out = ∞), but an impedance conversion circuit for converting this into a short circuit is not necessary on the peak amplifier 101 side. On the other hand, since the impedance conversion circuit 201 is provided on the output side of the carrier amplifier 100, the optimum impedance condition for expecting the load side from the carrier amplifier 100 during linear operation and saturation operation can be directly and easily controlled. Is possible.
　このように、本発明は、直列負荷接続形のドハティ増幅器において、キャリア増幅器の出力側に設けたインピーダンス変換回路を用いてキャリア増幅器に対する線形動作時と飽和動作時の最適な負荷インピーダンス条件を直接的に制御することを可能とするドハティ増幅器を提供する。これによりキャリア増幅器に対する動作レベルに応じた最適な負荷インピーダンス条件を容易に実現することが可能となる。 As described above, according to the present invention, in the Doherty amplifier of the series load connection type, the optimum load impedance condition for the linear operation and the saturation operation for the carrier amplifier is directly determined using the impedance conversion circuit provided on the output side of the carrier amplifier. Provided is a Doherty amplifier that can be controlled. This makes it possible to easily realize the optimum load impedance condition corresponding to the operation level for the carrier amplifier.
実施の形態２．
　図８は、本発明の実施の形態２におけるドハティ増幅器の構成を示す回路図であり、基本的構成は、合成回路２１０の一部分の構成以外は図１に示す実施の形態１のドハティ増幅器と同じである。よって、図１に示す回路図における符号と同じ符号は同一もしくは相当部分を示しており、説明を省略する。図９はこの実施の形態２に用いる合成回路２１０の詳細構成を示す回路図である。 Embodiment 2. FIG.
FIG. 8 is a circuit diagram showing the configuration of the Doherty amplifier according to the second embodiment of the present invention. The basic configuration is the same as that of the Doherty amplifier according to the first embodiment shown in FIG. It is. Therefore, the same reference numerals as those in the circuit diagram shown in FIG. FIG. 9 is a circuit diagram showing a detailed configuration of the synthesis circuit 210 used in the second embodiment.
　図９に示された合成回路２１０は、基本波周波数ｆ０に対して１／４波長の長さを有する結合伝送線路３２０と１／４波長の長さを有する伝送線路３３０とを用いて構成されたバランである。結合伝送線路３２０は、互いに平行に近接して配置された、第１伝送線路３２１および第２伝送線路３２２で構成されている。第１伝送線路３２１は、第１端子ｐ１および第２端子ｐ２を有し、第２伝送線路３２２は、第１端子ｐ１に対向する第４端子ｐ４および第２端子ｐ２に対向する第３端子ｐ３を有している。１／４波長の長さを有する伝送線路３３０は、第８端子ｐ８および第７端子ｐ７を有している。即ち、この合成回路２１０は、図２に示した合成回路２００における第２結合伝送線路３１０を用いないで構成したものである。第２端子ｐ２はグランドに短絡されている。第４端子ｐ４と第７端子ｐ７は互いに接続されている。第１端子ｐ１はグランドとの間に不平衡端子Ｔ１を成し、第３端子ｐ３と第８端子ｐ８はそれぞれ、互いに逆相となる平衡端子Ｔ２、Ｔ３を成している。 The combining circuit 210 shown in FIG. 9 is configured using a coupled transmission line 320 having a length of ¼ wavelength with respect to the fundamental frequency f 0 and a transmission line 330 having a length of ¼ wavelength. Balun. The coupled transmission line 320 includes a first transmission line 321 and a second transmission line 322 that are arranged close to each other in parallel. The first transmission line 321 has a first terminal p1 and a second terminal p2, and the second transmission line 322 is a fourth terminal p4 facing the first terminal p1 and a third terminal p3 facing the second terminal p2. have. The transmission line 330 having a length of ¼ wavelength has an eighth terminal p8 and a seventh terminal p7. That is, the synthesis circuit 210 is configured without using the second coupled transmission line 310 in the synthesis circuit 200 shown in FIG. The second terminal p2 is shorted to ground. The fourth terminal p4 and the seventh terminal p7 are connected to each other. The first terminal p1 forms an unbalanced terminal T1 with the ground, and the third terminal p3 and the eighth terminal p8 form balanced terminals T2 and T3 that are in opposite phases to each other.
　図９に示す実施の形態２のドハティ増幅器の合成回路２１０に用いるバランは、図２に示す実施の形態１のドハティ増幅器の合成回路２００に用いるバランと等価の特性であり、この結果、実施の形態２のドハティ増幅器は、実施の形態１のドハティ増幅器と同様の動作をする。 The balun used in the Doherty amplifier combining circuit 210 of the second embodiment shown in FIG. 9 has characteristics equivalent to the balun used in the Doherty amplifier combining circuit 200 of the first embodiment shown in FIG. The Doherty amplifier according to the second embodiment operates in the same manner as the Doherty amplifier according to the first embodiment.
実施の形態３．
　図１０は、本発明の実施の形態３におけるドハティ増幅器の構成を示す回路図であり、実施の形態１を示す図１におけるインピーダンス変換回路２０１に代えて、基本波周波数ｆ０に対して１／４波長の長さを有する１／４波長伝送線路２０３を用いて構成されている。なお、実施の形態１～２のドハティ増幅器の回路図における符号と同じ符号は、同一もしくは相当部分を示しており、説明を省略する。また、合成回路２００は、実施の形態２と同様に図９に示す合成回路２１０を用いて構成してもよい。 Embodiment 3 FIG.
Figure 10 is a circuit diagram showing the configuration of a Doherty amplifier according to a third embodiment of the present invention, instead of the impedance conversion circuit 201 of FIG. 1 showing the first embodiment, the fundamental wave frequency f 0 1 / A quarter wavelength transmission line 203 having a length of 4 wavelengths is used. Note that the same reference numerals as those in the circuit diagrams of the Doherty amplifiers of Embodiments 1 and 2 indicate the same or corresponding parts, and the description thereof is omitted. Further, the synthesis circuit 200 may be configured using the synthesis circuit 210 shown in FIG. 9 as in the second embodiment.
　本実施の形態３においては、特に、１／４波長伝送線路２０３の特性インピーダンスＺ０をＺ０＝Ｒとすると、合成回路側を見込むインピーダンスＺ２＝Ｒ／２をＺ１＝２Ｒに、また、Ｚ２＝ＲをＺ１＝Ｒにインピーダンス変換することができる。
　なお、１／４波長伝送線路２０３の位相遅延θｔはほぼ９０度となるので、分配回路２０２における位相差θｄは、式（５）の関係から、ほぼ９０度となるように設計される。
　このような実施の形態３においても実施の形態１～２と同様の効果も得ることができる。 In the third embodiment, particularly when the characteristic impedance Z 0 of the quarter-wave transmission line 203 is Z 0 = R, the impedance Z 2 = R / 2 for which the combined circuit side is expected is changed to Z 1 = 2R, and , Z 2 = R can be impedance converted to Z 1 = R.
Since the phase delay θ t of the ¼ wavelength transmission line 203 is approximately 90 degrees, the phase difference θ d in the distribution circuit 202 is designed to be approximately 90 degrees from the relationship of Expression (5). .
In the third embodiment, the same effects as in the first and second embodiments can be obtained.
実施の形態４．
　図１１は、本発明の実施の形態４におけるドハティ増幅器の回路図であり、図１２および図１３は実施の形態４に用いる合成回路２２０の詳細構成を示す回路図である。図１３に示す合成回路２２０は、図１２における第２結合伝送線路３１０を用いないで構成した他の例を示している。なお、実施の形態１～３のドハティ増幅器の回路図における符号と同じ符号は、同一もしくは相当部分を示しており、説明を省略する。 Embodiment 4 FIG.
FIG. 11 is a circuit diagram of the Doherty amplifier according to the fourth embodiment of the present invention, and FIGS. 12 and 13 are circuit diagrams showing a detailed configuration of the synthesis circuit 220 used in the fourth embodiment. The synthesis circuit 220 illustrated in FIG. 13 illustrates another example configured without using the second coupled transmission line 310 in FIG. 12. Note that the same reference numerals as those in the circuit diagrams of the Doherty amplifiers of Embodiments 1 to 3 indicate the same or corresponding parts, and a description thereof will be omitted.
　図１２の合成回路２２０は、図２に示す実施の形態１のドハティ増幅器の合成回路に用いるバランにおいて、互いに接続された第４端子ｐ４と第７端子ｐ７の間の第９端子ｐ９に２次高調波を注入もしくは抽出する注入抽出端子Ｔ４を有した２次高調波注入抽出回路３４０を設けたものである。２次高調波注入抽出回路３４０は、例えば図１２に示すように、基本波周波数ｆ０対して１／４波長の伝送線路３４１と３４２とを直列接続し、直列接続された接続点に２次高調波を注入もしくは抽出する注入抽出端子Ｔ４を設け、さらに伝送線路３４１の他端を開放端とすることにより構成できる。これにより、基本波には影響を与えることなく、２次高調波の注入抽出が可能となり、その結果、２次高調波周波数に対する最適な回路条件を容易に実現できるようになる。 In the balun used in the Doherty amplifier combining circuit according to the first embodiment shown in FIG. 2, the combining circuit 220 in FIG. 12 is secondary to the ninth terminal p9 between the fourth terminal p4 and the seventh terminal p7 connected to each other. A second harmonic injection extraction circuit 340 having an injection extraction terminal T4 for injecting or extracting harmonics is provided. For example, as shown in FIG. 12, the second-order harmonic injection extraction circuit 340 connects the transmission lines 341 and 342 having a quarter wavelength with respect to the fundamental frequency f 0 in series, and the second order is connected to the connection point connected in series. An injection extraction terminal T4 for injecting or extracting harmonics may be provided, and the other end of the transmission line 341 may be an open end. As a result, injection and extraction of the second harmonic can be performed without affecting the fundamental wave, and as a result, an optimum circuit condition for the second harmonic frequency can be easily realized.
　図１３の合成回路２２０は、図９に示す実施の形態２のドハティ増幅器の合成回路に用いるバランにおいて、互いに接続された第４端子ｐ４と第７端子ｐ７の間の第９端子ｐ９に２次高調波を注入もしくは抽出する注入抽出端子Ｔ４を有した２次高調波注入抽出回路３４０を設けたものであり、図１２の合成回路２２０と等価の特性となる。
　このような実施の形態４においても実施の形態1～３と同様の効果も得ることができる。 In the balun used in the Doherty amplifier combining circuit according to the second embodiment shown in FIG. 9, the combining circuit 220 in FIG. 13 is secondary to the ninth terminal p9 between the fourth terminal p4 and the seventh terminal p7 connected to each other. A second harmonic injection extraction circuit 340 having an injection extraction terminal T4 for injecting or extracting harmonics is provided, and has characteristics equivalent to those of the synthesis circuit 220 of FIG.
In the fourth embodiment, the same effects as in the first to third embodiments can be obtained.
　実施の形態５．
　図１４は、本発明の実施の形態５におけるドハティ増幅器の構成を示す回路図であり、図１５は実施の形態５に用いる分配回路２０４の詳細構成を示す回路図である。なお、実施の形態１～４のドハティ増幅器の回路図における符号と同じ符号は、同一もしくは相当部分を示しており、説明を省略する。また、合成回路２００は、実施の形態２と同様に合成回路２１０を用いて構成してもよい。 Embodiment 5 FIG.
FIG. 14 is a circuit diagram showing a configuration of the Doherty amplifier according to the fifth embodiment of the present invention, and FIG. 15 is a circuit diagram showing a detailed configuration of the distribution circuit 204 used in the fifth embodiment. Note that the same reference numerals as those in the circuit diagrams of the Doherty amplifiers of Embodiments 1 to 4 indicate the same or corresponding parts, and the description thereof is omitted. Further, the synthesis circuit 200 may be configured using the synthesis circuit 210 as in the second embodiment.
　分配回路２０４は、バラン４００と２次高調波を注入もしくは抽出する注入抽出端子Ｔ５を有した２次高調波注入抽出回路４０５と位相調整線路４０１とで構成される。
　２次高調波注入抽出回路４０５は、基本波には影響を与えることなく、２次高調波の注入抽出を可能とするもので、その結果、２次高調波周波数に対する最適な回路条件を容易に実現できるようになる。
　このような実施の形態５においても実施の形態１～３と同様の効果も得ることができる。 The distribution circuit 204 includes a balun 400, a second harmonic injection extraction circuit 405 having an injection extraction terminal T5 for injecting or extracting the second harmonic, and a phase adjustment line 401.
The second harmonic injection extraction circuit 405 enables the injection extraction of the second harmonic without affecting the fundamental wave. As a result, the optimum circuit condition for the second harmonic frequency can be easily obtained. Can be realized.
In the fifth embodiment, the same effects as in the first to third embodiments can be obtained.
　実施の形態６．
　図１６は、本発明の実施の形態６におけるドハティ増幅器の回路図である。なお、実施の形態１～５のドハティ増幅器の回路図における符号と同じ符号は、同一もしくは相当部分を示しており、説明を省略する。また、合成回路２２０は、実施の形態４と同様に図１２に示す合成回路２２０または図１３に示す合成回路２２０のいずれを用いて構成してもよい。 Embodiment 6 FIG.
FIG. 16 is a circuit diagram of a Doherty amplifier according to the sixth embodiment of the present invention. Note that the same reference numerals as those in the circuit diagrams of the Doherty amplifiers of Embodiments 1 to 5 denote the same or corresponding parts, and a description thereof will be omitted. Further, the synthesis circuit 220 may be configured using either the synthesis circuit 220 shown in FIG. 12 or the synthesis circuit 220 shown in FIG. 13 as in the fourth embodiment.
　分配回路２０４は、図１５に示す実施の形態５における分配回路と同様にバラン４００と２次高調波を注入もしくは抽出する注入抽出端子Ｔ５を有した２次高調波注入抽出回路４０５と位相調整線路４０１とで構成される。
　２次高調波注入抽出回路４０５は、基本波には影響を与えることなく、２次高調波の注入抽出を可能とするもので、その結果、２次高調波周波数に対する最適な回路条件を容易に実現できるようになる。
　このような実施の形態６においても実施の形態１～５と同様の効果も得ることができる。 Similarly to the distribution circuit in the fifth embodiment shown in FIG. 15, the distribution circuit 204 includes a balun 400 and a second harmonic injection extraction circuit 405 having an injection extraction terminal T5 for injecting or extracting the second harmonic, and a phase adjustment line. 401.
The second harmonic injection extraction circuit 405 enables the injection extraction of the second harmonic without affecting the fundamental wave. As a result, the optimum circuit condition for the second harmonic frequency can be easily obtained. Can be realized.
In the sixth embodiment, the same effects as in the first to fifth embodiments can be obtained.
実施の形態７．
　図１７は、本発明の実施の形態７におけるドハティ増幅器の構成を示す回路図である。
　合成回路として、実施の形態４で示した合成回路２２０を用い、分配回路として、実施の形態５で示した分配回路２０４を用いている。合成回路２２０は、実施の形態４と同様に図１２に示す合成回路２２０または図１３に示す合成回路２２０のいずれを用いて構成してもよい。
合成回路２２０の２次高調波を注入もしくは抽出する注入抽出端子Ｔ４と分配回路２０４の２次高調波を注入もしくは抽出する注入抽出端子Ｔ５との間に、２次高調波の振幅と位相を調整する２次高調波振幅・位相調整回路２０５を装荷して構成される。 Embodiment 7 FIG.
FIG. 17 is a circuit diagram showing a configuration of a Doherty amplifier according to the seventh embodiment of the present invention.
The combining circuit 220 shown in Embodiment 4 is used as the combining circuit, and the distribution circuit 204 shown in Embodiment 5 is used as the distribution circuit. The combining circuit 220 may be configured using either the combining circuit 220 shown in FIG. 12 or the combining circuit 220 shown in FIG. 13 as in the fourth embodiment.
The amplitude and phase of the second harmonic are adjusted between the injection extraction terminal T4 for injecting or extracting the second harmonic of the synthesis circuit 220 and the injection extraction terminal T5 for injecting or extracting the second harmonic of the distribution circuit 204. The second harmonic amplitude / phase adjustment circuit 205 is loaded.
　本構成とすることにより、ドハティ増幅器の出力側で発生した２次高調波を適切な振幅、位相で入力側に注入する２次高調波に対するフィードバック、または、ドハティ増幅器の入力側で発生した２次高調波を適切な振幅、位相で出力側に注入する２次高調波に対するフィードフォワードが可能となり、これによりドハティ増幅器の高効率化や低歪化が可能となる。
　このような実施の形態７においても実施の形態１～６と同様の効果も得ることができる。 By adopting this configuration, the secondary harmonic generated at the output side of the Doherty amplifier is fed back to the input side with an appropriate amplitude and phase, or the secondary harmonic generated at the input side of the Doherty amplifier. It is possible to feed forward the second harmonic that injects the harmonic with an appropriate amplitude and phase to the output side, thereby enabling higher efficiency and lower distortion of the Doherty amplifier.
In the seventh embodiment, the same effects as in the first to sixth embodiments can be obtained.
本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することができる。 The present invention can be freely combined with each other within the scope of the present invention, or can be appropriately modified or omitted.
１００　キャリア増幅器、１０１　ピーク増幅器、２００，２１０，２２０　合成回路、２０１　インピーダンス変換回路、２０２，２０４　分配回路、２０３　１／４波長伝送線路、２０５　２次高調波振幅・位相調整回路、３００　第１結合伝送線路、３０１　第１伝送線路、３０２　第２伝送線路、３１０　第２結合伝送線路、３１１　第３伝送線路、３１２　第４伝送線路、３２０　結合伝送線路、３２１　第１伝送線路、３２２　第２伝送線路、３３０　伝送線路、３４０，４０５　２次高調波注入抽出回路、３４１，３４２　伝送線路、４００　バラン、４０１，４０３　位相調整線路、Ｓ１　入力信号、Ｓ２　第１入力信号、Ｓ３　第２入力信号、Ｓ４　第１出力信号、Ｓ５　第２出力信号、ｐ１　第１端子、ｐ２　第２端子、ｐ３　第３端子、ｐ４　第４端子、ｐ５　第５端子、ｐ６　第６端子、ｐ７　第７端子、ｐ８　第８端子、ｐ９　第９端子、Ｔ１　不平衡端子、Ｔ２，Ｔ３　平衡端子、Ｔ４，Ｔ５　注入抽出端子。 100 carrier amplifier, 101 peak amplifier, 200, 210, 220 synthesis circuit, 201 impedance conversion circuit, 202, 204 distribution circuit, 203 1/4 wavelength transmission line, 205 second harmonic amplitude / phase adjustment circuit, 300 first coupling Transmission line, 301 first transmission line, 302 second transmission line, 310 second coupled transmission line, 311 third transmission line, 312 fourth transmission line, 320 coupled transmission line, 321 first transmission line, 322 second transmission line , 330 transmission line, 340, 405 second harmonic injection extraction circuit, 341, 342 transmission line, 400 balun, 401, 403 phase adjustment line, S1 input signal, S2 first input signal, S3 second input signal, S4 second 1 output signal, S5 second output signal, p1 first terminal, p2 second terminal p3 3rd terminal, p4 4th terminal, p5 5th terminal, p6 6th terminal, p7 7th terminal, p8 8th terminal, p9 9th terminal, T1 unbalanced terminal, T2, T3 balanced terminal, T4, T5 injection Extraction terminal.

Claims (8)

  1. 　入力信号を互いに位相差を有する第１入力信号および第２入力信号に分配する分配回路と、前記第１入力信号を増幅するキャリア増幅器と、前記第２入力信号を増幅するとともに線形動作となる小信号動作時においては出力インピーダンスが開放となるピーク増幅器と、前記キャリア増幅器の出力側に接続されたインピーダンス変換回路と、前記キャリア増幅器で増幅され前記インピーダンス変換回路を介して出力される第１出力信号と前記ピーク増幅器で増幅され出力される第２出力信号とを合成する、バランで構成される合成回路とを備え、前記キャリア増幅器は前記インピーダンス変換回路を介して前記合成回路の一方の平衡端子に接続され、前記ピーク増幅器は前記合成回路の他方の平衡端子に接続されており、前記合成回路の不平衡端子から合成された出力信号が出力されることを特徴とするドハティ増幅器。 A distribution circuit that distributes an input signal to a first input signal and a second input signal having a phase difference from each other, a carrier amplifier that amplifies the first input signal, and a small amplifier that amplifies the second input signal and performs linear operation. A peak amplifier whose output impedance is open during signal operation, an impedance conversion circuit connected to the output side of the carrier amplifier, and a first output signal that is amplified by the carrier amplifier and output via the impedance conversion circuit And a second output signal amplified and output by the peak amplifier, and a synthesis circuit composed of a balun. The carrier amplifier is connected to one balanced terminal of the synthesis circuit via the impedance conversion circuit. Connected, and the peak amplifier is connected to the other balanced terminal of the synthesis circuit. Doherty amplifier, characterized in that the output signal synthesized from 衡端Ko is output.
  2. 　前記合成回路は、基本波周波数に対して１／４波長の長さを有した第１結合伝送線路および第２結合伝送線路を用いて構成されたバランであって、
    前記第１結合伝送線路は、互いに平行に近接して配置された第１伝送線路および第２伝送線路で構成され、前記第１伝送線路は、第１端子および第２端子を有し、前記第２伝送線路は、前記第１端子に対向して第４端子および前記第２端子に対向して第３端子を有しており、
    前記第２結合伝送線路は、互いに平行に近接して配置された第３伝送線路および第４伝送線路で構成され、前記第３伝送線路は、第５端子および第６端子を有し、前記第４伝送線路は、前記第５端子に対向して第８端子および前記第６端子に対向して第７端子を有しており、
    前記第２端子と第５端子と第６端子はグランドに短絡され、前記第４端子と第７端子は互いに接続され、前記第１端子はグランドとの間に不平衡端子を成し、前記第３端子と第８端子はそれぞれ、互いに逆相となる平衡端子を成していることを特徴とする請求項１に記載のドハティ増幅器。     The synthesis circuit is a balun configured using a first coupled transmission line and a second coupled transmission line having a length of ¼ wavelength with respect to a fundamental frequency,
    The first coupled transmission line includes a first transmission line and a second transmission line arranged in parallel and close to each other, the first transmission line having a first terminal and a second terminal, The two transmission lines have a fourth terminal facing the first terminal and a third terminal facing the second terminal,
    The second coupled transmission line includes a third transmission line and a fourth transmission line that are arranged close to each other in parallel, and the third transmission line has a fifth terminal and a sixth terminal, The four transmission lines have an eighth terminal facing the fifth terminal and a seventh terminal facing the sixth terminal,
    The second terminal, the fifth terminal, and the sixth terminal are short-circuited to the ground, the fourth terminal and the seventh terminal are connected to each other, the first terminal forms an unbalanced terminal with the ground, and the first terminal 2. The Doherty amplifier according to claim 1, wherein each of the third terminal and the eighth terminal forms a balanced terminal having a phase opposite to each other.
  3. 　前記合成回路は、基本波周波数に対して１／４波長の長さを有する結合伝送線路と１／４波長の長さを有する伝送線路とを用いて構成されたバランであって、
    前記結合伝送線路は、互いに平行に近接して配置された第１伝送線路および第２伝送線路で構成され、前記第１伝送線路は、第１端子および第２端子を有し、前記第２伝送線路は、前記第１端子に対向する第４端子および前記第２端子に対向する第３端子を有しており、
    前記伝送線路は、第７端子および第８端子を有しており、
    前記第２端子はグランドに短絡され、前記第４端子と第７端子は互いに接続され、前記第１端子はグランドとの間に不平衡端子を成し、前記第３端子と第８端子はそれぞれ、互いに逆相となる平衡端子を成していることを特徴とする請求項1に記載のドハティ増幅器。     The combining circuit is a balun configured using a coupled transmission line having a length of ¼ wavelength with respect to a fundamental frequency and a transmission line having a length of ¼ wavelength,
    The coupled transmission line includes a first transmission line and a second transmission line arranged close to each other in parallel, and the first transmission line has a first terminal and a second terminal, and the second transmission line The line has a fourth terminal facing the first terminal and a third terminal facing the second terminal,
    The transmission line has a seventh terminal and an eighth terminal,
    The second terminal is short-circuited to the ground, the fourth terminal and the seventh terminal are connected to each other, the first terminal forms an unbalanced terminal with the ground, and the third terminal and the eighth terminal are respectively 2. The Doherty amplifier according to claim 1, wherein the Doherty amplifiers are balanced terminals that are out of phase with each other.
  4. 　前記インピーダンス変換回路は、あらかじめ決められた特性インピーダンスを有するとともに基本波周波数に対して１／４波長の長さを有する１／４波長伝送線路で構成されていることを特徴とする請求項１から請求項３のいずれか一項に記載のドハティ増幅器。 2. The impedance conversion circuit includes a quarter wavelength transmission line having a predetermined characteristic impedance and a length of a quarter wavelength with respect to a fundamental frequency. The Doherty amplifier according to claim 3.
  5. 　前記合成回路は、２次高調波を注入もしくは抽出する注入抽出端子を有する２次高調波注入抽出回路が装荷されたバランで構成されていることを特徴とする請求項１から請求項４のいずれか一項に記載のドハティ増幅器。 5. The synthesizer circuit includes a balun loaded with a second harmonic injection extraction circuit having an injection extraction terminal for injecting or extracting a second harmonic. A Doherty amplifier according to any one of the preceding claims.
  6. 　前記分配回路は、２次高調波を注入もしくは抽出する注入抽出端子を有する２次高調波注入抽出回路を装荷したバランと位相調整線路とから構成されていることを特徴とする請求項１から請求項４のいずれか一項に記載のドハティ増幅器。 2. The distribution circuit according to claim 1, wherein the distribution circuit includes a balun loaded with a second harmonic injection extraction circuit having an injection extraction terminal for injecting or extracting a second harmonic and a phase adjustment line. Item 5. The Doherty amplifier according to any one of Items 4 to 5.
  7. 　前記合成回路は、２次高調波を注入もしくは抽出する注入抽出端子を有する２次高調波注入抽出回路が装荷されたバランで構成され、前記分配回路は、２次高調波を注入もしくは抽出する注入抽出端子を有する２次高調波注入抽出回路を装荷したバランと位相調整線路とから構成されていることを特徴とする請求項１から請求項４のいずれか一項に記載のドハティ増幅器。 The synthesis circuit is composed of a balun loaded with a second harmonic injection extraction circuit having an injection extraction terminal for injecting or extracting a second harmonic, and the distribution circuit is an injection for injecting or extracting the second harmonic. 5. The Doherty amplifier according to claim 1, comprising a balun loaded with a second harmonic injection extraction circuit having an extraction terminal and a phase adjustment line.
  8. 　前記合成回路の２次高調波を注入もしくは抽出する注入抽出端子と、前記分配回路の２次高調波を注入もしくは抽出する注入抽出端子との間に、２次高調波の振幅と位相を調整する２次高調波振幅・位相調整回路が装荷されていることを特徴とする請求項７に記載のドハティ増幅器。 The amplitude and phase of the second harmonic are adjusted between the injection extraction terminal for injecting or extracting the second harmonic of the synthesis circuit and the injection extraction terminal for injecting or extracting the second harmonic of the distribution circuit. The Doherty amplifier according to claim 7, wherein a second harmonic amplitude / phase adjustment circuit is loaded.
PCT/JP2016/087584 2016-12-16 2016-12-16 Doherty amplifier WO2018109930A1 (en)

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WO2022259892A1 (en) * 2021-06-10 2022-12-15 株式会社村田製作所 Amplification circuit and high-frequency circuit
WO2023127435A1 (en) * 2021-12-28 2023-07-06 株式会社村田製作所 Power amplification circuit and power amplification module

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WO2022255389A1 (en) * 2021-06-02 2022-12-08 株式会社村田製作所 High frequency module and communication device
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