WO2018105336A1 - Resistivity measuring method - Google Patents

Resistivity measuring method Download PDF

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WO2018105336A1
WO2018105336A1 PCT/JP2017/041005 JP2017041005W WO2018105336A1 WO 2018105336 A1 WO2018105336 A1 WO 2018105336A1 JP 2017041005 W JP2017041005 W JP 2017041005W WO 2018105336 A1 WO2018105336 A1 WO 2018105336A1
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resistivity
bias voltage
mercury
semiconductor single
single crystal
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PCT/JP2017/041005
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French (fr)
Japanese (ja)
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史高 久米
光義 船木
久寿 樫野
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信越半導体株式会社
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Publication of WO2018105336A1 publication Critical patent/WO2018105336A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant

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  • the present invention relates to a resistivity measuring method, and more particularly to a resistivity measuring method by a CV method.
  • a CV (capacitance-voltage) method using mercury as an electrode is known.
  • a Schottky junction is formed by bringing a mercury electrode into contact with the surface of a semiconductor single crystal wafer such as a silicon epitaxial layer, and the reverse bias voltage is continuously changed from 1 V, for example, to the mercury electrode.
  • the depletion layer is expanded inside the semiconductor single crystal wafer to change its capacity.
  • the dopant concentration at the desired depth is calculated from the relationship between the reverse bias voltage and the capacitance, and the dopant concentration is converted into the resistivity using a conversion formula such as ASTM STANDARDS F723.
  • ASTM STANDARDS F723 converting the dopant concentration to resistivity using the conversion formula of ASTM STANDARDS F723 is simply referred to as ASTM conversion.
  • Patent Document 1 discloses that static electricity is eliminated.
  • the same surface of the main surface of the semiconductor single crystal wafer is used for daily management of the resistivity measurement device or for re-measurement of the resistivity for product guarantee. If the position is measured several times in succession, the resistivity tends to decrease gradually or increase gradually.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a resistivity measurement method by the CV method that can more reliably measure the resistivity of a semiconductor single crystal wafer. .
  • the present invention provides a mercury electrode forming step in which mercury is brought into contact with a semiconductor single crystal wafer to form a mercury electrode, a forward bias voltage applying step of applying a forward bias voltage to the mercury electrode, A CV measurement step of measuring the capacitance of the semiconductor single crystal wafer that changes by applying a reverse bias voltage to the mercury electrode, and a resistivity calculation step of calculating a resistivity from the relationship between the reverse bias voltage and the capacitance.
  • a resistivity measurement method is provided.
  • the forward bias refers to applying a voltage in a direction in which a current flows between a semiconductor single crystal wafer forming a Schottky junction and a mercury electrode.
  • the charge accumulated between the mercury electrode and the semiconductor single crystal wafer is canceled by the reverse charge supplied by the forward bias and disappears, so that the resistivity can be measured more accurately and accurately. It is possible to measure resistivity with good characteristics.
  • the applied amount of the forward bias voltage is increased as the resistivity of the semiconductor single crystal wafer is lower.
  • the resistivity measurement with better reproducibility can be achieved by adjusting the forward bias voltage application amount as described above. Can do.
  • the resistivity measuring method of the present invention it is possible to reduce the tendency of the resistivity that becomes apparent when the semiconductor single crystal wafer is continuously measured CV multiple times to gradually decrease or gradually increase.
  • the resistivity of the semiconductor single crystal wafer can be measured more reliably.
  • FIG. 1 is a schematic explanatory diagram when a forward bias is applied to a semiconductor single crystal wafer, where (1) is a state in which a forward bias is applied to a semiconductor single crystal wafer where charge remains, and (2) is the thickness of a depletion layer after forward bias is applied. (3) shows a state in which a depletion layer having a normal level thickness is formed.
  • FIG. 1 is a schematic process diagram showing an example of the resistivity measurement method of the present invention.
  • the mercury electrode formation process (process a), the forward bias voltage application process (process b), and the CV measurement process (process c).
  • the resistivity calculation step (step d) indicate that the present invention performs in this order.
  • FIG. 2 is a schematic view showing a mercury probe 10 as an example of a CV method measuring apparatus used in the resistivity measuring method of the present invention.
  • the semiconductor single crystal wafer 1 for example, mercury 31 and 32 stored in the storage containers 12 and 13 are guided upward from below to the main surface of a silicon epitaxial wafer in which a silicon epitaxial layer is formed on a silicon single crystal substrate. Contact with each other to form mercury electrodes 33 and 34, and CV measurement is performed to obtain the resistivity.
  • the semiconductor single crystal wafer 1 other than silicon can be applied to the resistivity measurement of a compound semiconductor single crystal wafer such as GaP, GaN, SiC.
  • the semiconductor single crystal wafer 1 is held on the stage 11 with its main surface to be measured facing downward, and is placed above the mercury electrodes 33 and 34.
  • mercury 31 and 32 stored in the storage containers 12 and 13 rise through the conduits 15 and 16 and come into contact with the main surface of the semiconductor single crystal wafer 1.
  • a reverse bias voltage V is applied to the mercury electrode 34, while the mercury electrode 33 is connected to the ground 61.
  • mercury 31 and 32 used as electrodes are contaminated by particles adhering to the main surface of the semiconductor single crystal wafer 1 every time they come into contact with the semiconductor single crystal wafer 1, the resistance of the mercury 31 and 32 gradually increases. Adversely affects the measured values of the physical characteristics. In order to prevent this, the mercury 31, 32 that has contacted the semiconductor single crystal wafer 1 is temporarily returned to the storage containers 12, 13, and the entire mercury 31, 32 is bubbled and cleaned, and then the mercury 31, 32 is used again for the electrodes. Supply.
  • the mercury 31 and 32 rub against the inner walls of the storage containers 12 and 13 to generate static electricity.
  • the storage containers 12 and 13 are made of, for example, polycarbonate, they are charged to the-(minus) electrode.
  • mercury 31 and 32 are charged to the + (plus) electrode.
  • the mercury 31, 32 rises through the conduits 15, 16, the mercury 31, 32 rubs against the inner walls of the conduits 15, 16 and generates static electricity.
  • the conduits 15 and 16 are made of, for example, Teflon (registered trademark), they are charged to the-(minus) electrode.
  • mercury 31 and 32 are charged to the + (plus) electrode.
  • the storage containers 12 and 13 are connected to the ground wires 52 and 54 via the conductive rubber sheets 41 and 42 covering the storage containers 12 and 13.
  • the conduits 15 and 16 are connected to the ground wires 51 and 53 through conductive rubber sheets 43 and 44 covering the conduits 15 and 16.
  • the conductive rubber sheets 41, 42, 43, 44 are mixed with a conductive material such as carbon or silver and have a low resistivity of about 0.008 ⁇ ⁇ cm. Static electricity generated in the conduits 15 and 16 can be easily absorbed and escaped to the ground wires 51, 52, 53 and 54 connected to the grounds 62 and 63.
  • a CV characteristic measurement system 100 for measuring resistivity shown in FIG. 3 includes a mercury prober 130 (mercury prober 10 in FIG. 2) that contacts the semiconductor single crystal wafer 1 using mercury 31 and 32 as electrodes, and the mercury.
  • a high frequency is supplied via measurement cables 161 and 162 connected to the prober 130, a forward bias voltage is applied, and then a reverse bias voltage is applied to the semiconductor single crystal wafer 1 to form a depletion layer and the depletion layer.
  • a reverse bias voltage V is applied to the mercury electrode 34 formed with a Schottky junction with the semiconductor single crystal wafer 1 placed in the mercury prober 130 using the LCR meter 140.
  • the capacitance C is measured by the LCR meter 140 while changing the capacitance C by expanding the depletion layer inside the semiconductor single crystal wafer 1 while changing the capacitance C continuously.
  • the resistivity is calculated from the relationship between the reverse bias voltage V and the capacitance C of the depletion layer.
  • the timing for applying the forward bias voltage may be before or after the reverse bias voltage V is applied.
  • setting the timing for applying the forward bias voltage after applying the reverse bias voltage V applies the forward bias voltage.
  • the timing is set before the application of the next reverse bias voltage V. Therefore, once the reverse bias voltage V is applied and the CV measurement process is performed, the charge accumulated between the mercury electrode and the wafer can be removed by the subsequent forward bias voltage application process. Then, since the next CV measurement is performed, it is possible to prevent the charge from accumulating and the resistivity from gradually increasing / decreasing as in the conventional method.
  • FIG. 6 illustrates resistivity fluctuations when the forward bias voltage is not applied (conventional method) and when it is applied (the present invention) when the resistivity of the P-type silicon epitaxial layer is repeatedly measured.
  • the forward bias voltage is applied from -1V to -18V while increasing the absolute value at 1V intervals, and then the reverse bias voltage V is applied while increasing from + 1V to + 15V at 1V intervals. Measurements were made.
  • the forward bias voltage When the forward bias voltage is not applied, the resistivity gradually decreases, whereas when the forward bias voltage is applied, the resistivity can be made substantially constant.
  • the forward bias voltage application method does not necessarily need to gradually increase the absolute value to the desired voltage. For example, a constant voltage may be applied as the forward bias.
  • the amount of forward bias voltage to be applied is preferably increased as the resistivity of the semiconductor single crystal wafer 1 is lower.
  • FIG. 7A shows the relationship between the resistivity of the P-type silicon epitaxial layer and the forward bias voltage
  • FIG. 7B shows the relationship between the resistivity of the N-type silicon epitaxial layer and the forward bias voltage.
  • the applied amount of the forward bias voltage is repeated at the same position even if it is smaller than the value obtained from the relationship shown in FIGS. 7A and 7B or constant regardless of the resistivity. It is possible to suppress a tendency that the resistivity when the CV measurement is performed gradually increases (or decreases).
  • a negative ( ⁇ ) voltage, N is applied to the mercury electrode 34 formed by bringing the semiconductor single crystal wafer 1 and the mercury 32 into contact with each other to form a Schottky junction.
  • a positive (+) voltage is applied as a forward bias (FIG. 8 (1)).
  • the semiconductor single crystal wafer 1 Since the semiconductor single crystal wafer 1 has a higher impurity concentration as the resistivity is lower, more charges are likely to remain on the mercury electrode 34 in contact with the semiconductor single crystal wafer 1. Therefore, it is desirable to increase the amount of forward bias voltage applied as the resistivity of the semiconductor single crystal wafer 1 is lower.
  • step a mercury is brought into contact with a semiconductor wafer to form a mercury electrode (mercury electrode forming step) (step a). Then, after the forward bias voltage application step (step b) to the semiconductor single crystal wafer 1 is completed, the reverse bias voltage V is applied to the mercury electrode 34 while continuously changing using the LCR meter 140, and the semiconductor single crystal A CV measurement step (step c) is performed in which a depletion layer is expanded inside the wafer 1 to change the capacitance C, and the capacitance C is measured by the LCR meter 140.
  • the forward bias voltage application step (step b) may be performed after the CV measurement step (step c). In this case, as described above, the forward bias voltage application step (step b) is performed after the CV measurement step (step c) before the next CV measurement step (step c) at the same position. A forward bias voltage application step (step b) is performed.
  • a resistivity calculation step (step d) is performed in which the resistivity is calculated from the relationship between the reverse bias voltage V and the depletion layer capacitance C.
  • a CV characteristic is obtained.
  • the reverse bias voltage and the capacity into the following formulas (1) and (2), for example, the depth W in the semiconductor single crystal wafer 1 and the dopant concentration N (W) at the depth W are calculated. Therefore, a dopant concentration profile in the depth direction can be obtained.
  • W A ⁇ 0 ⁇ Si / C (1)
  • N (W) 2 / (q ⁇ 0 ⁇ Si A 2 ) ⁇ ⁇ d (C ⁇ 2 ) / dV ⁇ ⁇ 1 (2)
  • A is the electrode area
  • ⁇ 0 is the vacuum dielectric constant
  • ⁇ Si is the relative dielectric constant of Si
  • q is the charge amount of electrons.
  • the dopant concentration at that depth is obtained.
  • the dopant concentration can be converted to resistivity by converting the obtained dopant concentration by a conversion formula such as ASTM STANDARDDS F723.
  • Example 1 The resistivity measurement method of the present invention was implemented. Specifically, (Step a) to (Step d) shown in FIG. 1 were repeated.
  • the P-type silicon epitaxial layer 1 having a resistivity of about 0.9 ⁇ cm is subjected to CV measurement five times using the mercury probe 10 shown in FIG. 2, the absolute value is increased at intervals of 1V from ⁇ 1V to ⁇ 18V each time.
  • the resistivity was measured by applying the reverse bias voltage V while increasing it from 1V to + 15V at 1V intervals.
  • the CV value (coefficient of variation) obtained by dividing the standard deviation ⁇ by the average value of the measured values was 0.03%.
  • Example 1 The P-type silicon epitaxial layer 1 having a resistivity of about 0.9 ⁇ cm used in the measurement in Example 1 was subjected to CV measurement five times without applying a forward bias voltage as in the conventional method to obtain the resistivity. . As a result, the CV value was 0.15%.
  • the resistivity measurement method of the present invention by applying a forward bias voltage, the charge accumulated between the mercury electrode and the semiconductor single crystal wafer can be removed when a reverse bias voltage is applied.
  • the thickness of the depletion layer formed in the single crystal wafer can be maintained at a normal level, and the tendency of the resistivity to gradually decrease or gradually increase can be suppressed. As a result, it is possible to improve the repeatability measurement accuracy of the resistivity.
  • the present invention is not limited to the above embodiment.
  • the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

The present invention provides a resistivity measuring method comprising: a mercury electrode forming step of forming a mercury electrode by bringing mercury into contact with a semiconductor single crystalline wafer; a forward bias voltage application step of applying a forward bias voltage to the mercury electrode; a C-V measuring step of applying a reverse bias voltage to the mercury electrode, and measuring a varying capacitance of the semiconductor single crystalline wafer; and a resistivity computing step of computing a resistivity on the basis of a relationship between the reverse bias voltage and the capacitance. In this way, a resistivity measuring method using a C-V technique is provided by which the resistivity of a semiconductor single crystalline wafer can be more reliably measured.

Description

抵抗率測定方法Resistivity measurement method
 本発明は抵抗率測定方法に関し、より詳しくは、C-V法による抵抗率測定方法に関する。 The present invention relates to a resistivity measuring method, and more particularly to a resistivity measuring method by a CV method.
 従来、抵抗率を測定する方法の一つに、電極として水銀を用いるC-V(capacitance - voltage)法が知られている。電極として水銀を用いるC-V法では、シリコンエピタキシャル層等の半導体単結晶ウェーハの表面に水銀電極を接触させてショットキー接合を形成し、水銀電極に逆バイアス電圧を例えば1Vから連続的に変化させながら印加することにより半導体単結晶ウェーハの内部に空乏層を拡げてその容量を変化させる。 Conventionally, as one of methods for measuring resistivity, a CV (capacitance-voltage) method using mercury as an electrode is known. In the CV method using mercury as an electrode, a Schottky junction is formed by bringing a mercury electrode into contact with the surface of a semiconductor single crystal wafer such as a silicon epitaxial layer, and the reverse bias voltage is continuously changed from 1 V, for example, to the mercury electrode. When applied, the depletion layer is expanded inside the semiconductor single crystal wafer to change its capacity.
 そして、逆バイアス電圧と容量の関係から所望深さにおけるドーパント濃度を算出し、さらにASTM STANDARDS F723等の換算式を用いて、ドーパント濃度を抵抗率に換算する。以下、ASTM STANDARDS F723の換算式を用いてドーパント濃度を抵抗率に換算することを単にASTM換算という。 Then, the dopant concentration at the desired depth is calculated from the relationship between the reverse bias voltage and the capacitance, and the dopant concentration is converted into the resistivity using a conversion formula such as ASTM STANDARDS F723. Hereinafter, converting the dopant concentration to resistivity using the conversion formula of ASTM STANDARDS F723 is simply referred to as ASTM conversion.
 水銀電極を用いて半導体単結晶ウェーハの電気的特性を繰返し測定する際に、再現性の向上した電気的特性を得るため、水銀溜めや水銀の導管をアースし、水銀が移動する際に発生する静電気を除電することが特許文献1に開示されている。 When measuring the electrical characteristics of a semiconductor single crystal wafer repeatedly using a mercury electrode, this occurs when mercury moves to ground the mercury reservoir or mercury conduit in order to obtain electrical characteristics with improved reproducibility. Patent Document 1 discloses that static electricity is eliminated.
特開2015-99833号公報JP-A-2015-99833
 例えば、電極として水銀を用いるC-V法による抵抗率測定方法において、その抵抗率測定装置を日常管理するため、あるいは製品保証用の抵抗率を再測定するため、半導体単結晶ウェーハ主表面の同じ位置を複数回連続して測定すると、抵抗率がしだいに低くなったり、しだいに高くなったりする傾向がある。 For example, in the resistivity measurement method by the CV method using mercury as an electrode, the same surface of the main surface of the semiconductor single crystal wafer is used for daily management of the resistivity measurement device or for re-measurement of the resistivity for product guarantee. If the position is measured several times in succession, the resistivity tends to decrease gradually or increase gradually.
 本発明は上記課題を解決するために為されたものであり、半導体単結晶ウェーハの抵抗率をより確実に測定することができるC-V法による抵抗率測定方法を提供することを目的とする。 The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a resistivity measurement method by the CV method that can more reliably measure the resistivity of a semiconductor single crystal wafer. .
 上記目的を達成するために、本発明は、半導体単結晶ウェーハに水銀を接触させて水銀電極となす水銀電極形成工程と、前記水銀電極に順バイアス電圧を印加する順バイアス電圧印加工程と、前記水銀電極に逆バイアス電圧を印加して変化する前記半導体単結晶ウェーハの容量を測定するC-V測定工程と、前記逆バイアス電圧と前記容量の関係から抵抗率を演算する抵抗率演算工程とを有することを特徴とする抵抗率測定方法を提供する。
 なお、本発明において順バイアスとは、ショットキー接合を形成する半導体単結晶ウェーハと水銀電極の間に、電流が流れる方向に電圧を印加することである。
To achieve the above object, the present invention provides a mercury electrode forming step in which mercury is brought into contact with a semiconductor single crystal wafer to form a mercury electrode, a forward bias voltage applying step of applying a forward bias voltage to the mercury electrode, A CV measurement step of measuring the capacitance of the semiconductor single crystal wafer that changes by applying a reverse bias voltage to the mercury electrode, and a resistivity calculation step of calculating a resistivity from the relationship between the reverse bias voltage and the capacitance. A resistivity measurement method is provided.
In the present invention, the forward bias refers to applying a voltage in a direction in which a current flows between a semiconductor single crystal wafer forming a Schottky junction and a mercury electrode.
 これにより、水銀電極と半導体単結晶ウェーハとの間に溜まった電荷が順バイアスにより供給される逆の電荷により打ち消されて消滅するので、抵抗率をより確実に精度よく測定することができ、再現性の良い抵抗率測定ができる。 As a result, the charge accumulated between the mercury electrode and the semiconductor single crystal wafer is canceled by the reverse charge supplied by the forward bias and disappears, so that the resistivity can be measured more accurately and accurately. It is possible to measure resistivity with good characteristics.
 このとき、前記順バイアス電圧の印加量は、前記半導体単結晶ウェーハの抵抗率が低いほど大きくすることが望ましい。 At this time, it is desirable that the applied amount of the forward bias voltage is increased as the resistivity of the semiconductor single crystal wafer is lower.
 抵抗率が低いほど不純物濃度が高く、半導体単結晶ウェーハと水銀電極との間に電荷がたまりやすいため、上記のように順バイアス電圧の印加量を調整すれば、より再現性の良い抵抗率測定ができる。 The lower the resistivity, the higher the impurity concentration and the more likely the electric charge is to accumulate between the semiconductor single crystal wafer and the mercury electrode. Therefore, the resistivity measurement with better reproducibility can be achieved by adjusting the forward bias voltage application amount as described above. Can do.
 本発明の抵抗率測定方法によると、半導体単結晶ウェーハを複数回連続してC-V測定する際に顕在化する抵抗率がしだいに低くなったり、しだいに高くなったりする傾向を低減できるので、半導体単結晶ウェーハの抵抗率をより確実に測定することができる。 According to the resistivity measuring method of the present invention, it is possible to reduce the tendency of the resistivity that becomes apparent when the semiconductor single crystal wafer is continuously measured CV multiple times to gradually decrease or gradually increase. The resistivity of the semiconductor single crystal wafer can be measured more reliably.
本発明の抵抗率測定方法の一例を示す概略工程図である。It is a schematic process drawing which shows an example of the resistivity measuring method of this invention. 本発明の抵抗率測定方法に用いられるC-V法測定装置の一例の水銀プローバを示す概略図である。It is the schematic which shows the mercury probe of an example of the CV method measuring apparatus used for the resistivity measuring method of this invention. 本発明の抵抗率測定方法に用いられるC-V特性測定システムである。It is a CV characteristic measurement system used for the resistivity measurement method of the present invention. 従来法によりP型シリコンエピタキシャル層の抵抗率を繰り返しC-V測定して求める際に現れる傾向である。This tendency appears when the resistivity of the P-type silicon epitaxial layer is repeatedly obtained by CV measurement by the conventional method. 従来法によりN型シリコンエピタキシャル層の抵抗率を繰り返しC-V測定して求める際に現れる傾向である。This tendency appears when the resistivity of the N-type silicon epitaxial layer is repeatedly obtained by CV measurement by the conventional method. P型シリコンエピタキシャル層の抵抗率を繰り返しC-V測定して求める際、順バイアス電圧を印加しない場合と印加する場合の抵抗率変動の例示である。When determining the resistivity of a P-type silicon epitaxial layer by repeatedly measuring CV, it is an example of resistivity variation when a forward bias voltage is not applied and when it is applied. (a)P型シリコンエピタキシャル層の抵抗率と順バイアス電圧の関係の例示である。(b)N型シリコンエピタキシャル層の抵抗率と順バイアス電圧の関係の例示である。(A) It is an illustration of the relationship between the resistivity of a P-type silicon epitaxial layer, and a forward bias voltage. (B) It is an illustration of the relationship between the resistivity of an N type silicon epitaxial layer, and a forward bias voltage. 半導体単結晶ウェーハに順バイアスを印加する際の概略説明図で、(1)は電荷が残存する半導体単結晶ウェーハに順バイアスを印加する状態、(2)は順バイアス印加後に空乏層の厚さが正常なレベルに戻った状態、(3)は正常レベル厚さの空乏層が形成された状態を示す。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic explanatory diagram when a forward bias is applied to a semiconductor single crystal wafer, where (1) is a state in which a forward bias is applied to a semiconductor single crystal wafer where charge remains, and (2) is the thickness of a depletion layer after forward bias is applied. (3) shows a state in which a depletion layer having a normal level thickness is formed.
 以下に、本発明の実施形態を図面に基づいて説明する。図1は、本発明の抵抗率測定方法の一例を示す概略工程図であり、水銀電極形成工程(工程a)と、順バイアス電圧印加工程(工程b)と、C-V測定工程(工程c)と、抵抗率演算工程(工程d)とを本発明がこの順に行うことを示す。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic process diagram showing an example of the resistivity measurement method of the present invention. The mercury electrode formation process (process a), the forward bias voltage application process (process b), and the CV measurement process (process c). ) And the resistivity calculation step (step d) indicate that the present invention performs in this order.
 図2は、本発明の抵抗率測定方法に用いられるC-V法測定装置の一例の水銀プローバ10を示す概略図である。半導体単結晶ウェーハ1として例えばシリコン単結晶基板上にシリコンエピタキシャル層が形成されてなるシリコンエピタキシャルウェーハの主表面に、収納容器12,13に収納された水銀31,32を下方から上方向に導くとともに接触させて水銀電極33,34となしてC-V測定して抵抗率を求める。シリコン以外の半導体単結晶ウェーハ1として、GaP、GaN、SiC等の化合物半導体単結晶ウェーハの抵抗率測定に適用できる。 FIG. 2 is a schematic view showing a mercury probe 10 as an example of a CV method measuring apparatus used in the resistivity measuring method of the present invention. As the semiconductor single crystal wafer 1, for example, mercury 31 and 32 stored in the storage containers 12 and 13 are guided upward from below to the main surface of a silicon epitaxial wafer in which a silicon epitaxial layer is formed on a silicon single crystal substrate. Contact with each other to form mercury electrodes 33 and 34, and CV measurement is performed to obtain the resistivity. The semiconductor single crystal wafer 1 other than silicon can be applied to the resistivity measurement of a compound semiconductor single crystal wafer such as GaP, GaN, SiC.
 図2に示す水銀プローバ10において、半導体単結晶ウェーハ1は、測定されるその主表面を下向きにしてステージ11に保持され、水銀電極33,34の上方に載置される。C-V測定して抵抗率を求める際、収納容器12,13に収納された水銀31,32は、導管15,16内を通って上昇し、半導体単結晶ウェーハ1の主表面に接触することによりショットキー接合を形成して水銀電極33,34となる。水銀電極34には逆バイアス電圧Vが印加される一方、水銀電極33はアース61に接続される。 In the mercury prober 10 shown in FIG. 2, the semiconductor single crystal wafer 1 is held on the stage 11 with its main surface to be measured facing downward, and is placed above the mercury electrodes 33 and 34. When the resistivity is obtained by CV measurement, mercury 31 and 32 stored in the storage containers 12 and 13 rise through the conduits 15 and 16 and come into contact with the main surface of the semiconductor single crystal wafer 1. To form mercury electrodes 33 and 34. A reverse bias voltage V is applied to the mercury electrode 34, while the mercury electrode 33 is connected to the ground 61.
 電極として用いる水銀31,32が半導体単結晶ウェーハ1に接触する度に該半導体単結晶ウェーハ1の主表面に付着したパーティクルにより汚染されると、水銀31,32の抵抗がしだいに高くなり、電気的特性の測定値に悪影響を及ぼすようになる。これを防止するため、半導体単結晶ウェーハ1に接触した水銀31,32を収納容器12,13に一旦戻し、水銀31,32全体をバブリングして清浄化した後に水銀31,32を電極用に再び供給する。 When mercury 31 and 32 used as electrodes are contaminated by particles adhering to the main surface of the semiconductor single crystal wafer 1 every time they come into contact with the semiconductor single crystal wafer 1, the resistance of the mercury 31 and 32 gradually increases. Adversely affects the measured values of the physical characteristics. In order to prevent this, the mercury 31, 32 that has contacted the semiconductor single crystal wafer 1 is temporarily returned to the storage containers 12, 13, and the entire mercury 31, 32 is bubbled and cleaned, and then the mercury 31, 32 is used again for the electrodes. Supply.
 このバブリングを行うとき、水銀31,32は収納容器12,13の内壁と擦れて静電気を発生する。収納容器12,13が例えばポリカーボネート製の場合、-(マイナス)極に帯電する。これに対し、水銀31,32は+(プラス)極に帯電する。 When performing this bubbling, the mercury 31 and 32 rub against the inner walls of the storage containers 12 and 13 to generate static electricity. When the storage containers 12 and 13 are made of, for example, polycarbonate, they are charged to the-(minus) electrode. On the other hand, mercury 31 and 32 are charged to the + (plus) electrode.
 また、水銀31,32が導管15,16内を通って上昇するとき、水銀31,32は導管15,16の内壁と擦れて静電気を発生する。導管15,16が例えばテフロン(登録商標)製の場合、-(マイナス)極に帯電する。これに対し、水銀31,32は+(プラス)極に帯電する。 Further, when the mercury 31, 32 rises through the conduits 15, 16, the mercury 31, 32 rubs against the inner walls of the conduits 15, 16 and generates static electricity. When the conduits 15 and 16 are made of, for example, Teflon (registered trademark), they are charged to the-(minus) electrode. On the other hand, mercury 31 and 32 are charged to the + (plus) electrode.
 そのため、収納容器12、13は、該収納容器12、13を被覆する導電性ゴムシート41,42を介してアース線52,54に接続される。また、導管15,16は該導管15,16を被覆する導電性ゴムシート43,44を介してアース線51,53に接続される。導電性ゴムシート41,42,43,44には、例えばカーボンや銀などの導電性材料が配合されており、0.008Ω・cm程度の低抵抗率であるために、収納容器12,13や導管15,16に発生する静電気を容易に吸収し、アース62,63に接続するアース線51,52,53,54に逃がすことができる。 Therefore, the storage containers 12 and 13 are connected to the ground wires 52 and 54 via the conductive rubber sheets 41 and 42 covering the storage containers 12 and 13. The conduits 15 and 16 are connected to the ground wires 51 and 53 through conductive rubber sheets 43 and 44 covering the conduits 15 and 16. The conductive rubber sheets 41, 42, 43, 44 are mixed with a conductive material such as carbon or silver and have a low resistivity of about 0.008 Ω · cm. Static electricity generated in the conduits 15 and 16 can be easily absorbed and escaped to the ground wires 51, 52, 53 and 54 connected to the grounds 62 and 63.
 図3に示す抵抗率を測定するためのC-V特性測定システム100は、水銀31,32を電極として半導体単結晶ウェーハ1に接触させる水銀プローバ130(図2の水銀プローバ10)と、該水銀プローバ130に連結された測定ケーブル161,162を介して高周波を供給し、順バイアス電圧を印加した後に、半導体単結晶ウェーハ1に逆バイアス電圧を印加することにより空乏層を形成させるとともに該空乏層の容量を計測するLCRメータ140と、該LCRメータ140にGPIB(General Purpose Interface Bus)ケーブル163を介して接続されたPC(パーソナルコンピューター)150にインストールされ、逆バイアス電圧と空乏層の容量から抵抗率を算出する解析ソフトとを有する。 A CV characteristic measurement system 100 for measuring resistivity shown in FIG. 3 includes a mercury prober 130 (mercury prober 10 in FIG. 2) that contacts the semiconductor single crystal wafer 1 using mercury 31 and 32 as electrodes, and the mercury. A high frequency is supplied via measurement cables 161 and 162 connected to the prober 130, a forward bias voltage is applied, and then a reverse bias voltage is applied to the semiconductor single crystal wafer 1 to form a depletion layer and the depletion layer. LCR meter 140 for measuring the capacitance of the device, and a PC (personal computer) 150 connected to the LCR meter 140 via a GPIB (General Purpose Interface Bus) cable 163, the resistance from the reverse bias voltage and the capacitance of the depletion layer Analysis software for calculating rates
 半導体単結晶ウェーハ1の抵抗率を測定する際は、水銀プローバ130内に載置した半導体単結晶ウェーハ1とショットキー接合を形成した水銀電極34に、LCRメータ140を用いて逆バイアス電圧Vを連続的に変化させながら印加し、半導体単結晶ウェーハ1の内部に空乏層を拡げて容量Cを変化させつつ、その容量CをLCRメータ140により計測する。そして、PC150にインストールされた解析ソフトを用いて、逆バイアス電圧Vと空乏層の容量Cの関係から抵抗率を算出する。 When measuring the resistivity of the semiconductor single crystal wafer 1, a reverse bias voltage V is applied to the mercury electrode 34 formed with a Schottky junction with the semiconductor single crystal wafer 1 placed in the mercury prober 130 using the LCR meter 140. The capacitance C is measured by the LCR meter 140 while changing the capacitance C by expanding the depletion layer inside the semiconductor single crystal wafer 1 while changing the capacitance C continuously. Then, using the analysis software installed in the PC 150, the resistivity is calculated from the relationship between the reverse bias voltage V and the capacitance C of the depletion layer.
 図2と同様な水銀プローバ10を用い、従来法により半導体単結晶ウェーハ1として、例えばシリコン単結晶基板上に形成されたP型シリコンエピタキシャル層の抵抗率を繰り返し測定すると(同じ位置でC-V測定を繰り返し、抵抗率を求めると)、図4に示すように、抵抗率がしだいに低くなる傾向がある。また、N型シリコンエピタキシャル層の抵抗率を繰り返し測定すると、図5に示すように、抵抗率がしだいに高くなる傾向がある。これは、抵抗率測定を繰り返す度、すなわち逆バイアス電圧Vを印加する度に、水銀プローバ10の水銀電極34と半導体単結晶ウェーハ1の間に、電荷が蓄積していくためと考えられる。 When the resistivity of a P-type silicon epitaxial layer formed on, for example, a silicon single crystal substrate is repeatedly measured as a semiconductor single crystal wafer 1 by a conventional method using a mercury probe 10 similar to that of FIG. 2 (CV at the same position). When the measurement is repeated to obtain the resistivity), the resistivity tends to gradually decrease as shown in FIG. Further, when the resistivity of the N-type silicon epitaxial layer is repeatedly measured, the resistivity tends to gradually increase as shown in FIG. This is presumably because charge is accumulated between the mercury electrode 34 of the mercury probe 10 and the semiconductor single crystal wafer 1 every time the resistivity measurement is repeated, that is, every time the reverse bias voltage V is applied.
 そこで、本発明では、順バイアス電圧を印加することにより、逆バイアス電圧Vを印加する際に水銀電極34と半導体単結晶ウェーハ1の間に蓄積される電荷を除去する。順バイアス電圧を印加するタイミングは、逆バイアス電圧Vを印加する前でも後でもよい。半導体単結晶ウェーハに水銀電極を接触させて、同じ位置で繰り返しC-V測定を行う場合、順バイアス電圧を印加するタイミングを逆バイアス電圧Vの印加後に設定することは、順バイアス電圧を印加するタイミングをその次の逆バイアス電圧Vの印加前に設定することになる。従って、一旦逆バイアス電圧Vを印加してC-V測定工程を行い、水銀電極とウェーハの間に蓄積される電荷を、その後の順バイアス電圧印加工程により除去することができる。そして、次のC-V測定を行うことになるので、従来法のように電荷が蓄積して抵抗率が漸増・漸減するのを防ぐことができる。 Therefore, in the present invention, by applying a forward bias voltage, charges accumulated between the mercury electrode 34 and the semiconductor single crystal wafer 1 when the reverse bias voltage V is applied are removed. The timing for applying the forward bias voltage may be before or after the reverse bias voltage V is applied. When the mercury electrode is brought into contact with the semiconductor single crystal wafer and CV measurement is repeatedly performed at the same position, setting the timing for applying the forward bias voltage after applying the reverse bias voltage V applies the forward bias voltage. The timing is set before the application of the next reverse bias voltage V. Therefore, once the reverse bias voltage V is applied and the CV measurement process is performed, the charge accumulated between the mercury electrode and the wafer can be removed by the subsequent forward bias voltage application process. Then, since the next CV measurement is performed, it is possible to prevent the charge from accumulating and the resistivity from gradually increasing / decreasing as in the conventional method.
 図6に、P型シリコンエピタキシャル層の抵抗率を繰り返し測定する際、順バイアス電圧を印加しない場合(従来法)と印加する場合(本発明)の抵抗率変動を例示する。図6の例では、順バイアス電圧を-1Vから-18Vまで1V間隔で絶対値を増加させながら印加した後に、逆バイアス電圧Vを+1Vから+15Vまで1V間隔で増加させながら印加することにより抵抗率測定を行った。順バイアス電圧を印加しない場合は抵抗率がしだいに低くなるのに対し、順バイアス電圧を印加すると、抵抗率をほぼ一定にすることができる。ただし、順バイアス電圧の印加方法は、必ずしも所望電圧まで絶対値を漸次増加させる必要がなく、例えば、順バイアスとして一定の電圧を印加させてもよい。 FIG. 6 illustrates resistivity fluctuations when the forward bias voltage is not applied (conventional method) and when it is applied (the present invention) when the resistivity of the P-type silicon epitaxial layer is repeatedly measured. In the example of FIG. 6, the forward bias voltage is applied from -1V to -18V while increasing the absolute value at 1V intervals, and then the reverse bias voltage V is applied while increasing from + 1V to + 15V at 1V intervals. Measurements were made. When the forward bias voltage is not applied, the resistivity gradually decreases, whereas when the forward bias voltage is applied, the resistivity can be made substantially constant. However, the forward bias voltage application method does not necessarily need to gradually increase the absolute value to the desired voltage. For example, a constant voltage may be applied as the forward bias.
 印加する順バイアス電圧の印加量は、半導体単結晶ウェーハ1の抵抗率が低いほど大きくすることが好ましい。その例として、図7(a)にP型シリコンエピタキシャル層の抵抗率と順バイアス電圧の関係、図7(b)にN型シリコンエピタキシャル層の抵抗率と順バイアス電圧の関係を示す。ただし、順バイアス電圧の印加量は、図7(a)、図7(b)の関係より求められる値より小さくても、また、抵抗率に関わらず一定であっても、同じ位置での繰り返しC-V測定を行った際の抵抗率がしだいに高くなる(または低くなる)傾向を抑制することができる。 The amount of forward bias voltage to be applied is preferably increased as the resistivity of the semiconductor single crystal wafer 1 is lower. As an example, FIG. 7A shows the relationship between the resistivity of the P-type silicon epitaxial layer and the forward bias voltage, and FIG. 7B shows the relationship between the resistivity of the N-type silicon epitaxial layer and the forward bias voltage. However, the applied amount of the forward bias voltage is repeated at the same position even if it is smaller than the value obtained from the relationship shown in FIGS. 7A and 7B or constant regardless of the resistivity. It is possible to suppress a tendency that the resistivity when the CV measurement is performed gradually increases (or decreases).
 より具体的には、半導体単結晶ウェーハ1と水銀32とを接触させてショットキー接合を形成した水銀電極34に、半導体単結晶ウェーハ1がP型の場合には負(-)の電圧、N型の場合には正(+)の電圧を順バイアスとして印加する(図8(1))。 More specifically, when the semiconductor single crystal wafer 1 is P-type, a negative (−) voltage, N, is applied to the mercury electrode 34 formed by bringing the semiconductor single crystal wafer 1 and the mercury 32 into contact with each other to form a Schottky junction. In the case of a mold, a positive (+) voltage is applied as a forward bias (FIG. 8 (1)).
 すると、水銀電極34と半導体単結晶ウェーハ1の間に残存する電荷が順バイアスにより供給される逆の電荷により打ち消されて消滅するので、半導体単結晶ウェーハ1内に形成される空乏層35の厚さが正常なレベルに戻る(図8(2))。この状態で水銀電極34に逆バイアス電圧を印加すると、正常レベル厚さの空乏層35が形成される(図8(3))ようになるので、同じ位置での繰り返しC-V測定を行った際の、抵抗率がN型の場合には上昇、P型の場合は下降する傾向が改善される。 Then, the charge remaining between the mercury electrode 34 and the semiconductor single crystal wafer 1 is canceled by the reverse charge supplied by the forward bias and disappears. Therefore, the thickness of the depletion layer 35 formed in the semiconductor single crystal wafer 1 Returns to a normal level (FIG. 8 (2)). When a reverse bias voltage is applied to the mercury electrode 34 in this state, a depletion layer 35 having a normal level thickness is formed (FIG. 8 (3)), so repeated CV measurements were performed at the same position. In this case, the tendency to increase when the resistivity is N type and to decrease when the resistivity is P type is improved.
 半導体単結晶ウェーハ1は、抵抗率が低いほど不純物濃度が高いので、半導体単結晶ウェーハ1に接触する水銀電極34にもより多くの電荷が残存しやすい。そのため、半導体単結晶ウェーハ1の抵抗率が低いほど、順バイアス電圧の印加量を大きくすることが望ましい。 Since the semiconductor single crystal wafer 1 has a higher impurity concentration as the resistivity is lower, more charges are likely to remain on the mercury electrode 34 in contact with the semiconductor single crystal wafer 1. Therefore, it is desirable to increase the amount of forward bias voltage applied as the resistivity of the semiconductor single crystal wafer 1 is lower.
 以上のように、本発明においては、まず、図2、3に示すような装置を用い、半導体ウェーハに水銀を接触させて水銀電極をなす(水銀電極形成工程)(工程a)。そして、半導体単結晶ウェーハ1に対する順バイアス電圧印加工程(工程b)が終了後、LCRメータ140を用いて水銀電極34に対して逆バイアス電圧Vを連続的に変化させながら印加し、半導体単結晶ウェーハ1の内部に空乏層を拡げて容量Cを変化させつつ、その容量CをLCRメータ140により計測するC-V測定工程(工程c)を行う。同じ位置での繰り返し測定の場合は、順バイアス電圧印加工程(工程b)をC-V測定工程(工程c)の後に行っても良い。この場合、前述したように順バイアス電圧印加工程(工程b)をC-V測定工程(工程c)の後に行うことは、同じ位置での次のC-V測定工程(工程c)の前に順バイアス電圧印加工程(工程b)を行うこととなる。 As described above, in the present invention, first, using a device as shown in FIGS. 2 and 3, mercury is brought into contact with a semiconductor wafer to form a mercury electrode (mercury electrode forming step) (step a). Then, after the forward bias voltage application step (step b) to the semiconductor single crystal wafer 1 is completed, the reverse bias voltage V is applied to the mercury electrode 34 while continuously changing using the LCR meter 140, and the semiconductor single crystal A CV measurement step (step c) is performed in which a depletion layer is expanded inside the wafer 1 to change the capacitance C, and the capacitance C is measured by the LCR meter 140. In the case of repeated measurement at the same position, the forward bias voltage application step (step b) may be performed after the CV measurement step (step c). In this case, as described above, the forward bias voltage application step (step b) is performed after the CV measurement step (step c) before the next CV measurement step (step c) at the same position. A forward bias voltage application step (step b) is performed.
 続いて、PC150にインストールされた解析ソフトを用いて、逆バイアス電圧Vと空乏層の容量Cの関係から抵抗率を演算する抵抗率演算工程(工程d)を行う。このとき、逆バイアス電圧Vと容量Cの関係をグラフにプロットすると、C-V特性が得られる。さらに、逆バイアス電圧と容量を例えば下記の(1)式と(2)式に代入すると、半導体単結晶ウェーハ1内の深さWならびに、深さWにおけるドーパント濃度N(W)を算出することができるので、深さ方向におけるドーパント濃度のプロファイルを得ることができる。
   W=AεεSi/C   ・・・(1)
   N(W)=2/(qεεSi)×{d(C-2)/dV}-1・・・(2)
ここで、Aは電極面積、εは真空誘電率、εSiはSiの比誘電率、qは電子の電荷量である。
Subsequently, using the analysis software installed in the PC 150, a resistivity calculation step (step d) is performed in which the resistivity is calculated from the relationship between the reverse bias voltage V and the depletion layer capacitance C. At this time, when the relationship between the reverse bias voltage V and the capacitance C is plotted on a graph, a CV characteristic is obtained. Further, by substituting the reverse bias voltage and the capacity into the following formulas (1) and (2), for example, the depth W in the semiconductor single crystal wafer 1 and the dopant concentration N (W) at the depth W are calculated. Therefore, a dopant concentration profile in the depth direction can be obtained.
W = Aε 0 ε Si / C (1)
N (W) = 2 / (qε 0 ε Si A 2 ) × {d (C −2 ) / dV} −1 (2)
Here, A is the electrode area, ε 0 is the vacuum dielectric constant, ε Si is the relative dielectric constant of Si, and q is the charge amount of electrons.
 そして、深さ方向におけるドーパント濃度プロファイルの中で、測定深さを指定すると、その深さにおけるドーパント濃度が得られる。また、得られたドーパント濃度をASTM STANDARDS F723等の換算式により換算することにより、ドーパント濃度を抵抗率に換算することができる。以上のような本発明であれば、従来法では、特に繰り返しC-V測定の際、半導体ウェーハと水銀電極の間に電荷が蓄積して抵抗率が漸増・漸減してしまうのを抑制し、より確実に再現性高く抵抗率を高精度に求めることが可能である。 Then, when the measurement depth is specified in the dopant concentration profile in the depth direction, the dopant concentration at that depth is obtained. In addition, the dopant concentration can be converted to resistivity by converting the obtained dopant concentration by a conversion formula such as ASTM STANDARDDS F723. According to the present invention as described above, in the conventional method, in particular, in the repeated CV measurement, it is possible to suppress the accumulation of electric charges between the semiconductor wafer and the mercury electrode and the resistivity from gradually increasing / decreasing, It is possible to determine the resistivity with high accuracy and high reproducibility.
 なお、同じ位置で水銀電極の形成、C-V測定、抵抗率演算を行い、再度水銀電極の形成からやり直して繰り返す場合でも、水銀電極の形成を行い、水銀電極を維持したまま同じ位置でC-V測定を繰り返す場合でも、電荷は溜まっていくので、本発明はどちらの場合に対しても有効である。
 繰り返しのパターンについてより具体的に説明する。
 例えば、同じ位置で図1の(工程a)~(工程d)を繰り返すことができる。すなわち、水銀をウェーハ主表面に接触させてショットキー接合を形成し、順バイアス電圧印加、逆バイアス電圧印加、抵抗率演算を順に行い、その後水銀をウェーハ主表面から離し、次の測定のために、同じ位置に水銀をウェーハ主表面に再度接触させて上記手順を繰り返すことができる(図1の矢印(1)参照)。
 また、(工程a)を行い、そのまま同じ位置で(工程b)(工程c)(工程d)を繰り返すことも可能である。すなわち、ショットキー接合を形成したままの状態で、順バイアス電圧印加、逆バイアス電圧印加、抵抗率演算を繰り返すことができる(図1の矢印(2)参照)。
 さらには、(工程a)を行い、そのまま同じ位置で(工程b)(工程c)を繰り返してから(工程d)を行うことも可能である。すなわち、ショットキー接合を形成したまま、順バイアス電圧印加、逆バイアス電圧印加を繰り返し行い、最後にまとめて抵抗率演算を行うこともできる。(図1の矢印(3)参照)。
 いずれにしろ、電荷の蓄積による抵抗率の漸増・漸減を抑制して測定することができる。
Even when the mercury electrode is formed at the same position, the CV measurement, and the resistivity calculation are performed again after repeating the formation of the mercury electrode, the mercury electrode is formed and the C electrode is maintained at the same position while maintaining the mercury electrode. Even when the −V measurement is repeated, the charge accumulates, and the present invention is effective in both cases.
The repeated pattern will be described more specifically.
For example, (Step a) to (Step d) in FIG. 1 can be repeated at the same position. In other words, mercury is brought into contact with the main surface of the wafer to form a Schottky junction, forward bias voltage application, reverse bias voltage application, and resistivity calculation are performed in order, and then the mercury is separated from the wafer main surface for the next measurement. The above procedure can be repeated by bringing mercury into contact with the main surface of the wafer again at the same position (see arrow (1) in FIG. 1).
It is also possible to perform (step a) and repeat (step b) (step c) (step d) at the same position as it is. That is, forward bias voltage application, reverse bias voltage application, and resistivity calculation can be repeated with the Schottky junction still formed (see arrow (2) in FIG. 1).
Furthermore, it is also possible to perform (Step d) after performing (Step a) and repeating (Step b) and (Step c) at the same position. That is, the forward bias voltage application and the reverse bias voltage application are repeatedly performed with the Schottky junction formed, and finally the resistivity calculation can be performed collectively. (See arrow (3) in FIG. 1).
In any case, measurement can be performed while suppressing a gradual increase / decrease in resistivity due to charge accumulation.
 以下、本発明の実施例及び比較例を示して本発明をより具体的に説明するが、本発明はこれら実施例に限定されるものではない。 Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples of the present invention, but the present invention is not limited to these examples.
[実施例1]
 本発明の抵抗率測定方法を実施した。具体的には図1に示す(工程a)~(工程d)を繰り返し行った。抵抗率約0.9ΩcmのP型シリコンエピタキシャル層1を図2に示す水銀プローバ10を用いて5回繰り返しC-V測定する際、毎回-1Vから-18Vまで1V間隔で絶対値を増加させながら順バイアスを印加した後に、逆バイアス電圧Vを1Vから+15Vまで1V間隔で増加させながら印加することにより抵抗率測定を行った。その結果、測定値の平均値で標準偏差σを割って求めるCV値(変動係数)は、0.03%であった。
[Example 1]
The resistivity measurement method of the present invention was implemented. Specifically, (Step a) to (Step d) shown in FIG. 1 were repeated. When the P-type silicon epitaxial layer 1 having a resistivity of about 0.9 Ωcm is subjected to CV measurement five times using the mercury probe 10 shown in FIG. 2, the absolute value is increased at intervals of 1V from −1V to −18V each time. After applying the forward bias, the resistivity was measured by applying the reverse bias voltage V while increasing it from 1V to + 15V at 1V intervals. As a result, the CV value (coefficient of variation) obtained by dividing the standard deviation σ by the average value of the measured values was 0.03%.
[比較例1]
 実施例1で測定に用いた抵抗率約0.9ΩcmのP型シリコンエピタキシャル層1を、従来法のように、順バイアス電圧を印加せずに5回繰り返しC-V測定し抵抗率を求めた。その結果、CV値は、0.15%であった。
[Comparative Example 1]
The P-type silicon epitaxial layer 1 having a resistivity of about 0.9 Ωcm used in the measurement in Example 1 was subjected to CV measurement five times without applying a forward bias voltage as in the conventional method to obtain the resistivity. . As a result, the CV value was 0.15%.
 本発明の抵抗率測定方法によると、順バイアス電圧を印加することにより、逆バイアス電圧を印加する際に水銀電極と半導体単結晶ウェーハの間に蓄積される電荷を除去できるので、繰り返し測定時に半導体単結晶ウェーハ内に形成される空乏層の厚さを正常なレベルに保つことができ、抵抗率がしだいに低くなったり、しだいに高くなったりする傾向を抑制できる。その結果、抵抗率の繰り返し測定精度を向上することができる。 According to the resistivity measurement method of the present invention, by applying a forward bias voltage, the charge accumulated between the mercury electrode and the semiconductor single crystal wafer can be removed when a reverse bias voltage is applied. The thickness of the depletion layer formed in the single crystal wafer can be maintained at a normal level, and the tendency of the resistivity to gradually decrease or gradually increase can be suppressed. As a result, it is possible to improve the repeatability measurement accuracy of the resistivity.
 なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。 Note that the present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

Claims (2)

  1.  半導体単結晶ウェーハに水銀を接触させて水銀電極となす水銀電極形成工程と、
     前記水銀電極に順バイアス電圧を印加する順バイアス電圧印加工程と、
     前記水銀電極に逆バイアス電圧を印加して変化する前記半導体単結晶ウェーハの容量を測定するC-V測定工程と、
     前記逆バイアス電圧と前記容量の関係から抵抗率を演算する抵抗率演算工程とを有すること
     を特徴とする抵抗率測定方法。
    A mercury electrode forming process in which mercury is brought into contact with a semiconductor single crystal wafer to form a mercury electrode;
    Applying a forward bias voltage to the mercury electrode;
    A CV measurement step of measuring a capacitance of the semiconductor single crystal wafer that changes by applying a reverse bias voltage to the mercury electrode;
    A resistivity measurement method comprising: calculating a resistivity from a relationship between the reverse bias voltage and the capacitance.
  2.  前記順バイアス電圧の印加量は、前記半導体単結晶ウェーハの抵抗率が低いほど大きくすることを特徴とする請求項1に記載の抵抗率測定方法。 The resistivity measurement method according to claim 1, wherein the amount of forward bias voltage applied is increased as the resistivity of the semiconductor single crystal wafer is lower.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130809A (en) * 1993-11-08 1995-05-19 Dainippon Screen Mfg Co Ltd Measurement of c-v of semiconductor wafer and measurement of movable ion quantity
JP2013046030A (en) * 2011-08-26 2013-03-04 Shin Etsu Handotai Co Ltd Ozone gas generation device, silicon oxide film formation method, and evaluation method of silicon single crystal wafer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130809A (en) * 1993-11-08 1995-05-19 Dainippon Screen Mfg Co Ltd Measurement of c-v of semiconductor wafer and measurement of movable ion quantity
JP2013046030A (en) * 2011-08-26 2013-03-04 Shin Etsu Handotai Co Ltd Ozone gas generation device, silicon oxide film formation method, and evaluation method of silicon single crystal wafer

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