WO2018094658A1

WO2018094658A1 - Data transmission method, sending device and receiving device

Info

Publication number: WO2018094658A1
Application number: PCT/CN2016/107133
Authority: WO
Inventors: 刘晓健; 魏岳军
Original assignee: 华为技术有限公司
Priority date: 2016-11-24
Filing date: 2016-11-24
Publication date: 2018-05-31

Abstract

Disclosed are a data transmission method, a sending device and a receiving device, which are used for improving a gain obtained when LDPC codes are interleaved. The method comprises: a sending device encoding information data to obtain first LDPC codes, and then according to a mapping distribution, interleaving the first LDPC codes to obtain a second LDPC code. Compared with the method in the prior art of using a threshold for analysis, in the embodiments of the present invention, a mapping distribution is pre-calculated, and then according to the mapping distribution, first LDPC codes are interleaved. Since a mapping distribution is obtained according to a check matrix and a modulation mode of a first LDPC code, an optimal mapping distribution corresponding to the first LDPC code can be obtained through calculation, so that interleaved LDPC codes can obtain the maximum gain. By means of experimental result analysis, the interleaving method in the embodiments of the present invention, compared with that in the background art, can obtain a larger gain.

Description

Data transmission method, transmitting device and receiving device

Technical field

The embodiments of the present invention relate to the field of coding technologies, and in particular, to a data transmission method, a sending device, and a receiving device.

Background technique

The BICM system model using Low Density Parity Check Code (LDPC) is shown in Figure 10. The dotted line in the figure indicates bit interleaved code modulation iterative decoding (BICM-). The ID) system, if not considering the feedback loop, is a normal BICM system.

In the BICM system using LDPC shown in Figure 1, the gain of BICM is based on two facts: 1) In the codeword of the irregular LDPC code, the bits of the different checksums of the corresponding check matrix are differently protected; 2) high order Among the modulation symbols, the bit in the upper position has higher reliability than the lower bit. Therefore, by interleaving, the bits of different degrees of protection in the LDPC code are allocated to different reliability positions of the high-order symbols according to a certain ratio, and a certain performance gain can be obtained.

Although greater gains can be obtained by modifying the constellation diagram and redesigning the check matrix, these changes are too large. In practical systems, it is more likely to be adopted to obtain BICM performance through a bit interleaver under standard high-order modulation (such as Quadrature Amplitude Modulation (QAM)) and given parity check matrix conditions. Gain.

In the prior art, the interleaving method in the interleaver is mainly proposed in the reference "Vitale Giovanni, Mignone Vittoriag. Permutation of LDPC coded bits to be applied before QAM constellation mapping [P]. EP 2294738 B1, 2006", after encoding The LDPC codeword bitstream writes _Ng ( _Ng is an integer multiple of the number of bits of the debug symbol) in the order of the columns, performs column swapping, and then reads in the order of the rows. The scheme of column exchange is optimized according to a specific LDPC code check matrix, and the optimization criterion may be threshold analysis or bit error rate simulation.

The disadvantage of the above method is that although the bits of different protection capabilities are mapped to the symbol positions of different reliability according to a certain ratio, since the number of N _g is limited, even if column switching is performed, it is difficult to obtain an optimal mapping ratio. Therefore, the gain it obtains is limited.

Summary of the invention

The embodiment of the invention provides a data transmission method, a sending device and a receiving device, which are used to improve the gain obtained when the LDPC code is interleaved.

In a first aspect, an embodiment of the present invention provides a data transmission method, including:

After the sending device encodes the information data, the first LDPC code is obtained;

Transmitting, by the sending device, the first LDPC code according to a mapping distribution to obtain a second LDPC code.

In the embodiment of the present invention, the transmitting device obtains the first LDPC code by encoding the information data, and then interleaves the first LDPC code according to the mapping distribution to obtain a second LDPC code, which is compared with the threshold analysis method in the background art. In the embodiment of the present invention, a mapping distribution is pre-calculated, and then the first LDPC code is interleaved according to the mapping distribution. The mapping distribution in the embodiment of the present invention may be obtained according to a check matrix and a modulation mode of the first LDPC code. Therefore, an optimal mapping distribution corresponding to the first LDPC code can be obtained by calculation, so that the interleaved LDPC code obtains the maximum gain, and the experimental results are analyzed, and the embodiment of the present invention is compared with the interleaving in the background art. In this way, a larger gain can be obtained, thereby increasing the gain obtained when the LDPC code is interleaved.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the mapping distribution includes at least one mapping ratio m _j,i ,

a ratio of a bit of the second LDPC code whose weight is i in the second LDPC code corresponding to a position of the jth reliability level of the modulation symbol is m _j,i , where

i is an integer and is a value of any column in the interval [dv.min, dv.max], dv.min is equal to the minimum column weight of the check matrix of the second LDPC code, dv.max and the first The maximum column weight of the parity check matrix of the two LDPC codes is equal.

j is a positive integer and is any reliability level in the [1, L] interval, and L is the number of reliability levels of the modulation symbols corresponding to the modulation scheme.

With reference to the first aspect, in a second possible implementation manner of the first aspect, the sending, by using the mapping, the first LDPC code is interleaved to obtain a second LDPC code, including:

Transmitting, by the sending device, a variable node whose weight is i in the first LDPC code to a position of the jth reliability level of the corresponding modulation symbol in the second LDPC code according to the mapping distribution, so that the The ratio of the bit having the column weight i in the second LDPC code to the position of the jth reliability level of the modulation symbol in the second LDPC code is m _j,i .

In conjunction with the first possible implementation of the first aspect or the second possible implementation of the first aspect, in a third possible implementation of the first aspect, the mapping ratio m _j,i satisfies the following equation Group constraints:

Wherein, the system of equations comprises L+K equations, L is a number of reliability levels of modulation symbols corresponding to the modulation mode, and K is a column in a base matrix of a check matrix of the first LDPC code The number of weights, Λ _i is the proportion of the variable nodes whose column weight is i in the base matrix, 0 ≤ m _{j, i} ≤ 1.

In the above embodiments of the invention, the conditions for satisfying the mapping proportion in the mapping distribution are given, and an optimal mapping ratio can be obtained by solving the equations, so that an optimal mapping distribution can be obtained, thereby improving the gain obtained during interleaving. .

With reference to the first aspect, or any one of the first to the third possible implementation manners of the first aspect, in a fourth possible implementation manner of the first aspect, the method further includes:

The transmitting device respectively obtains L real bits and L imaginary bits from the second LDPC code into one modulation symbol, wherein the L real bits have L different reliability levels, L imaginary parts The bits have L different reliability levels, and the L real bits and the L imaginary bits are respectively from different positions in the second LDCP code.

With reference to the first aspect, or any one of the first to the third possible implementation manners of the first aspect, in a fifth possible implementation manner of the first aspect, the method further includes:

The transmitting device includes L groups of memories for storing L types of reliability level bits of the second LDPC code, and the total number of bits stored in any two groups of the L group memories is the same. The reliability of the memory within a group is the same, and the reliability of the memory between any two groups of the L group of memories is different;

If each set of memory includes one memory, the transmitting device reads 1 bit from each of the L sets of memories to form L real bits, and the transmitting device from each of the L sets of memories A memory reads 1 bit to form L imaginary bits, and the L real bits and the L imaginary bits are respectively arranged according to the reliability of the L group of memories, and the transmitting device will Mapping the L real bits and the L imaginary bits into one modulation symbol; or

If each group of memories includes 2 ^r memories, r is a positive integer, the transmitting device reads 1 bit from the 2 ^r memories in the L group memory as real bits, 1 bit as imaginary bits Constructing 2 ^r bit sequences, wherein each of the 2 ^r bit sequences is composed of L real bits and L imaginary bits, respectively, L real bits in each bit sequence From the L group of memories, and arranged in descending order of reliability of the L sets of memories, the L imaginary bits in each bit sequence are respectively from the L group of memories, and according to The reliability of the L-group memories is ranked from high to low, and each bit sequence is used to map one modulation symbol.

In the above embodiment, since the bits with different degrees of protection are allocated to the different reliability positions of the symbols according to a certain ratio, the optimal mapping effect can be obtained.

With reference to the first aspect, or any one of the possible implementation manners of the first to fifth possible implementation manners of the first aspect, in a sixth possible implementation manner of the first aspect, the first LDPC code The check matrix has a Raptor like structure.

In conjunction with the fourth possible implementation of the first aspect, or the fifth possible implementation of the first aspect, in a seventh implementation manner of the first aspect, the method further includes: the sending device Modulation symbols are modulated and transmitted.

In a second aspect, the embodiment of the present invention further provides a data transmission method, including:

The receiving device acquires the second LDPC code by demodulating the received signal;

The receiving device deinterleaves the second LDPC code to obtain a first LDPC code, where a bit with a column weight i in the second LDPC code is reliable in the jth type of the corresponding modulation symbol in the second LDPC code. The ratio of the position of the degree series is m _j,i , where

In the foregoing embodiment of the present invention, the LDPC code received by the receiving device is obtained by deinterleaving the first LDPC code, and the second LDPC code is obtained by interleaving the first LDPC code according to the interleaving ratio, and the interleaving ratio is according to the modulation mode. The reliability level of the corresponding modulation symbol and the column weight of the LDPC code are obtained. In this embodiment, since the optimal interleaving ratio can be obtained by calculation, the optimal interleaving effect can be obtained, and the interleaving is improved. Gain.

In conjunction with the second aspect, in a first possible implementation of the second aspect, the mapping ratio m _j,i satisfies the constraints of the following system of equations:

With reference to the second aspect or the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the check matrix of the first LDPC code has a Raptor like structure.

With reference to the second aspect or the first possible implementation manner of the second aspect, or the second possible implementation manner, in a third possible implementation manner of the second aspect, the method further includes: the receiving device pair The first LDPC code performs channel decoding to obtain information data.

In a third aspect, the embodiment of the present invention further provides a sending device, including:

a coding unit, configured to encode the information data to obtain an LDPC code;

And an interleaving unit, configured to interleave the first LDPC code according to the mapping distribution to obtain a second LDPC code.

With reference to the third aspect, in a first possible implementation manner of the third aspect, the mapping distribution includes at least one mapping ratio m _j,i ,

With reference to the third aspect, in a second possible implementation manner of the third aspect, the interleaving unit is specifically configured to:

And distributing, according to the mapping distribution, a bit of the first LDPC code with a weight of i to a position of the jth reliability level of the corresponding modulation symbol in the second LDPC code, so that the second LDPC code is The ratio of the bit whose weight is i in the second LDPC code corresponding to the position of the jth reliability level of the modulation symbol is m _j,i .

In conjunction with the first possible implementation of the third aspect or the second possible implementation of the third aspect, in a third possible implementation manner of the third aspect, the mapping ratio m _j,i satisfies the following equation Group constraints:

Wherein, the system of equations comprises L+K equations, L is a number of reliability levels of modulation symbols corresponding to the modulation mode, and K is a base matrix corresponding to a check matrix of the first LDPC code The number of column weight categories, Λ _i is the proportion of the variable nodes whose column weight is i in the base matrix, 0 ≤ m _{j, i} ≤ 1.

Combining any of the first to third possible implementations of the third aspect or the third aspect In a fourth possible implementation manner of the third aspect, the sending device further includes: a first mapping unit, configured to separately obtain L real bits and L imaginary parts from the second LDPC code The bit map is a modulation symbol, wherein L real bits have L different reliability levels, L imaginary bits have L different reliability levels, L real bits and L imaginary bits They are from different locations in the second LDCP code.

With reference to the third aspect, or any one of the possible implementation manners of the first to the third possible implementation manners of the third aspect, in a fifth possible implementation manner of the third aspect, the sending device further includes L a group memory for storing L bits of the reliability level of the second LDPC code, wherein the total number of bits stored in any two groups of the L group memory is the same, and the memory in any one of the L group memories The reliability is the same, and the reliability of the memory between any two groups of the L group of memories is different;

The transmitting device further includes a second mapping unit, configured to read 1 bit from each of the L sets of memory to form L real bits if each set of memory includes 1 memory, Each memory in the L group of memories reads 1 bit to form L imaginary bits, and the L real bits and the L imaginary bits are respectively arranged according to the reliability of the L group of memories from high to low. Mapping the L real bits and the L imaginary bits into one modulation symbol; or

If each group of memories includes 2 ^r memories and r is a positive integer, one bit is read from the 2 ^r memories of the L group memories as real bits, and 1 bit is used as imaginary bits, and 2 is formed. ^r bit sequences, wherein each of the 2 ^r bit sequences consists of L real bits and L imaginary bits, the L real bits in each bit sequence are from the L group of memories, and arranged according to the reliability of the L group of memories from high to low, wherein the L imaginary bits in each bit sequence are respectively from the L group of memories, and according to the L group The reliability of the memory corresponds to a high to low order, and each bit sequence is used to map one modulation symbol.

With reference to the third aspect, or any one of the possible implementation manners of the first to fifth possible implementation manners of the third aspect, in a sixth possible implementation manner of the third aspect, the first LDPC code The check matrix has a Raptor like structure.

With reference to the fourth possible implementation of the third aspect, or the fifth possible implementation manner of the third aspect, in a seventh implementation manner of the third aspect, the sending device further includes a sending unit, The modulation symbols are modulated and transmitted.

In a fourth aspect, the embodiment of the present invention further provides a receiving device, including:

a receiving unit, configured to receive a signal;

a demapping unit, configured to obtain a second LDPC code by demodulating the signal;

a deinterleaving unit, configured to deinterleave the second LDPC code to obtain a first LDPC code, where a bit with a column weight i in the second LDPC code corresponds to a modulation symbol in the second LDPC code The ratio of the positions of the reliability levels is m _j,i , where

In conjunction with the fourth aspect, in a first possible implementation of the fourth aspect, the mapping ratio m _j,i satisfies the constraints of the following system of equations:

With reference to the fourth aspect, or the first possible implementation manner of the fourth aspect, in a second possible implementation manner of the fourth aspect, the check matrix of the first LDPC code has a Raptor like structure.

With reference to the fourth aspect, or the first possible implementation manner of the fourth aspect, or the second possible implementation manner, in a third possible implementation manner of the fourth aspect, the receiving device further includes a decoding unit, Channel decoding is performed on the first LDPC code to obtain information data.

In a fifth aspect, the embodiment of the present invention further provides a sending device, including:

An encoder for encoding the information data to obtain an LDPC code;

An interleaver is configured to interleave the first LDPC code according to a mapping distribution to obtain a second LDPC code.

In the embodiment of the present invention, the transmitting device obtains the first LDPC code by encoding the information data, and then interleaves the first LDPC code according to the mapping distribution to obtain a second LDPC code, which is compared with the threshold analysis method in the background art. In the embodiment of the present invention, a mapping distribution is pre-calculated, and then the first LDPC code is interleaved according to the mapping distribution. The mapping distribution in the embodiment of the present invention may be obtained according to a check matrix and a modulation mode of the first LDPC code. Therefore, an optimal mapping distribution corresponding to the first LDPC code can be obtained by calculation, so that the interleaved LDPC code obtains the maximum gain, and the embodiment of the present invention compares with the background. The interleaving method in the technique can obtain a larger gain, thereby improving the gain obtained when the LDPC code is interleaved.

With reference to the fifth aspect, in a first possible implementation manner of the fifth aspect, the mapping distribution includes at least one mapping ratio m _j,i ,

With reference to the fifth aspect, in a second possible implementation manner of the fifth aspect, the interleaver is specifically configured to:

With reference to the first possible implementation of the fifth aspect or the second possible implementation of the fifth aspect, in a third possible implementation manner of the fifth aspect, the mapping ratio m _j,i satisfies the following equation Group constraints:

With reference to the fifth aspect, or any one of the first to the third possible implementation manners of the fifth aspect, in a fourth possible implementation manner of the fifth aspect, the sending device further includes a mapping And for respectively obtaining L real bits and L imaginary bits from the second LDPC code into one modulation symbol, wherein the L real bits have L different reliability levels, L imaginary parts The bits have L different reliability levels, and the L real bits and the L imaginary bits are respectively from different positions in the second LDCP code.

With reference to the fifth aspect, or any one of the possible implementation manners of the first to the third possible implementation manners of the fifth aspect, in a fifth possible implementation manner of the fifth aspect, the sending device further includes L a group memory for storing L bits of the reliability level of the second LDPC code, wherein the total number of bits stored in any two groups of the L group memory is the same, and the memory in any one of the L group memories The reliability is the same, and the reliability of the memory between any two groups of the L group of memories is different;

The transmitting device further includes a mapper, configured to read 1 bit from each of the L sets of memory to form L real bits, if each set of memory includes 1 memory, from the L group Each memory in the memory reads 1 bit to form L imaginary bits, and the L real bits and the L imaginary bits are respectively arranged according to the reliability of the L group of memories, and Mapping the L real bits and the L imaginary bits into one modulation symbol; or

With reference to the fifth aspect, or any one of the possible implementation manners of the first to fifth possible implementation manners of the fifth aspect, in a sixth possible implementation manner of the fifth aspect, the first LDPC code The check matrix has a Raptor like structure.

With reference to the fourth possible implementation manner of the fifth aspect, or the fifth possible implementation manner of the fifth aspect, in a seventh implementation manner of the fifth aspect, the sending device further includes a transmitter, The modulation symbols are modulated and transmitted.

In a sixth aspect, the embodiment of the present invention further provides a receiving device, including:

a receiver for receiving a signal;

a demapper for obtaining a second LDPC code by demodulating the signal;

a deinterleaver, configured to deinterleave the second LDPC code to obtain a first LDPC code, where a bit with a column weight i in the second LDPC code corresponds to a modulation symbol in the second LDPC code The ratio of the positions of the reliability levels is m _j,i , where

In the foregoing embodiment of the present invention, the LDPC code received by the receiving device is obtained by deinterleaving the first LDPC code, and the second LDPC code is obtained by interleaving the first LDPC code according to the interleaving ratio, and the interleaving ratio is according to the modulation mode. The reliability level of the corresponding modulation symbol and the column weight of the LDPC code As a result, in this embodiment, since the optimal interleaving ratio can be obtained by calculation, the optimal interleaving effect can be obtained, and the gain obtained during interleaving is improved.

With reference to the sixth aspect, in a first possible implementation manner of the sixth aspect, the mapping ratio m _j,i satisfies the constraint of the following system group:

With reference to the sixth aspect, or the first possible implementation manner of the sixth aspect, in a second possible implementation manner of the sixth aspect, the check matrix of the first LDPC code has a Raptor like structure.

With reference to the sixth aspect or the first possible implementation manner or the second possible implementation manner of the sixth aspect, in a third possible implementation manner of the sixth aspect, the receiving device further includes a decoder, Channel decoding is performed on the first LDPC code to obtain information data.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below.

1 is a block diagram of a BICM system using an LDPC code in the prior art;

2 is a flowchart of a method for data transmission according to an embodiment of the present invention;

FIG. 3 is a flowchart of a method for calculating a mapping distribution according to an embodiment of the present invention;

4 is a schematic diagram 1 of a comparison of gain results according to an embodiment of the present invention;

FIG. 5 is a second schematic diagram of gain comparison according to an embodiment of the present invention; FIG.

FIG. 6 is a schematic diagram 3 of a comparison of gain results according to an embodiment of the present invention; FIG.

FIG. 7 is a flowchart of a method for data transmission according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a mapping process according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a mapping process according to an embodiment of the present invention;

FIG. 10 is a schematic flowchart of a method for data transmission according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a sending device according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of a receiving device according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram of a sending device according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a receiving device according to an embodiment of the present invention.

detailed description

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The embodiment of the present invention provides two methods for data transmission, one for a transmitting device side and the other for a receiving device side. For a transmitting device, it has an encoding function, an interleaving function, a mapping function, and a sending function, and is configured for a receiving device. It has a receiving function, a demapping function, a deinterleaving function, and a decoding function. The transmitting device provided by the embodiment of the present invention may be a device that integrates an encoder, an interleaver, a mapper, and a transmitter, and the receiving device may be a device that integrates a receiver, a demapper, a deinterleaver, and a decoder. In the communication system, the sending device may be a terminal, and the receiving device may be a base station or other network device, and the sending device may also be a base station or other network device, and the receiving device may be a terminal.

In practical applications, for the convenience of calculation, the check matrix of the LDPC code can usually be defined by a base matrix of a smaller size, which may also be referred to as a base matrix corresponding to the check matrix of the LDPC code, or an LDPC code. Base matrix. Parity check matrix H of binary LDPC code with dimension JZ*LZ Can be described as follows:

Each of the elements h _j,l ,0≤j≤J, 0≤l≤L is a zero matrix of Z*Z size or a superposition of multiple unit cyclic shift arrays (or one unit cyclic shift array) The cyclic shift array. For convenience, H can be described by a base matrix B(H) of size J × L:

Wherein, when h _j,l is a zero matrix, b _{j,l is} defined as "-"; when h _j,l is a unit shift matrix, b _{j,l is} defined as the shift parameter of h _j,l (When h _j,l is the right shift of the unit matrix, b _j,l >0; when h _j,l is the left shift of the unit matrix, b _j,l <0; when h _j,l When it is a unit matrix, b _j,l =0); when b _j,l is a cyclic shift array superimposed by multiple unit shift arrays, b _{j,l is} defined as shifting h _j,l An array of bit parameters combined.

The matrix B(H) is the original base matrix of the LDPC code. Further, the original base matrix is optimized to obtain a base matrix of the LDPC code, and the specific method is: for any element in the original base matrix of the LDPC code, If the element is a zero matrix, the element corresponding to the position of the element in the base matrix of the LDPC code is set to 0; if the element is a non-zero matrix, the base matrix of the LDPC code corresponds to the position of the element The element is set to 1.

For example, the modulation mode is 256QAM, and the codeword is (1944,972) Quasi Cyclic Low Density Parity-Check (QC-LDPC) in IEEE802.11n. The check matrix of the code is optimized to the base matrix B' ₁ (H) as shown below:

The base matrix B' ₁ (H) is a 12*24 matrix in which each element is used to represent a matrix of 81*81 (ie 1944/24=81), and if an element in B' ₁ (H) If it is 0, it means that the corresponding position in the base matrix of the LDPC code is a matrix of 81*81; if an element in B' ₁ (H) is 1, it means that the corresponding position in the base matrix of the LDPC code is one. A non-zero matrix of 81*81.

For a check matrix (or for a base matrix), it uniquely corresponds to a column weight form, taking the base matrix B' ₁ (H) of the above LDPC code as an example, wherein there are four types of column weights, respectively: 2, 3, 4, 11, each accounted for: 11/24, 9/24, 1/24, 3/24. The check matrix and its corresponding base matrix have the same column weight type, each column weight value and the proportion of each column weight.

And for a given modulation mode, the number of reliability levels is also determined. For example, for the modulation mode of 256QAM, the number of corresponding reliability levels is 4, respectively, the reliability level is 1 , reliability level 2, reliability level 3, reliability level 4.

Based on the above description, the method of transmitting data on the transmitting device side and the method of transmitting data on the receiving device side will be described in detail below.

2 is a flowchart of a method for data transmission according to an embodiment of the present invention. The method is performed by a sending device, and the method includes the following steps:

Step 201: The sending device encodes the information data to obtain a first LDPC code.

Step 202: The transmitting device interleaves the first LDPC code according to the mapping distribution to obtain a second LDPC code.

In the foregoing step 201, the sending device encodes the information data to obtain the first LDPC code, that is, the first LDPC code is the encoded information data, where the first LDPC code corresponds to a check matrix, and corresponds to a modulation mode. It should be noted that the modulation method herein is not an arbitrary modulation method, but after determining the modulation mode of the information data, the modulation mode of the first LDPC code, that is, the modulation mode and information data of the first LDPC code, is determined. The modulation method is the same, and the modulation modes are 256QAM, 64QAM, 512QAM, and the like. The LDPC code can be represented as a sequence of bits, each bit corresponding to a variable node in the check matrix of the LDPC code. If a bit in the LDPC code corresponds to a column of the variable node in the LDPC code check matrix, the bit is referred to as a bit with a column weight of i in the various embodiments herein. The position at which each bit is located has a level of reliability of the modulation symbols, and bits at different positions may have the same level of reliability. The mapping ratio m _j,i may be a ratio of a bit whose weight is i in the LDPC code in the LDPC code where the reliability level is j.

In the foregoing step 202, the mapping distribution is composed of a plurality of mapping proportions m _j,i , the mapping distribution may be pre-calculated, and the mapping distribution is stored to the sending device, and the transmitting device performs the first LDPC code according to the stored mapping distribution. Interleaving, thereby obtaining an interleaved second LDPC code, wherein the mapping distribution may be obtained according to a check matrix and a modulation mode of the first LDPC code. It can be seen that after the interleaving, the mapping distribution of the LDPC code may change, that is, the mapping distribution of the first LDPC code may be different from the mapping distribution of the second LDPC code, for example, one or more m _{j,i are} different.

In an embodiment of the present invention, the mapping distribution according to the first LDPC code is obtained according to the check matrix and the modulation mode of the first LDPC code, so that a mapping corresponding to the first LDPC code can be obtained by calculation. The distribution is such that the interleaved LDPC code obtains the maximum gain. By analyzing the experimental results, the embodiment of the present invention can obtain a larger gain than the interleaving method in the background art, thereby improving the gain obtained when the LDPC code is interleaved. .

In the embodiment of the present invention, the base matrix of the second LDPC code is obtained by exchanging the base matrix column of the first LDPC code, and thus the base matrix of the second LDPC code has the same size as the base matrix of the first LDPC code, and Have the same column weight category, and the maximum column weight value and the minimum column weight value are also The same, that is, in the embodiment of the present invention, the check matrix, the base matrix of the first LDPC code, and the check matrix and the base matrix of the second LDPC code have the same column weight type, maximum column weight value, and minimum Column weight value.

In the embodiment of the present invention, dv.min is used to represent the minimum column weight value, dv.max is used to represent the maximum column weight value, and L is used to indicate the number of reliability levels of the modulation symbols corresponding to the modulation mode.

Based on the above representation method, the mapping distribution for interleaving in the embodiment of the present invention has the following structural features: including at least one mapping ratio m _j,i , and m _j,i indicating that the bit with the column weight i in the second LDPC code is a ratio of a position of the jth reliability level corresponding to the modulation symbol in the second LDPC code, wherein

i is an integer and is a value of any column in the interval [dv.min, dv.max], dv.min is equal to the minimum column weight of the check matrix of the second LDPC code, dv.max and the second LDPC The maximum column weight of the check matrix of the code is equal.

Therefore, based on the structural characteristics of the mapping distribution, the specific method for the transmitting device to interleave the first LDPC code into the second LDPC code is: the transmitting device distributes the bits of the first LDPC code to the i according to the mapping distribution. The position of the jth reliability level corresponding to the modulation symbol in the two LDPC codes, such that the ratio of the bit of the second LDPC code whose weight is i in the second LDPC code corresponding to the position of the jth reliability level of the modulation symbol For m _j,i .

In a possible implementation, each mapping ratio m _j,i satisfies the constraints of the following system of equations:

Wherein, the system of equations includes L+K equations, L is a reliability level of a modulation symbol corresponding to a modulation mode of the first LDPC code, and K is a type of column weight in a base matrix of the first LDPC code, _i is the proportion of the variable nodes whose column weight is i in the base matrix of the first LDPC code, 0 ≤ m _{j, i} ≤ 1.

It should be noted that the above is merely an example, and the present invention is not limited thereto.

The following describes a method for obtaining a mapping distribution according to a specific example. Referring to FIG. 3, the steps for calculating a mapping distribution include:

Step 301: Obtain a system of equations according to a reliability level of a modulation symbol corresponding to a modulation mode of the first LDPC code and a proportion of each column weight in a base matrix of the first LDPC code, where the equation group includes L+K Equation, L is the reliability level of the modulation symbol corresponding to the modulation mode of the first LDPC code, and K is the type of the column weight in the base matrix of the first LDPC code.

Step 302: Determine an optimization space of the system of equations.

Step 303: Determine an interleaving ratio corresponding to a lowest convergence threshold in the optimization space, and use the determined interleaving ratio as an interleaving ratio corresponding to the first LDPC code, and obtain a mapping distribution according to the interleaving ratio.

The above steps 301 to 303 can be performed using a computing device having computing power, such as a personal computer, a server, or the like.

In the above step 301, the equations are specifically:

Wherein, the system of equations includes L+K equations, L is the number of reliability levels of modulation symbols corresponding to the modulation mode of the first LDPC code, and K is the type of column weight in the base matrix of the first LDPC code. , Λ _i is the proportion of the variable nodes whose column weight is i in the base matrix of the first LDPC code, 0 ≤ m _{j, i} ≤ 1.

For example, taking the base matrix B' ₁ (H) of the above LDPC code as an example, there are four types of column weights, namely: 2, 3, 4, and 11, respectively, and the respective proportions are: 11/24 , 9/24, 1/24, 3/24; and there are 4 kinds of reliability positions of 256QAM (ie, L=4), so the obtained system of equations T ₁ is:

After obtaining the system of equations shown above, it is necessary to solve the above equations. In the above equations, since the number of equations (8) is smaller than the number of unknowns (16), it is necessary to first select the optimization. Space is then solved based on the optimization space.

Therefore, in step 302, the optimization space of the above system of equations is determined. There are many methods for determining the optimization space of a system of equations, and it belongs to the prior art solution, which is only briefly explained in the embodiment of the present invention.

For the above equations, a part of m _{j,i is} selected to form an optimization space, wherein the criterion is: after the remaining m _{j,i is taken} as an unknown number into L+K equations, the equation has a solution and the equation The solution has the largest solution space. In this way, the optimization space can be minimized to achieve the purpose of reducing the amount of optimization calculation.

Taking the above equation group T ₁ as an example, the corresponding optimization space is: (m ₃₂ , m ₄₂ , m ₁₃ , m ₄₃ , m ₁₄ , m ₂₄ , m ₄₄ , m ₂₁₁ , m ₃₁₁ ), and the dimension is 9; The unknowns are m ₁₂ , m ₂₂ , m ₂₃ , m ₃₃ , m ₃₄ , m _{1 11} , m _{4 11} . The initial value of each element in the optimization space is set to the real number in the interval [0,1], and the solution of the unknown number must also fall within the interval [0,1].

After obtaining the optimization space of the equations, the above equations will be solved based on the selected optimization space.

In the foregoing step 303, the process of obtaining the interleaving ratio corresponding to the lowest convergence threshold in the optimized space based on the optimization space is as follows:

Step A: Assigning m _j,i in the optimization space.

Step B: Determine a set of target solutions of the equations according to the current values of m _j,i in the optimization space.

If the target solution of the group is the final solution, it needs to be verified according to the subsequent steps. If it is determined to be the optimal solution, it is output, otherwise the target solution needs to be re-determined.

Step C: determining, according to the target solution, a maximum signal-to-noise ratio (SNR) value of the non-convergence corresponding to the posterior soft information of each variable node of the base matrix of the first LDPC code, and determining the determined The maximum SNR value that cannot be converged is used as the current generation value.

In this step, under a given target solution, a maximum SNR value that does not converge corresponding to the posterior soft information of each variable node of the base matrix is found. That is, when the a posteriori soft information of each variable node of the base matrix can converge under the current SNR value, the SNR value is decreased, and it is determined whether the posterior soft information of each variable node of the base matrix can converge under the current SNR value. If convergence is possible, the SNR value continues to decrease until the a posteriori soft information of each variable node of the base matrix does not converge at the current SNR value.

The a posteriori soft information of each variable node of the base matrix of the first LDPC code is not converged under the current SNR value, and the a posteriori soft information of each variable node of the base matrix satisfies the preset stop convergence under the current SNR value. The condition that the convergence condition is stopped may be, for example, that the convergence value is always the same within the specified number of iterations, and there is no change; or the variation range of the convergence value is less than the preset change threshold within the specified number of iterations; or the total number of iterations The preset total number of iterations threshold is reached; of course, other preset stop convergence conditions may also be used. As long as the preset stop convergence condition is satisfied, the convergence value at the time of convergence is stopped as the lowest convergence threshold.

Step D: determining whether the maximum SNR value that cannot be converged under the current target solution is the same as the maximum SNR value that cannot be converged under the previous target solution. If they are the same, the current target solution is used as the interlace corresponding to the lowest convergence threshold in the optimization space. If the ratio is not the same, proceed to step E.

Step E: Adjust the value of m _j,i in the optimization space according to the current generation value, and return to step B.

In this step, specifically, the value of m _j,i in the optimization space may be adjusted according to the difference optimization algorithm and the current generation value.

In the above steps A to E, it is a double iterative method, wherein the outer iteration is used to adjust the intersection The target solution of the scale equation system is used to determine the maximum SNR value that cannot be converged corresponding to the posterior soft information of each variable node of the base matrix under the current target solution. For example, suppose that when the target solution is a1, the maximum SNR value obtained is b1; when the target solution is a2, it can continue to iterate on the basis of b1 to obtain a smaller b2 than b1; For a3, it can continue to iterate on the basis of b2 to obtain a smaller b3 than b2; until the iteration stop condition is satisfied, the final SNR value is taken as the output result.

In the above embodiment, when determining the interleaving ratio corresponding to the lowest convergence threshold in the optimization space, a double iterative method is used, and an optimal solution can be found, and the SNR value corresponding to the optimal solution is the variable of the base matrix. The maximum SNR value of the a posteriori soft information corresponding to the node cannot be converged, and the optimal solution is used as the final determined interleaving ratio. This embodiment can implement the convergence solution to find the optimal solution and ensure the accuracy of the interleaving ratio. And it has been proved by experiments that a certain performance BICM gain can be achieved; and this embodiment obtains the best interleaving ratio by mathematical operation, and has a faster calculation speed than the simulation method in the background art.

Optionally, the embodiment of the present invention further provides a possible implementation manner of the foregoing step C, which specifically includes the following steps:

Step C1: Obtain channel mutual information of each reliability position of the modulation symbol corresponding to the first LDPC code by simulation according to the current SNR value;

Specifically, the channel mutual information amount of each reliability position of the high-order modulation symbol can be obtained by Monte Carlo simulation. For example, the 64QAM symbol has three kinds of reliability, and their channel mutual information amounts are represented by I ₁ , I ₂ , and I ₃ , respectively.

Step C2: Determine, according to the current target solution and the channel mutual information of each reliability position of the high-order modulation symbol corresponding to the determined first LDPC code, determine, by demodulating the mutual information obtained from the channel, the variable nodes of the base matrix of the first LDPC code respectively ;

Specifically, for example, if the column weight of the kth column of B'(H) is i, the mutual information obtained by the corresponding variable node from the channel can be calculated as follows:

Step C3: Obtaining a change of the base matrix according to mutual information obtained by each variable node of the base matrix Mutual information between the quantity node and the check node;

Specifically, all Iv _k obtained in the above step C3 can be used as an input of the PEXIT algorithm, and then the mutual information between the variable node and the check node of the base matrix is iteratively solved according to the calculation step of the PEXIT algorithm.

Step C4: Obtain mutual information between each variable node of the base matrix of the first LDPC code, mutual information between the variable node of the base matrix of the first LDPC code, and the check node, to obtain a base matrix of the first LDPC code. A posteriori soft information of each variable node;

Step C5: determining whether the a posteriori soft information of each variable node of the base matrix of the first LDPC code converges under the current SNR value, and if not, determining the determined maximum SNR value that cannot be converged as the current generation value; , the current SNR value is lowered by the set step size and the process proceeds to step C1.

The value of the posterior soft information of all variable nodes approaches 1 and a threshold is set in the actual operation. When the difference between all the values and 1 is less than the threshold (for example, 0.0001) , it is considered to converge, otherwise it is considered not to converge.

In the above embodiment, a method for determining a maximum SNR value that cannot be converged corresponding to a posteriori soft information of each variable node of a base matrix of the first LDPC code is provided for a certain target solution, wherein the first LDPC is combined The mutual information obtained by each variable node of the base matrix of the code, the mutual information between the variable node of the base matrix of the first LDPC code and the check node, and the posterior softness of each variable node of the base matrix of the first LDPC code is obtained. Information, and by continuously reducing the SNR value, the final iteration finds a corresponding maximum SNR value that cannot be converged. This embodiment uses an iterative method to accurately determine the posterior soft information corresponding to each variable node of the base matrix under a target solution. The maximum SNR value that cannot be converged has higher accuracy, which can guarantee the final determination of the interleaving ratio.

Taking the above equation group T ₁ as an example, the obtained optimal solution (ie, the map distribution) is as shown in Table 1 below:

m_j,i m _j,i	i＝2i=2	i＝3i=3	i＝4i=4	i＝11i=11
j＝1j=1	0.2269820.226982	0.3000000.300000	0.8000000.800000	0.001060.00106
j＝2j=2	0.1874180.187418	0.3626490.362649	0.0577600.057760	0.205600.20560
j＝3j=3	0.2856000.285600	0.2373510.237351	0.1222400.122240	0.200000.20000

j=4

0.300000

0.100000

0.020000

0.59333

Table 1

Therefore, the transmitting device may be configured to interleave the first LDPC code according to the mapping distribution shown in Table 1, to obtain a second LDPC code, where the transmitting device distributes the bits of the first LDPC code with the i to the first according to the mapping distribution. The position of the jth reliability level corresponding to the modulation symbol in the two LDPC codes, such that the ratio of the bit of the second LDPC code whose weight is i in the second LDPC code corresponding to the position of the jth reliability level of the modulation symbol For m _j,i . For example, according to Table 1, the ratio of the bit weighted to 2 in the first LDPC code to the first reliability level of the second LDPC code is 0.226982, and the ratio of the position distributed to the position of the second reliability level is 0.187418, so that the ratio of the bit having a column weight of 2 in the second LDPC code to the position of the first reliability level is 0.226982, and the ratio of the position of the second reliability level is 0.187418. For example, in the first LDPC code, there are 100 bits with a column weight of 2, and after interleaving, the number of bits in the second LDPC code that is 2 in the position of the first reliability level is 22 or 23, and the second The number of bits with a weight of 2 at the position of the reliability level is 18 or 19, and the number of bits can be rounded or rounded as needed. It should be noted that the examples herein are only examples and are not limited thereto.

The first LDPC code corresponding to the B' ₁ (H) is interleaved to obtain a second LDPC code, and the PEXIT analysis tool in the optimization method can calculate the convergence threshold after the interleaving is 7.697dB, and converges in the non-interleaving case. The threshold is 8.097 dB, so theoretically interleaving by the method of the embodiment of the present invention, a gain of about 0.4 dB can be obtained.

FIG. 4 is a schematic diagram of comparison of gain results according to an embodiment of the present invention. The figure is a schematic diagram of gain obtained when interleaving a first LDPC code to obtain a second LDPC code according to the mapping distribution shown in Table 1. The simulated channel environment is Additive White Gaussian Noise (AWGN) channel, and the demodulation method is Log-MAP. In BICM system, the decoding algorithm is Error Back Propagation (BP) algorithm. The maximum number of iterations is set to 50. In the BICM-ID side system, the decoding algorithm is BP algorithm, the maximum number of iterations is set to 50 times, and the maximum number of iterative demodulation decodings is set to 10 times.

As can be seen from FIG. 4, the optimized interleaving ratio gain given by the embodiment of the present invention is significant. The BICM system has a gain of about 0.4 dB at a FER of 10 ^-1 , which is very close to the results of the PEXIT analysis. The BICM-ID system has a gain of about 1 dB at a FER of 10 ^-1 .

A specific embodiment will be given below to illustrate the implementation process of the embodiment of the present invention.

The modulation mode is 256QAM, and the codeword is the (1944, 1296) QC-LDPC code in IEEE802.11n. The base matrix B ₂ '(H) of the code (ie, the first LDPC code) is structured as follows:

There are four types of columns in the matrix, which are 2, 3, 6, and 8, respectively. They account for 7/24, 12/24, 1/24, and 4/24, respectively; there are 4 reliability positions for 256QAM ( L=4).

The system of equations T ₂ obtained from the constraints is:

For the above equation T ₂ , the optimization space is set to (m ₃₂ , m ₄₂ , m ₁₃ , m ₄₃ , m ₁₆ , m ₂₆ , m ₄₆ , m ₂₈ , m ₃₈ ) with a dimension of 9; the unknown is m ₁₂ m ₂₂ , m ₂₃ , m ₃₃ , m ₃₆ , m ₁₈ , m ₄₈ . The initial value of each element in the optimization space is set to the real number in the interval [0,1], and the unknown number obtained after bringing it into the equation group T ₂ must also fall within the interval [0,1].

The optimized interleaving map obtained by the optimization algorithm is shown in Table 2 below:

m_j,i m _j,i	i＝2i=2	i＝3i=3	i＝6i=6	i＝8i=8
j＝1j=1	0.0025110.002511	0.3275000.327500	0.4243750.424375	0.4070120.407012
j＝2j=2	0.0027620.002762	0.4437530.443753	0.4456250.445625	0.0525000.052500
j＝3j=3	0.5447270.544727	0.1653090.165309	0.0432030.043203	0.0400000.040000
j＝4j=4	0.4500000.450000	0.0634380.063438	0.0867970.086797	0.50040.5004

Table 2

The first LDPC code corresponding to the B' ₂ (H) is interleaved to obtain a second LDPC code, and the PEXIT analysis tool in the optimization method can calculate the convergence threshold of the interleaving to be 10.718 dB, and converge in the non-interleaving case. The threshold is 10.891 dB, so theoretically interleaving by the method of the embodiment of the present invention, a gain of about 0.17 dB can be obtained.

5 is a schematic diagram of comparison of gain results according to an embodiment of the present invention. The simulated channel environment is an AWGN channel, and the demodulation method is Log-MAP. In the BICM system, the decoding algorithm is BP algorithm, and the maximum number of iterations is set. 50 times. In the BICM-ID side system, the decoding algorithm is BP algorithm, the maximum number of iterations is set to 50 times, and the maximum number of iterative demodulation decodings is set to 10 times.

As can be seen from FIG. 5, the optimized interleaving ratio gain given by the embodiment of the present invention is significant. The BICM system has a gain of approximately 0.2 dB at a FER of 10 ^-1 , which is very close to the results of the PEXIT analysis. The gain of the BICM-ID is approximately 0.4 dB.

The modulation mode is 256QAM, and the codeword is the (1944, 1458) QC-LDPC code in IEEE802.11n. The base matrix B ₃ '(H) of the code (ie, the first LDPC code) is structured as follows:

There are three types of columns in the matrix, namely 2, 3, and 6, which account for 6/24, 13/24, and 5/24, respectively; there are 4 reliability positions for 256QAM (L=4).

The system of equations T ₃ obtained from the constraints is:

For the above equation T ₃ , the optimization space is set to (m ₃₂ , m ₄₂ , m ₁₃ , m ₄₃ , m ₁₆ , m ₂₆ ) with a dimension of 6; the unknown is m ₁₂ , m ₂₂ , m ₂₃ , m ₃₃ , m ₃₆ , m ₄₆ . The initial value of each element in the optimization space is set to the real number in the interval [0,1], and the unknown number obtained after bringing it into the equation group T ₃ must also fall within the interval [0,1].

The optimal solution (ie, the interleaving map) obtained by the optimization algorithm is shown in Table 3 below:

m_j,i m _j,i	i＝2i=2	i＝3i=3	i＝6i=6
j＝1j=1	0.0001250.000125	0.2687500.268750	0.4176040.417604
j＝2j=2	0.0127700.012770	0.3788430.378843	0.1685310.168531
j＝3j=3	0.5253240.525324	0.2198850.219885	0.0858140.085814
j＝4j=4	0.4617810.461781	0.1325220.132522	0.328050.32805

table 3

The first LDPC code corresponding to the B' ₃ (H) is interleaved to obtain a second LDPC code, and the PEXIT analysis tool in the optimization method can calculate the convergence threshold of the interleaving to be 12.237 dB, and converge in the non-interleaving case. The threshold is 12.323 dB, so theoretically interleaving by the method of the embodiment of the present invention, a gain of about 0.086 dB can be obtained.

6 is a schematic diagram of comparison of gain results according to an embodiment of the present invention. The simulated channel environment is an AWGN channel, and the demodulation method is Log-MAP. In the BICM system, the decoding algorithm is BP algorithm, and the maximum number of iterations is set. 50 times. In the BICM-ID side system, the decoding algorithm is BP algorithm, the maximum number of iterations is set to 50 times, and the maximum number of iterative demodulation decodings is set to 10 times.

As can be seen from FIG. 6, the optimized interleaving ratio gain given by the embodiment of the present invention is significant. The BICM system has a gain of approximately 0.12 dB at a FER of 10 ^-1 , which is very close to the results of the PEXIT analysis. The gain of the BICM-ID is approximately 0.2 dB.

Optionally, after the foregoing step 202, the method further includes the step of mapping the second LDPC code. Referring to FIG. 7, the method for data transmission according to the embodiment of the present invention is further provided. :

Step 203: The transmitting device separately obtains L real bits and L imaginary bits into a modulation symbol from the second LDPC code, where L real bits have L different reliability levels, L virtual The partial bits have L different reliability levels, and the L real bits and the L imaginary bits are respectively from different positions in the second LDCP code. Here, as described in the foregoing embodiment, L is the number of reliability levels of modulation symbols corresponding to the modulation scheme.

If the second LDPC code includes 2n*L bits, the transmitting device acquires L real bits and L imaginary bits into a modulation symbol each time the unmapped bit position is obtained, wherein the L real bits have L For different reliability levels, the L imaginary bits have L different reliability levels and are respectively from different positions in the second LDPC code, and the second LDPC code can be mapped into n modulation symbols. For example, the number of reliability levels in the second LDPC code is 2, and the second LDPC code includes {a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ , a ₇ , a ₈ }, wherein The bits of one reliability level are {a ₁ , a ₂ , a ₃ , a ₄ }, and the bits having the second reliability level are {a ₅ , a ₆ , a ₇ , a ₈ }, then { a ₁ , a ₅ } as the real part sequence, {a ₂ , a ₆ } as the imaginary part sequence, together mapped to one modulation symbol m ₁ ; {a ₃ , a ₇ } as the real part sequence, {a ₄ , a ₈ } as an imaginary sequence, mapped together as a modulation symbol m ₂ . It should be noted that this is just an example.

Further, before the mapping, the bits in the real part sequence and the imaginary part sequence may be arranged in descending order of reliability level, for example, based on the LDPC code of the foregoing example, if the first reliability level The number is lower than the second reliability level, then {a ₅ , a ₁ } is the real part sequence, and {a ₆ , a ₂ } is used as the imaginary part sequence, and is mapped together as one modulation symbol m ₁ ; {a ₇ , a ₃ } As a real part sequence, {a ₈ , a ₄ } is taken as an imaginary part sequence and mapped together as one modulation symbol m ₂ . It should be noted that these are only convenient examples.

The above step 203 is a process of mapping the second LDPC code obtained after interleaving.

Optionally, a specific process for mapping the second LDPC code obtained by interleaving is provided, where the sending device includes L sets of memory for storing bits of L reliability levels of the second LDPC code, respectively. The total number of bits stored in any two groups in the L group memory is the same, the reliability of the memory in any one of the L group memories is the same, and the reliability of the memory between any two groups in the L group memory is different.

The following two scenarios are explained:

Case 1: Each group of memory includes 1 memory

The transmitting device reads 1 unread bits from each memory in the L group memory to form L real bits, and reads 1 unread bits from each memory in the L group memory to form L imaginary bits. The L real bits and the L imaginary bits are respectively arranged according to the reliability of the L group of memories, and are mapped to one modulation symbol.

FIG. 8 is a schematic diagram of a mapping process according to an embodiment of the present invention. FIG. 8 is a schematic diagram based on the mapping distribution shown in Table 1 above, wherein the number of groups of the memory is L=4, and each group only includes One memory, thus a total of four memories, and four memories correspond to different degrees of reliability.

Based on Table 1 above, it can be obtained that the number of bits stored in each of the four memories is respectively (where the total number of bits in each group of memories is 486 (ie, 1944/4=486)):

The number of bits of the corresponding column weights of 2, 3, 4, 11 included in the memory corresponding to the first reliability level of the symbol (ie, the memory 1 in FIG. 8) are respectively 203, 219, 64, 0;

The number of bits of the corresponding column weights of 2, 3, 4, 11 included in the memory corresponding to the symbol second reliability level (ie, the memory 2 in FIG. 8) are 167, 265, 4, 50, respectively;

The number of bits of the corresponding column weights of 2, 3, 4, 11 included in the memory corresponding to the third reliability level of the symbol (ie, the memory 3 in FIG. 8) are 255, 174, 9, and 48, respectively;

The number of bits of the corresponding column weights of 2, 3, 4, and 11 included in the memory corresponding to the symbol fourth reliability level (ie, the memory 4 in FIG. 8) are 266, 71, 4, and 145, respectively.

The order of the bits in each group of memory is independent of performance, and can be specifically arranged according to actual conditions.

Based on the above memory, firstly, one unread ratio is read sequentially from the L group memory. The special bits form L real bits according to the reliability of the L group memories from high to low; then, the unread 1 bits are sequentially read from the L group memories, according to the L group. The reliability corresponding to the memory is from high to low, forming L imaginary bits; finally, one modulation symbol is mapped according to the L real bits and the L imaginary bits.

Taking FIG. 8 as an example, one bit is sequentially read from the memory 1 to the memory 4, and four bits are obtained to form a real part of one bit sequence; then, one bit is sequentially read from the memory 1 to the memory 4, respectively. Obtaining 4 bits to form an imaginary part of a sequence of bits; thus obtaining a sequence of bits and mapping the sequence of bits to a modulation symbol on the constellation.

The above steps are repeated until all the bits are read out to obtain a plurality of modulation symbols on the constellation.

Case 2, each group of memory includes 2 ^r memories, r is a positive integer

This situation is similar to the case 1, except that each set of memory contains 2 ^r memories. Specifically, the mapping method is: the transmitting device reads one unread bit from the 2 ^r memories in the L group memory as A real bit, an unread bit as an imaginary bit, constitutes 2 ^r bit sequences, wherein each of the 2 ^r bit sequences consists of L real bits and L imaginary bits The L real bits and the L imaginary bits in each bit sequence are arranged in descending order of reliability corresponding to the L sets of memories, wherein each bit sequence is used to map a modulation symbol. Map 2 ^r modulation symbols.

For example, referring to FIG. 9, FIG. 9 is a schematic diagram of a mapping process according to an embodiment of the present invention, where r=1 is taken as an example, that is, a second LDPC code is divided into L groups of memories, where each group of memory includes two Memory, the memory in the same group has the same level of reliability, and the reliability level of the memory between different groups is different.

Taking the above Table 1 as an example, it can be obtained that the number of bits stored in each group of memories in the L group memory is (where L=4, and the total number of bits in each group of memories is 486 (ie, 1944/4=486)):

The number of bits of the corresponding column weights of 2, 3, 4, 11 included in the memory corresponding to the first reliability level of the symbol (ie, the memory 1 + the memory 2 in FIG. 9) are 203, 219, 64, 0, respectively;

The number of bits of the corresponding column weights of 2, 3, 4, 11 included in the memory corresponding to the symbol second reliability level (ie, the memory 3 + the memory 4 in FIG. 9) are 167, 265, 4, 50, respectively;

The number of bits of the corresponding column weights of 2, 3, 4, 11 included in the memory corresponding to the symbol third reliability level (ie, the memory 5 + the memory 6 in FIG. 9) are 255, 174, 9, 48, respectively;

The number of bits of the corresponding column weights of 2, 3, 4, and 11 included in the memory corresponding to the fourth reliability level of the symbol (i.e., the memory 7 + the memory 8 in FIG. 9) are 266, 71, 4, and 145, respectively.

Wherein, how many bits are stored in each memory in each group of memory, which is set according to the actual situation, and is not limited thereto. For example, taking the first group of memories as an example, the memory 1 and the memory 2 are included, wherein the memory The sum of the bits in 1 and the memory 2 is: the number of bits corresponding to the column weights of 2, 3, 4, and 11, is 203, 219, 64, and 0, respectively. For example, for the memory 1, the number of bits corresponding to 2, 3, 4, and 11 is 100, 100, 10, and 0, respectively; for the memory 2, the number of bits corresponding to 2, 3, 4, and 11 is 103, 119, and 54, respectively. 0, of course, can also be any other allocation method.

When mapping is performed, when it is necessary to read a bit from a group, bits can be read from any of the memories of the group. For example, one bit can be read from the memory 1 shown in FIG. One bit is read in the memory 4, one bit is read from the memory 5, one bit is read from the memory 7, and four bits are obtained to form a real part of one bit sequence; read from the memory 2 One bit is read from the memory 3, one bit is read from the memory 6, one bit is read from the memory 8, and four bits are obtained to form an imaginary part of one bit sequence, thereby constituting one bit. A sequence of bits and maps the sequence of bits to a modulation symbol on the constellation. Since the sum of the bits of all memory stored in one memory bank is the same, the mapping can be done correctly.

The advantage of providing multiple memories in a memory bank in the above manner is that the multiple symbols can be mapped in parallel to increase the BICM gain.

Optionally, the transmitting device in the embodiment of the present invention may further modulate and transmit the modulation symbol obtained in step 203 above.

Optionally, the check matrix of the first LDPC code in the embodiment of the present invention may also be a check matrix having a Raptor like structure. In this case, the mapping proportion in the mapping distribution has the following characteristics: according to the mapping The ratio of the shots is such that the majority of the bits corresponding to the smallest and largest columns of the check matrix of the first LDPC code are mapped to the lower reliability bits to obtain the second LDPC code.

Based on the same inventive concept, an embodiment of the present invention further provides a data transmission method. As shown in FIG. 10, the method is performed by a receiving device, and the receiving device is configured to receive a modulation symbol from a sending device, where the method specifically includes the following step:

Step 1001: The receiving device acquires a second LDPC code by demodulating the received signal.

Step 1002: The receiving device deinterleaves the second LDPC code to obtain a first LDPC code, where a bit with a column weight i in the second LDPC code corresponds to a jth type of the modulation symbol in the second LDPC code. The ratio of the position of the reliability level is m _j,i , where

In the above step 1001, the signal received by the receiving device is encoded by the transmitting device to obtain a first LDPC code, and the first LDPC code is interleaved to obtain a second LDPC code, and the second LDPC code is mapped and modulated. The signal is obtained and sent to the receiving device. Therefore, after receiving the signal sent by the transmitting device, the receiving device first performs demodulation (including demapping further) to obtain a second LDPC code.

In the foregoing step 1002, the receiving device deinterleaves the second LDPC code to obtain a first LDPC code, where a bit with a column weight i in the second LDPC code corresponds to a jth type of the modulation symbol in the second LDPC code. The ratio of the positions of the reliability series is m _j,i , and optionally, the mapping ratio m _j,i satisfies the constraints of the following equations:

Wherein, the system of equations comprises L+K equations, L is a reliability level of a modulation symbol corresponding to the modulation mode, and K is a type of column weight in a base matrix of a check matrix of the first LDPC code The number of Λ _i is the proportion of the variable nodes whose column weight is i in the base matrix, 0 ≤ m _{j, i} ≤ 1.

Optionally, the check matrix of the first LDPC code has a Raptor like structure. In this case, the mapping ratio has the following feature: on the sending device side, according to the mapping ratio, the check matrix of the first LDPC code is listed. Most of the bits corresponding to the smallest and largest columns are mapped to locations with lower reliability to obtain a second LDPC code.

Optionally, the receiving device further performs channel decoding on the first LDPC code to obtain decoded information data.

Based on the same inventive concept, the embodiment of the present invention further provides a sending device 1100, where the sending device 1100 is configured to perform the data transmission on the sending device side, as shown in FIG.

The encoding unit 1101 is configured to: after encoding the information data, obtain an LDPC code;

The interleaving unit 1102 is configured to perform interleaving on the first LDPC code according to the mapping distribution to obtain a second LDPC code.

In the embodiment of the present invention, the transmitting device obtains the first LDPC code by encoding the information data, and then interleaves the first LDPC code according to the mapping distribution to obtain a second LDPC code, which is compared with the threshold analysis method in the background art. In the embodiment of the present invention, a mapping distribution is pre-calculated, and then the first LDPC code is interleaved according to the mapping distribution. The mapping distribution in the embodiment of the present invention may be obtained according to a check matrix and a modulation mode of the first LDPC code. Therefore, an optimal mapping distribution corresponding to the first LDPC code can be obtained by calculation, so that the interleaved LDPC code obtains the maximum gain, and the interleaving method in the embodiment of the present invention is compared with the background technology. , a larger gain can be obtained, thereby increasing the gain obtained when the LDPC code is interleaved.

Optionally, the mapping distribution includes at least one mapping ratio m _j,i ,

Optionally, the interleaving unit 1102 is configured to: distribute, according to the mapping distribution, a bit with a weight of i in the first LDPC code to a jth reliability of a corresponding modulation symbol in the second LDPC code. Position of the series, such that the ratio of the bit of the second LDPC code whose weight is i is the position of the jth reliability level of the modulation symbol in the second LDPC code is m _j,i ;

i is an integer and is a value of any column in the interval [dv.min, dv.max], dv.min is equal to the minimum column weight of the check matrix of the first LDPC code, dv.max and the first The maximum column weight of the parity check matrix of an LDPC code is equal.

Optionally, the mapping ratio m _j,i satisfies the constraints of the following system of equations:

Optionally, the sending device further includes a first mapping unit 1103, configured to separately obtain L real bits and L imaginary bits into a modulation symbol from the second LDPC code, where, The real bits have L different reliability levels, the L imaginary bits have L different reliability levels, and the L real bits and the L imaginary bits are respectively from different positions in the second LDCP code.

Optionally, the sending device further includes an L group of memories, configured to store bits of L reliability levels of the second LDPC code, where the total number of bits stored in any two groups in the L group of memories is the same. The reliability of the memory in any one of the L group memories is the same, and the reliability of the memory between any two groups of the L group memories is different;

The transmitting device further includes a second mapping unit 1104, configured to read 1 bit from each memory in the L group of memory to form L real bits if each group of memories includes one memory. Each memory in the L-group memory reads 1 bit to form L imaginary bits, and the L real bits and the L imaginary bits are respectively according to the reliability of the L-group memory from high to low. Arrange, map to a modulation symbol; or,

Optionally, the check matrix of the first LDPC code has a Raptor like structure.

Optionally, the sending device further includes a sending unit 1105, configured to modulate and transmit the modulation symbol.

Based on the same inventive concept, the embodiment of the present invention further provides a receiving device 1200, where the receiving device 1200 is configured to perform data transmission on the receiving device side, as shown in FIG. 12, including:

a receiving unit 1201, configured to receive a signal;

a demapping unit 1202, configured to obtain a second LDPC code by demodulating the signal;

The deinterleaving unit 1203 is configured to deinterleave the second LDPC code to obtain a first LDPC code, where a bit with a column weight i in the second LDPC code corresponds to a modulation symbol in the second LDPC code The ratio of the positions of the j reliability levels is m _j,i , where

Optionally, the receiving device further includes a decoding unit 1204, configured to perform channel decoding on the first LDPC code to obtain information data.

Based on the same inventive concept, the embodiment of the present invention further provides a transmitting device 1300, as shown in FIG. 13, including an encoder 1301, an interleaver 1302, a mapper 1303, a transmitter 1304, and an L-group memory 1305;

The encoder 1301 is configured to encode the information data to obtain an LDPC code.

The interleaver 1302 is configured to interleave the first LDPC code according to a mapping distribution to obtain a second LDPC code.

Optionally, the interleaver 1302 is specifically configured to:

And distributing, according to the mapping distribution, a bit of the first LDPC code with a weight of i to a position of the jth reliability level of the corresponding modulation symbol in the second LDPC code, so that the second LDPC code is The ratio of the bit of the column i in the second LDPC code corresponding to the position of the jth reliability level of the modulation symbol is m _j,i ;

Optionally, the mapper 1303 is configured to separately obtain L real bits and L imaginary bits into a modulation symbol from the second LDPC code, where the L real bits have L different types. The reliability level, the L imaginary bits have L different reliability levels, and the L real bits and the L imaginary bits are respectively from different positions in the second LDCP code.

Optionally, the L group of memories 1305 are respectively configured to store bits of L reliability levels of the second LDPC code, and the total number of bits stored in any two groups in the L group of memories is the same, the L group The reliability of the memory in any group in the memory is the same, and the reliability of the memory between any two groups of the L group memory is different;

The mapper 1303 is specifically configured to: if each group of memories includes one memory, read 1 bit from each of the L groups of memories to form L real bits, from the L group of memories. Each memory reads 1 bit to form L imaginary bits, and the L real bits and the L imaginary bits are respectively arranged according to the reliability of the L group of memories, and the L real bits and the L imaginary bits are mapped into one modulation symbol; or

Optionally, the transmitter 1304 is configured to modulate and transmit the modulation symbol.

Based on the same inventive concept, an embodiment of the present invention further provides a receiving device 1400, including a receiver 1401, a demapper 1402, a deinterleaver 1403, and a decoder 1404;

The receiver 1401 is configured to receive a signal;

The demapper 1402 is configured to obtain a second LDPC code by demodulating the signal;

The deinterleaver 1403 is configured to perform deinterleaving on the second LDPC code to obtain a first LDPC code, where a bit of the second LDPC code with a weight of i is correspondingly modulated in the second LDPC code. The ratio of the position of the jth reliability level of the symbol is m _j,i , where

Optionally, the decoder 1404 is configured to perform channel decoding on the first LDPC code to obtain information data.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, or a computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. Instructions are provided for implementation in the flowchart The steps of a process or a plurality of processes and/or block diagrams of a function specified in a block or blocks.

While the preferred embodiment of the invention has been described, it will be understood that Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and the modifications and

It will be apparent to those skilled in the art that various modifications and changes can be made in the present invention without departing from the scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention

Claims

A method for data transmission, comprising:

The transmitting device encodes the information data to obtain a first low density parity check LDPC code;

Transmitting, by the sending device, the first LDPC code according to a mapping distribution to obtain a second LDPC code.
The method according to claim 1, wherein said mapping distribution comprises at least one mapping ratio m j,i ,

a ratio of a bit of the second LDPC code whose weight is i in the second LDPC code corresponding to a position of the jth reliability level of the modulation symbol is m j,i , where

i is an integer and is a value of any column in the interval [dv.min, dv.max], dv.min is equal to the minimum column weight of the check matrix of the second LDPC code, dv.max and the first The maximum column weight of the parity check matrix of the two LDPC codes is equal.

j is a positive integer and is any reliability level in the [1, L] interval, and L is the number of reliability levels of the modulation symbols corresponding to the modulation scheme.
The method according to claim 2, wherein the transmitting device interleaves the first LDPC code according to a mapping distribution to obtain a second LDPC code, including:

Transmitting, by the sending device, a bit with a weight of i in the first LDPC code to a position of a jth reliability level of the corresponding modulation symbol in the second LDPC code according to the mapping distribution, so that the first The ratio of the bit whose weight is i in the two LDPC codes in the second LDPC code corresponds to the position of the jth reliability level of the modulation symbol is m j,i .
The method according to any one of claims 1 to 3, wherein the mapping distribution is obtained according to a check matrix and a modulation mode of the first LDPC code.
The method according to claim 4, wherein said mapping ratio m j,i satisfies the constraints of the following system of equations:

Wherein, the system of equations comprises L+K equations, L is a number of reliability levels of modulation symbols corresponding to the modulation mode, and K is a column in a base matrix of a check matrix of the first LDPC code The number of weights, Λ i is the proportion of the variable nodes whose column weight is i in the base matrix, 0 ≤ m j, i ≤ 1.
The method according to any one of claims 1 to 5, further comprising:

The transmitting device respectively obtains L real bits and L imaginary bits into a modulation symbol from the second LDPC code, wherein the L real bits have L different reliability levels, and the L imaginary bits have L different reliability levels, L real bits and L imaginary bits are respectively from different positions in the second LDCP code.
The method according to any one of claims 1 to 5, further comprising:

The transmitting device includes L groups of memories for storing L types of reliability level bits of the second LDPC code, and the total number of bits stored in any two groups of the L group memories is the same. The reliability of the memory within a group is the same, and the reliability of the memory between any two groups of the L group of memories is different;

If each set of memory includes one memory, the transmitting device reads 1 bit from each of the L sets of memories to form L real bits, and the transmitting device from each of the L sets of memories A memory reads 1 bit to form L imaginary bits, and the L real bits and the L imaginary bits are respectively arranged according to the reliability of the L group of memories, and the transmitting device will Mapping the L real bits and the L imaginary bits into one modulation symbol; or

If each group of memories includes 2 r memories, r is a positive integer, the transmitting device reads 1 bit from the 2 r memories in the L group memory as real bits, 1 bit as imaginary bits Constructing 2 r bit sequences, wherein each of the 2 r bit sequences is composed of L real bits and L imaginary bits, respectively, L real bits in each bit sequence From the L group of memories, and arranged in descending order of reliability of the L sets of memories, the L imaginary bits in each bit sequence are respectively from the L group of memories, and according to The reliability of the L-group memories is ranked from high to low, and each bit sequence is used to map one modulation symbol.
The method according to any one of claims 1 to 7, wherein the check matrix of the first LDPC code has a Raptor like structure.
The method according to any one of claims 1 to 8, wherein the method further comprises:

The transmitting device modulates and transmits the modulation symbol.
A method for data transmission, comprising:

The receiving device acquires the second LDPC code by demodulating the received signal;

The receiving device deinterleaves the second LDPC code to obtain a first LDPC code, where a bit with a column weight i in the second LDPC code is reliable in the jth type of the corresponding modulation symbol in the second LDPC code. The ratio of the position of the degree series is m j,i , where

i is an integer and is a value of any column in the interval [dv.min, dv.max], dv.min is equal to the minimum column weight of the check matrix of the second LDPC code, dv.max and the first The maximum column weight of the parity check matrix of the two LDPC codes is equal.

j is a positive integer and is any reliability level in the [1, L] interval, and L is the number of reliability levels of the modulation symbols corresponding to the modulation scheme.
The method according to claim 10, characterized in that said mapping ratio m j,i satisfies the constraints of the following system of equations:

Wherein, the system of equations comprises L+K equations, L is a number of reliability levels of modulation symbols corresponding to the modulation mode, and K is a column in a base matrix of a check matrix of the first LDPC code The number of weights, Λ i is the proportion of the variable nodes whose column weight is i in the base matrix, 0 ≤ m j, i ≤ 1.
The method according to claim 10 or 11, wherein the check matrix of the first LDPC code has a Raptor like structure.
The method according to any one of claims 10 to 12, wherein the method further comprises:

The receiving device performs channel decoding on the first LDPC code to obtain information data.
A transmitting device, comprising:

a coding unit, configured to encode the information data to obtain a first LDPC code;

And an interleaving unit, configured to interleave the first LDPC code according to the mapping distribution to obtain a second LDPC code.
The transmitting device according to claim 14, wherein the mapping distribution comprises at least one mapping ratio m j,i ,

a ratio of a bit of the second LDPC code whose weight is i in the second LDPC code corresponding to a position of the jth reliability level of the modulation symbol is m j,i , where

i is an integer and is a value of any column in the interval [dv.min, dv.max], dv.min is equal to the minimum column weight of the check matrix of the second LDPC code, dv.max and the first The maximum column weight of the parity check matrix of the two LDPC codes is equal.

j is a positive integer and is any reliability level in the [1, L] interval, and L is the number of reliability levels of the modulation symbols corresponding to the modulation scheme.
The transmitting device according to claim 14, wherein the interleaving unit is specifically configured to:

And distributing, according to the mapping distribution, a bit of the first LDPC code with a weight of i to a position of the jth reliability level of the corresponding modulation symbol in the second LDPC code, so that the second LDPC code is The ratio of the bit whose weight is i in the second LDPC code corresponding to the position of the jth reliability level of the modulation symbol is m j,i .
The transmitting device according to any one of claims 14 to 16, wherein the mapping distribution is obtained according to a check matrix and a modulation mode of the first LDPC code.
The transmitting device according to claim 17, wherein said mapping ratio m j,i satisfies a constraint of the following system of equations:

Wherein, the system of equations comprises L+K equations, L is a number of reliability levels of modulation symbols corresponding to the modulation mode, and K is a column in a base matrix of a check matrix of the first LDPC code The number of weights, Λ i is the proportion of the variable nodes whose column weight is i in the base matrix, 0 ≤ m j, i ≤ 1.
The transmitting device according to any one of claims 14 to 18, wherein the transmitting device further comprises a first mapping unit, configured to respectively acquire L real bits and L imaginary parts from the second LDPC code The bit map is a modulation symbol, wherein L real bits have L different reliability levels, L imaginary bits have L different reliability levels, L real bits and L imaginary bits They are from different locations in the second LDCP code.
The transmitting device according to any one of claims 14 to 18, wherein the transmitting device further comprises an L group of memories for storing bits of L reliability levels of the second LDPC code, respectively. The total number of bits stored in any two groups in the L group memory is the same, the reliability of the memory in any one of the L group memories is the same, and the reliability of the memory between any two groups of the L group memories is different;

The transmitting device further includes a second mapping unit, configured to read 1 bit from each of the L sets of memory to form L real bits if each set of memory includes one memory, Each memory in the L group of memories reads 1 bit to form L imaginary bits, and the L real bits and the L imaginary bits respectively follow the reliability of the L group of memories from high to Low alignment, mapping the L real bits and the L imaginary bits into one modulation symbol; or

If each group of memories includes 2 r memories and r is a positive integer, one bit is read from the 2 r memories of the L group memories as real bits, and 1 bit is used as imaginary bits, and 2 is formed. r bit sequences, wherein each of the 2 r bit sequences consists of L real bits and L imaginary bits, the L real bits in each bit sequence are from the L group of memories, and arranged according to the reliability of the L group of memories from high to low, wherein the L imaginary bits in each bit sequence are respectively from the L group of memories, and according to the L group The reliability of the memory corresponds to a high to low order, and each bit sequence is used to map one modulation symbol.
The transmitting device according to any one of claims 14 to 20, characterized in that the check matrix of the first LDPC code has a Raptor like structure.
The transmitting device according to claim 14 or 21, wherein the transmitting device further comprises a transmitting unit configured to modulate and transmit the modulation symbol.
A receiving device, comprising:

a receiving unit, configured to receive a signal;

a demapping unit, configured to obtain a second LDPC code by demodulating the signal;

a deinterleaving unit, configured to deinterleave the second LDPC code to obtain a first LDPC code, where a bit with a column weight i in the second LDPC code corresponds to a modulation symbol in the second LDPC code The ratio of the positions of the reliability levels is m j,i , where

i is an integer and is a value of any column in the interval [dv.min, dv.max], dv.min is equal to the minimum column weight of the check matrix of the second LDPC code, dv.max and the first The maximum column weight of the parity check matrix of the two LDPC codes is equal.

j is a positive integer and is any reliability level in the [1, L] interval, and L is the number of reliability levels of the modulation symbols corresponding to the modulation scheme.
The receiving device according to claim 23, characterized in that said mapping ratio m j,i satisfies the constraints of the following system of equations:

Wherein, the system of equations comprises L+K equations, L is a number of reliability levels of modulation symbols corresponding to the modulation mode, and K is a column in a base matrix of a check matrix of the first LDPC code The number of weights, Λ i is the proportion of the variable nodes whose column weight is i in the base matrix, 0 ≤ m j, i ≤ 1.
The receiving device according to claim 23 or 24, wherein the check matrix of the first LDPC code has a Raptor like structure.
The receiving device according to any one of claims 23 to 25, wherein the receiving device further comprises a decoding unit, configured to perform channel decoding on the first LDPC code to obtain information data.