WO2018093675A1

WO2018093675A1 - Hemt having conduction barrier between drain fingertip and source

Info

Publication number: WO2018093675A1
Application number: PCT/US2017/061075
Authority: WO
Inventors: Jungwoo Joh; Naveen Tipirneni; Chang Soo Suh; Sameer Pendharkar
Original assignee: Texas Instruments Japan Ltd; Texas Instruments Inc
Current assignee: Texas Instruments Japan Ltd; Texas Instruments Inc
Priority date: 2016-11-17
Filing date: 2017-11-10
Publication date: 2018-05-24
Anticipated expiration: 2019-05-17
Also published as: US9882041B1; CN109952634A; US10680093B2; US11177378B2; CN109952634B; US20180151713A1; US20200303535A1

Abstract

In described examples, a high electron mobility transistor (HEMT) (340) includes an active layer (104) on a substrate (102), and a Group IIIA-N barrier layer (106) on the active layer (104). An isolation region (110) is through the barrier layer (106) to provide at least one isolated active area (106/104) including the barrier layer (106) on the active layer (104). A gate (114) is over the barrier layer (106). A drain includes at least one drain finger (120a) including a fingertip (120a₁) having a drain contact (120b) extending into the barrier layer (106) to contact to the active layer (104), and a source (122) having a source contact (122a) extending into the barrier layer (106) to contact to the active layer (104). The source (122) forms a loop that encircles the drain. The isolation region (110) includes a portion (110") positioned between the source (122) and drain contact (120b), so a conduction barrier is in a length direction between the drain contact (120b) of the fingertip (120a₁) and the source (122).

Description

HEMT HAVING CONDUCTION BARRIER BETWEEN DRAIN FINGERTIP AND SOURCE

[0001] This relates to Group IIIA-N (e.g., Gallium Nitride) high electron mobility field effect transistors (HEMTs).

BACKGROUND

[0002] Gallium-nitride (GaN) is a commonly used Group IIIA-N material for electronic devices, where Group IDA elements such as Ga (and boron, aluminum, indium, and thallium) are also sometimes referred to as Group 13 elements. GaN is a binary IIIA/V direct band gap semiconductor that has a Wurtzite crystal structure. Its relatively wide band gap of 3.4 eV at room temperature (vs. 1.1 eV for silicon at room temperature) affords it special properties for a wide variety of applications in optoelectronics, and high-power and high-frequency electronic devices.

[0003] GaN-based HEMTs feature a junction between two materials with different band gaps to form a heteroj unction or heterostructure. The HEMT structure is based on a very high electron mobility, described as a two-dimensional electron gas (2DEG) which forms just below a heterostructure interface between a barrier layer (that typically comprises AlGaN) on a generally intrinsic active layer (that typically comprises GaN) due to the piezoelectric effect and a natural polarization effect. A power FET device has a gate, source electrode, and drain electrode, where the source electrode and drain electrode each include contacts that extend through the top barrier layer to form an ohmic contact with the underlying 2DEG in the surface of the active layer. One Group IIIA-N HEMT layout is a drain centered layout, in which the high voltage drain area is completely enclosed by the gate and by the source. This layout has advantages including regarding device isolation, edge termination, and leakage current control.

SUMMARY

[0004] In described examples, for drain centered Group IIIA-N HEMT during device operation near the drain contact of the fingertip of the drain finger, generally a high concentration of 'hot' carriers can degrade and destroy (e.g., melt) the device, especially under high power switching conditions. By providing an isolation region that is through the barrier layer around the drain contact fingertip of the drain finger, so that a resulting conduction barrier is provided in a length direction of the drain finger between the drain contact of the fingertip and the source, the conduction barrier suppresses the hot carrier injection problem, thus improving device robustness and reliability.

[0005] The isolation region can be formed by patterning the barrier layer to form an active area Mesa structure having adjacent conduction barriers, or can comprise an implanted isolation region with no need for etching the barrier layer. In the case of an active area Mesa having an adjacent conduction barrier, the Mesa boundary can be rounded by using a grey scale mask to suppress leakage or breakdown that may otherwise occur along the Mesa edge.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIGS. 1 A-C provide successive top perspective cross sectional views that correspond to steps in an example method for forming a Group IIIA-N HEMT having an isolation region including a portion positioned between the source and the drain contact, so a conduction barrier is in a length direction of the drain finger between the drain contact fingertip and the source, according to an example embodiment. The view in FIG. 1C is rotated 180 degrees from the views shown in FIGS. 1A and IB, and is only showing a portion of the active areas shown in FIGS. 1 A and IB.

[0007] FIG. 2 is a top view of a Group IIIA-N HEMT having a drain fingertip on an isolation region, according to an example embodiment.

[0010] FIG. 3A is a zoomed in top view of a portion of a conventional Group IIIA-N HEMT having a drain centered layout.

[0011] FIG. 3B is a zoomed in top view of a portion of a first example Group IIIA-N HEMT having a drain centered layout with an isolation region including a portion positioned between the source and the drain contact, so a conduction barrier is in a length direction of the drain finger between the drain contact of the fingertip and the source.

[0012] FIG. 3C is a zoomed in top view of a portion of a second example Group IIIA-N HEMT having a drain centered layout with an isolation region including a portion positioned between the source and the drain contact, so a conduction barrier is in a length direction of the drain finger between the drain contact of the fingertip and the source.

[0013] FIG. 3D is a zoomed in top view of a portion of another Group IIIA-N HEMT having a drain centered layout with an isolation region including an isolation region portion positioned between the source and the drain contact, so a conduction barrier is in a length direction of the drain finger between the drain contact of the fingertip and the source. The HEMT features its drain contact extending in the length direction of the drain finger beyond the source contact to further suppress the current crowding effect.

[0014] FIG. 4 shows actual 600V hard switching yield data that compares results from a Group IIIA-N HEMT having a conventional drain centered layout and a described Group IIIA-N HEMT having a drain centered layout with a drain contact on an isolation region including a portion positioned between the source and the drain contact, so a conduction barrier is in a length direction of the drain finger between the drain contact fingertip and the source.

DETAILED DESCRIPTION OF EXAMPLE EMB ODFMENT S

[0015] The drawings are not necessarily drawn to scale. In the drawings, like reference numerals designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may be optional to implement a methodology in accordance with this description.

[0016] The terms "coupled to" or "couples with" (and the like), as used herein without further qualification, describe either an indirect or direct electrical connection. Thus, if a first device "couples" to a second device, that connection can be through a direct electrical connection where only parasitics are in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal, but may adjust its current level, voltage level and/or power level.

[0017] FIGS. 1 A-C provide successive top perspective cross sectional views that correspond to steps in an example method for forming a described Group IIIA-N HEMT having an isolation region including a portion positioned between the source and the drain contact, so a conduction barrier is in a length direction of the drain contact of the drain contact fingertip and the source, according to an example embodiment. As described hereinabove, the view in FIG. 1C is rotated 180 degrees from the view shown in FIGS. 1A and IB, and is only showing a portion of the active areas shown in FIGS. 1A and IB.

[0018] An in-process HEMT is shown in FIG. 1A comprising a substrate 102, at least one Group IIIA-N buffer layer 103 on the substrate 102, a Group IIIA-N active layer 104 on the buffer layer 103, and a Group IIIA-N barrier layer 106 on the active layer 104. A 2DEG is formed in the active layer 104 near its heteroj unction throughout its interface with the barrier layer 106. The barrier layer 106, the active layer 104 and the buffer layer 103 are generally all epitaxial layers on the substrate 102. A patterned masking material 108 (e.g., photoresist) is shown on the barrier layer 106 that is used to define the isolation regions 110 which defines the active areas. The T-shape pattern shape shown is only for example.

[0019] The substrate 102 can comprises sapphire, silicon, silicon carbide (SiC) or GaN. The Group IIIA-N buffer layer 103 is generally present on the substrate 102, but is not needed when a gallium nitride (GaN) substrate is used. For example, the active layer 104 can comprise 25 to 1,000 nanometers of GaN. The active layer 104 may be formed so as to minimize crystal defects which may have an adverse effect on electron mobility. The active layer 104 is commonly undoped (e.g., undoped GaN).

[0020] For example, the barrier layer 106 can comprise 8 to 30 nanometers of Al_xGai_-xN or In_xAl_yGai_-x-yN. Also, for example, a composition of Group IIIA elements in the barrier layer 106 may be 24 to 28 percent atomic weight aluminum nitride and 72 to 76 percent atomic weight gallium nitride. Forming the barrier layer 106 on the active layer 104 generates a 2DEG in the active layer 104 throughout its interface with the barrier layer 106 just below the barrier layer 106, such as with an electron density of l >< 10¹² to 2>< 10¹³ cm^~2. The barrier layer 106 may include an optional capping layer, such as comprising GaN, on a top surface of the barrier layer 106.

[0021] The patterned masking material 108 functioning as an isolation mask is used to form isolation regions 110 that define at least isolated active area from the barrier layer 106 and active layer 104, with the results shown in FIG. IB showing two active area 106/104. FIG. IB shows isolation regions 110 that lack the barrier layer 106 which surround an isolated active area 106/104 having the barrier layer 106 on the active layer 104 to provide the 2DEG. For example, the isolation mask using the patterned masking material 108 may include 200 nanometers to 2 microns of photoresist formed by a photolithographic process. The forming the isolation regions 110 can comprises a Mesa etch process. For example, a blanket barrier layer 106 can be patterned using a greyscale mask followed by an etch to provide rounded edges. As shown in FIG. IB, this Mesa etch process besides etching through the barrier layer 106 also removes a portion of the active layer 104.

[0022] Uusing a greyscale mask enables micro-lithographers to shape resist using a single exposure with a custom attenuating mask comprising sub-resolution pixels. The isolation process using patterned masking material 108 may also be an isolation implant(s) which selectively implants dopants into the barrier layer 106 and into the active layer 104 to form a heavily doped isolation barrier. In either case the isolation region 110 functions as a conduction barrier that reduces or eliminates electrical current in the 2DEG from crossing therethrough.

[0023] A gate 114, drain contact 120b and a source 122 with source contact 122a are formed within the active areas 106/104 with the results shown in FIG. 1C for a portion of active areas 106/104 that include a portion of a drain contact 120b with its drain finger 120a including the drain fingertip 120al and a portion of the source 122 and source contact 122a shown. As described hereinabove, the view in FIG. 1C is rotated 180 degrees from the view shown in FIGS. 1 A and IB, and each active area 106/104 is only a portion of what is shown in FIGS. 1 A and IB. The gate 114 is shown formed over the barrier layer 106. The source contacts and drain contacts are generally formed by a masked etch process that selectively etches part of the thickness of the barrier layer 106 to extend into the barrier layer 106 to provide good (low resistance) contact to the 2DEG in the active layer 104 near the interface between the barrier layer 106 and the active layer 104.

[0024] Although not shown in the view provided, the source 122 forms a complete loop that encircles the drain (see FIG. 2 for a source 122 providing encirclement of the drain 120). FIG. 1C shows an example active area boundary 141 and the position of a conventional active area boundary 147. The position of the active area boundary 141 results in the fingertip 120ai being over isolation region 110 including an isolation region portion positioned between the source 122 and the drain contact 120b, so a conduction barrier is in a length direction of the drain contact 120b in the drain finger 120a between the drain contact of the fingertip 120ai and the source 122. In contrast, the position of the conventional active area boundary 147 results in the fingertip 120ai being over the active area 106/104, so no conduction barrier is in a length direction of the drain contact 120b in the drain finger 120a between the drain contact of the fingertip 120ai and the source 122, which undesirably results in hot carriers flowing between the source 122 and the drain contact 120b in the fingertip 120a during device operation as described hereinabove.

[0025] The gate 114, drain including drain contact 120b and the source including the source contact 122a all generally comprise a metal, such as a TiW alloy in one particular embodiment. The respective electrodes can be formed by sputtering a metal stack, such as Ti/Al/TiN in another particular embodiment. Although not shown in FIG. 1C, the source and the drain metal layers are generally on top of a dielectric layer that is on top of the barrier layer 106 and over the gate to prevent shorts to the gate.

[0026] FIG. 2 is a top view of an integrated circuit (IC) 250 including a 2-finger Group IIIA-N HEMT 200 having an isolation region 110 including an isolation portion positioned between the source 122 and the drain contact 120b of the drain 120, so a conduction barrier is in a length direction of the drain contact 120b in the drain fingers 120a between their fingertip 120al and the source 122, according to an example embodiment. IC 250 also includes other circuitry shown as blocks 240 and 245 on another active area 106/104, such as for realizing a DC/DC power converter IC. Although not explicitly shown in FIG. 2 (or FIGS. 3A-3D), electrical isolation is between the metal providing the gate 114 and the source 122. In one embodiment, a dielectric layer is over the metal of the gate 114, where the metal of the source 122 is on top of the dielectric layer on the gate metal to form field plates. In another embodiment, a spacing is between the metal of the source 122 and the gate 114, so that this dielectric layer between the source and gate metal is not needed.

[0027] The area of the drain 120 is shown completely enclosed by both the gate 114 and by the source 122. The active area 106/104 is shown to be enclosed by the isolation region 110 which includes only active layer 104 (no barrier layer 106). The active area 106/104 in this embodiment can comprise a Mesa (raised in height due to unremoved barrier layer 106 on the active layer 104) as compared to the isolation region 110 which in the Mesa embodiment lacks at least the barrier layer 106. The gate is 114. The example active area boundary 141 (also in FIG. 2) is shown below the drain contact 120b.

[0028] FIG. 3A is a zoomed in top view of a portion of a conventional Group IIIA-N HEMT 300 having a drain centered layout. Electron flow during operation of HEMT 300 is shown by the arrows extending in a 180 degree arc in a path from the source 122 to the drain contact 120b in the fingertip 120al of the drain finger 120a. This electron flow pattern results in a high concentration of 'hot' carriers that can degrade and destroy (e.g., melt) the HEMT device especially under high current switching conditions.

[0029] FIG. 3B is a zoomed in top view of a portion of a Group IIIA-N HEMT 320 having a drain centered layout with an isolation region 110 including an isolation region portion 110' positioned between the source 122 and the drain contact 120b, so a conduction barrier is in a length direction of the drain finger 120a between drain contact 120b of the fingertip 120al and the source 122. By providing an isolation region portion 110' that is through the barrier layer 106 to expose at least the active layer 104 around the fingertip 120al of the drain finger 120a, so that a resulting conduction barrier is provided in a length direction of the drain finger between the drain contact 120b of the fingertip 120al and the source 122, the conduction barrier suppresses the hot carrier injection problem, thus improving device robustness and reliability. The conduction barrier 110' is shown blocking conduction through at least a 150 degree arc in a path from the source 122 to the drain contact 120b of the fingertip 120al .

[0030] FIG. 3C is a zoomed in top view of a portion of a Group IIIA-N HEMT 340 having a drain centered layout with an isolation region 110 including an isolation region portion 110" positioned between the source 122 and the drain contact 120b, so a conduction barrier is in a length direction of the drain finger 120a between the drain contact 120b of the fingertip 120al and the source 122. The pulled back position of the active area boundary 141 results in the isolation cut line and thus the isolation region portion 110" being separated from, shown being below, the drain contact 120b. By providing an isolation region portion 110' that is through the barrier layer 106 to expose the active layer 104 around the fingertip 120al of the drain finger 120a, so a resulting conduction barrier 110" is provided in a length direction of the drain finger between the drain contact 120b of the fingertip 120al and the source 122, the hot carrier injection problem is suppressed, thus improving device robustness and reliability.

[0031] FIG. 3D is a zoomed in top view of a portion of another Group IIIA-N HEMT 370 having a drain centered layout with an isolation region 110 including an isolation region portion 110" positioned between the source 122 and the drain contact 120b, so a conduction barrier is in a length direction of the drain finger 120a between the drain contact 120b in the fingertip 120al and the source 122. As in FIG. 3C, the pulled back position of the active area boundary 141 results in the isolation cut line and thus the isolation region portion 110" being separated from, shown being below, the drain contact 120b. HEMT 370 features its drain contact 120b extending in the length direction of the drain finger 120a beyond the source contact 122a to further suppress the current crowding effect, and is otherwise analogous to the HEMT 340 shown in FIG. 3C. The drain contact extension distance shown as 375 can be from about 1 μπι to about 100 μπι.

[0032] Described HEMTs apply to both enhancement and depletion mode devices. Described HEMTs can be embodied as discrete devices or on ICs such as power converters (e.g., DC/DC converters) and power switches.

[0033] FIG. 4 shows actual 600V hard switching yield data that compares results from a conventional Group IIIA-N HEMT having a drain centered layout and a described Group IIIA-N HEMT having a drain centered layout with a described isolation region 110 including a portion positioned between the source and drain contact, so a conduction barrier is in a length direction of the drain finger between the drain contact 120b of the fingertip 120al and the source 122. The switching yield is shown to be > 99% for the described Group IIIA-N HEMT as compared to about 72% for the conventional Group IIIA-N HEMT.

[0034] Described embodiments can be used to form semiconductor die that may be discrete devices or part of integrated circuits integrated into a variety of assembly flows to form a variety of different devices and related products. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements, including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, Insulated Gate Bipolar Transistor (IGBT), CMOS, BiCMOS and MEMS.

[0035] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

CLAIMS What is claimed is:

1. A method of forming a high electron mobility transistor (HEMT), comprising:

providing a substrate;

forming a Group IIIA-N active layer on the substrate;

forming a Group IIIA-N barrier layer on the active layer;

forming at least one isolation region through the barrier layer to provide at least one isolated active area comprising the barrier layer on the active layer;

forming a gate over the barrier layer;

forming a drain comprising at least one drain finger including a fingertip having a drain contact extending into the barrier layer to provide contact to the active layer, and

forming a source having a source contact extending into the barrier layer to provide contact to the active layer, wherein the source forms a loop that encircles the drain,

wherein the isolation region includes a portion positioned between the source and the drain contact, so a conduction barrier is in a length direction of the drain finger between the drain contact of the fingertip (drain contact fingertip) and the source.

2. The method of claim 1, wherein the fingertip is a curved region, and the conduction barrier blocks conduction through at least a 150 degree arc in a path from the source to the drain contact fingertip.

3. The method of claim 1, wherein the forming the isolation region comprises a Mesa etch process that etches through the barrier layer.

4. The method of claim 3, wherein the forming the isolation region comprises patterning using a greyscale mask so that the Mesa etch process provides rounded edges for edges of the isolated active area.

5. The method of claim 1, wherein the forming the isolation region comprises a masked ion implantation process.

6. The method of claim 1, comprising forming at least one buffer layer on the substrate before forming the Group IIIA-N active layer, wherein the substrate comprises silicon, wherein the Group IIIA-N active layer comprises undoped GaN, and the barrier layer comprises AlGaN.

7. The method of claim 1, wherein the drain contact extends beyond the source contact to further suppress a current crowding effect.

8. The method of claim 1, wherein the HEMT is part of an integrated circuit (IC) formed in and on the substrate.

9. A high electron mobility transistor (HEMT), comprising:

a substrate;

an active layer on the substrate;

a Group IIIA-N barrier layer on the active layer;

at least one isolation region through the barrier layer to provide at least one isolated active area comprising the barrier layer on the active layer;

a gate over the barrier layer;

a drain comprising at least one drain finger including a fingertip including a drain contact extending into the barrier layer to provide contact to the active layer, and

a source including a source contact extending into the barrier layer to provide contact to the active layer, wherein the source forms a loop that encircles the drain;

10. The HEMT of claim 9, wherein the substrate comprises sapphire, silicon, or silicon carbide (SiC).

11. The HEMT of claim 9, wherein the active area comprises a Mesa.

12. The HEMT of claim 9, wherein the drain contact extends beyond the source contact to further suppress a current crowding effect.

13. The HEMT of claim 9, wherein the active area of the isolation region comprises a doped region.

14. The HEMT of claim 9, wherein the HEMT is part of an integrated circuit (IC) formed in and on the substrate.

15. The HEMT of claim 9, comprising at least one buffer layer on the substrate before, wherein the substrate comprises silicon, wherein the active layer comprises undoped GaN, and the barrier layer comprises AlGaN.

16. The HEMT of claim 9, wherein the fingertip is a curved region, and the conduction barrier blocks conduction through at least a 150 degree arc in a path from the source to the drain contact fingertip.