KR20230055221A - GaN RF HEMT Structure and fabrication method of the same - Google Patents

Abstract

The present invention relates to a GaN RF HEMT device and a method for manufacturing the same, wherein a stress reducing substrate 10 and a portion of an upper portion of the stress reducing substrate 10 partially exposed by a first insulating film 22 are separated by a predetermined distance from each other. Contacts the stress reducing substrate 10 through a window formed in the ohmic metal film 21 and the second insulating film 25 disposed above the first insulating film 22 and the ohmic metal film 21. The gate metal 26, the source field plate 27 disposed to be spaced apart from the side surface of the gate metal, and contacting the source field plate 27 and insulated from the gate metal 26, the source-side ohmic It is in contact with the connection metal line 28 extending to the upper side of the metal film 21, the source electrode formed in the region connecting the source-side ohmic metal film 21 and the connection metal line 28, and the drain-side ohmic metal film. It may include a drain electrode and an air bridge 35 electrically connecting a plurality of the source electrodes.

Description

GaN RF HEMT device and its manufacturing method {GaN RF HEMT Structure and fabrication method of the same}

The present invention relates to the structure of a GaN RF HEMT device and its manufacturing method, and to the structure and manufacturing method of a new GaN device that implements a high-performance RF semiconductor using the HEMT (High Electron Mobility Transistor) epitaxial structure of a WBG (Wide Band Gap) semiconductor. It is about its manufacturing method.

So far, most RF semiconductor devices have been developed and used using Si semiconductors that are inexpensive and have long-term reliability and stability, or GaAs and InP-based compound semiconductors with excellent performance.

Among them, the performance of GaAs or InP-based compound semiconductors is excellent at high frequencies of several GHz or higher, but their biggest weakness is that they are physically and electrically vulnerable to shock and unstable.

In recent years, the importance of environment and energy efficiency has increased, and mobile communication including 5G and various radar industries are growing. Such high mobility applications and systems require higher efficiency and smaller RF semiconductors that are resistant to various physical, thermal, and electrical shocks.

Thus, attempts to develop and apply power semiconductors using WBG semiconductor materials such as SiC, GaN, and Ga ₂ O ₃ are active.

As a related technology, US patent US8,404,508B2 (registered on March 26, 2013, Enhancement mode GaN HEMT device and method for fabricating the same) has a structure in which a simple gate and a field plate surrounding the gate are arranged, and a power semiconductor use for

In RF applications that apply high frequencies, electric stress relief by the field plate is insufficient and a large capacitance is applied between the gate and the source, which is disadvantageous to high frequency operation.

In addition, European Patent Publication EP01965433A3 (published on July 29, 2009, High voltage GaN transistor) proposes a device structure in which successive primary, secondary, and tertiary field plates are applied in forming a gate, from 600V to 900V with 5~6.6 mΩ-cm ² low resistance.

However, trench etch is applied to adjust the threshold voltage of the gate, but this method is very disadvantageous in securing reproducibility and uniformity.

In addition, US patent US8,120,064B2 (Wide bandgap transistor devices with field plates, registered on January 21, 2009) uses a gate field plate for the cross-sectional structure of the device, and the gate field plate is 1, 2 , shows the form of arranging up to 3 steps.

A source field plate is more effective in alleviating ESD or electrical stress, but gate operation and reliability are unstable because only a plurality of gate field plates are designed.

And as another example of related prior art, Effects of gate shaping and consequent process changes on AlGaN/GaN HEMT reliability (J. Moreke, M. Tapajna, M. Uren, Y. Umesh, M. Kuball, IPSS (Physica Status Solids) Vol A209, No. 12, pp. 2646-2652 (2012)).

Gate shapes are presented for quadrilateral, slanted and recess slanted structures to show the stability of slanted structures compared to vertical quadrilaterals. However, for the stability of the gate, the shape of the lower part of the gate also needs precise management.

In addition, a recessed-gate structure approach toward normally off high-voltage AlGaN/GaN HEMT for power electronic applications (S. Saito, Y. Takada, and I. Omura, IEEE Trans. on Electronic Devices, 2006) is fabricated with a recessed gate structure. It is written about the element that has been made.

Like the trench etching, the recess etching also has problems in reproducibility and uniformity, and furthermore, since the recessed area is large, the source-gate resistance and the gate-drain resistance increase, thereby reducing the performance of the device.

And High breakdown voltage AlGaN-GaN HEMTs achieved by multiple fiels plates(H. Xing, Y. Dora, A. Chini, S. Heikman, S. Keller, U.K. Mishra, IEEE Device Lwtters Vol. 25, No. 4, (2004 )), the electrical stress control is not sufficient, and the field plate must be manufactured three times in turn, which makes the process complicated and expensive.

In addition, a normally-on, depletion mode GaN FET device, which is a representative conventional technology, is the oldest and has a simple structure that can be easily manufactured, but has limitations in operating in a normally-on mode.

In order to drive normally-off (enhancement mode), it is manufactured and used as a cascode circuit combined with Si MOSFET. Therefore, if the volume increases and the performance is limited, the unit price of the product increases.

As described above, the prior art has been developed in various forms. An attempt was made to apply a horizontal, vertical, metal-semiconductor junction, and field plate using a heterojunction HEMT structured WBG semiconductor.

However, for GaN RF HEMT semiconductor devices that operate high-frequency and high-power signals with high efficiency, performance improvement by many technological developments is still required.

In particular, conventional mechanical stress and electrical stress problems are a significant cause of reducing yield and reliability in GaN semiconductor devices, and various techniques for controlling them have been attempted, but are not yet sufficient. am.

Therefore, in order to expand the application of GaN semiconductor devices, there is a need for a method of relieving mechanical stress and electrical stress in the manufacturing process as well as the structure of the device.

As in the case of the prior art described above, technology development has been conducted for various structures and material types for GaN RF semiconductor devices. However, conventional semiconductor devices have problems requiring various improvements.

For example, the driving voltage and driving current are low, thermally unstable, non-linearly operated, or generate a lot of heat and have low electrical efficiency.

In particular, as described above, the problem of low yield or low reliability of the manufacturing process due to mechanical stress and electrical stress requires significant technological progress.

Currently, because a driver circuit for GaN RF semiconductors must be specially designed and used due to these technical limitations, the problem of lack of compatibility and additional power consumption becomes an obstacle to the expansion of applications.

Therefore, it is very important to develop a high-performance new device that can solve the problems caused by mechanical and electrical stress related to the operation characteristics of these GaN RF semiconductor devices.

The technical problem to be solved by the present invention is to provide a GaN RF HEMT device capable of relieving mechanical stress and electrical stress and a manufacturing method thereof.

A GaN RF HEMT device according to an aspect of the present invention for solving the above problems is a stress reducing substrate 10 and an upper portion of the stress reducing substrate 10 partially exposed by the first insulating film 22 The stress is reduced through a window formed in the ohmic metal film 21 disposed at a predetermined distance apart from each other and the second insulating film 25 disposed on the first insulating film 22 and the ohmic metal film 21. A gate metal 26 in contact with the substrate 10, a source field plate 27 disposed to be spaced apart from the side surface of the gate metal, and in contact with the source field plate 27 and insulated from the gate metal 26 The connection metal line 28 extending to the upper side of the source-side ohmic metal film 21, and the source electrode and drain side formed in the region connecting the source-side ohmic metal film 21 and the connection metal line 28 It may include a drain electrode contacting the ohmic metal film and an air bridge 35 electrically connecting the plurality of source electrodes.

In addition, a GaN RF HEMT device manufacturing method according to another aspect of the present invention includes the steps of a) fabricating a stress reducing substrate 10, and b) partially forming an ohmic metal film 21 on top of the stress reducing substrate , defining a source and a drain; c) forming a gate metal 26 between the source and drain, and forming a source field plate 27 between the gate metal 26 and the drain; d ) extending a connection metal line 28 in contact with the source field plate 27 and insulated from the gate metal 26 toward the source side; e) the connection metal line to the source-side ohmic metal film 21 ( 28) and forming a drain electrode on the drain-side ohmic metal film 21 as well as forming a source electrode connected to the source electrode, and f) forming an air bridge connecting the source electrode.

The present invention reduces mechanical stress from wafer to unit chip level, minimizes electrical stress, and provides low on-resistance, high threshold voltage, and stable gate driving voltage.

Therefore, there is an effect of improving process yield and reliability by solving problems of mechanical stress and electrical stress, and there is an effect of securing operation stability without using a special driver circuit.

1 to 17 are cross-sectional views of a manufacturing process of a GaN RF HEMT device according to a preferred embodiment of the present invention.
18 is a plan configuration diagram according to an embodiment of the present invention.
Fig. 19 is a cross-sectional configuration diagram of Fig. 18;
20 to 25 are characteristic graphs comparing the present invention and the prior art.

Hereinafter, a GaN RF HEMT device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art, and the embodiments described below may be modified in many different forms, and the embodiments of the present invention The scope is not limited to the examples below. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the spirit of the invention to those skilled in the art.

Terms used in this specification are used to describe specific embodiments and are not intended to limit the present invention. As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. Also, when used herein, "comprise" and/or "comprising" specifies the presence of the recited shapes, numbers, steps, operations, elements, elements, and/or groups thereof. and does not exclude the presence or addition of one or more other shapes, numbers, operations, elements, elements and/or groups. As used herein, the term "and/or" includes any one and all combinations of one or more of the listed items.

Although terms such as first and second are used in this specification to describe various members, regions, and/or regions, it is obvious that these members, parts, regions, layers, and/or regions are not limited by these terms. . These terms do not imply any particular order, top or bottom, or superiority or inferiority, and are used only to distinguish one element, region or region from another element, region or region. Thus, a first element, region or region described in detail below may refer to a second element, region or region without departing from the teachings of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to drawings schematically illustrating embodiments of the present invention. In the drawings, variations of the depicted shape may be expected, depending, for example, on manufacturing techniques and/or tolerances. Therefore, the embodiments of the present invention should not be construed as being limited to the specific shape of the region shown in this specification, but should include, for example, a change in shape caused by manufacturing.

1 to 17 are cross-sectional views of a manufacturing process of a GaN RF HEMT device according to a preferred embodiment of the present invention.

First, as shown in FIG. 1, a seed layer 12, a buffer layer 13, a GaN active layer 14, an AlGaN layer 15, and an insulating film layer 16 are sequentially formed on the top of a semiconductor substrate 11. form

The semiconductor substrate 11 may use Si, sapphire, SiC, AlN, or the like.

In growing the epitaxial structure of AlGaN/GaN HEMT on the top of the semiconductor substrate 11, there is a difference in lattice constant and thermal expansion coefficient depending on the type of substrate 11 used because it is a heterojunction.

Therefore, due to the mechanical stress generated between the epitaxial layer and the semiconductor substrate 11, the entire semiconductor substrate 11 is bent, and in severe cases, cracks occur from the edge of the wafer.

In order to solve this problem, attempts are being made to minimize stress during the growth process of the seed layer 12 and the buffer layer 13. However, mechanical stress still occurs between the semiconductor substrate 11 and the AlGaN/GaN HEMT epitaxial layer at a level of 0.1 to 0.8 MPa.

Low-temperature GaN, Al _y Ga _1-y N, and GaN/Al _y Ga _1-y N superlattice layers can be grown and used as the buffer layer 13 and can be applied in various forms in which they are combined.

Subsequently, the active layer 14 where 2DEG is generated is grown. The active layer 14 is an undoped-Ga layer.

Subsequently, an Al _x Ga _1-x N layer (15, hereinafter abbreviated as an AlGan layer) is continuously grown on the active layer 14 .

Here, the Al _x Ga _1-x N epitaxial layer 15 controlled by x, the Al content, is also referred to as a spacer layer.

An insulating film layer 16 is deposited on top of the above-described AlGaN (15) layer to protect the surface.

The insulating film layer 16 is called SPF (surface passivation film), and an oxide film or a nitride film may be used.

Mainly, the insulating film layer 16 uses an insulator thin film such as SiON, and the thickness is adjusted to a level of 30 to 200 nm.

In the present invention, the Al content (x) in the AlGaN layer 15 for forming the 2DEG is controlled between 0.1 and 0.4 and the thickness is controlled between 10 and 40 nm to control the density and mobility of the 2DEG, which is the channel layer of the carrier. .

As a result, a 2DEG is formed on the GaN side between the GaN active layer 14/Al _x Ga _1-x N layer 15 to complete the HEMT epitaxial structure for device fabrication. In the present invention, the 2DEG layer has an electron density of >9x10 ¹² cm ⁻² and a mobility of >1900 cm ² /Vsec, and the HEMT epistructure is grown and used.

Next, in FIG. 2, a photoresist (PR) pattern is formed by phototransfer, and the formed insulating film layer 16, AlGaN layer 15, GaN active layer 14, and buffer layer 13 are formed using the PR pattern. A portion of the seed layer 12 is etched to expose an upper portion of the semiconductor substrate 11 .

That is, an edge trim is formed.

Using this method, defective areas concentrated on the edge are removed, and the stress is somewhat relieved to achieve stable edge treatment.

Therefore, in the process of device processing, even if there is an external impact, it is possible to prevent substrate destruction during the process of cracks, slips, and defects that are manifested and propagated.

Then, as shown in FIG. 3, in order to form scribe lanes of device chips to be manufactured, an insulating film layer 16, an AlGaN layer 15, and a GaN active layer 14 are formed through phototransfer and etching processes. ) is etched to expose the lower buffer layer 13.

In this process, the mechanical stress applied between the AlGaN/GaN HEMT epitaxial layer and the semiconductor substrate 11 is also partially relieved.

Then, as shown in FIG. 4, a trench structure is formed in the center of the scribe lane in which the insulating film layer 16, the AlGaN layer 15, and the GaN active layer 14 are etched, and the semiconductor substrate 11 below. After exposing a part of ), a trench insulating film 17 is formed.

The trench structure completely reaches the lower semiconductor substrate 11, and the grown AlGaN/GaN epitaxial layer is completely cut. Therefore, since the AlGaN/GaN epitaxial layer is short-circuited on the front wafer due to the size of the HEMT device to be manufactured, mechanical stress is locally localized at the unit chip level.

As the isolation is performed at the unit chip level, the mechanical stress applied between the epitaxial layer and the semiconductor substrate 11 is relaxed. When the stress is relaxed and the defects on the edge are removed, the warpage of the wafer is reduced and the mechanical shock that can be received during the process step is also strengthened.

Therefore, both the uniformity and yield of the device fabrication process are improved due to the phenomenon of stress relaxation and reduction of warpage.

As such, the structure shown in FIG. 4 forms a Stress Relieved HEMT substrate (hereinafter referred to as SRHS, 10).

5 shows a process of forming a metal junction for an ohmic junction on the top of the SRHS 10.

As the ohmic metal film 21 formed by phototransfer and etching or lift-off process, a single layer of metal such as Ti, Ni, Al, Pt, Pd, Mo, Ta or Ti/TiN, Ti It is composed of two or more composite layers such as /Ni/Ti/Al.

Then, as shown in FIG. 6, a first insulating film 22 is deposited on the entire upper surface of the structure of FIG. 5 to passivate the surface, followed by rapid heat treatment at a high temperature of 800 ^° C or higher for 1 to 5 min. It forms an ohmic contact with low resistance.

In order to minimize the heat generated when constant current flows, contact resistance must be reduced, and in order to ensure stable operation of the device from electrical and thermal shock, contact resistance is low and physically stable and strong against electro-migration. Metal bonding is important.

Then, as shown in FIG. 7, a PR pattern defining an ion implantation region is formed by photo-transfer for ion implantation in the AlGaN / GaN portion of the device,

For device isolation, ionized atoms such as Ar and P are ion-implanted with high energy of 60 to 200 keV under the condition of >1x10 ¹⁵ cm ⁻² ion amount to form the ion implantation region 23 .

Then, as shown in FIG. 8 , a pattern is formed by photo-transfer to the first gate junction pattern, and a contact window 24 of the first gate junction is formed by etching.

Then, as shown in FIG. 9, a second gate having a stepped structure capable of depositing a second insulating film 25, forming a pattern by photo-transfer to the second gate junction, and etching it to enlarge the field plate toward the drain. Forms a contact window.

The gate length can be reduced using the second gate pattern, and the shape of a unique gate field plate (GFP) can be determined.

Although the structure using the patterns of the first gate junction and the second gate junction has been described in this embodiment, it is also possible to fabricate a device using only the first gate pattern.

Then, as shown in FIG. 10, the gate metal 26 is formed by lift-off or etching.

A pattern of the gate metal 26 is formed by photo-transfer, and a gate metal film is formed using a PR mask. At this time, along with the gate metal, the source field plate 27 is formed in a T-shape in the drain direction next to the gate.

As the gate metal 26, a multi-layered dissimilar metal such as Ni/Pt/Ti/Al, Ni.Pt/Ni/Pt/Au, or Ni/Pt/Ti/WTi is deposited and used. At this time, in order to lower the resistance of the gate, the thickness of the Al, Au, and WTi layers, which are the main conductive layers, is adjusted to be 1 to 2 μm or more.

Then, as shown in FIG. 11, a connection metal line 28 for electrically connecting the source metal and the source field plate is formed. The connection metal line 28 may be used by combining metals such as Al, Ni, Ti, and Au in a single layer or multi-layer structure.

Then, as shown in FIG. 12, a third insulating film 29 is deposited, a contact window with the ohmic junction on the source and drain sides is opened, a metal thin film for metal wiring of the source and drain is deposited, and an optical photograph is taken. The first metal layer 30 is formed by transfer and etching or lift-off.

The first metal layer 30 is formed by depositing a metal thin film having a thickness of 2 to 6 um to form a pattern and etching it.

The first metal layer 30 uses a combination of various metal materials such as Ai, Ti/Al, Ni/Au, and Ti/Al/Ni/Au in a single layer or multiple layers.

Then, as shown in FIG. 13, a fourth insulating film 31 is deposited on the entire upper surface of the structure.

At this time, considering the problem of electrical interference between the semiconductor substrate side and the metal line, the thickness of the fourth insulating film 31 is adjusted to about 1 to 3 μm.

Then, as shown in FIG. 14, a photoresist pattern 32 is formed using photophototransfer. The photoresist pattern 32 is a structure covering the top of two devices and the top of the first metal layer 30 positioned between the two devices.

A portion of the fourth insulating layer 31 on both sides of the photoresist pattern 32 is removed to expose an upper portion of the first metal layer 30 positioned on both sides of the device.

Then, as shown in FIG. 15, Ni layer 33 is formed by depositing Ni.

Then, a photoresist pattern 34 is formed to limit a space where an air bridge can be formed.

The Ni layer 33 is for performing electroplating.

The Ni layer 33 is deposited with a thickness of 30 nm or more and adjusted to have a good step coverage.

Then, as shown in FIG. 16, an air bridge 35 is formed using electroplating. The air bridge 35 is usually formed with a thickness of 2 to 4 μm by electroplating Au to minimize resistance.

Then, as shown in FIG. 17, the photoresist patterns 32 and 34 and the exposed Ni layer 33 are removed.

18 is a plan configuration diagram of the present invention.

The source and drain portions are formed by alternating three and two, respectively, and the gate is composed of four. Actual products are manufactured in a series or parallel structure of a number of unit elements according to the level of the desired current.

Here, the connecting metal line 28 connecting the source and the source field plate 27 is disposed on the edge side of the source pad.

FIG. 19 is an overall cross-sectional configuration diagram of an element in which the cross-sectional structure shown in FIG. 17 is disposed on both sides, and is the same element as the plan view of FIG. 18 .

There is a gate formed of a plurality of source-drain and T-shaped gate field plates, and a triangular source field plate is disposed next to it. The source pads are all connected by an air bridge 35 to minimize the resistance of the source electrode.

20 shows the relief of mechanical stress in the GaN HEMT epitaxial layer grown on the Si (111) substrate in the steps of edge trim, scribe lane, and trench separation. It is explained that it is done according to

The present invention localizes the mechanical stress from the substrate level to the unit area of the unit chip, and it can be seen that the stress is reduced by controlling the width of the scribe lane and the trench to 50um/10um, 100um/30um, and 200um/50um. .

Since the effective area decreases when the scribe lane increases, an appropriate level of optimization is required.

21 is a graph of I-V characteristics measured in a pulse mode after off-state electrical stress is applied.

In the off state where the gate voltage (Vgs) is maintained below the takeover voltage (V _th ), a voltage exceeding a certain level (V _ds-q ) is applied to the drain to apply electrical stress for 4 ms, and then several gate voltages (V Drain current (I ds ) is measured at drain-source voltage (V _ds-q ) under the condition of a quiescent state for ₃ ms while _gs-q ) is applied.

In the off-state state, an electric field is focused at the bottom of the gate by the voltage applied to the drain, and hot electrons are generated. Hot electrons generated by electrical stress are trapped by the upper AlGaN layer 15 and the insulating film layer 16, and trapping also occurs in the GaN active layer 14.

Due to these traps, the electron density is reduced in the surrounding 2DEG layer, and the current density is also severely reduced in the I-V characteristic of the pulse mode.

22 shows I-V characteristics for DC and pulse operation in the initial device to which no electrical stress is applied. Since electrons are not trapped by electrical stress in the insulating film between the gate and drain of the device and the GaN epitaxial layer, the characteristics of DC and pulse operation remain almost the same.

23 is a result of measuring I-V characteristics in a pulse mode after applying an off-state electrical stress of a conventional device.

The results measured in DC and pulse modes are significantly different. In particular, as a result measured in the pulse mode, the on-resistance (R _on ) increased to a serious level, and the driving ability of the grain current was severely reduced.

This is because electrons are trapped in the AlGaN, insulating film, and GaN layer above and below the 2DEG existing between the gate and the drain in the conventional device, which is weak against electrical stress, and the 2DEG concentration decreases, resulting in a sharp decrease in the current flow through the channel.

24 is an I-V characteristic of the present invention.

After applying the off-state electrical stress, the I-V characteristics of the pulse mode measured are almost equivalent to those measured in the DC mode. This is because, in the case of the present invention, the structure of the T-shape gate field plate and the source field plate is designed to relieve electrical stress.

In addition, by minimizing the low-resistance ohmic junction and the capacitance ( _CSG ) component between the source and the gate, the efficiency of the device can be maximized with a small on-resistance (R _on ) in forward operation by increasing the current driving force.

As such, the current driving capability of the device is 100 mA/mm or more, and the on-resistance (R _on ) is controlled to 5 mΩcm ² or less.

25 is a graph comparing RF characteristics between the present invention and a conventional device.

As shown therein, by comparing the RF characteristics of the present invention with the prior art having a difference in the distribution of electrical stress, the current gain H ₂₁ and the power gain U of Mason's gain are explained. It is a case.

Define f _t and f _max in the limit where current gain and power gain become units.

Compared to the prior art, in the case of the present invention, f _t and f _max are increased to show the effect of improving performance. The effective gate length and gate-drain interval can be reduced, and the gate-source capacitance (C _gs ) is small, so the high-frequency operation performance of the device is improved.

As described above, in the present invention, the high-mobility carrier of the 2DEG of the HEMT structure provides a cause for the operation of the device with high conduction at high frequency and high voltage. This increases efficiency and reduces the size of passive elements in equivalent circuits, thereby minimizing the volume of a high-power RF system. The performance and advantages of the device of the present invention can be said to be essential for high frequency-high power wireless circuits operating at high speed.

It is obvious to those skilled in the art that the present invention is not limited to the above embodiments and can be variously modified or modified and implemented within the scope of the technical gist of the present invention. will be.

11: semiconductor substrate 12: seed layer
13: buffer layer 14: GaN active layer
15: AlGaN layer 16: insulating film layer
17: trench insulation film 10: stress reduction substrate
21: ohmic metal film 22: first insulating film
23: ion implantation area 24: contact window
25: second insulating film 26: gate metal
27: source field plate 28: connecting metal wire
29: third insulating film 30: first metal layer
31: fourth insulating film 32, 34: photoresist pattern
33: Ni layer 35: Air bridge

Claims (5)

stress reducing substrate 10;
an ohmic metal film 21 spaced apart from each other by a predetermined interval on a part of the upper part of the stress reducing substrate 10, a part of which is exposed by the first insulating film 22;
a gate metal 26 in contact with the stress reducing substrate 10 through a window formed in the second insulating film 25 disposed on the first insulating film 22 and the ohmic metal film 21;
a source field plate (27) spaced apart from the side surface of the gate metal;
a connection metal line 28 in contact with the source field plate 27 and extending to an upper side of the source-side ohmic metal film 21 while being insulated from the gate metal 26;
a source electrode formed in a region connecting the source-side ohmic metal film 21 and the connection metal line 28 and a drain electrode contacting the drain-side ohmic metal film; and
A GaN RF HEMT device including an air bridge 35 electrically connecting a plurality of the source electrodes. According to claim 1,
The stress reducing substrate 10,
semiconductor substrate 11;
a seed layer 12 and a buffer layer 13 sequentially stacked on a portion of the upper portion of the semiconductor substrate 11 and spaced apart from each other at a predetermined interval;
a trench insulating layer 17 positioned between the seed layer 12 and the buffer layer 13; and
A GaN RF HEMT device including a GaN active layer 14, an AlGaN layer 15, and an insulating film layer 16 sequentially stacked on the upper center of the buffer layer 13. According to claim 1,
The source field plate,
GaN RF HEMT device, characterized in that 'T' type. a) fabricating a stress reducing substrate 10;
b) partially forming an ohmic metal film 21 on top of the stress reducing substrate to define a source and a drain;
c) forming a gate metal 26 between the source and the drain, and forming a 'T' shaped source field plate 27 between the gate metal 26 and the drain;
d) extending a connection metal line 28 that contacts the source field plate 27 and is insulated from the gate metal 26 toward the source side;
e) forming a source electrode connected to the connection metal line 28 on the source-side ohmic metal film 21 and forming a drain electrode on the drain-side ohmic metal film 21; and
f) a GaN RF HEMT device manufacturing method comprising the step of forming an air bridge connecting the source electrode. According to claim 4,
In step a),
a-1) sequentially forming a seed layer 12, a buffer layer 13, a GaN active layer 14, an AlGaN layer 15, and an insulating film layer 16 on the semiconductor substrate 11;
a-2) The stacked structure from the insulating film layer 16 to the seed layer 12 is patterned, and the seed layer 12, buffer layer 13, and GaN active layer located on a part of the semiconductor substrate 11 (14), forming a laminated structure of an AlGaN layer 15 and an insulating film layer 16;
a-3) forming a trench dividing an element formation region in a stacked structure from the insulating film layer 16 to the GaN active layer 14; and
a-4) a GaN RF HEMT device manufacturing method comprising the step of forming a trench insulation film 17 extending from the central portion of the buffer layer 13 exposed by the formation of the trench to the lower semiconductor substrate 11.

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