WO2018092025A1

WO2018092025A1 - Lateral heterojunctions between a first layer and a second layer of transition metal dichalcogenide

Info

Publication number: WO2018092025A1
Application number: PCT/IB2017/057118
Authority: WO
Inventors: Lain-Jong Li; Hao-Ling Tang; Ming-Hui Chiu
Original assignee: King Abdullah University of Science and Technology KAUST
Current assignee: King Abdullah University of Science and Technology KAUST
Priority date: 2016-11-16
Filing date: 2017-11-15
Publication date: 2018-05-24
Anticipated expiration: 2019-05-16
Also published as: US10784353B2; CN110199395A; US20200058743A1

Abstract

A device comprising: at least one first layer, such as a graphene layer, at least one second layer of transition metal dichalcogenide, wherein the at least one first layer and the at least one second layer of transition metal dichalcogenide form at least one heterojunction. The first and second layers are laterally displaced but may overlap over a length of 0 nm to 500 nm. A low-resistance contact is formed. The device can be a transistor including a field effect transistor. The layers can be formed by chemical vapor deposition. The graphene can be heavily p-doped. Transistor performance data are described.

Description

LATERAL HETEROJUNCTIONS BETWEEN A FIRST LAYER AND A SECOND LAYER OF TRANSITION METAL DICHALCOGENIDE

BACKGROUND

Two dimensional nanostructures are becoming increasingly important for next generation semiconductor technology. For example, transition metal dichalcogenides (TMDs) such as M0S2 and WSe2 have been recognized as two-dimensional monolayer semiconductors which are promising for advanced electronics and opto-electronics (including meeting the targets of ITRS roadmaps for smaller semiconductor sizes). One major challenge for developing TMD-based electronic devices is that TMDs such as WSe2tend to form a substantial Schottky barrier (SB) with commonly used contact metals. One approach is to adopt extreme high or low work function metal such as Palladium (Pd) or Indium (In) [W. Liu et al., Nano Lett., 13, p. 1983, 2013]. Another approach is applying doping processes such as chemical (NO2) doping [H. Fang et al., Nano Lett., 12, p. 3788, 2012] and ionic-liquid gating [H.J. Chuang et al., Nano Lett., 14, p. 3594, 2014; "Chuang reference"]. These

approaches are not achieving enough low resistance and are not compatible with modern solid state electronics due to poor doping stability, low thermal stability of indium, and slow switching speed, respectively.

Graphene and boron nitride lateral heterostructures are known. See, for example, Levendorf et al., "Graphene and Boron Nitride Lateral Heterostructures for Atomically Thin Circuity," Nature, 488, 627-632, August 30, 2012; and US Patent No. 8,906,787.

Use of TMDs in a transistor is described in US Patent Publication 2014/0197459. Articles which refer to vertical TMD-graphene heterostructures include: Britnell et al., Science, 2012, 335 (6071), 947; Yu et al., Nat Mater. 2013, 12 (3), 246; and Georgiou et al., Nat.

Nanotechnol., 2013, 8 (2), 100. See also, Loan et al., Advanced

Materials, 26, 28, 2014, 4838 (graphene/MoS2 heterostructural stacking film). CN 103928340 and CN 102270692 also describe graphene structures.

Despite these advances, a need exists for better two-dimensional devices based on TMDs with improved Schottky barrier properties enabling more progress in the miniaturization of electronic and optoelectronic devices.

SUMMARY

Aspects and embodiments described herein include devices and articles, methods of making such devices and articles, and methods of using such devices and articles.

A first aspect provides for a device comprising: at least one first layer, wherein the first layer has a thickness of 20 nm or less; at least one second layer, different from the first, which is a transition metal dichalcogenide layer, wherein the second layer has a thickness of 20 nm or less; wherein the at least one first layer and the at least one second layer form at least one lateral heterojunction.

In one embodiment, the lateral heterojunction is a lateral penetrating heterojunction.

In one embodiment, the lateral heterojunction is a lateral penetrating heterojunction characterized by a penetration length which is from 1 nm to 500 nm.

In one embodiment, the lateral heterojunction is characterized by an overlapped length which is from 0 nm to 500 nm. In one embodiment, the lateral heterojunction is characterized by an overlapped length which is from 1 nm to 500 nm.

In one embodiment, the first layer is a graphene layer, a boron nitride layer, a phosphorene layer, or a transition metal dichalcogenide layer which is different from the second layer.

In one embodiment, the first layer is an un-doped graphene layer, a p-doped graphene layer, or an n-doped graphene layer.

In one embodiment, the first layer is a p-doped graphene layer or an n-doped graphene layer, and the second layer is a p-type transition metal dichalcogenide or an n-type transition metal dichalcogenide.

In one embodiment, the device comprises at least two domains for the first layer, and each of the two domains are in contact with the second layer of transition metal dichalcogenide to form at least two lateral heterojunctions.

In one embodiment, the device comprises at least two domains for the first layer, and each of the two domains are in contact with the second layer of transition metal dichalcogenide to form at least two lateral heterojunctions. The lateral heterojunctions can be lateral interpenetrating junctions.

In one embodiment, the device comprises at least two domains for the first layer, wherein one of the two domains is in contact with the second layer which is an n-type second layer, and the other of the two domains is in contact with the second layer which is a p-type second layer.

In one embodiment, the device is a transistor, a photo-sensor, a solar cell, or a light-emitting diode.

Another aspect is a method of making the device(s) as described and/or claimed herein comprising forming on a substrate the at least one first layer, forming the at least one second layer, different from the first, with seed growth from the first layer, wherein the at least one first layer and the at least one second layer form at least one lateral

heterojunction.

In one embodiment, the forming step for the second layer comprises chemical vapor deposition or physical vapor deposition, and wherein the forming step for the first layer comprises patterning the first layer.

In one embodiment, the method of patterning the first layer comprises dry etching or wet etching.

Another aspect provides for a structure or a device comprising: at least one first layer, wherein the first layer has a thickness of 20 nm or less, at least one second layer, different from the first, which is a transition metal dichalcogenide (TMD) layer, wherein the second layer has a thickness of 20 nm or less, wherein the at least one first layer and the at least one second layer form at least one lateral penetrating heterojunction.

More particularly, another aspect provides for a structure or device comprising: at least one graphene layer, and at least one layer of transition metal dichalcogenide, wherein the at least one graphene layer and the at least one layer of transition metal dichalcogenide form at least one lateral penetrating heterojunction.

In one embodiment, the first layer is a graphene layer, a boron nitride layer, a phosphorene layer, or a transition metal dichalcogenide layer which is different from the second layer. In one embodiment, the first layer is a graphene layer, whereas in another embodiment, the first layer is a phosphorene layer, whereas in another embodiment, the first layer is a transition metal dichalcogenide layer which is different from the second layer. In one embodiment, the first Iayer is an un-doped graphene layer, a p-doped graphene Iayer, or an n-doped graphene Iayer. In one embodiment, the first Iayer is a p-doped graphene Iayer or an n-doped graphene layer, and the second Iayer is a p-type transition metal dichalcogenide or an n-type transition metal dichalcogenide. In one embodiment, the first Iayer is a p-doped graphene Iayer. In one embodiment, the first Iayer is an n-doped graphene Iayer. In one embodiment, the second Iayer is a p-type transition metal

dichalcogenide. In one embodiment, the second Iayer is an n-type transition metal dichalcogenide.

In one embodiment, the lateral penetrating heterojunction is characterized by a penetration length which is from 1 nm to 500 nm.

In one embodiment, the device comprises at least two domains for the first layer, and each of the two domains are in contact with the second Iayer of transition metal dichalcogenide to form at least two lateral interpenetrating heterojunctions.

In one embodiment, the device comprises at least two domains for the first Iayer, wherein one of the two domains is in contact with the second Iayer which is an n-type second Iayer, and the other of the two domains is in contact with the second Iayer which is a p-type second layer.

In one embodiment, the device is, for example, a transistor, a photo-sensor, a solar cell, or a light-emitting diode.

Methods of making this device are also provided. For example, one embodiment provides for a method of making the device as described and/or claimed herein comprising forming on a substrate the at least one first Iayer, forming the at least one second Iayer, different from the first, with seed growth from the first Iayer, wherein the at least one first layer and the at least one second layer form at least one lateral penetrating heterojunction.

In one embodiment, the forming step for the second layer comprises chemical vapor deposition or physical vapor deposition, and wherein the forming step for the first layer comprises patterning the first layer. In one embodiment, the forming step for the second layer comprises chemical vapor deposition or physical vapor deposition. In another embodiment, the forming step for the first layer comprises patterning the first layer.

In one embodiment, the method of patterning the first layer comprises dry etching or wet etching. In one embodiment, the

patterning comprises dry etching; in another embodiment, it comprises wet etching.

In a preferred embodiment, a low-resistance contact can be achieved with the lateral heterojunction of monolayer WSe2 as the second layer and heavily p-doped graphene as the first layer. In a preferred embodiment, heavily p-doped graphene laterally connected to WSe2 serves as a good contact material. Base on this preferred embodiment, a WSe2 p-FET has been fabricated successfully on a patterned graphene sheet. In preferred embodiments, a p-FET based on such low-resistance contact structures can be used for high- performance electronics and opto-electronics based on these ultrathin monolayer semiconductors.

The inventive structures and devices can pave the way in at least some embodiments for sub 5 nm node integrated circuit technology by using an atomically thin channel. Good transfer and output

characteristics can be achieved for at least some embodiments. Also, good thermal stability can be achieved for at least some embodiments. Preferred methods are IC compatible and can be integrated with, for example, graphene roll to roll methods.

BRIEF DESCRIPTION OF THE DRAWINGS

Figures 1 (a)-(b). Figure 1(a) provides a schematic example for the growth of (a) graphene, and (b) WSe2 in hot wall furnaces. Graphene was synthesized on copper foil using ChU carried by Ar/hfe at 800- 1 ,100°C. For the WSe2 monolayer, the WOsand Se powders were used as the precursors, and the growth was performed at 600-1 ,000°C.

Figures 2(a)-(h). Figure 2(a) shows schematic illustration for the process flow to form graphene-WSe2 lateral heterostructures. (b), (c) Top view OM images presenting patterned graphene before and after WSe2 C VD growth respectively (graphene labelled as G and WSe2 labelled as W). (d)-(e) Raman spatial mappings of (d) graphene G band and (e) WSe2 E' band respectively, (f) Raman spectra of graphene before and after WSe2 CVD growth, (g)-(h) The point PL and Raman spectra of WSe2 respectively.

Figures 3(a)-(d). The cross-sectional high-resolution TEM images of (a) the MLG region, (b) The overlapped MLG-WSe2 heteroju notion region, (c) The WSe2 few layers near the junction transit to a monolayer once the location is away from the junction, (d) The monolayer WSe2 channel region. The scale bars are 5nm.

Figure 4. Additional cross-sectional HR-TEM images presenting MLG- WSe2 heterojunction. Figure 5. Schematic illustration of the layer of transition metal

chalcogenide penetrates into the interlayer space of the first layer (MLG).

Figures 6(a)-(e). (a) Optical image of as-patterned MLG. (b) Raman spectra taken along a line from sapphire to MLG as marked in (a), (c) Optical image of the MLG-WSe2 heterojunction. Corresponding Raman spatial mappings for the integrated intensity of (d) graphene G band and (e) degenerate E' and ΑΊ modes of WSe2. (c)-(e) show that the WSe2 grows from graphene edge and forms a seamless lateral heterojunction.

Figure 7 shows the fabrication processes for a top-gated transistor based on the graphene-WSez lateral heterostructure.

Figures 8(a)-(e) show the electrical characteristics of the graphene- WSe2 lateral heterostructure. (a) Transistor geometry of single layer graphene (SLG), multilayer graphene (MLG) and p-doped small grain multilayer graphene (sMLG) source/drain defined as scheme A, B and C respectively, (b) The transfer curves of the transistors comparing SLG (Scheme A), MLG (Scheme B) and p-doped sMLG (Scheme C). (c) Raman spectra for the sMLG: i, as-patterned; ii, after WSe2 growth; iii, after 300 °C annealing of doped sMLG-WSe2 in air for 1hr. (d) The schematic doping effect takes place at defect sites or the grain

boundaries (e) The schematic band diagram of the p-doped sMLG-WSe2 junction.

Figures 9(a)-(b). Additional transistor performance of p-sMLG-WSe2 FET with (a) output curve and (b) transfer curve. Figures 10(a)-(c). (a) Schematic illustration of the device structure, (b) The transfer curves and (c) the ON-current cumulative probability plot (at VG= -3V) for various devices.

Figure 11. The transfer curve of a WSe2 p-FET with p-doped SMLG contacted by Ti electrode metal. Since the p-doped MLG is responsible for the preference of injection carrier type, unipolar p-type FET is always obtained even including a low work function metal Ti.

Figures 12(a)-(d) show some non-limiting examples of semiconductor devices.

DETAILED DESCRIPTION

INTRODUCTION

Priority US provisional application serial number 62/422,984 filed November 16, 2016 is hereby incorporated by reference in its entirety for all purposes including the working examples, Figures 1-17, and claims.

All references cited herein are incorporated herein by reference.

Additional description for the elements of the aspects and

embodiments summarized above are provided below.

FIRST LAYER INCLUDING A GRAPHENE LAYER

The first layer can be a conducting, semiconducting, or insulating layer. The first layer can be, for example, a graphene layer, a boron nitride layer, a phosphorene layer, or a transition metal dichalcogenide (TMD) layer which is different from the second layer. Phosphorene is described in, for example, Liu et al., "Phosphorene: A New 2D Material with High Carrier Mobility," ACS Nano, 8, 4033-4041 (2014). If the first layer is a TMD layer, description for this first TMD layer is provided below for the second layer which is a TMD layer. In particular, graphene layers are preferred.

The first layer can be a monolayer or a few layered material.

There can be, for example, 1 layer to 20 layers, or 1 layer to 10 layers, or 1 layer to 5 layers, or one layer, or two layers, or three layers, in the total first layer. The first layer thickness can be, for example, 20 nm or less, or about 10 nm or less, or about 0.3 nm to about 10 nm, or about 0.5 nm to about 10 nm, or about 1.0 nm to about 10 nm, or about 1.5 nm to about 10 nm or about 2 nm to about 6 nm, or about 4 nm. The minimum thickness for the layer can be, for example, 0.1 nm, or 0.2 nm, or 0.3 nm, or 0.4 nm, or 0.5 nm, or 0.6 nm, or 0.7 nm, or 0.8 nm, or 0.9 nm, or 1.0 nm.

The first layer can be patterned. Patterning can be carried out by, for example, beam lithography or photolithography. The first layer can be doped. The patterning can provide different domains or different layers separated from each other.

Graphene layers are known in the art, and the total thickness of the graphene layer can be varied. For example, they can be only one atomic layer thick or they can have n layers of graphene as in so-called few layered graphene. The number of graphene layers can be, for example, 1 layer to 20 layers, or 1 layer to 10 layers, or 1 layer to 5 layers. In one embodiment, the graphene layer is few layer graphene. Multi-layered graphene can be also formed. In another embodiment, the graphene layer has a thickness of about 0.3 nm to about 10 nm. The graphene layer thickness can be, for example, about 2 nm to about 6 nm, or about 4 nm. In another embodiment, the graphene layer is large area graphene. Each graphene layer can provide about 0.4 nm per layer for the total thickness.

In one embodiment, the graphene layer is patterned. Patterning can provide a sharp edge. The sharp edge, for example, can provide for further growth of the transition metal chalcogenide layer. Patterning provides a well-defined graphene domain on the substrate surface.

The graphene layer can be un-doped or it can be doped, including p-doped or n-doped. In one embodiment, the graphene layer is p- doped. In one embodiment, the graphene layer is heavily p-doped. In another embodiment, the graphene layer is lightly p-doped. In other embodiments, the graphene layer is n-doped, whether lightly n-doped or heavily n-doped. The graphene can be surface doped via surface adsorption. Also, graphene can be substitutional^ doped where a carbon atom is replaced.

The graphene layer can be prepared by methods known in the art including chemical vapor deposition, electrochemical exfoliation, or mechanical exfoliation. Graphene layers also can be transferred from one substrate to another substrate.

The graphene layer can be a large area graphene including a wafer scale graphene layer. Roll-to-roll CVD growth can be carried out with transfer techniques to form graphene films which can have a length dimension of at least 1 inch, or at least ten inches, or at least 30 inches. See, e.g., Bae et al., Nature Nanotechnology, 2010, 5, 574.

Graphene layers are described in, for example, US Pat. Pub.

2015/0102807, including their use with metal chalcogenides.

SECOND LAYER, TRANSITION METAL DICHALCOGENIDE (TMD) LAYER Transition metal dichalcogenide layers are known in the art (and can be called MX2, wherein M is the transition metal and X is the chalcogen). They can be direct band gap semiconductors with

bandgaps of about 0.7 eV to about 2.2 eV, or about 1.2 eV to about 1.8 eV. They can show n or p behavior. See, for example, Chhowalla et al., Nature Chemistry, 5, 263 (2013).

In one embodiment, the transition metal dichalcogenide layer is a sulfide, selenide, or telluride layer.

In one embodiment, the transition metal of the transition metal dichalcogenide is molybdenum, tungsten, titanium, zirconium, hafnium, vanadium, niobium, or tantalum.

In one embodiment, the transition metal dichalcogenide is molybdenum sulfide or tungsten selenide.

Specific examples include M0S2, WSe2, MoSe2, SnSe, SnSe2, MoTe₂, WS₂, WTe₂₎ TiS₂, TiSe₂, TiTe₂, ZrS₂, ZrSe₂, ZrTe₂, HfS₂, HfSe₂, HfTe₂, VS₂, VSe₂, VTe₂, NbS₂, NbSe2, NbTe₂₎ TaS₂, TaSe₂ or TaTe₂.

As known in the art, the thickness of the transition metal

dichalcogenide layer can be varied. In one embodiment, the layer has a thickness of 20 nm or less, or 10 nm or less, or about 0.5 nm to about 10 nm. The range in thickness can be, for example, 1 nm to 20 nm, or 1 nm to 10 nm, or 1 nm to 5 nm. The thickness can be, for example, about 0.5 nm to about 5 nm. In one embodiment, the transition metal

dichalcogenide layer is a monolayer. The minimum thickness for the layer can be, for example, 0.1 nm, or 0.2 nm, or 0.3 nm, or 0.4 nm, or 0.5 nm, or 0.6 nm, or 0.7 nm, or 0.8 nm, or 0.9 nm, or 1.0 nm.

The second layer can be a monolayer or comprise multiple layers such as, for example, at least one layer, two layers, or at least two layers, or 1 layer to 15 layers, or 1 layer to 10 layers, or 1 layer to 5 layers. Transition metal dichalcogenide layers can be prepared by vapor deposition whether by chemical vapor deposition or physical vapor deposition. Examples of chalcogenide (X) precursors include X, H2X, and (alkyl)₂X such as (CH₃)₂X, (C₂H₅)2X, and C₃H₈X. Growth

temperature can be, for example, 300°C to 1 ,000°C, or 500°C to

1 ,000°C. Growth pressure can be, for example, 10 mtorr to 760 torr.

The second layer can be doped.

LATERAL HETEROJUNCTION(S) AND HETEROSTRUCTURES

The device can provide for one, two, three, or more lateral heterojunctions based on the first and second layers. Lateral

heterojunctions are known in the art and can be distinguished from vertical heterojunctions. The examples for the vertical heterojunctions include: Zhang et al., Nature.com, Scientific Reports, 4:3826, DOI:

10.1038/srep03826. described graphene layer stacked on M0S2 layer. Nanosheets of graphene have been combined with nanosheets of M0S2 as described in Zhou et al., Chem. Commun., 2013, 49, 1838 for lithium storage. Graphene-like layered metal dichalcogenide/graphene composites are described in Materials Today, 17, 4, 184, May 2014 in the context of applications in energy storage and conversion.

The at least one first layer (e.g., graphene layer) and the at least one layer of transition metal dichalcogenide can form at least one lateral heterojunction and, more particularly, a lateral penetrating

heterojunction.

In one embodiment, the device comprises at least two first layers (e.g., two graphene layers), and each of the two first layers (e.g., graphene layers) are in contact with the layer of transition metal dichalcogenide to form at least two lateral heterojunctions, and in particular, at least two lateral heterojunctions, including at least two lateral penetrating heterojunctions.

In one embodiment, the first layer (e.g., graphene layer) stitched with the layer of transition metal chalcogenide laterally through edge contacting. The first layer is not overlapped with the layer of transition metal chalcogenide.

In one embodiment, the first layer is stacked with the layer of transition metal chalcogenide forming a multilayer stacking contact with a range of overlapped region. The layer of transition metal chalcogenide can be beneath or above the first layer at the overlapped region (Figure 3(b)). The overlapped length can be, for example, 0 nm to 500 nm, or 1 nm to 500 nm, or 1 nm to 200 nm, or 1 nm to 100 nm, or 1 nm to 50 nm, or 1 nm to 20 nm, or one 1 nm to 10 nm, or 2 nm to 10 nm, or 1 nm to 5 nm or 2 nm to 5 nm, or 11 nm to 20 nm. Overlapped length can be determined by TEM analysis.

In one embodiment, the first layer is stacked with the layer of transition metal chalcogenide forming a multilayer stacking contact with a range of overlapped region. The first layer has an interlayer space and the layer of transition metal chalcogenide penetrates into the interlayer space, which is schematic illustrated in Figure 5 for one embodiment (graphene on the left; WSe2 on the right). This forms a lateral

penetrating or interpenetrating heterojunction. The penetration length can be, for example, 1 nm to 500 nm, or 1 nm to 200 nm, or 1 nm to 100 nm, or 1 nm to 50 nm, or 1 nm to 20 nm, or one 1 nm to 10 nm, or 2 nm to 10 nm, or 1 nm to 5 nm or 2 nm to 5 nm, or 11 nm to 20 nm.

Penetration length also can be determined by TEM analysis.

In one embodiment, the lateral heterojunction is a seamless heterojunction. In one embodiment, the heterojunction is a monolayer heterojunction.

In one embodiment, the heterojunction is a few-layered (multi- layered) heterojunction.

In one embodiment, the heterojunction shows ohmic contact behavior (see, for example, Figure 9). In one embodiment, the second layer of transition metal chalcogenide and the first layer (e.g., graphene layer) are formed by chemical vapor deposition. Li et al., Science, 2015, 349, 524 TMD lateral heterostructures prepared by CVD.

METHOD OF MAKING AND CHARACTERIZING

Methods known in the art and described in the working examples can be used to prepare the various components of the layers, the junctions, the transistors, and the devices described herein. For example, microfabrication and/or patterning can be carried out through photolithography and/or etching processes (e.g., reactive ion etching or O2 plasma).

Also, for example, chemical vapor deposition and transfer methods can be used to form the first layer (e.g., graphene layer) and metal dichalcogenide layer. In a transfer method, a film or layer can be transferred from one substrate to another. For example, a film or layer prepared by CVD can be transferred. Substrates are known in the art and include, for example, sapphire, glass, polymer, kapton, polyimide, quartz, Si02/Si, silicon, GaN, GaAs, copper, and the like. PMMA- assisted transfer methods can be carried out.

Also, methods known in the art and described in the working examples can be used to characterize the various components of the layers, the junctions, the transistors, and the devices described herein. To form heterojunctions of two materials, the first material on the substrate can be transferred or grown by CVD. The second material can be then grown by CVD. For example, graphene can be transferred onto a substrate as a first layer, and then a TMD layer can be grown.

Alternatively, both materials can be grown by CVD.

Lateral heterojunction can be formed by controlling the CVD conditions of the second material to avoid vertical growth on the top of the first material.

CVD temperature can be, for example, 300°C to 1 ,000°C, or 600°C to 1 ,000°C. Pressure can range from 10 mtorr to 760 torr. The transition metal precursor is not limited but can be, for example, MO2, MO3, M(CO)₆, MC , MC , or MCI5 (where M is the metal).

DEVICES AND APPLICATIONS

The lateral heterojunction structures described herein having low contact resistance can be used in various structures and devices including in, for example, ultra-thin semiconductor electronic or optoelectronic devices. Devices include, for example, p-n junction, bipolar junction transistor, MOSFET, LED, solar cell, laser, light detector, photodetector devices, and can be integrated to touch screen,

transparent displays, and other similar integrated functions and devices. Flexible electronics, low power electronics, quantum computing, and valleytronics are other areas of application and devices. In particular, transistors and field effect transistors can be made. Various gate embodiments can be used including the top-gate arrangement.

Insulators and conductors can be used as known in the transistor arts. High-κ dielectric insulators (e.g., aluminum oxide, hafnium oxide) can be used. Particular focus is placed on transistors having active components of very small size allowing for further miniaturization of electronic and opto-electronic devices.

For a channel layer, the length and width can be adapted for the need, whether nanoscale or microscale, depending on the lithography limitation, as known in the art. For example, about 2 nm by e-beam lithography to about 50 microns by photolithography.

Figures 12(a)-(d) show four additional examples of devices based on metal (701), dielectric material (702), graphene (703), p-type T D material (704), n-type TMD material (706), and substrate (705).

The first layer can be in ohmic contact with any metal ranging from large work function metals to low work function metals.

DEVICE CHARACTERISTICS

Transistors, including field effect transistors, can be prepared and tested as known in the art. Transfer and output characteristics can be measured. Good properties and combination of properties can be achieved.

In one embodiment, for example, the device is a field effect transistor which has an /loff ratio of about 10⁴ or more, or 10⁵ or more, or 10⁶ or more, or 10⁷ or more, or 10⁸ or more.

In one embodiment, the device is a field effect transistor which has a carrier mobility of about 10 cm²/V-s or more at about 25°C, about 20 cm² V-s or more at about 25°C, or about 30 cm²/V-s or more at about 25°C.

In one embodiment, the device is a field effect transistor which has an loff value of 10 pA or less.

In one embodiment, the device is a field effect transistor which has a subthreshhold swing (SS) of about 130 mV/dec or less. In one embodiment, the device is a field effect transistor which has an on state current of about 2.13 μΑ/μιη or more, or 3 μΑ/μιη or more.

In one embodiment, the graphene layer although doped has a thermal stability in annealing of at least 250°C, or at least 300°C, or at least 400°C, or at least 500°C.

EXCLUDING FEATURES

In some embodiments, features in the structures or methods can be excluded. For example, the phrases "consisting essentially of or "consisting of can be used to exclude features as known in the art. Basic and novel characteristics of the claimed inventions are described herein.

For example, in one embodiment, ionic liquid gating as described in the Chuang reference, and references cited therein (Perera et al., ACS Nano 2013, 7 (5), 4449), is not used. Hence, in one embodiment, the device does not comprise an ionic liquid. In another embodiment, the at least one graphene layer does not contact an ionic liquid. Also ionic gels can be excluded. Ionic gels are described in, for example, J.K. Huang et al., ACS Nano, 8, p. 923, 2014.

In one embodiment, mechanical or micromechanical exfoliation is not used to prepare the layers as described herein.

In one embodiment, NO2 doping is not used.

WORKING EXAMPLES

Additional embodiments are provided by the following non-limiting working examples including cited references and the figures.

Growth of Lateral Graphene/WSe2 Heterostructures: Figure 1 illustrates the methods of growing graphene [K.K. Kim et al., Nanotechnol., 21 , p. 285205, 2010] and WSe₂ layers [J.K. Huang et al., ACS Nano, 8, p. 923, 2014] using chemical vapor deposition. As- grown large-area multilayer graphene (MLG) was transferred onto c- plane sapphire substrates using the PMMA-assisted transfer technique [Y.C. Lin et al., Nanoscale, 4, p. 6637, 2012]. Optical lithography and dry etching are used to form the desired graphene patterns. MLG-WSe2 heterostructures are formed after growing WSe2 monolayers to the regions without graphene, where a schematic illustration of the process is provided in Figure 2a. The patterned graphene films occupy the left- and right-hand sides and the sapphire surface is exposed in the center region as shown in the optical micrograph in Figure 2b. With the CVD growth (tungsten trioxide and selenium precursors are used for the CVD growth under Ar/H2), the WSe₂ monolayer selectively fills the center region and there is no visible gap as shown in Figure 2c. The

photoluminescence and Raman spectroscopies are adopted to

characterize the MLG-WSe2 heterostructures. Figures 2d and 2e are the Raman intensity mappings for the G band (1577 cm^"1) of graphene and the degenerate E' and ΑΊ bands for WSe₂ respectively. These mappings prove that WSe2 exists only in the center region but not on the top of the graphene layers. Figure 2f compares the single point Raman spectra of MLG before (curve i, as-patterned graphene) and after (curve ii, graphene with WSe₂ stitched laterally) the area-selective WSe2 growth. The Raman peak height ratio of 2D/G (< 1 ) in the curve i corroborates that the as-patterned graphene is multilayered. An obvious and broad D band emerges at about 1350 cm^"1 after the growth of WSe2, which is attributed to the conversion of residual photoresists (used for MLG patterning) to amorphous carbon formed after the high temperature process. Figure 2g shows the photoluminescence peak at 1.62 eV, and Figure 2h displays the degenerate Raman E' and ΑΊ modes for WSe2 at 250 cm^-1, indicating that the WSe2 grown in the channel area is a monolayer.

Figure 3 displays that the graphene film is 3.7 nm thick (ten graphene layers). Few-layered WSe2 is found at the patterned graphene edge, and WSe2 growth is more likely to penetrate into the space between MLG and sapphire substrate, forming a thicker overlapped junction as shown in Figure 3(b). The overlapped (vertically stacked) region is around tens of nanometers. Additional junction cross-section images are provided in Figure 4. Out of overlap region, the layer number of WSe2 gradually reduces from few-layers at the junction to a monolayer when the location is away from the junction. The layer number near the junction at the left of Figure 2(c) is 4 and reduces layer by layer until it totally transits to a monolayer at the channel region.

Figure 6(b) shows the Raman line scan is carried out for the 5 locations from sapphire to the MLG region crossing the patterned edge as marked in Figure 6(a). First, no Raman signal is observed on the exposed sapphire at location a. Then the graphene characteristic peaks, G and 2D bands, are observed near the patterned graphene edge at the locations b, c and d. The presence of a pronounced D band at 1350 cm^"1 indicates that the O2 plasma bombardment induces structural change of graphene while it disappears in location e once the location is away from the edge (only G and 2D band remained). The defects at the patterned MLG edges may provide many nucleation sites for the multilayer WSe2 growth. One can observe the triangular WSe2 grains along the graphene using optical microscope (Figure 6(c)).

Raman spatial mappings of 2D band in graphene and degenerate E' and ΑΊ modes in WSe2 are provided to confirm the distribution of two materials (Figure 6(d) and Figure 6(e)). One can conclude that a seamless MLG-WSe2 lateral junction is formed.

Device Fabrication:

FET devices based on the graphene/WSe2 lateral junction structures were fabricated. Figure 7 details the process flow, where the graphene layers are the actual S and D materials and the Pd evaporated on graphene is used for electrical probing.

Electrical Characteristics:

To explore the electrical performance of the graphene-WSe2 heterojunction, the WSe2 transistors using SLG (single layer graphene) and MLG S/D are fabricated, where Figure 8(a) schemes A and B represent the SLG-WSe2 and MLG-WSe2 respectively. An Hf02 gate dielectric layer (1.5 nm of Hf02 deposited by e-gun followed by 28.5 nm of Hf02 by ALD) and a Pd gate metal (75 nm) were deposited for top- gate FET geometry with the channel width (W) of 20 μιτι and length (L) of 10 pm. The top gate metal has 5 μητι overlap to both the MLG and SLG graphene S/D. Transfer curves for schemes A and B both exhibit p-type transport behaviors as shown in Figure 8. The on-state current of the device from scheme B (MLG) is one order of magnitude larger than that from scheme A (SLG). The resistance between the metal and the graphene film is very small and negligible, therefore the graphene-WSe2 junction resistance (Rj) plays a crucial role in the electrical transport characteristics. The Rj of the device are extracted by the Y-function method (H.-Y. Chang et al., Appl. Phys. Lett. 2014, 104, 113504) and the Rj from scheme B (1.5*10⁷ Ω·μητι) is about 16 times smaller than that from scheme A (2.4*10⁸ Ω·μηι). The hole barrier at the MLG-WSe2 junction is lower likely due to the following reasons (1) a higher carrier concentration of MLG, (2) a high carrier concentration and the smaller band gap of few-layered WSe2 at the contact region.

Doping of MLG for enhancing device performance

For the typically grown and patterned MLG (with the average grain size around 20 μιτι) , the Raman G and 2D bands at 1577 cm^-1 and 2689 cm^-1, do not show any obvious shift after the WSe2 growth. However, one observed that the MLG having a smaller grain size (around 3 urn; abbreviated as sMLG) tends to be p-doped after WSe2 growth,

evidenced by the blue shift in Raman features observed in both G band (from 1577 cm^"1 to 1588 cm ¹) and 2D band (from 2684 cm^"1 to 2700 cnrr ¹) as shown in Figure 8(c) curve ii. The curve i is the Raman before WSe₂ growth for comparison. The doping effect is suggested taking place along the grain boundaries or at some defect sites (Figure 8(d)). One can perform a separate experiment to verify that the doping is likely caused by the unintentional oxidation, where the oxygen source may come from the unavoidable air leak in CVD systems. Interestingly, the p-doping phenomenon in sMLG remains stable even after the sMLG- WSe2 structure is annealed at 300°C in ambient air for 1 hr, as proved by the unchanged Raman features (curve iii). Therefore, the following electrical measurement is retained in ambient air at room temperature.

The field effect transistor based on the doped sMLG-WSe2 heterojunction is fabricated with W/L=18/19pm named Scheme C in Figure 8(a). Since the oxygen doping withdraws electrons and thereby shifts the Fermi level of sMLG downward with respect to the its mid-gap (The qualitative illustration of the band diagram is shown in Figure 8(e)), the hole barrier is reduced at sMLG-WSe2 junction. The on-state current, red curve of Figure 8(b) with lon/loff ratio exceeds 10⁷, is enhanced at least by two orders of magnitude compared with the undoped case (Scheme B). The enhancement is even more than 1000 times larger than the Scheme A. Additional transfer and output curves of Scheme C are provided in Figures 9(a) and 9(b). The Rj = 4.9 *10⁴ Ω·μιτι for the scheme C is 100 times and 1000 times smaller than the scheme B and scheme A respectively. A low-field mobility μ (about) 84 cmW's is also extracted based on the Y-function (/o/Vg™) method at VDS= -0.5V. The C_ox = 5.5 * 10^~7 F/cm² is the calculated gate oxide capacitance for 30 nm of Hf02. The performance is comparable (in the same order) to the reported results using other high mobility approach. One can also separately prepare and discuss WSe2 transistors directly contacted to the conventional metal (Figure 10), where a multilayered stacking heterojunction, Scheme B or C, exhibits better performance than the pure metal junction (Scheme D). Therefore, one can conclude that the MLG heterojunction can reduce the contact resistance. On the other hand, the p-doped graphene S/D actually govern the polarity of the transistor regardless of metal WF; for example, the unipolar hole transport is obtained (Figure 11) even a low WF electrode Ti is used (4.3eV, close to the conduction band of WSe2 at ~ 4.0eV). Note that the devices formed using this approach demonstrates quite consistent unipolar behaviors, different from the reported ambipolar WSe2 FETs which are strongly affected by the metal WF (H. Fang et al., Nano Lett. 2012, 12, 3788-3792).

Claims

WHAT IS CLAIMED IS:

1. A device comprising:

at least one first layer, wherein the first layer has a thickness of 20 nm or less;

at least one second layer, different from the first, which is a transition metal dichalcogenide layer, wherein the second layer has a thickness of 20 nm or less;

wherein the at least one first layer and the at least one second layer form at least one lateral heterojunction.

2. The device of claim 1 , wherein the lateral heterojunction is a lateral penetrating heterojunction.

3. The device of any one of claims 1-2, wherein the lateral

heterojunction is a lateral penetrating heterojunction characterized by a penetration length which is from 1 nm to 500 nm.

4. The device of any one of claims 1-3, wherein the lateral

heterojunction is characterized by an overlapped length which is from 0 nm to 500 nm.

5. The device of any one of claims 1-4, wherein the lateral

heterojunction is characterized by an overlapped length which is from 1 nm to 500 nm.

6. The device any one of claims 1-5, wherein the first layer is a

graphene layer, a boron nitride layer, a phosphorene layer, or a transition metal dichalcogenide layer which is different from the second layer.

7. The device of any one of claims 1-6, wherein the first layer is an un- doped graphene layer, a p-doped graphene layer, or an n-doped graphene layer.

8. The device of any one of claims 1-7, wherein the first layer is a p- doped graphene layer or an n-doped graphene layer, and the second layer is a p-type transition metal dichalcogenide or an n-type transition metal dichalcogenide.

9. The device of any one of claims 1-8, wherein the device comprises at least two domains for the first layer and each of the two domains are in contact with the second layer of transition metal dichalcogenide to form at least two lateral heterojunctions.

10. The device of any one of claims 1-9, wherein the device comprises at least two domains for the first layer and each of the two domains are in contact with the second layer of transition metal dichalcogenide to form at least two lateral interpenetrating heterojunctions.

11. The device of any one of claims 1-10, wherein the device comprises at least two domains for the first layer, wherein one of the two domains is in contact with the second layer which is an n-type second layer, and the other of the two domains is in contact with the second layer which is a p- type second layer.

12. The device of any one of claims 1-11 , wherein the device is a transistor, a photo-sensor, a solar cell, or a light-emitting diode.

13. A method of making the device of any one of claims 1-12 comprising forming on a substrate the at least one first layer, forming the at least one second layer, different from the first, with seed growth from the first layer, wherein the at least one first layer and the at least one second layer form at least one lateral heteroju notion.

14. The method of claim 13, wherein the forming step for the second layer comprises chemical vapor deposition or physical vapor deposition, and wherein the forming step for the first layer comprises patterning the first layer.

15. The method of any one of claims 13 or 14, wherein the method of patterning the first layer comprises dry etching or wet etching.