WO2018085981A1 - Oled display, array substrate, and preparation method therefor - Google Patents

Oled display, array substrate, and preparation method therefor Download PDF

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Publication number
WO2018085981A1
WO2018085981A1 PCT/CN2016/105045 CN2016105045W WO2018085981A1 WO 2018085981 A1 WO2018085981 A1 WO 2018085981A1 CN 2016105045 W CN2016105045 W CN 2016105045W WO 2018085981 A1 WO2018085981 A1 WO 2018085981A1
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Prior art keywords
gate insulating
region
insulating layer
metal oxide
layer
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PCT/CN2016/105045
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French (fr)
Chinese (zh)
Inventor
叶江波
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深圳市柔宇科技有限公司
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Priority to PCT/CN2016/105045 priority Critical patent/WO2018085981A1/en
Priority to CN201680034408.8A priority patent/CN107820639A/en
Publication of WO2018085981A1 publication Critical patent/WO2018085981A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present application relates to the field of OLED display technologies, and in particular, to an OLED display, an array substrate, and a method of fabricating the same.
  • the OLED (Organic Light-Emitting Diode) display has the advantages of self-luminous, wide viewing angle, almost infinite contrast, low power consumption, and extremely high reaction speed. Therefore, it is increasingly used in display devices.
  • the existing OLED display structure there is a certain overlap region between the source and the drain and the gate in the thin film transistor, thereby forming a parasitic capacitance in the region.
  • the gate voltage control thin film transistor When the gate voltage control thin film transistor is turned on, the data line charges the pixel electrode to the pixel voltage, and when the gate voltage controls the thin film transistor to turn off, the pixel voltage is stored.
  • the change of the gate voltage causes the pixel electrode to generate a trip voltage through the parasitic capacitance, and the magnitude of the trip voltage is proportional to the capacitance value of the parasitic capacitance. Therefore, after the thin film transistor is turned off, the voltage is tripped and the actual pixel voltage is made smaller than The charging voltage when the thin film transistor is turned on, resulting in poor display.
  • the purpose of the present application is to provide an array substrate and a manufacturing method thereof, which can reduce the parasitic capacitance value under the premise of ensuring the magnitude of the track current, thereby improving the display effect of the array substrate.
  • Another object of the present application is to provide an OLED display using the above array substrate.
  • the present application provides an array substrate including a substrate, a gate formed on the substrate, a gate insulating layer formed on the substrate and the gate, and a gate insulating layer formed on the gate insulating layer a metal oxide semiconductor layer, a source and a drain formed on the metal oxide semiconductor layer and the gate insulating layer, and an opening between the source and the drain, the metal oxide
  • the semiconductor layer is partially exposed to the opening, the gate insulating layer includes a first region, the first region is opposite to the opening, and a thickness of the first region of the gate insulating layer is smaller than the gate insulating layer The thickness of the outer region of the first region.
  • the gate insulating layer further includes a second region, the second region is opposite to the gate and the drain, and a thickness of the second region of the gate insulating layer is greater than the gate insulating layer The thickness of the area outside the second area.
  • the ratio of the thickness of the first region of the gate insulating layer to the thickness of the second region of the gate insulating layer ranges from 1/2 to 1/4.
  • the ratio of the thickness of the first region of the gate insulating layer to the thickness of the second region of the gate insulating layer is 1/3.
  • the present application provides an OLED display, comprising the array substrate of any of the above.
  • the present application provides a method for fabricating an array substrate, which includes the following steps:
  • the step of performing the etching of the gate insulating layer includes dry etching the gate insulating layer such that the thickness of the first region of the gate insulating layer is smaller than the gate insulating layer The thickness of the area other than the first area.
  • the step of forming a metal oxide semiconductor layer over the gate insulating layer includes forming a metal oxide thin film layer on the gate insulating layer;
  • the second photoresist is stripped.
  • the step of forming a metal oxide thin film layer on the gate insulating layer comprises forming the metal oxide thin film layer on a gate insulating layer by a sputtering method.
  • the metal Forming the oxide semiconductor layer partially in the opening step includes: forming a source/drain film layer on the metal oxide semiconductor layer and the gate insulating layer;
  • the third photoresist is provided with a hollow region, and the hollow region is opposite to the first region;
  • the source and drain thin film layers are etched by using the third photoresist as a shielding layer to form the source and the drain and an opening directly under the hollow region, and the metal oxide semiconductor layer is exposed. At the opening;
  • the third photoresist is stripped.
  • the multi-gray mask is a halftone mask or a gray mask.
  • the gate insulating layer between the drain and the gate is kept constant for the thickness of the gate portion, and the drain is reduced by increasing the thickness of other portions of the gate insulating layer.
  • the value of the parasitic capacitance Cgd between the pole and the gate reduces the value of the parasitic capacitance Cgd under the premise of ensuring the size of the opening current, thereby improving the display effect of the array substrate.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
  • FIG. 2 is a block diagram of an OLED display provided by an embodiment of the present application.
  • FIG. 3 is a flow chart showing a method of fabricating the array substrate shown in FIG. 1.
  • 4 to 11 are schematic views showing a method of fabricating the array substrate shown in FIG. 3.
  • C ⁇ * S / (4 ⁇ kd), where ⁇ is the dielectric constant, S is the facing area of the capacitor plate, d is the distance of the capacitor plate, and k is the electrostatic force constant.
  • the size of the parasitic capacitance is changed by increasing the thickness of the insulating layer between the drain and the gate.
  • the increase of the thickness of the insulating layer between the drain and the gate causes the conductivity factor of the channel above the insulating layer to decrease, causing the channel current to drop, thereby affecting the operating characteristics of the thin film transistor and reducing the imaging effect of the OLED display.
  • the array substrate of the present application can reduce the parasitic capacitance without reducing the conductivity factor value of the channel, thereby improving the imaging effect of the OLED display.
  • the array substrate 100 includes a substrate 10 , a gate 20 , a gate insulating layer 30 , a metal oxide semiconductor layer 40 , and a source/drain layer 50 .
  • the source and drain layers 50 include a source 51 and a drain 52.
  • the substrate 10 is a transparent glass substrate.
  • the gate electrode 20 is formed on the substrate 10, and the gate insulating layer 30 covers the gate electrode 20 and the substrate 10.
  • the gate insulating layer 30 includes a first region 31 and a second region 32. The first region 31 faces an opening 53 between the source 51 and the drain 52, and the second region 32 faces the gate and the drain.
  • the thickness of the first region 31 is smaller than the thickness of the region of the gate insulating layer 30 other than the first region 31. In other words, the first region 31 is the region having the smallest thickness on the gate insulating layer 30.
  • the thickness of the second region 32 is greater than the thickness of the gate insulating layer 30 except for the region outside the second region. In other words, the second region 32 is the region having the largest thickness on the gate insulating layer 30.
  • the metal oxide semiconductor layer 40 is formed on the gate insulating layer 30 and covers the first region 31. The metal oxide semiconductor layer 40 faces the gate electrode 20.
  • the source and drain layers 50 are formed in the On the gate insulating layer 30, the source and drain layers 50 cover the metal oxide semiconductor layer 40.
  • An opening 53 is formed between the source 51 and the drain 52, and the opening 53 leads to the metal oxide semiconductor layer 40. That is, the metal oxide semiconductor layer 40 is partially exposed to the opening 53.
  • the bottom of the opening 53 faces the first region 31 of the gate insulating layer 30.
  • the parasitic capacitance Cgd generated between the drain 52 and the gate 20 affects the performance of the array substrate 100.
  • the thickness of the gate insulating layer 30 between the drain 52 and the gate 20 is kept constant for the portion of the opening 53 by adding the gate insulating layer 30 to the first region. The thickness of the outer region, thereby reducing the value of the parasitic capacitance Cgd between the drain 52 and the gate 20.
  • the array substrate of the present application reduces the value of the parasitic capacitance Cgd under the premise of ensuring the size of the opening current, thereby improving the display effect of the array substrate.
  • a thickness ratio of the first region 31 of the gate insulating layer to the second region 32 of the gate insulating layer ranges from 1/4 to 1/2. In this range, it is ensured that the array substrate has sufficient channel current and the value of the parasitic capacitance Cgd can be minimized.
  • the ratio of the thickness of the first region 31 of the gate insulating layer to the thickness of the second region 32 of the gate insulating layer is 1/3.
  • the gate 20 may be made of a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the requirement.
  • a gate metal layer composed of a plurality of layers of metal may also satisfy the requirement.
  • it may be made of a copper or copper alloy material.
  • the metal oxide semiconductor layer 40 may be IGZO (indium gallium zinc oxide), HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In2O3:Sn, In2O3. :Mo, Cd2SnO4, ZnO: Al, TiO2: Nb, Cd-Sn-O or other metal oxides.
  • IGZO indium gallium zinc oxide
  • HIZO IZO
  • a-InZnO a-InZnO
  • ZnO:F In2O3:Sn, In2O3.
  • Mo Cd2SnO4, ZnO: Al
  • TiO2: Nb Cd-Sn-O or other metal oxides.
  • it can be made of IGZO material.
  • the gate insulating layer 30 should be made of a material having a high dielectric constant.
  • the gate insulating layer 30 may be selected from, but not limited to, TiO 2 , Ta 2 O 5 or HfO 2 .
  • the present application further provides an OLED display 200 including the array substrate 100 of any one of the above.
  • the OLED display 200 can be applied to any product or component having display function including, but not limited to, electronic paper, OLED television, mobile phone, digital photo frame, tablet computer, and the like.
  • the present application further provides a method for manufacturing the above array substrate 100, which mainly includes The following steps:
  • S1 sequentially forming a gate electrode and a gate insulating layer on the substrate, wherein the gate insulating layer includes a first region.
  • a first metal thin film is deposited on the substrate 10.
  • the first metal film may be selected from a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs.
  • a pattern of a gate line (not shown), a common electrode line (not shown), and a gate electrode 20 is formed by a patterning process using a common photoresist layer.
  • a gate insulating layer 30 is deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method, and the gate insulating layer 30 includes a first region 31 and a second region 32.
  • the gate insulating layer 30 may be selected from high dielectric constant materials including, but not limited to, silicon oxide, silicon nitride, or a mixture of the two.
  • S3 providing a multi-gray mask, exposing and developing the first photoresist by using the multi-gray mask to form a half on the first region facing the first photoresist Exposure area.
  • the multi-gray mask may be a half tone mask or a gray tone mask.
  • the multi-gray mask 70 is provided with a semi-transmissive region 71.
  • the multi-gray mask 70 is covered over the first photoresist 60.
  • the first photoresist 60 is exposed and developed (ie, photolithographically). After the first photoresist 60 is subjected to a photolithography process, the first photoresist 60 forms a half exposure region 61 in the semi-transmissive region 71. It can be understood that the half exposure area 61 faces the first area 31.
  • S4 etching the gate insulating layer by using the first photoresist as a shielding layer, such that a thickness of the first region of the gate insulating layer is smaller than the gate insulating layer except the first region The thickness of the area outside.
  • an etching process is required in this step.
  • a dry etching process may be selected.
  • the gate insulating layer 30 is etched by dry etching. It can be understood that, when the dry etching is performed, the first photoresist 60 is first etched, because the half exposure region 61 of the first photoresist 60 is smaller than other regions of the first photoresist 60.
  • the first region 31 of the half-exposed region 61 of the first photoresist 60 facing the gate insulating layer 30 is etched, and the second region 32 is not etched.
  • the thickness of the first region 31 of the gate insulating layer 30 is smaller than the thickness of the gate insulating layer 30 except for the region outside the first region.
  • the thickness of the second region 32 of the gate insulating layer 30 is greater than the gate insulating layer due to the protection of the first photoresist 30
  • the thickness of the area other than the second area is the first region 31 is the region having the smallest thickness on the gate insulating layer 30.
  • the second region 32 is the region having the largest thickness on the gate insulating layer 30. It can be understood that the thickness of the first region 31 of the gate insulating layer 30 is smaller than the thickness of the second region 32 of the gate insulating layer 30.
  • the thickness of the gate insulating layer 30 corresponding to the region is smaller than the gate insulating layer 30.
  • the gate insulating layer 30 described in the present application refers to a region of the gate insulating layer that covers the first photoresist 60 during the manufacturing process.
  • S6 includes:
  • a metal oxide semiconductor layer 40 is deposited on the gate insulating layer 30 by sputtering or thermal evaporation.
  • the metal oxide semiconductor layer 40 may be IGZO (indium gallium zinc oxide), HIZO, IZO. , a-InZnO, a-InZnO, ZnO: F, In2O3: Sn, In2O3: Mo, Cd2SnO4, ZnO: Al, TiO2: Nb, Cd-Sn-O or other metal oxide.
  • IGZO indium gallium zinc oxide
  • HIZO IZO
  • a-InZnO a-InZnO
  • ZnO F
  • In2O3 Sn
  • In2O3 Mo
  • Cd2SnO4 ZnO
  • Al TiO2: Nb
  • it can be made of IGZO material.
  • a metal oxide thin film layer under the second photoresist 80 is left to form the metal oxide semiconductor layer 40.
  • the metal oxide thin film layer of the region not covered by the second photoresist 80 is etched.
  • S7 includes the following steps:
  • the source/drain film layer 50 is deposited on the gate insulating layer 30 by sputtering or thermal evaporation.
  • the source/drain film layer 50 may be selected from a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs.
  • it may be made of a copper or copper alloy material.
  • the hollowed out region 91 may be formed on the third photoresist 90 by a photolithography process.
  • the source/drain film layer is etched by wet etching in a subsequent step, and the etchant etches the source/drain film layer through the hollow region 91 to form an opening 53. It can be understood that the opening 53 between the source 51 and the drain to be formed faces the hollowed out region 91.
  • S73 etching the source/drain film layer by using the third photoresist as a shielding layer to form the source and the drain and an opening directly under the hollow region, the metal oxide semiconductor A layer is exposed to the opening.
  • the opening 53 is formed below the hollowed out area 91.
  • the opening 53 is interposed between the source 51 and the drain 52, and the opening 53 leads to the metal oxide semiconductor layer 40. That is, the metal oxide semiconductor layer 40 is exposed to the opening 53.
  • the third photoresist 90 may be removed by an ashing process or a wet etching process.
  • a first photoresist is formed on the gate insulating layer by a multi-gray mask, and the first photoresist is formed in a region of the gate to form a half-exposure region, and then passes through
  • the etching process has a thickness at a portion of the gate insulating layer corresponding to the half exposed region that is smaller than a thickness of other portions of the gate insulating layer, thereby reducing a parasitic capacitance Cgd under the premise of ensuring a channel current. The value, which in turn improves the display of the array substrate.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

Provided are an array substrate and a preparation method therefor. The array substrate comprises a substrate (10), a gate (20) formed on the substrate (10), a gate insulation layer (30) formed on the substrate (10) and the gate (20), a metal oxide semiconductor layer (40) formed on the gate insulation layer (30), and a source (51) and a drain (52) formed on the metal oxide semiconductor layer (40) and the gate insulation layer (30). An opening (53) is formed between the source (51) and the drain (52), and the metal oxide semiconductor layer (40) is partially exposed out of the opening (53). The gate insulation layer (30) comprises a first region (31), and the first region (31) directly faces to the opening (53). The thickness of the first region (31) of the gate insulation layer (30) is smaller than that of a region (32) of the gate insulation layer (30) except the first region. The thickness of a part, directly facing to the gate (20), of the gate insulation layer (30) between the drain (52) and the gate (20) is kept unchanged, and the thickness of the other part of the gate insulation layer (30) is increased, thereby reducing a value of a parasitic capacitance between the drain (52) and the gate (20).

Description

OLED显示器、阵列基板及其制作方法OLED display, array substrate and manufacturing method thereof 技术领域Technical field
本申请涉及OLED显示技术领域，尤其涉及一种OLED显示器、阵列基板及其制作方法。The present application relates to the field of OLED display technologies, and in particular, to an OLED display, an array substrate, and a method of fabricating the same.
背景技术Background technique
OLED(Organic Light-Emitting Diode，有机发光二极管)显示器具有自发光、广视角、几乎无穷高的对比度、较低耗电、极高反应速度等优点。因而越来越多地应用于显示装置中。The OLED (Organic Light-Emitting Diode) display has the advantages of self-luminous, wide viewing angle, almost infinite contrast, low power consumption, and extremely high reaction speed. Therefore, it is increasingly used in display devices.
现有的OLED显示器结构中，薄膜晶体管中源极和漏极与栅极之间存在一定的重叠区域，从而在该区域形成寄生电容。当栅极电压控制薄膜晶体管导通时，数据线为像素电极充电至像素电压，当栅极电压控制薄膜晶体管截止时，像素电压被存储。然而，栅极电压的变化会通过寄生电容使得像素电极产生跳变电压，且跳变电压的大小与寄生电容的电容值成正比，因此，薄膜晶体管截止后，跳变电压并使实际像素电压小于薄膜晶体管导通时的充电电压，从而导致显示效果较差。In the existing OLED display structure, there is a certain overlap region between the source and the drain and the gate in the thin film transistor, thereby forming a parasitic capacitance in the region. When the gate voltage control thin film transistor is turned on, the data line charges the pixel electrode to the pixel voltage, and when the gate voltage controls the thin film transistor to turn off, the pixel voltage is stored. However, the change of the gate voltage causes the pixel electrode to generate a trip voltage through the parasitic capacitance, and the magnitude of the trip voltage is proportional to the capacitance value of the parasitic capacitance. Therefore, after the thin film transistor is turned off, the voltage is tripped and the actual pixel voltage is made smaller than The charging voltage when the thin film transistor is turned on, resulting in poor display.
申请内容Application content
本申请的目的在于提供阵列基板及其制作方法，能够在保证道电流大小的前提下，减小了寄生电容值，进而提升了阵列基板的显示效果。The purpose of the present application is to provide an array substrate and a manufacturing method thereof, which can reduce the parasitic capacitance value under the premise of ensuring the magnitude of the track current, thereby improving the display effect of the array substrate.
本申请的另一目的在于提供一种采用上述阵列基板的OLED显示器。Another object of the present application is to provide an OLED display using the above array substrate.
为实现上述目的，本申请提供如下技术方案：To achieve the above objective, the present application provides the following technical solutions:
本申请提供一种阵列基板，其中，包括基板、形成于所述基板上的栅极、形成于所述基板和所述栅极上的栅极绝缘层、形成于所述栅极绝缘层上的金属氧化物半导体层、形成于所述金属氧化物半导体层及所述栅极绝缘层上的源极和漏极，所述源极和所述漏极之间设有开口，所述金属氧化物半导体层部分露出于所述开口，所述栅极绝缘层包括第一区域，所述第一区域正对所述开口，所述栅极绝缘层第一区域的厚度小于所述栅极绝缘层除所述第一区域外区域的厚度。 The present application provides an array substrate including a substrate, a gate formed on the substrate, a gate insulating layer formed on the substrate and the gate, and a gate insulating layer formed on the gate insulating layer a metal oxide semiconductor layer, a source and a drain formed on the metal oxide semiconductor layer and the gate insulating layer, and an opening between the source and the drain, the metal oxide The semiconductor layer is partially exposed to the opening, the gate insulating layer includes a first region, the first region is opposite to the opening, and a thickness of the first region of the gate insulating layer is smaller than the gate insulating layer The thickness of the outer region of the first region.
其中，所述栅极绝缘层还包括第二区域，所述第二区域正对所述栅极和所述漏极，所述栅极绝缘层第二区域的厚度大于所述栅极绝缘层除第二区域之外区域的厚度。The gate insulating layer further includes a second region, the second region is opposite to the gate and the drain, and a thickness of the second region of the gate insulating layer is greater than the gate insulating layer The thickness of the area outside the second area.
其中，所述栅极绝缘层第一区域厚度与所述栅极绝缘层第二区域厚度比值范围为1/2-1/4。The ratio of the thickness of the first region of the gate insulating layer to the thickness of the second region of the gate insulating layer ranges from 1/2 to 1/4.
其中，所述栅极绝缘层第一区域厚度与栅极绝缘层第二区域厚度的比值为1/3。The ratio of the thickness of the first region of the gate insulating layer to the thickness of the second region of the gate insulating layer is 1/3.
本申请提供一种OLED显示器，其中，包括上述任意一项所述的阵列基板。The present application provides an OLED display, comprising the array substrate of any of the above.
本申请提供一种阵列基板的制作方法，其中，包括如下步骤：The present application provides a method for fabricating an array substrate, which includes the following steps:
在基板上依次形成栅极和栅极绝缘层，其中，所述栅极绝缘层包括第一区域；Forming a gate and a gate insulating layer sequentially on the substrate, wherein the gate insulating layer includes a first region;
在所述栅极绝缘层上涂覆第一光阻；Coating a first photoresist on the gate insulating layer;
提供一多灰阶掩膜版，利用所述多灰阶掩膜版对所述第一光阻进行曝光、显影，以在所述第一光阻正对所述第一区域形成半曝光区域；Providing a multi-gray mask, exposing and developing the first photoresist by using the multi-gray mask to form a half exposure region facing the first region in the first photoresist;
以所述第一光阻为遮蔽层，对所述栅极绝缘层进行蚀刻，使得所述栅极绝缘层的所述第一区域厚度小于所述栅极绝缘层除所述第一区域之外区域的厚度；Etching the gate insulating layer with the first photoresist as a shielding layer, such that a thickness of the first region of the gate insulating layer is smaller than the gate insulating layer except the first region The thickness of the area;
剥离所述第一光阻；Peeling the first photoresist;
在所述栅极绝缘层上方形成金属氧化物半导体层；Forming a metal oxide semiconductor layer over the gate insulating layer;
在所述金属氧化物半导体层及所述栅极绝缘层上形成源极、漏极及介于二者之间的开口，所述开口正对所述第一区域，所述金属氧化物半导体层部分露出于所述开口。Forming a source, a drain, and an opening therebetween between the metal oxide semiconductor layer and the gate insulating layer, the opening facing the first region, the metal oxide semiconductor layer Partially exposed to the opening.
其中，所述对所述栅极绝缘层进行蚀刻步骤中，包括对所述栅极绝缘层进行干法蚀刻，使得所述栅极绝缘层的所述第一区域厚度小于所述栅极绝缘层除所述第一区域外区域的厚度。The step of performing the etching of the gate insulating layer includes dry etching the gate insulating layer such that the thickness of the first region of the gate insulating layer is smaller than the gate insulating layer The thickness of the area other than the first area.
其中，所述在所述栅极绝缘层上方形成金属氧化物半导体层步骤中，包括在所述栅极绝缘层上形成金属氧化物薄膜层；The step of forming a metal oxide semiconductor layer over the gate insulating layer includes forming a metal oxide thin film layer on the gate insulating layer;
在所述金属氧化物薄膜层正对所述栅极的区域形成第二光阻；Forming a second photoresist in a region of the metal oxide thin film layer facing the gate;
以所述第二光阻为遮蔽层，对所述金属氧化物薄膜层进行蚀刻，以在所述 第二光阻下方形成所述金属氧化物半导体层；Etching the metal oxide thin film layer with the second photoresist as a shielding layer to Forming the metal oxide semiconductor layer under the second photoresist;
剥离所述第二光阻。The second photoresist is stripped.
其中，所述在所述栅极绝缘层上形成金属氧化物薄膜层步骤中，包括通过溅射法在栅极绝缘层上形成所述金属氧化物薄膜层。Wherein the step of forming a metal oxide thin film layer on the gate insulating layer comprises forming the metal oxide thin film layer on a gate insulating layer by a sputtering method.
其中，所述在所述金属氧化物半导体层及所述栅极绝缘层上形成源极、漏极及介于二者之间的开口，所述开口正对所述第一区域，所述金属氧化物半导体层部分露出于所述开口步骤中包括：在所述金属氧化物半导体层及所述栅极绝缘层上形成源漏极薄膜层；Wherein the source, the drain and an opening therebetween are formed on the metal oxide semiconductor layer and the gate insulating layer, the opening is opposite to the first region, the metal Forming the oxide semiconductor layer partially in the opening step includes: forming a source/drain film layer on the metal oxide semiconductor layer and the gate insulating layer;
在所述源漏极薄膜层上形成第三光阻，所述第三光阻上设有镂空区，所述镂空区正对所述第一区域；Forming a third photoresist on the source/drain film layer, the third photoresist is provided with a hollow region, and the hollow region is opposite to the first region;
以所述第三光阻为遮蔽层，对所述源漏极薄膜层进行蚀刻，以形成所述源极、漏极及位于所述镂空区正下方的开口，所述金属氧化物半导体层露出于所述开口；The source and drain thin film layers are etched by using the third photoresist as a shielding layer to form the source and the drain and an opening directly under the hollow region, and the metal oxide semiconductor layer is exposed. At the opening;
剥离所述第三光阻。The third photoresist is stripped.
其中，所述多灰阶掩膜版为半色调掩膜版或灰色调掩膜版。。Wherein, the multi-gray mask is a halftone mask or a gray mask. .
本申请实施例具有如下优点或有益效果：The embodiments of the present application have the following advantages or benefits:
本申请中将所述漏极与所述栅极间的栅极绝缘层正对于所述栅极部分的厚度保持不变，通过增加栅极绝缘层上其他部分的厚度，从而减小所述漏极与所述栅极之间的寄生电容Cgd的值。本申请的阵列基板在保证开口电流大小的前提下，减小了寄生电容Cgd的值，进而提升了阵列基板的显示效果。In the present application, the gate insulating layer between the drain and the gate is kept constant for the thickness of the gate portion, and the drain is reduced by increasing the thickness of other portions of the gate insulating layer. The value of the parasitic capacitance Cgd between the pole and the gate. The array substrate of the present application reduces the value of the parasitic capacitance Cgd under the premise of ensuring the size of the opening current, thereby improving the display effect of the array substrate.
附图说明DRAWINGS
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings to be used in the embodiments will be briefly described below. Obviously, the drawings in the following description are only some of the present application. For the embodiments, those skilled in the art can obtain other drawings according to the drawings without any creative work.
图1为本申请一种实施方式提供的阵列基板结构示意图。FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
图2为本申请一种实施方式提供的OLED显示器框图。2 is a block diagram of an OLED display provided by an embodiment of the present application.
图3是图1所示的阵列基板的制作方法流程示意图。3 is a flow chart showing a method of fabricating the array substrate shown in FIG. 1.
图4-图11是图3所示阵列基板的制作方法示意图。 4 to 11 are schematic views showing a method of fabricating the array substrate shown in FIG. 3.
具体实施方式detailed description
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope are the scope of the present application.
本申请以下实施例中所采用的序数限定词，第一、第二等仅是为了清楚地说明本申请中相似的特征的区别性的用语，不代表相应的特征的排列顺序或者使用顺序。The ordinal qualifiers used in the following embodiments of the present application, the first, second, etc. are merely for the purpose of clearly indicating the distinctive features of the similar features in the present application, and do not represent the order of the corresponding features or the order of use.
根据电容计算公式：C＝ε*S/(4πkd)，其中ε是为介电常数，S为电容极板的正对面积，d为电容极板的距离，k则是静电力常数。Calculate according to the capacitance: C = ε * S / (4πkd), where ε is the dielectric constant, S is the facing area of the capacitor plate, d is the distance of the capacitor plate, and k is the electrostatic force constant.
可以理解的是，通过增大漏极与栅极之间的绝缘层的厚度，从而改变寄生电容的大小。但是，漏极与栅极之间的绝缘层厚度的增加，会使得绝缘层上方的沟道的导电因子值下降，造成沟道电流下降，从而影响薄膜晶体管的工作特性，降低OLED显示器的成像效果。本申请的阵列基板可以在降低寄生电容的同时，又不会降低沟道的导电因子值，从而提升了OLED显示器的成像效果。It can be understood that the size of the parasitic capacitance is changed by increasing the thickness of the insulating layer between the drain and the gate. However, the increase of the thickness of the insulating layer between the drain and the gate causes the conductivity factor of the channel above the insulating layer to decrease, causing the channel current to drop, thereby affecting the operating characteristics of the thin film transistor and reducing the imaging effect of the OLED display. . The array substrate of the present application can reduce the parasitic capacitance without reducing the conductivity factor value of the channel, thereby improving the imaging effect of the OLED display.
请参阅图1，本申请一种实施方式中，阵列基板100包括：基板10、栅极20、栅极绝缘层30、金属氧化物半导体层40和源漏极层50。所述源漏极层50上包括源极51和漏极52。所述基板10为透明玻璃基板。所述栅极20形成于所述基板10上，所述栅极绝缘层30覆盖于所述栅极20及基板10之上。所述栅极绝缘层30包括第一区域31和第二区域32。所述第一区域31正对所述源极51和所述漏极52之间的开口53，所述第二区域32正对所述栅极和所述漏极。第一区域31的厚度小于所述栅极绝缘层30除所述第一区域31之外区域的厚度。换而言之，所述第一区域31为所述栅极绝缘层30上厚度最小的区域。所述第二区域32的厚度大于所述栅极绝缘层30除第二区域外区域的厚度。换而言之，所述第二区域32为所述栅极绝缘层30上厚度最大的区域。所述金属氧化物半导体层40形成于所述栅极绝缘层30上，并覆盖所述第一区域31。所述金属氧化物半导体层40正对所述栅极20。所述源漏极层50形成于所述 栅极绝缘层30上，所述源漏极层50覆盖所述金属氧化物半导体层40。所述源极51和所述漏极52之间形成有开口53，所述开口53通向所述金属氧化物半导体层40。也就是说，所述金属氧化物半导体层40部分露出于所述开口53。所述开口53底部正对所述栅极绝缘层30第一区域31。Referring to FIG. 1 , in an embodiment of the present application, the array substrate 100 includes a substrate 10 , a gate 20 , a gate insulating layer 30 , a metal oxide semiconductor layer 40 , and a source/drain layer 50 . The source and drain layers 50 include a source 51 and a drain 52. The substrate 10 is a transparent glass substrate. The gate electrode 20 is formed on the substrate 10, and the gate insulating layer 30 covers the gate electrode 20 and the substrate 10. The gate insulating layer 30 includes a first region 31 and a second region 32. The first region 31 faces an opening 53 between the source 51 and the drain 52, and the second region 32 faces the gate and the drain. The thickness of the first region 31 is smaller than the thickness of the region of the gate insulating layer 30 other than the first region 31. In other words, the first region 31 is the region having the smallest thickness on the gate insulating layer 30. The thickness of the second region 32 is greater than the thickness of the gate insulating layer 30 except for the region outside the second region. In other words, the second region 32 is the region having the largest thickness on the gate insulating layer 30. The metal oxide semiconductor layer 40 is formed on the gate insulating layer 30 and covers the first region 31. The metal oxide semiconductor layer 40 faces the gate electrode 20. The source and drain layers 50 are formed in the On the gate insulating layer 30, the source and drain layers 50 cover the metal oxide semiconductor layer 40. An opening 53 is formed between the source 51 and the drain 52, and the opening 53 leads to the metal oxide semiconductor layer 40. That is, the metal oxide semiconductor layer 40 is partially exposed to the opening 53. The bottom of the opening 53 faces the first region 31 of the gate insulating layer 30.
可以理解的是，在阵列基板100中，所述漏极52与所述栅极20之间产生的寄生电容Cgd会影响阵列基板100的性能。本申请中将所述漏极52与所述栅极20之间的栅极绝缘层30正对于所述开口53部分的厚度保持不变，通过增加栅极绝缘层30上除所述第一区域之外区域的厚度，从而减小所述漏极52与所述栅极20之间的寄生电容Cgd的值。本申请的阵列基板在保证开口电流大小的前提下，减小了寄生电容Cgd的值，进而提升了阵列基板的显示效果。It can be understood that in the array substrate 100, the parasitic capacitance Cgd generated between the drain 52 and the gate 20 affects the performance of the array substrate 100. In the present application, the thickness of the gate insulating layer 30 between the drain 52 and the gate 20 is kept constant for the portion of the opening 53 by adding the gate insulating layer 30 to the first region. The thickness of the outer region, thereby reducing the value of the parasitic capacitance Cgd between the drain 52 and the gate 20. The array substrate of the present application reduces the value of the parasitic capacitance Cgd under the premise of ensuring the size of the opening current, thereby improving the display effect of the array substrate.
本申请一种实施方式中，所述栅极绝缘层第一区域31厚度与所述栅极绝缘层第二区域32厚度比值范围为1/4-1/2。在此范围内既保证了阵列基板具有足够的沟道电流，又能够最大程度减小寄生电容Cgd的值。In an embodiment of the present application, a thickness ratio of the first region 31 of the gate insulating layer to the second region 32 of the gate insulating layer ranges from 1/4 to 1/2. In this range, it is ensured that the array substrate has sufficient channel current and the value of the parasitic capacitance Cgd can be minimized.
进一步优选的，所述栅极绝缘层第一区域31厚度与栅极绝缘层第二区域32厚度的比值为1/3。Further preferably, the ratio of the thickness of the first region 31 of the gate insulating layer to the thickness of the second region 32 of the gate insulating layer is 1/3.
可选的，所述栅极20可以选用Cr、W、Cu、Ti、Ta、Mo等金属或合金，由多层金属组成的栅金属层也能满足需要。优选的，可以选用铜或铜合金材料制成。Optionally, the gate 20 may be made of a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the requirement. Preferably, it may be made of a copper or copper alloy material.
可选的，所述金属氧化物半导体层40可以是采用IGZO(indium gallium zinc oxide，铟镓锌氧化物)、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:Nb、Cd-Sn-O或其他金属氧化物制成。优选的，可以选用IGZO材料制成。Optionally, the metal oxide semiconductor layer 40 may be IGZO (indium gallium zinc oxide), HIZO, IZO, a-InZnO, a-InZnO, ZnO:F, In2O3:Sn, In2O3. :Mo, Cd2SnO4, ZnO: Al, TiO2: Nb, Cd-Sn-O or other metal oxides. Preferably, it can be made of IGZO material.
可选的，为了进一步提高等效电容值，所述栅极绝缘层30应选用高介电常数的材料。具体的，所述栅极绝缘层30可以选用包括但不限于TiO2、Ta2O5或HfO2等。Optionally, in order to further increase the equivalent capacitance value, the gate insulating layer 30 should be made of a material having a high dielectric constant. Specifically, the gate insulating layer 30 may be selected from, but not limited to, TiO 2 , Ta 2 O 5 or HfO 2 .
请参阅图2，本申请还提供一种OLED显示器200，该OLED显示面板200包括上述任意一种所述的阵列基板100。所述OLED显示器200可以应用于包括但不限于为：电子纸、OLED电视、移动电话、数码相框、平板电脑等任何具有显示功能的产品或部件。Referring to FIG. 2 , the present application further provides an OLED display 200 including the array substrate 100 of any one of the above. The OLED display 200 can be applied to any product or component having display function including, but not limited to, electronic paper, OLED television, mobile phone, digital photo frame, tablet computer, and the like.
请参阅图3，本申请还提供一种上述阵列基板100的制造方法，主要包括 如下步骤：Referring to FIG. 3 , the present application further provides a method for manufacturing the above array substrate 100, which mainly includes The following steps:
S1：在基板上依次形成栅极和栅极绝缘层，其中，所述栅极绝缘层包括第一区域。S1: sequentially forming a gate electrode and a gate insulating layer on the substrate, wherein the gate insulating layer includes a first region.
具体的，请结合参阅图4，在所述基板10上沉积第一金属薄膜。所述第一金属薄膜可以选用Cr、W、Cu、Ti、Ta、Mo等金属或合金，由多层金属组成的栅金属层也能满足需要。通过构图工艺利用普通光阻层形成栅线(图未示出)、公共电极线(图未示出)和栅极20的图形。然后在此基础上通过PECVD(等离子体增强化学气相沉积法)方法沉积栅极绝缘层30，栅极绝缘层30包括第一区域31和第二区域32。栅极绝缘层30可以选用包括但不限于氧化硅、氮化硅或二者的混合物等高介电常数的材料。Specifically, referring to FIG. 4, a first metal thin film is deposited on the substrate 10. The first metal film may be selected from a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs. A pattern of a gate line (not shown), a common electrode line (not shown), and a gate electrode 20 is formed by a patterning process using a common photoresist layer. Then, on this basis, a gate insulating layer 30 is deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method, and the gate insulating layer 30 includes a first region 31 and a second region 32. The gate insulating layer 30 may be selected from high dielectric constant materials including, but not limited to, silicon oxide, silicon nitride, or a mixture of the two.
S2：在所述栅极绝缘层上涂覆第一光阻。S2: coating a first photoresist on the gate insulating layer.
S3：提供一多灰阶掩膜版，利用所述多灰阶掩膜版对所述第一光阻进行曝光、显影，以在所述第一光阻正对所述第一区域上形成半曝光区域。S3: providing a multi-gray mask, exposing and developing the first photoresist by using the multi-gray mask to form a half on the first region facing the first photoresist Exposure area.
具体的，请参阅图5。所述多灰阶掩膜版可以为半色调掩膜版(Half tone mask)或灰色调掩膜版(Gray tone mask)。所述多灰阶掩膜版70上设置有半透光区71。将所述多灰阶掩膜版70遮盖在所述第一光阻60上方。对所述第一光阻60进行曝光、显影(即光刻)。所述第一光阻60经过光刻工艺后，所述第一光阻60在正对所述半透光区71形成半曝光区域61。可以理解的是，所述半曝光区域61正对所述第一区域31。Specifically, please refer to Figure 5. The multi-gray mask may be a half tone mask or a gray tone mask. The multi-gray mask 70 is provided with a semi-transmissive region 71. The multi-gray mask 70 is covered over the first photoresist 60. The first photoresist 60 is exposed and developed (ie, photolithographically). After the first photoresist 60 is subjected to a photolithography process, the first photoresist 60 forms a half exposure region 61 in the semi-transmissive region 71. It can be understood that the half exposure area 61 faces the first area 31.
S4：以所述第一光阻为遮蔽层，对所述栅极绝缘层进行蚀刻，使得所述栅极绝缘层的所述第一区域厚度小于所述栅极绝缘层除所述第一区域之外区域的厚度。S4: etching the gate insulating layer by using the first photoresist as a shielding layer, such that a thickness of the first region of the gate insulating layer is smaller than the gate insulating layer except the first region The thickness of the area outside.
请结合参阅图6，具体的，在该步骤中需要进行蚀刻工艺，优选的，可以选用干法蚀刻工艺。通过干法蚀刻对所述栅极绝缘层30进行蚀刻。可以理解的是，进行干法蚀刻时，首先会对所述第一光阻60进行蚀刻，由于所述第一光阻60的半曝光区域61较所述第一光阻60其他区域的厚度小，所述栅极绝缘层30正对所述第一光阻60的半曝光区域61的第一区域31会被蚀刻到，所述第二区域32未被蚀刻。也就是说，所述栅极绝缘层30的所述第一区域31的厚度小于所述栅极绝缘层30除所述第一区域外区域的厚度。由于第一光阻的保护作用，所述栅极绝缘层30的第二区域32的厚度大于所述栅极绝缘层 30除第二区域之外区域的厚度。换而言之，所述第一区域31为所述栅极绝缘层30上厚度最小的区域。所述第二区域32为所述栅极绝缘层30上厚度最大的区域。可以理解的是，所述栅极绝缘层30所述第一区域31的厚度小于所述栅极绝缘层30的第二区域32的厚度。Please refer to FIG. 6 in combination. Specifically, an etching process is required in this step. Preferably, a dry etching process may be selected. The gate insulating layer 30 is etched by dry etching. It can be understood that, when the dry etching is performed, the first photoresist 60 is first etched, because the half exposure region 61 of the first photoresist 60 is smaller than other regions of the first photoresist 60. The first region 31 of the half-exposed region 61 of the first photoresist 60 facing the gate insulating layer 30 is etched, and the second region 32 is not etched. That is, the thickness of the first region 31 of the gate insulating layer 30 is smaller than the thickness of the gate insulating layer 30 except for the region outside the first region. The thickness of the second region 32 of the gate insulating layer 30 is greater than the gate insulating layer due to the protection of the first photoresist 30 The thickness of the area other than the second area. In other words, the first region 31 is the region having the smallest thickness on the gate insulating layer 30. The second region 32 is the region having the largest thickness on the gate insulating layer 30. It can be understood that the thickness of the first region 31 of the gate insulating layer 30 is smaller than the thickness of the second region 32 of the gate insulating layer 30.
可以理解的是，若所述栅极绝缘层30上有未覆盖所述第一光阻60的区域，则该区域对应的所述栅极绝缘层30的厚度小于所述栅极绝缘层30正对于所述栅极20部分的厚度。本申请中所述的所述栅极绝缘层30指的是制造过程中栅极绝缘层上覆盖了所述第一光阻60的区域。It can be understood that if the gate insulating layer 30 has a region that does not cover the first photoresist 60, the thickness of the gate insulating layer 30 corresponding to the region is smaller than the gate insulating layer 30. For the thickness of the portion of the gate 20 . The gate insulating layer 30 described in the present application refers to a region of the gate insulating layer that covers the first photoresist 60 during the manufacturing process.
S5：剥离所述第一光阻；S5: peeling off the first photoresist;
S6：在所述栅极绝缘层上方形成金属氧化物半导体层；S6: forming a metal oxide semiconductor layer over the gate insulating layer;
具体的，S6包括：Specifically, S6 includes:
S61：所述栅极绝缘层上形成金属氧化物薄膜层；S61: forming a metal oxide thin film layer on the gate insulating layer;
具体的，请参阅图7。在所述栅绝缘层30上通过溅射或热蒸发的方法沉积金属氧化物半导体层40，金属氧化物半导体层40可以是采用IGZO(indium gallium zinc oxide，铟镓锌氧化物)、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:Nb、Cd-Sn-O或其他金属氧化物制成。优选的，可以选用IGZO材料制成。Specifically, please refer to Figure 7. A metal oxide semiconductor layer 40 is deposited on the gate insulating layer 30 by sputtering or thermal evaporation. The metal oxide semiconductor layer 40 may be IGZO (indium gallium zinc oxide), HIZO, IZO. , a-InZnO, a-InZnO, ZnO: F, In2O3: Sn, In2O3: Mo, Cd2SnO4, ZnO: Al, TiO2: Nb, Cd-Sn-O or other metal oxide. Preferably, it can be made of IGZO material.
S62：在所述金属氧化物薄膜层正对所述栅极的区域形成第二光阻；S62: forming a second photoresist in a region of the metal oxide thin film layer facing the gate;
S63：以所述第二光阻为遮蔽层，对所述金属氧化物薄膜层进行蚀刻，以在所述第二光阻下方形成所述金属氧化物半导体层；S63: etching the metal oxide thin film layer with the second photoresist as a shielding layer to form the metal oxide semiconductor layer under the second photoresist;
请参阅图8，所述第二光阻80下方的金属氧化物薄膜层被保留以形成所述金属氧化物半导体层40。第二光阻80未覆盖的区域的金属氧化物薄膜层被蚀刻。Referring to FIG. 8, a metal oxide thin film layer under the second photoresist 80 is left to form the metal oxide semiconductor layer 40. The metal oxide thin film layer of the region not covered by the second photoresist 80 is etched.
S64：剥离所述第二光阻。S64: peeling off the second photoresist.
S7：在所述金属氧化物半导体层及所述栅极绝缘层上形成源极、漏极及介于二者之间的开口，所述开口正对所述第一区域，所述金属氧化物半导体层部分露出于所述开口。S7: forming a source, a drain, and an opening therebetween between the metal oxide semiconductor layer and the gate insulating layer, the opening facing the first region, the metal oxide A portion of the semiconductor layer is exposed to the opening.
具体的，S7包括如下步骤： Specifically, S7 includes the following steps:
S71：在所述金属氧化物半导体层及所述栅极绝缘层上形成源漏极薄膜层；S71: forming a source/drain film layer on the metal oxide semiconductor layer and the gate insulating layer;
具体的，请参阅图9。在所述栅绝缘层30上通过溅射或热蒸发的方法沉积所述源漏极薄膜层50。所述源漏极薄膜层50可以选用Cr、W、Cu、Ti、Ta、Mo等金属或合金，由多层金属组成的栅金属层也能满足需要。优选的，可以选用铜或铜合金材料制成。Specifically, please refer to Figure 9. The source/drain film layer 50 is deposited on the gate insulating layer 30 by sputtering or thermal evaporation. The source/drain film layer 50 may be selected from a metal or an alloy such as Cr, W, Cu, Ti, Ta, Mo, etc., and a gate metal layer composed of a plurality of layers of metal may also satisfy the needs. Preferably, it may be made of a copper or copper alloy material.
S72：在所述源漏极薄膜层上形成第三光阻，所述第三光阻正对所述第一区域设有镂空区；S72: forming a third photoresist on the source/drain film layer, wherein the third photoresist is disposed in the first region with a hollow region;
具体的，请参阅图10。可以通过光刻工艺在所述第三光阻90上形成所述镂空区91。以便后续步骤中采用湿法蚀刻对源漏极薄膜层进行蚀刻，蚀刻液经所述镂空区91对所述源漏极薄膜层进行蚀刻，从而形成开口53。可以理解的是，将要形成的所述源极51和漏极之间开口53正对所述镂空区91。Specifically, please refer to Figure 10. The hollowed out region 91 may be formed on the third photoresist 90 by a photolithography process. The source/drain film layer is etched by wet etching in a subsequent step, and the etchant etches the source/drain film layer through the hollow region 91 to form an opening 53. It can be understood that the opening 53 between the source 51 and the drain to be formed faces the hollowed out region 91.
S73：以所述第三光阻为遮蔽层，对所述源漏极薄膜层进行蚀刻，以形成所述源极、漏极及位于所述镂空区正下方的开口，所述金属氧化物半导体层露出于所述开口。S73: etching the source/drain film layer by using the third photoresist as a shielding layer to form the source and the drain and an opening directly under the hollow region, the metal oxide semiconductor A layer is exposed to the opening.
具体的，请结合参阅图11。可以理解的是，所述镂空区91下方形成所述开口53。所述开口53介于所述源极51和所述漏极52之间，所述开口53通向所述金属氧化物半导体层40。也就是说，所述金属氧化物半导体层40露出于所述开口53。Specifically, please refer to Figure 11. It can be understood that the opening 53 is formed below the hollowed out area 91. The opening 53 is interposed between the source 51 and the drain 52, and the opening 53 leads to the metal oxide semiconductor layer 40. That is, the metal oxide semiconductor layer 40 is exposed to the opening 53.
S74：剥离所述第三光阻。S74: peeling off the third photoresist.
请参阅图1，可以通过灰化工艺或者湿法蚀刻工艺去除所述第三光阻90。Referring to FIG. 1, the third photoresist 90 may be removed by an ashing process or a wet etching process.
本申请的阵列基板制作方法中，通过多灰阶掩膜版在栅极绝缘层上形成第一光阻，且所述第一光阻正对所述栅极的区域形成半曝光区域，进而通过蚀刻工艺在所述栅极绝缘层对应于所述半曝光区域的部分的厚度小于所述栅极绝缘层其他部分的厚度，从而在保证沟道电流大小的前提下，减小了寄生电容Cgd的值，进而提升了阵列基板的显示效果。In the method for fabricating an array substrate of the present application, a first photoresist is formed on the gate insulating layer by a multi-gray mask, and the first photoresist is formed in a region of the gate to form a half-exposure region, and then passes through The etching process has a thickness at a portion of the gate insulating layer corresponding to the half exposed region that is smaller than a thickness of other portions of the gate insulating layer, thereby reducing a parasitic capacitance Cgd under the premise of ensuring a channel current. The value, which in turn improves the display of the array substrate.
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。 The embodiments of the present application have been described in detail above. The principles and implementations of the present application are described in the specific examples. The description of the above embodiments is only used to help understand the method and core ideas of the present application. A person skilled in the art will have a change in the specific embodiments and the scope of the application according to the idea of the present application. In summary, the content of the present specification should not be construed as limiting the present application.

Claims (11)

  1. 一种阵列基板，其特征在于，包括基板、形成于所述基板上的栅极、形成于所述基板和所述栅极上的栅极绝缘层、形成于所述栅极绝缘层上的金属氧化物半导体层、形成于所述金属氧化物半导体层及所述栅极绝缘层上的源极和漏极，所述源极和所述漏极之间设有开口，所述金属氧化物半导体层部分露出于所述开口，所述栅极绝缘层包括第一区域，所述第一区域正对所述开口，所述栅极绝缘层第一区域的厚度小于所述栅极绝缘层除所述第一区域之外区域的厚度。An array substrate, comprising: a substrate, a gate formed on the substrate, a gate insulating layer formed on the substrate and the gate, and a metal formed on the gate insulating layer An oxide semiconductor layer, a source and a drain formed on the metal oxide semiconductor layer and the gate insulating layer, and an opening between the source and the drain, the metal oxide semiconductor a layer portion is exposed at the opening, the gate insulating layer includes a first region, the first region is opposite to the opening, and a thickness of the first region of the gate insulating layer is smaller than a thickness of the gate insulating layer The thickness of the area outside the first area.
  2. 如权利要求1所述的阵列基板，其特征在于，所述栅极绝缘层还包括第二区域，所述第二区域正对所述栅极和所述漏极，所述栅极绝缘层第二区域的厚度大于所述栅极绝缘层除第二区域之外区域的厚度。The array substrate according to claim 1, wherein the gate insulating layer further comprises a second region, the second region facing the gate and the drain, the gate insulating layer The thickness of the two regions is greater than the thickness of the region of the gate insulating layer other than the second region.
  3. 如权利要求2所述的阵列基板，其特征在于，所述栅极绝缘层第一区域厚度与所述栅极绝缘层第二区域厚度比值范围为1/4-1/2。The array substrate according to claim 2, wherein a ratio of a thickness of the first region of the gate insulating layer to a thickness of the second region of the gate insulating layer ranges from 1/4 to 1/2.
  4. 如权利要求2或3所述的阵列基板，其特征在于，所述栅极绝缘层第一区域厚度与所述栅极绝缘层第二区域厚度的比值为1/3。The array substrate according to claim 2 or 3, wherein a ratio of a thickness of the first region of the gate insulating layer to a thickness of the second region of the gate insulating layer is 1/3.
  5. 一种OLED显示器，其特征在于，包括权利要求1-4任意一项所述的阵列基板。An OLED display comprising the array substrate according to any one of claims 1 to 4.
  6. 一种阵列基板的制作方法，其特征在于，包括如下步骤：A method for fabricating an array substrate, comprising the steps of:
    在基板上依次形成栅极和栅极绝缘层，其中，所述栅极绝缘层包括第一区域；Forming a gate and a gate insulating layer sequentially on the substrate, wherein the gate insulating layer includes a first region;
    在所述栅极绝缘层上涂覆第一光阻；Coating a first photoresist on the gate insulating layer;
    提供一多灰阶掩膜版，利用所述多灰阶掩膜版对所述第一光阻进行曝光、显影，以在所述第一光阻正对所述第一区域形成半曝光区域；Providing a multi-gray mask, exposing and developing the first photoresist by using the multi-gray mask to form a half exposure region facing the first region in the first photoresist;
    以所述第一光阻为遮蔽层，对所述栅极绝缘层进行蚀刻，使得所述栅极绝缘层的所述第一区域厚度小于所述栅极绝缘层除所述第一区域之外区域的厚度；Etching the gate insulating layer with the first photoresist as a shielding layer, such that a thickness of the first region of the gate insulating layer is smaller than the gate insulating layer except the first region The thickness of the area;
    剥离所述第一光阻；Peeling the first photoresist;
    在所述栅极绝缘层上方形成金属氧化物半导体层；Forming a metal oxide semiconductor layer over the gate insulating layer;
    在所述金属氧化物半导体层及所述栅极绝缘层上形成源极、漏极及介于二 者之间的开口，所述开口正对所述第一区域，所述金属氧化物半导体层部分露出于所述开口。Forming a source, a drain, and a second on the metal oxide semiconductor layer and the gate insulating layer An opening between the openings facing the first region, the metal oxide semiconductor layer portion being exposed to the opening.
  7. 如权利要求6所述的阵列基板的制作方法，其特征在于，所述对所述栅极绝缘层进行蚀刻步骤中，包括对所述栅极绝缘层进行干法蚀刻，使得所述栅极绝缘层的所述第一区域厚度小于所述栅极绝缘层除所述第一区域外区域的厚度。The method of fabricating an array substrate according to claim 6, wherein the step of etching the gate insulating layer comprises dry etching the gate insulating layer to insulate the gate The thickness of the first region of the layer is less than the thickness of the region of the gate insulating layer other than the first region.
  8. 如权利要求6所述的阵列基板的制作方法，其特征在于，所述在所述栅极绝缘层上方形成金属氧化物半导体层步骤中，包括在所述栅极绝缘层上形成金属氧化物薄膜层；The method of fabricating an array substrate according to claim 6, wherein the step of forming a metal oxide semiconductor layer over the gate insulating layer comprises forming a metal oxide film on the gate insulating layer Floor;
    在所述金属氧化物薄膜层正对所述栅极的区域形成第二光阻；Forming a second photoresist in a region of the metal oxide thin film layer facing the gate;
    以所述第二光阻为遮蔽层，对所述金属氧化物薄膜层进行蚀刻，以在所述第二光阻下方形成所述金属氧化物半导体层；Etching the metal oxide thin film layer with the second photoresist as a shielding layer to form the metal oxide semiconductor layer under the second photoresist;
    剥离所述第二光阻。The second photoresist is stripped.
  9. 如权利要求8所述的阵列基板的制作方法，其特征在于，所述在所述栅极绝缘层上形成金属氧化物薄膜层步骤中，包括通过溅射法在栅极绝缘层上形成所述金属氧化物薄膜层。The method of fabricating an array substrate according to claim 8, wherein the step of forming a metal oxide thin film layer on the gate insulating layer comprises forming the same on a gate insulating layer by a sputtering method Metal oxide film layer.
  10. 如权利要求6所述的阵列基板的制作方法，其特征在于，所述在所述金属氧化物半导体层及所述栅极绝缘层上形成源极、漏极及介于二者之间的开口，所述开口正对所述第一区域，所述金属氧化物半导体层部分露出于所述开口步骤中包括：在所述金属氧化物半导体层及所述栅极绝缘层上形成源漏极薄膜层；The method of fabricating an array substrate according to claim 6, wherein the source, the drain, and an opening therebetween are formed on the metal oxide semiconductor layer and the gate insulating layer The opening is opposite to the first region, and the partially exposing the metal oxide semiconductor layer to the opening step includes: forming a source/drain film on the metal oxide semiconductor layer and the gate insulating layer Floor;
    在所述源漏极薄膜层上形成第三光阻，所述第三光阻上设有镂空区，所述镂空区正对所述第一区域；Forming a third photoresist on the source/drain film layer, the third photoresist is provided with a hollow region, and the hollow region is opposite to the first region;
    以所述第三光阻为遮蔽层，对所述源漏极薄膜层进行蚀刻，以形成所述源极、漏极及位于所述镂空区正下方的开口，所述金属氧化物半导体层露出于所述开口；The source and drain thin film layers are etched by using the third photoresist as a shielding layer to form the source and the drain and an opening directly under the hollow region, and the metal oxide semiconductor layer is exposed. At the opening;
    剥离所述第三光阻。The third photoresist is stripped.
  11. 如权利要求6所述的阵列基板的制作方法，其特征在于，所述多灰阶掩膜版为半色调掩膜版或灰色调掩膜版。 The method of fabricating an array substrate according to claim 6, wherein the multi-gray mask is a halftone mask or a gray mask.
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