WO2018076650A1 - 监控axi总线的方法、装置和计算机可读存储介质 - Google Patents

监控axi总线的方法、装置和计算机可读存储介质 Download PDF

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Publication number
WO2018076650A1
WO2018076650A1 PCT/CN2017/082573 CN2017082573W WO2018076650A1 WO 2018076650 A1 WO2018076650 A1 WO 2018076650A1 CN 2017082573 W CN2017082573 W CN 2017082573W WO 2018076650 A1 WO2018076650 A1 WO 2018076650A1
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Prior art keywords
monitoring
module
axi bus
slave module
command
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French (fr)
Inventor
罗浩
石义军
王文楠
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring

Definitions

  • the present invention relates to an Advanced EXtensible Interface (AXI) bus technology of a System on a Chip (SoC), and more particularly to a method, apparatus and computer readable storage medium for monitoring an AXI bus.
  • AXI Advanced EXtensible Interface
  • SoC System on a Chip
  • the chip is a black box from the outside.
  • the observation and debugging methods are very limited. Unlike software, it can be debugged by modifying the program at any time, or it can be debugged step by step by setting some breakpoints.
  • Field Programmable Gate Array FPGA
  • FPGA Field Programmable Gate Array
  • the SoC system is used to transmit data using the AXI bus, which is a high performance, high bandwidth and low latency on-chip bus.
  • FIG. 1 is a schematic diagram of the structure of an AXI bus interconnect in a typical SoC system.
  • a typical SoC system as shown in Figure 1, three masters (master modules) and four slaves (slave modules) are attached to the AXI bus; for example,
  • the application will have the following scenario: master0 will initiate a write access to slave2, then master2 will read the data previously updated to slave2, but after master2 reads back the data, it is not expected data; because of the AXI bus
  • the fault may be caused by the AXI bus itself dying, response error or other reasons, so in the process of locating the problem, try to protect the site; however, there is currently no monitoring for the AXI bus.
  • the effective method of control for a huge SoC chip, once the problem occurs, the positioning problem is very difficult.
  • embodiments of the present invention are directed to a method apparatus and computer readable storage medium for monitoring an AXI bus.
  • Embodiments of the present invention provide a method for monitoring an AXI bus.
  • the method is applied to a device for monitoring an AXI bus.
  • a monitoring main module is serially connected to a monitoring slave module through a serial protocol interface line.
  • Forming a closed loop composed of the monitoring main module and the monitoring slave module, the method comprising:
  • the monitoring main module receives a serial protocol command sent by the chip to be detected; converts the serial protocol command into a custom serial bit frame command; and sends the customized serial bit frame command to the monitoring slave module ;
  • the monitoring main module receives the status information of the AXI bus sent by the monitoring slave module; wherein the status information of the AXI bus is converted into a universal by the monitoring slave module by the monitoring serial bit frame command
  • the parallel data read/write interface command is obtained by monitoring the AXI bus of the chip to be detected according to the general parallel data read/write interface command;
  • the monitoring main module determines the state of the AXI bus of the chip to be detected according to the state information of the AXI bus.
  • the custom serial bit frame command includes: a starting position, the monitoring main module identification number (IDentification, ID), a read/write indication, the monitoring slave module ID, an offset address, and an ending position.
  • the AXI method further includes:
  • the monitoring slave module completes the configuration of the read/write control information according to the universal parallel data read/write interface command, implements multiplexing of the read/write channel signals of the AXI bus, and completes collection and verification of signals of the AXI bus. , complete the state monitoring and capture setting, startup, recording and clearing of the AXI bus.
  • the read/write control information includes read/write control information of five data channels: aw, w, b, ar, r, and read/write control information of three categories: addr, data, and resp.
  • the monitoring slave modules are serially connected through the serial protocol interface line to form a monitoring slave module having an opening. a queue, the monitoring main module and the monitoring slave module with an opening form a closed loop through the serial protocol interface line;
  • the monitoring main modules are serially connected through the serial protocol interface line to form a monitoring main module queue having an opening.
  • the monitoring main module queue having an opening and the monitoring slave module are serially connected through the serial protocol interface line to form a closed loop;
  • the monitoring main modules are serially connected through the serial protocol interface line to form a monitoring main module having an opening.
  • a queue, the monitoring slave serial connection between the modules through the serial protocol interface line, forming a monitoring slave module queue having an opening, the monitoring main module queue having an opening and the monitoring slave module queue having an opening The serial protocol interface lines are serially connected to form a closed loop.
  • An embodiment of the present invention further provides an apparatus for monitoring an AXI bus, where the apparatus includes: a monitoring main module and a monitoring slave module; wherein the monitoring main module is serially connected to the monitoring slave module through a serial protocol interface line, Forming a closed loop composed of the monitoring main module and the monitoring slave module;
  • the monitoring main module is configured to receive a serial protocol command sent by the chip to be detected, convert the serial protocol command into a custom serial bit frame command, and send the customized serial bit frame command to the Monitoring slave module;
  • the monitoring slave module is configured to convert the custom serial bit frame command into a general parallel data read/write interface command, and perform the AXI bus of the to-be-detected chip according to the universal parallel data read/write interface command. Monitoring, obtaining status information of the AXI bus, and transmitting status information of the AXI bus to the monitoring main module;
  • the monitoring main module is further configured to determine a state of the AXI bus of the chip to be detected according to status information of the AXI bus.
  • the custom serial bit frame command includes: a starting position, the monitoring main module ID, a read/write indication, the monitoring slave module ID, an offset address, and an ending position.
  • the monitoring slave module includes:
  • a conversion unit configured to convert the custom serial bit frame command into a general parallel data read/write interface command
  • the monitoring unit includes:
  • a configuration subunit configured to complete configuration of read and write control information according to the universal parallel data read/write interface command
  • a multiplexing subunit configured to implement multiplexing of read and write channel signals of the AXI bus
  • Collecting and verifying subunits configured to complete collection and verification of signals of the AXI bus
  • the processing subunit is configured to complete setting, starting, recording, and clearing of status monitoring and fetching of the AXI bus.
  • the read/write control information includes read/write control information of five data channels: aw, w, b, ar, r, and read/write control information of three categories: addr, data, and resp.
  • the monitoring slave modules are serially connected through the serial protocol interface line to form an opening.
  • Monitoring a slave module queue, the monitoring master module and the monitoring slave module queue having an opening form a closed loop through the serial protocol interface line;
  • the monitoring main modules are serially connected through the serial protocol interface line to form a monitoring main module queue having an opening.
  • the monitoring main module queue having an opening and the monitoring slave module are serially connected through the serial protocol interface line to form a closed loop;
  • the monitoring main modules are serially connected through the serial protocol interface line to form a monitoring main module having an opening.
  • a queue, the monitoring slave serial connection between the modules through the serial protocol interface line, forming a monitoring slave module queue having an opening, the monitoring main module queue having an opening and the monitoring slave module queue having an opening The serial protocol interface lines are serially connected to form a closed loop.
  • Embodiments of the present invention also provide a computer readable storage medium having stored thereon a computer program, the computer program being executed by a processor to implement the steps of the method for monitoring an AXI bus.
  • the method, device and computer readable storage medium for monitoring an AXI bus convert a serial protocol command into a customized serial bit frame command by monitoring a serial module command sent by the main module to be sent by the chip to be detected.
  • the custom serial bit frame command is sent to the monitoring slave module; the monitoring main module receives the state information of the AXI bus sent from the monitoring module; wherein the state information of the AXI bus is converted by the monitoring slave module from the custom serial bit frame command
  • the universal parallel data read/write interface command is obtained by monitoring the AXI bus of the detection chip according to the general parallel data read/write interface command; the monitoring main module determines the state of the AXI bus of the to-be-detected chip according to the state information of the AXI bus; It realizes the determination of the status of each monitoring point and locates the monitoring point where the problem occurs. This can narrow the problem range. Once it is located within a small range, the difficulty of problem location will be greatly reduced, and the debugging efficiency can be reduced. Increased in levels
  • FIG. 1 is a schematic structural diagram of an AXI bus interconnection in a typical SoC system
  • Embodiment 1 is a flowchart of Embodiment 1 of a method for monitoring an AXI bus according to the present invention
  • Embodiment 1 is a structural diagram of Embodiment 1 of a method for monitoring an AXI bus according to the present invention
  • Embodiment 3a is a flowchart of Embodiment 2 of a method for monitoring an AXI bus according to the present invention
  • 3b is a structural diagram 1 of a second embodiment of a method for monitoring an AXI bus according to the present invention.
  • 3c is a structural diagram 2 of a second embodiment of a method for monitoring an AXI bus according to the present invention.
  • FIG. 4 is a structural diagram of a custom serial bit frame command according to Embodiment 2 of a method for monitoring an AXI bus according to the present invention
  • FIG. 5 is a structural diagram of a monitoring slave module according to Embodiment 2 of a method for monitoring an AXI bus according to the present invention
  • FIG. 6 is a working state diagram of a monitoring unit in a monitoring slave module according to Embodiment 2 of the method for monitoring an AXI bus according to the present invention
  • FIG. 7 is a flowchart of a configuration of monitoring a single-trigger of a matching item by monitoring a monitoring unit in an ar channel data of a monitoring unit in the module according to the second embodiment of the present invention
  • FIG. 8 is a flowchart of a configuration of monitoring a plurality of triggers in which a monitoring unit in a module monitors w channel data and sets data as a matching item according to a method for monitoring an AXI bus according to the second embodiment of the present invention
  • FIG. 9 is a flow chart of the configuration of monitoring the A channel of the AXI bus according to the second embodiment of the method for monitoring the sampling channel of the monitoring unit in the module, and setting the rep to the multiple trigger of the matching item;
  • FIG. 10 is a schematic structural diagram of an apparatus for monitoring an AXI bus according to the present invention.
  • each device connected to the SoC system communicates through the same interface protocol; therefore, the data is read and written. Divide into multiple stages, set a monitoring point for each stage, and narrow the scope of the problem, so that once positioned within a small range, the difficulty of problem location will be greatly reduced.
  • the process of reading and writing operations can be divided into two phases: a write operation of master0 and a read operation of master2.
  • the write operation of master0 can be further divided into master0 to AXI bus, AXI bus to slave2;
  • master2 read operation can be divided into master2 to AXI bus, AXI bus to slave2; if corresponding to these four stages, each In the stage, a monitoring point is set to further narrow the problem range. Once it is located within a small range, the difficulty of problem location will be greatly reduced.
  • FIG. 2A is a flowchart of Embodiment 1 of a method for monitoring an AXI bus according to the present invention
  • FIG. 2b is a structural diagram of Embodiment 1 of a method for monitoring an AXI bus according to the present invention.
  • the AXI bus is monitored according to an embodiment of the present invention.
  • the method is applied to a device for monitoring an AXI bus.
  • a monitoring main module (mon_master) is serially connected with a monitoring slave module (mon_slaver) through a serial protocol interface line, and is formed by a monitoring main module (mon_master) and monitoring.
  • the monitoring slave module (mon_slaver) is When there are two less, the monitoring slave modules (mon_slaver) are serially connected through the serial protocol interface line to form a monitoring slave module queue with an opening, the monitoring master module (mon_master) and the monitoring slave module (mon_slaver) queue having an opening.
  • the serial protocol interface line forms a closed loop;
  • the monitoring main module (mon_master) is at least two and the monitoring slave module (mon_slaver) is one, the monitoring main module (mon_master) is serially connected through the serial protocol interface line to form a monitoring main module (mon_master) having an opening.
  • a queue, a monitoring main module queue (mon_master) having an opening and a monitoring slave module (mon_slaver) are serially connected through a serial protocol interface line to form a closed loop;
  • the monitoring main module (mon_master) is at least two and the monitoring slave module (mon_slaver) is at least two
  • the monitoring main module (mon_master) is serially connected through a serial protocol interface line to form a monitoring main module having an opening ( Mon_master) queue, monitor slave module (mon_slaver) serial connection through serial protocol interface line, form monitoring slave module (mon_slaver) queue with opening, monitoring main module queue with opening and monitoring slave module with opening (mon_slaver
  • the queues are serially connected through a serial protocol interface line to form a closed loop.
  • the serial protocol interface line can be customized, or it can be a protocol that has been standardized, such as the Universal Asynchronous Receiver/Transmitter (UART) protocol.
  • UART Universal Asynchronous Receiver/Transmitter
  • the reason for using the serial protocol interface line is 3 Points: First, as a monitoring, the protocol is simple, too complicated interface is easy to make mistakes; second, the monitoring traffic demand is low, the low-speed protocol is sufficient; third, the number of interface signal lines is small, because the monitoring nodes are distributed throughout the chip, If the number of interface signal lines is too large, the entire monitoring interface will be worn around the entire chip, which will increase the difficulty of the back end wiring.
  • each monitoring main module (mon_master) and the function of each monitoring slave module (mon_slaver) are the same, in this embodiment, a monitoring main module (mon_master) and a monitoring slave module (mon_slaver) are used as an example. .
  • the method for monitoring an AXI bus includes the following steps:
  • Step 101 The monitoring main module receives a serial protocol command sent by the chip to be detected, converts the serial protocol command into a custom serial bit frame command, and sends the customized serial bit frame command to the Monitor the slave module.
  • the monitoring main module (mon_master) is checked with a simple serial protocol interface line.
  • the test chip is connected, and receives the serial protocol command sent by the chip to be detected;
  • the monitoring main module (mon_master) converts the serial protocol command into a custom serial bit frame command, that is, realizes “the external debugging interface of the chip to be detected to the internal Customize the conversion of the serial line interface”; after that, the custom serial bit frame command is sent to the monitor slave module (mon_slaver).
  • Step 102 The monitoring main module receives state information of the AXI bus sent by the monitoring slave module, where the state information of the AXI bus is the custom serial bit frame command by the monitoring slave module Converting to a general parallel data read/write interface command, and monitoring the AXI bus of the chip to be detected according to the general parallel data read/write interface command.
  • the monitoring main module receives the status information of the AXI bus sent from the monitoring module (mon_slaver), wherein the status information of the AXI bus is converted into a common parallel data read/write interface command by the monitoring slave module from the custom serial bit frame command. According to the general parallel data read/write interface command, the AXI bus of the detection chip is monitored.
  • the monitoring slave module (mon_slaver) first converts the custom serial bit frame command received through the serial protocol interface line into a general parallel data read/write interface command; and then, according to the general parallel data read
  • the write interface command monitors the AXI bus of the detection chip to obtain status information of the AXI bus; after that, the status information of the AXI bus is sent to the monitoring main module (mon_master).
  • Step 103 The monitoring main module determines a state of the AXI bus of the chip to be detected according to status information of the AXI bus.
  • the monitoring main module determines the state of the AXI bus of the chip to be detected according to the state information of the AXI bus; that is, determines the state of each monitoring point, and locates the monitoring point where the problem occurs, so that the problem range can be narrowed once positioned. Within a small range, the difficulty of problem location will be greatly reduced, and the debugging efficiency can be increased by several orders of magnitude.
  • the method for monitoring an AXI bus provided by an embodiment of the present invention, by monitoring a serial module command sent by a main module to be detected by a chip to be detected, converting a serial protocol command into a custom serial bit frame command, and customizing the serial bit frame command Sending to the monitoring slave module; the monitoring master module receives the state information of the AXI bus sent from the monitoring module; wherein the state information of the AXI bus is converted into a general parallel data read/write interface by the monitoring slave module from the custom serial bit frame command Command, root According to the general parallel data read/write interface command, the AXI bus of the detection chip is monitored; the monitoring main module determines the state of the AXI bus of the chip to be detected according to the state information of the AXI bus; and realizes the state of each monitoring point. Determine, locate the monitoring point where the problem occurs, so that the problem can be narrowed down. Once positioned within a small range, the difficulty of problem location will be greatly reduced, and the debugging efficiency can be increased by several levels.
  • FIG. 3A is a flow chart of a second embodiment of a method for monitoring an AXI bus according to the present invention
  • FIG. 3b is a structural diagram of a second embodiment of a method for monitoring an AXI bus according to the present invention. As shown in FIG. 3b, the monitoring AXI bus is provided in the embodiment of the present invention. The method is applied to a device for monitoring an AXI bus.
  • a monitoring main module passes through a custom serial interface line and a monitoring slave module formed by a plurality of monitoring slave modules (mon_slavers) ( Mon_slaver) Queue serial connection, forming a closed loop consisting of a monitoring master module (mon_master) and multiple monitoring slave modules (mon_slaver).
  • the method includes the following steps:
  • Step 201 The monitoring main module receives a serial protocol command sent by the chip to be detected.
  • the monitoring main module can be connected to the chip to be tested by the simple serial protocol interface line to receive the serial protocol command (WRITE/READ) sent by the input/output (I/O) port of the chip to be detected.
  • WRITE/READ serial protocol command
  • I/O input/output
  • the monitoring main module (mon_master) can be implemented by two;
  • FIG. 3c is a structural diagram 2 of the second embodiment of the method for monitoring the AXI bus of the present invention, as shown in FIG. 3c, the first monitoring The main module (mon_master0) and the second monitoring main module (mon_master1) are serially connected through a serial protocol interface line to form a monitoring main module (mon_master) queue with an opening, and the monitoring slave module (mon_slaver) is passed through a serial protocol.
  • the interface lines are serially connected to form a monitoring slave module (mon_slaver) queue having an opening, the monitoring main module queue having an opening and the monitoring slave module (mon_slaver) queue having an opening are serially connected through a serial protocol interface line to form a closed loop .
  • the first monitoring main module (mon_master0) is connected to the chip to be tested using a simple serial protocol interface line
  • the second monitoring main module (mon_master1) is connected by a simple serial protocol.
  • the port line is connected to a Central Processing Unit (CPU) system; the functions of the two monitoring main modules are the same, and the received commands are converted into internal serial format commands, the difference being that one receives the chip to be tested.
  • Serial protocol command a command that receives a CPU system.
  • the second monitoring main module (mon_master1) is connected to the CPU system through a serial protocol interface line.
  • the bus monitoring operation can be initiated by means of the CPU; the advantage of this structure is its convenience, one
  • the CPU debugger is enough to complete the whole debugging.
  • the debugger does not need to switch back and forth between the AXI bus monitoring interface and the CPU debugging interface.
  • the CPU debugging system can also perform some auxiliary printing or writing small programs to extract the monitored data. And analysis.
  • Step 202 The monitoring main module converts the serial protocol command into a custom serial bit frame command.
  • the monitoring main module stores the serial protocol command into the internal buffer (buffer), converts the serial protocol command into a custom serial bit frame command according to the serial bit protocol, and performs the following custom serial bit frame command. Specific instructions.
  • FIG. 4 is a structural diagram of a custom serial bit frame command according to Embodiment 2 of the method for monitoring an AXI bus of the present invention. As shown in FIG. 4, the structure length of the entire custom serial bit frame command is 32; Position, monitoring main module ID, read/write indication, monitoring slave module ID, offset address, end position;
  • Start_bit(1) The 1-bit start bit indicates the start position of the frame structure. In the idle state, the serial bit line is at a high level, and the first low level indicates a start position;
  • MID(1) 1bit master ID, indicating from which master, 1 bit supports up to 2 monitoring main modules (mon_master) (changes the bit width of the MID field in the frame structure, and the number of monitoring main modules (mon_master) can be supported. The maximum value also changes. If only one monitoring main module (mon_master) is used, the domain can be deleted);
  • Wr/rd(1) 1 bit read/write indication, 1 write, 0 read;
  • SID(5) 5bit slave ID, which is decoded from multiple monitoring and slave modules (mon_slave) nodes.
  • the number of monitoring slave modules (mon_slave) is selected according to the actual application, and can support up to 32 monitoring slave modules (mon_slave) (changing the bit width of the node address field in the frame structure, the maximum value that can be supported by the monitoring slave module (mon_slave) also changes);
  • Offset_addr(8) 8-bit offset address, which is decoded from multiple offset addresses of the selected monitor (mon_slave) node.
  • the number of offset addresses is selected according to the actual application and can support up to 256 monitors.
  • Slave module (mon_slave) (change the bit width of the offset address field in the frame structure, the maximum value that can be supported by the number of offset address registers also changes);
  • Data(16) The data field of the serial bit line frame structure, which can be customized according to the actual application;
  • Stop_bit(1) The 1bit end bit indicates the end position of the frame structure, the stop bit is high, the next bit of the end bit starts, and the serial bit line enters the idle state.
  • Step 203 The monitoring main module sends the custom serial bit frame command to the monitoring slave module.
  • the monitoring master module (mon_master) sends a custom serial bit frame command to the monitoring slave module (mon_slaver) via the serial bit line.
  • Step 204 The monitoring slave module converts the custom serial bit frame command into a general parallel data read/write interface command.
  • FIG. 5 is a structural diagram of a monitoring slave module according to Embodiment 2 of the method for monitoring an AXI bus according to the present invention.
  • the monitoring slave module (mon_slaver) includes a conversion unit (s2p_bridge) and a monitoring unit (amti);
  • the conversion unit (s2p_bridge) in (mon_slaver) converts the custom serial bit frame command into a general parallel data read/write interface command and sends it to the monitoring unit (amti) in the monitoring slave module (mon_slaver), the universal parallel
  • the data read/write interface command can be a read/write control signal interface command, which can be an address line or a data line interface command, and can be a static random access memory (SRAM) interface command, or can be similar to an SRAM interface command. Other interface commands.
  • each monitoring slave module receives the custom serial bit frame command at the same time.
  • the custom serial bit frame command will be passed to the next node intact.
  • Each monitoring slave module (mon_slaver) is set with a unique SID, and the conversion unit (s2p_bridge) will receive the serial-to-parallel conversion.
  • the SID is matched with the SID assigned to it. The matching will save the custom serial bit frame command at the local node and send it to the monitoring unit (amti) in the monitoring slave module (mon_slaver) for its use.
  • the monitoring slave module (mon_slaver) can be time-multiplexed; therefore, in the embodiment of the present invention, only one monitoring slave module (mon_slaver)
  • the specific composition of the monitoring unit (amti) and the specific functions are explained.
  • Step 205 The monitoring slave module monitors the AXI bus of the chip to be detected according to the general parallel data read/write interface command, and obtains state information of the AXI bus.
  • the monitoring unit (amti) in the monitoring slave module (mon_slaver) completes the configuration of the read/write control information according to the general parallel data read/write interface command, realizes the multiplexing of the read/write channel signals of the AXI bus, completes the signal collection of the AXI bus, and Verification, complete the status monitoring and capture setting, startup, recording and clearing of the AXI bus.
  • Step 206 The monitoring slave module sends status information of the AXI bus to the monitoring main module.
  • Step 207 The monitoring main module determines the state of the AXI bus of the chip to be detected according to the state information of the AXI bus.
  • FIG. 6 is a working state diagram of a monitoring unit in a monitoring slave module according to Embodiment 2 of the method for monitoring an AXI bus according to the present invention.
  • the configuration subunit (amti_cfg) in the monitoring unit (amti) is configured as The configuration of the read/write control information is completed according to the general parallel data read/write interface command;
  • the multiplexing subunit (amti_imux) in the monitoring unit (amti) is configured to implement multiplexing of the read/write channel signals of the AXI bus;
  • the collection and verification subunit (amti_check) is configured to complete the collection and verification of the AXI bus signal;
  • the processing unit (amti_sample) in the monitoring unit (amti) is configured to complete the status monitoring and capture of the AXI bus. Settings, startup, logging, and cleanup.
  • the monitoring unit configures and reads internal registers through the SRAM interface to perform status monitoring and data capture of the AXI bus.
  • the read/write control information includes read/write control information of five data channels: aw, w, b, ar, r, and read/write control information of three categories: addr, data, and resp.
  • Each class can be set with different matching switches.
  • the address channel has addr, id, len, size, and burst information.
  • an independent matching switch match_en is set for each information of addr, id, len, size, and burst.
  • the addr match switch when the addr match switch is turned on, the addr information will be used as a match. Before the sample is sampled, the expected value of the addr entry must be set. Once the expected value appears on the address channel, the capture is successful and the capture success status is recorded. At the same time, the monitoring unit (amti) saves the id, len, size, and burst information corresponding to the address channel; the combination of other matching switches can be analogized.
  • the data channel has data, id, and wstrb information.
  • an independent matching switch match_en is set for each piece of information of data, id, and wstrb. These matching switches can be turned on and off independently, or can be turned on and off in any combination. It works like the address channel above.
  • the response channel has resp and id information.
  • an independent matching switch match_en is set for each piece of information of resp and id. These matching switches can be turned on and off independently, and can be turned on and off in any combination.
  • the address channel is similar.
  • the combination order of address, data, and response can also be set.
  • the address channel matching supports triggering the data channel first.
  • the data channel matching supports the first trigger address channel.
  • the response channel matching supports the first trigger address or data channel.
  • the single trigger records the results on the first match and multiple triggers to record the latest matching results.
  • the following is to sample the aw channel data, set addr as a match, single-shot as an example, to sample w channel data, set data as a match, multiple triggers as an example, to sample w channel response, set resp as a match, more
  • the sub-trigger is an example, and the configuration flow of the related registers is respectively given.
  • FIG. 7 is a flowchart of a configuration of monitoring a single-trigger of a monitoring unit in a monitoring unit sampling ar channel data and setting addr as a matching item according to a second embodiment of the method for monitoring an AXI bus according to the present invention, as shown in FIG. 7 (each of the following processes)
  • the configuration and reading of the registers need to monitor the main module to initiate a phase
  • the command should be implemented), the process includes:
  • Step 301 Configure the axi_dbg_en switch (8'h00) to be 1.
  • Step 302 Configure the axi_rchn_sta_en switch (8'h01) to be 1.
  • step 303 the configuration a_single_trig_en (8'h34) is 1.
  • turn on the one-shot switch (support single mode, multiple trigger mode).
  • step 304 the configuration data_trig_off (8'h20) is 0.
  • Step 305 Configure id_match_adr_sel (8'h20) to be 2'b00.
  • id_match_adr_sel configures id_match_adr_sel to select the addr channel (id register for addr, data, res channel multiplexing).
  • Step 306 configuring a_time_catch_en (8'h34) to be 1.
  • step 307 the addr_match_en switch (8'h20) is turned on.
  • Step 308 configuring a sampling matching value addr_value (8'h21, 8'h22).
  • the value to be matched is written in the addr register.
  • Step 309 Configure a sampling matching mask value addr_mask (8'h23, 8'h24).
  • the corresponding addr_mask value is written according to the addr to be matched (supporting addr exact match and interval matching, by configuring addr_mask).
  • Step 310 Clear a_catch_ok (8'h33).
  • the capture completion flag is cleared, and once the capture is successful, the flag will be set again.
  • Step 311 Read the a_catch_ok state (8'h33).
  • the a_catch_ok status information is read.
  • Step 312 Determine whether a_catch_ok is equal to 1'b1.
  • step 313 determining whether the loop query grab success flag is set, if it has not been set, Indicates that there is no matching addr access, and returns to step 311; if the flag is set, step 313 is performed.
  • Step 313 Read related data information.
  • the relevant grab information (id, len, size, burst) is read.
  • FIG. 8 is a flow chart of the configuration of monitoring the AXI bus in the second embodiment of the method for monitoring the AXI bus in the monitoring unit, and sampling the w channel data in the monitoring unit, and setting data as a matching item, as shown in FIG. 8 (for each of the following processes)
  • the configuration and reading of the registers need to monitor the main module to initiate a corresponding command to achieve), the process includes:
  • Step 401 Configure the axi_dbg_en switch (8'h00) to be 1.
  • Step 402 Configure the axi_wchn_sta_en switch (8'h02) to be 1.
  • Step 403 Configure id_match_adr_sel (8'h20) to be 2'b01.
  • step 404 the data_match_en switch (8'h20) is turned on.
  • Step 405 Configure a sampling matching value data_value (8'h2b-8'h32).
  • the data register writes the value to be matched.
  • Step 406 clearing a_catch_ok (8'h33).
  • the capture completion flag is cleared, and once the capture is successful, the flag will be set again.
  • Step 407 Read the a_catch_ok state (8'h33).
  • the a_catch_ok status information is read.
  • Step 408 Determine whether a_catch_ok is equal to 1'b1.
  • step 409 determining whether the loop query grab success flag is set, if it has not been set, Indicates that there is no matching addr access, and returns to step 407; if the flag is set, step 409 is performed.
  • Step 409 Read related data information (the first few of id, strb, and burst).
  • FIG. 9 is a flow chart of the configuration of monitoring the AXI bus in the second embodiment of the present invention by monitoring the sampling channel w channel response of the monitoring unit and setting the rep to match the multiple triggers, as shown in FIG. 9 (in the following process
  • the configuration and reading of the registers need to monitor the main module to initiate a corresponding command to achieve) includes:
  • Step 501 Configure the axi_dbg_en switch (8'h00) to be 1.
  • Step 502 Configure the axi_wchn_sta_en switch (8'h02) to be 1.
  • turn on the axi_wchn_sta_en switch that is, the default mode is multiple triggers.
  • Step 503 Configure id_match_adr_sel (8'h20) to be 2'b10.
  • step 504 the data_match_en switch (8'h20) is turned on.
  • Step 505 Configure a sample matching value resp_value (8'h29).
  • the value to be matched is written in the resp register.
  • Step 506 clearing a_catch_ok (8'h33).
  • the capture completion flag is cleared, and once the capture is successful, the flag will be set again.
  • Step 507 reading the a_catch_ok state (8'h33).
  • the a_catch_ok status information is read.
  • Step 508 Determine whether a_catch_ok is equal to 1'b1.
  • step 509 determining whether the loop query grab success flag is set, if it has not been set, Indicates that there is no matching addr access, and returns to step 507; if the flag is set, step 509 is performed.
  • Step 509 Read related data information (id).
  • the related data information (id) is read.
  • the monitoring slave module sends the status information of the AXI bus to the monitoring main module after reading the related data information (id).
  • the monitoring unit (amti) in the monitoring module (mon_slaver) sends the status information (related data information) of the monitored and captured AXI bus to the monitoring main module (mon_master) through the custom serial interface.
  • the monitoring main module determines the state of the AXI bus of the chip to be detected according to the state information of the AXI bus.
  • the monitoring main module determines the state of the AXI bus of the chip to be detected according to the state information analysis of the AXI bus, locates the state problem, or the staff analyzes the state information of the AXI bus received by the monitoring main module (mon_master).
  • the status of the AXI bus of the chip to be detected is located, and the status problem is located; for example, the data of the storage address of the chip module to be detected is accidentally rewritten, and the ID of the address can be accurately rewritten by grasping and rewriting the ID of the address, and then the center of analysis is analyzed. Putting it into the rewriting source, you can quickly find out the reason for rewriting, greatly reducing the difficulty of problem location, and debugging efficiency can be technically increased.
  • the method for monitoring an AXI bus receives a serial protocol command sent by a chip to be detected by a monitoring main module; the monitoring main module converts the serial protocol command into a custom serial bit frame command; and monitors the main module Transmitting the custom serial bit frame command to the monitoring slave module; the monitoring slave module converting the custom serial bit frame command into a universal parallel data read/write interface command; monitoring the slave module according to the universal The parallel data read/write interface command monitors the AXI bus of the chip to be detected to obtain status information of the AXI bus; The slave module sends the state information of the AXI bus to the monitoring main module; the monitoring main module determines the state of the AXI bus of the chip to be detected according to the state information of the AXI bus; and realizes the state of each monitoring point Make a determination and locate the monitoring point where the problem occurs. This will narrow the problem. Once it is located within a small range, the difficulty of problem location will be greatly reduced, and the debugging efficiency can be increased by several
  • an apparatus 010 for monitoring an AXI bus according to an embodiment of the present invention includes: a monitoring main module 101 and a monitoring slave module 102;
  • the monitoring main module 101 is serially connected to the monitoring slave module 102 through a serial protocol interface line to form a closed loop composed of the monitoring main module 101 and the monitoring slave module 102;
  • the monitoring main module 101 is configured to receive a serial protocol command sent by the chip to be detected, convert the serial protocol command into a custom serial bit frame command, and send the customized serial bit frame command to the The monitoring slave module 102;
  • the monitoring slave module 102 is configured to convert the custom serial bit frame command into a general parallel data read/write interface command, and the AXI bus of the to-be-detected chip according to the universal parallel data read/write interface command Monitoring, obtaining status information of the AXI bus, and transmitting status information of the AXI bus to the monitoring main module 101;
  • the monitoring main module 101 is further configured to determine a state of the AXI bus of the chip to be detected according to status information of the AXI bus.
  • the custom serial bit frame command includes: a starting position, the monitoring main module ID, a read/write indication, the monitoring slave module ID, an offset address, and an ending position.
  • the monitoring slave module 102 includes: a converting unit 1021 and a monitoring unit 1022; wherein
  • the converting unit 1021 is configured to convert the custom serial bit frame command into a general parallel data read/write interface command
  • the monitoring unit 1022 includes: a configuration subunit 10221, a multiplexing subunit 10222, a collection and verification subunit 10223, and a processing subunit 10224;
  • the configuration subunit 10221 is configured to read and write an interface command according to the universal parallel data. Complete the configuration of the read and write control information;
  • the multiplexing subunit 10222 is configured to implement multiplexing of read and write channel signals of the AXI bus;
  • the collection and verification sub-unit 10223 is configured to complete collection and verification of signals of the AXI bus;
  • the processing sub-unit 10224 is configured to complete setting, starting, recording, and clearing of status monitoring and fetching of the AXI bus.
  • the read and write control information includes read and write control information of five data channels: aw, w, b, ar, r, and read and write control information of three categories: addr, data, and resp.
  • the monitoring slave modules 102 are serially connected through the serial protocol interface line. a monitoring slave module 102 having an opening, the monitoring main module 101 and the monitoring slave module 102 having an opening forming a closed loop through the serial protocol interface line;
  • the monitoring main modules 101 are serially connected through the serial protocol interface line to form a monitoring main module 101 having an opening. a queue, the monitoring main module 101 having an opening and the monitoring slave module 102 are serially connected through the serial protocol interface line to form a closed loop;
  • the monitoring main module 101 is at least two and the monitoring slave module 102 is at least two, the monitoring main modules 101 are serially connected through the serial protocol interface line to form a monitoring main with an opening.
  • the modules 101 are queued, and the monitoring slave modules 102 are serially connected through the serial protocol interface line to form a monitoring slave module 102 queue having an opening, the monitoring main module 101 having an opening and the opening having the opening.
  • the monitoring slave module 102 is serially connected through the serial protocol interface line to form a closed loop.
  • the device in this embodiment may be configured to perform the technical solution of the foregoing method embodiment, and the implementation principle and the technical effect are similar, and details are not described herein again.
  • the monitoring main module 101, the monitoring slave module 102, the converting unit 1021, the monitoring unit 1022, the configuration subunit 10221, the multiplexing subunit 10222, the collecting and verifying subunit 10223, and the processing subunit 10224 may all be Processor located in device 010 that monitors the AXI bus Such as CPU, Microprocessor Unit (MPU), Digital Signal Processor (DSP) or FPGA implementation.
  • MPU Microprocessor Unit
  • DSP Digital Signal Processor
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • an embodiment of the present invention further provides a computer readable storage medium, where the computer program is stored, and when the computer program is executed by the processor, the steps of the method for monitoring the AXI bus in the embodiment of the present invention are implemented.
  • the monitoring main module receives the serial protocol command sent by the chip to be detected, converts the serial protocol command into a custom serial bit frame command, and sends the customized serial bit frame command to the monitoring terminal.
  • the monitoring main module receives the status information of the AXI bus sent from the monitoring module; wherein the status information of the AXI bus is converted into a general parallel data read/write interface command by the monitoring slave module, according to the general purpose
  • the parallel data read/write interface command is obtained by monitoring the AXI bus of the detection chip; the monitoring main module determines the state of the AXI bus of the chip to be detected according to the state information of the AXI bus; and realizes determining the state of each monitoring point, Positioning the monitoring point where the problem occurs, this can narrow the problem. Once it is located within a small range, the difficulty of problem location will be greatly reduced, and the debugging efficiency can be increased by several levels.

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Abstract

一种监控AXI总线的方法，应用于监控AXI总线的装置（010），在监控AXI总线的装置（010）中，监控主模块（101）通过串行协议接口线与监控从模块（102）串行连接，形成由监控主模块（101）与监控从模块（102）组成的闭合环路，该方法包括：监控主模块接收待检测芯片发送的串行协议命令（201）；将串行协议命令转换成自定义串行比特帧命令（202）；将自定义串行比特帧命令发送至监控从模块（203）；监控从模块将自定义串行比特帧命令转换成通用的并行数据读写接口命令（204）；根据通用的并行数据读写接口命令对待检测芯片的AXI总线进行监控，得到AXI总线的状态信息（205）；将AXI总线的状态信息发送至监控主模块（206）；监控主模块根据AXI总线的状态信息确定出待检测芯片的AXI总线的状态（207）。同时还包括一种监控AXI总线的装置（010）和计算机可读存储介质。

Description

监控AXI总线的方法、装置和计算机可读存储介质
相关申请的交叉引用
本申请基于申请号为201610932607.2、申请日为2016年10月31日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及片上系统(System on a Chip，SoC)的高级可扩展接口(Advanced eXtensible Interface，AXI)总线技术，尤其涉及一种监控AXI总线的方法、装置和计算机可读存储介质。
背景技术
芯片一旦生产出来，从外部来看，就是一个黑盒，观测和调试手段非常有限，不像软件，可以通过随时修改程序进行调试，或者可以通过设置一些断点来分步调试；而对于现场可编程门阵列(Field Programmable Gate Array，FPGA)，也可以通过抓波形软件来实时抓取一些有用的波形来观察FPGA内部的工作状态，并且需要抓取的波形也是通过编程来实现的；目前芯片往往采用的是SoC系统，利用AXI总线进行数据传输，AXI总线是一种高性能、高带宽及低延迟的芯片内总线。
图1为典型的SoC系统中AXI总线互联的结构示意图，在如图1所示的典型SoC系统中，AXI总线上挂有3个master(主模块)以及4个slave(从模块)；例如，应用中会出现如下场景：master0要对slave2发起一次写访问，然后master2再将前面更新到slave2中的数据读走，但master2读回数据以后，发现并不是预期的数据；因为在采用AXI总线的SoC系统中，故障有可能是AXI总线本身挂死、响应错误或者其他原因，所以在定位问题的过程中，尽量要保护现场；但是，目前没有一种针对AXI总线进行监 控的有效方法，对于功能庞大的SoC芯片，一旦出现问题，定位问题的难度很大。
发明内容
有鉴于此，本发明实施例期望提供一种监控AXI总线的方法装置和计算机可读存储介质。
本发明实施例的技术方案是这样实现的：
本发明实施例提供一种监控AXI总线的方法，所述方法应用于监控AXI总线的装置，在所述监控AXI总线的装置中，监控主模块通过串行协议接口线与监控从模块串行连接，形成由所述监控主模块与所述监控从模块组成的闭合环路，所述方法包括：
所述监控主模块接收待检测芯片发送的串行协议命令；将所述串行协议命令转换成自定义串行比特帧命令；将所述自定义串行比特帧命令发送至所述监控从模块；
所述监控主模块接收所述监控从模块发送的所述AXI总线的状态信息；其中，所述AXI总线的状态信息是通过所述监控从模块将所述自定义串行比特帧命令转换成通用的并行数据读写接口命令，根据所述通用的并行数据读写接口命令对所述待检测芯片的AXI总线进行监控得到的；
所述监控主模块根据所述AXI总线的状态信息确定出所述待检测芯片的AXI总线的状态。
上述方案中，所述自定义串行比特帧命令包括：起始位置、所述监控主模块标识号(IDentification，ID)、读写指示、所述监控从模块ID、偏移地址、结束位置。
上述方案中，所述AXI方法还包括：
所述监控从模块根据所述通用的并行数据读写接口命令完成读写控制信息的配置，实现所述AXI总线的读写通道信号的复用，完成所述AXI总线的信号的收集和校验，完成所述AXI总线的状态监控和抓取的设置、启动、记录和清除。
上述方案中，所述读写控制信息包括：aw、w、b、ar、r五个数据通道的读写控制信息及addr、data、resp三个类别的读写控制信息。
上述方案中，若所述监控主模块为一个、所述监控从模块为至少两个时，所述监控从模块之间通过所述串行协议接口线串行连接，形成具有开口的监控从模块队列，所述监控主模块与所述具有开口的监控从模块队列通过所述串行协议接口线形成闭合环路；
或者，若所述监控主模块为至少两个、所述监控从模块为一个时，所述监控主模块之间通过所述串行协议接口线串行连接，形成具有开口的监控主模块队列，所述具有开口的监控主模块队列与所述监控从模块通过所述串行协议接口线串行连接，形成闭合环路；
或者，若所述监控主模块为至少两个、所述监控从模块为至少两个时，所述监控主模块之间通过所述串行协议接口线串行连接，形成具有开口的监控主模块队列，所述监控从模块之间通过所述串行协议接口线串行连接，形成具有开口的监控从模块队列，所述具有开口的监控主模块队列与所述具有开口的监控从模块队列通过所述串行协议接口线串行连接，形成闭合环路。
本发明实施例还提供一种监控AXI总线的装置，所述装置包括：监控主模块及监控从模块；其中，所述监控主模块通过串行协议接口线与所述监控从模块串行连接，形成由所述监控主模块与所述监控从模块组成的闭合环路；
所述监控主模块，配置为接收待检测芯片发送的串行协议命令，将所述串行协议命令转换成自定义串行比特帧命令，将所述自定义串行比特帧命令发送至所述监控从模块；
所述监控从模块，配置为将所述自定义串行比特帧命令转换成通用的并行数据读写接口命令，根据所述通用的并行数据读写接口命令对所述待检测芯片的AXI总线进行监控，得到所述AXI总线的状态信息，将所述AXI总线的状态信息发送至所述监控主模块；
所述监控主模块，还配置为根据所述AXI总线的状态信息确定出所述待检测芯片的AXI总线的状态。
上述方案中，所述自定义串行比特帧命令包括：起始位置、所述监控主模块ID、读写指示、所述监控从模块ID、偏移地址、结束位置。
上述方案中，所述监控从模块，包括：
转换单元，配置为将所述自定义串行比特帧命令转换成通用的并行数据读写接口命令；
监控单元；所述监控单元包括：
配置子单元，配置为根据所述通用的并行数据读写接口命令完成读写控制信息的配置；
复用子单元，配置为实现所述AXI总线的读写通道信号的复用；
收集和校验子单元，配置为完成所述AXI总线的信号的收集和校验；
处理子单元，配置为完成所述AXI总线的状态监控和抓取的设置、启动、记录和清除。
上述方案中，所述读写控制信息包括：aw、w、b、ar、r五个数据通道的读写控制信息及addr、data、resp三个类别的读写控制信息。
上述方案中，若所述监控主模块为一个、所述监控从模块为两个或两个以上时，所述监控从模块之间通过所述串行协议接口线串行连接，形成具有开口的监控从模块队列，所述监控主模块与所述具有开口的监控从模块队列通过所述串行协议接口线形成闭合环路；
或者，若所述监控主模块为至少两个、所述监控从模块为一个时，所述监控主模块之间通过所述串行协议接口线串行连接，形成具有开口的监控主模块队列，所述具有开口的监控主模块队列与所述监控从模块通过所述串行协议接口线串行连接，形成闭合环路；
或者，若所述监控主模块为至少两个、所述监控从模块为至少两个时，所述监控主模块之间通过所述串行协议接口线串行连接，形成具有开口的监控主模块队列，所述监控从模块之间通过所述串行协议接口线串行连接，形成具有开口的监控从模块队列，所述具有开口的监控主模块队列与所述具有开口的监控从模块队列通过所述串行协议接口线串行连接，形成闭合环路。
本发明实施例还提供了一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现上述监控AXI总线的方法的步骤。
本发明实施例提供的监控AXI总线的方法、装置和计算机可读存储介质，通过监控主模块接收待检测芯片发送的串行协议命令，将串行协议命令转换成自定义串行比特帧命令，将自定义串行比特帧命令发送至监控从模块；监控主模块接收监控从模块发送的AXI总线的状态信息；其中，AXI总线的状态信息是通过监控从模块将自定义串行比特帧命令转换成通用的并行数据读写接口命令，根据通用的并行数据读写接口命令对待检测芯片的AXI总线进行监控得到的；监控主模块根据AXI总线的状态信息确定出待检测芯片的AXI总线的状态；实现了对每个监控点的状态进行确定，定位到出现问题的监控点，这样可以将出问题范围缩小，一旦定位到一个小的范围以内，问题定位的难度将会极大降低，调试效率可以呈级数级增长。
附图说明
图1为典型的SoC系统中AXI总线互联的结构示意图；
图2a为本发明监控AXI总线的方法实施例一的流程图；
图2b为本发明监控AXI总线的方法实施例一的结构图；
图3a为本发明监控AXI总线的方法实施例二的流程图；
图3b为本发明监控AXI总线的方法实施例二的结构图一；
图3c为本发明监控AXI总线的方法实施例二的结构图二；
图4为本发明监控AXI总线的方法实施例二的自定义串行比特帧命令的结构图；
图5为本发明监控AXI总线的方法实施例二的监控从模块的结构图；
图6为本发明监控AXI总线的方法实施例二的监控从模块中的监控单元的工作状态图；
图7为本发明监控AXI总线的方法实施例二的监控从模块中的监控单元采样ar通道数据、设置addr为匹配项的单次触发的配置流程图；
图8为本发明监控AXI总线的方法实施例二的监控从模块中的监控单元采样w通道数据、设置data为匹配项的多次触发的配置流程图；
图9为本发明监控AXI总线的方法实施例二的监控从模块中的监控单元采样w通道响应、设置resp为匹配项的多次触发的配置流程图；
图10为本发明监控AXI总线的装置实施例的结构示意图。
具体实施方式
在本发明实施例的各种实施例中：针对SoC系统的特点，即连接到SoC系统上的各个设备，无论是master还是slave，均通过相同的接口协议互联通信；因此将数据的读写过程划分成多个阶段，为每个阶段设置一个监控点，将出现问题的范围缩小，这样一旦定位到一个小的范围以内，问题定位的难度将会极大降低。
例如，针对图1的AXI总线互联的场景，可以将读写操作的过程划分成2个阶段：master0的写操作、master2的读操作。进一步地，master0的写操作又可以分为master0到AXI总线、AXI总线到slave2；master2的读操作又可以分为master2到AXI总线、AXI总线到slave2；如果对应到这4个的阶段，每个阶段设置一个监控点，将出问题范围进一步缩小，一旦定位到一个小的范围以内，问题定位的难度将会极大降低。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
图2a为本发明监控AXI总线的方法实施例一的流程图，图2b为本发明监控AXI总线的方法实施例一的结构图，如图2b所示，本发明实施例提供的监控AXI总线的方法应用于监控AXI总线的装置，在监控AXI总线的装置中，监控主模块(mon_master)通过串行协议接口线与监控从模块(mon_slaver)串行连接，形成由监控主模块(mon_master)与监控从模块(mon_slaver)组成的闭合环路；这里需要说明的是，监控AXI总线的装置中的监控主模块(mon_master)及监控从模块(mon_slaver)的数量可以根据实际需求进行设置，在此不加以限定，但是需要满足以下条件。
若监控主模块(mon_master)为一个、监控从模块(mon_slaver)为至 少两个时，监控从模块(mon_slaver)之间通过串行协议接口线串行连接，形成具有开口的监控从模块队列，监控主模块(mon_master)与具有开口的监控从模块(mon_slaver)队列通过串行协议接口线形成闭合环路；
若监控主模块(mon_master)为至少两个、监控从模块(mon_slaver)为一个时，监控主模块(mon_master)之间通过串行协议接口线串行连接，形成具有开口的监控主模块(mon_master)队列，具有开口的监控主模块队列(mon_master)与监控从模块(mon_slaver)通过串行协议接口线串行连接，形成闭合环路；
若监控主模块(mon_master)为至少两个、监控从模块(mon_slaver)为至少两个时，监控主模块(mon_master)之间通过串行协议接口线串行连接，形成具有开口的监控主模块(mon_master)队列，监控从模块(mon_slaver)之间通过串行协议接口线串行连接，形成具有开口的监控从模块(mon_slaver)队列，具有开口的监控主模块队列与具有开口的监控从模块(mon_slaver)队列通过串行协议接口线串行连接，形成闭合环路。
这个串行协议接口线可以是自定义的，也可以是采用目前已经标准化的协议，比如通用异步收发传输器(Universal Asynchronous Receiver/Transmitter，UART)协议等，采用串行协议接口线的原因有3点：一是作为监控来用，协议要简单，太复杂的接口容易出错；二是监控流量需求低，低速协议就足够使用；三是接口信号线数量少，因为监控节点会分布于整个芯片，如果接口信号线的数目太多，整个监控接口在整个芯片穿来穿去，会增加后端布线的难度。
由于每个监控主模块(mon_master)的功能及每个监控从模块(mon_slaver)的功能相同，因此在本实施例中，以一个监控主模块(mon_master)及一个监控从模块(mon_slaver)来举例说明。
如图2a所示，本发明实施例提供的监控AXI总线的方法包括如下步骤：
步骤101、所述监控主模块接收待检测芯片发送的串行协议命令，将所述串行协议命令转换成自定义串行比特帧命令，将所述自定义串行比特帧命令发送至所述监控从模块。
首先，监控主模块(mon_master)通过简单的串行协议接口线与待检 测芯片连接，接收待检测芯片发送的串行协议命令；其次，监控主模块(mon_master)将该串行协议命令转换成自定义串行比特帧命令，即实现“待检测芯片外部调试接口到内部自定义串行线接口的转换”；之后，将自定义串行比特帧命令发送至监控从模块(mon_slaver)。
步骤102、所述监控主模块接收所述监控从模块发送的所述AXI总线的状态信息；其中，所述AXI总线的状态信息是通过所述监控从模块将所述自定义串行比特帧命令转换成通用的并行数据读写接口命令，根据所述通用的并行数据读写接口命令对所述待检测芯片的AXI总线进行监控得到的。
监控主模块(mon_master)接收监控从模块(mon_slaver)发送的AXI总线的状态信息，其中AXI总线的状态信息是通过监控从模块将自定义串行比特帧命令转换成通用的并行数据读写接口命令，根据通用的并行数据读写接口命令对待检测芯片的AXI总线进行监控得到的。
具体的可以解释为：监控从模块(mon_slaver)首先将通过串行协议接口线接收到的自定义串行比特帧命令转换成通用的并行数据读写接口命令；接着，根据该通用的并行数据读写接口命令对待检测芯片的AXI总线进行监控，得到AXI总线的状态信息；之后，将AXI总线的状态信息发送至监控主模块(mon_master)。
步骤103、所述监控主模块根据所述AXI总线的状态信息确定出所述待检测芯片的AXI总线的状态。
监控主模块根据AXI总线的状态信息确定出待检测芯片的AXI总线的状态；即对每个监控点的状态进行确定，定位到出现问题的监控点，这样可以将出问题范围缩小，一旦定位到一个小的范围以内，问题定位的难度将会极大降低，调试效率可以呈级数级增长。
本发明实施例提供的监控AXI总线的方法，通过监控主模块接收待检测芯片发送的串行协议命令，将串行协议命令转换成自定义串行比特帧命令，将自定义串行比特帧命令发送至监控从模块；监控主模块接收监控从模块发送的AXI总线的状态信息；其中，AXI总线的状态信息是通过监控从模块将自定义串行比特帧命令转换成通用的并行数据读写接口命令，根 据通用的并行数据读写接口命令对待检测芯片的AXI总线进行监控得到的；监控主模块根据AXI总线的状态信息确定出待检测芯片的AXI总线的状态；实现了对每个监控点的状态进行确定，定位到出现问题的监控点，这样可以将出问题范围缩小，一旦定位到一个小的范围以内，问题定位的难度将会极大降低，调试效率可以呈级数级增长。
为了更加体现出本发明的目的，在上述实施例的基础上，进一步地举例说明。
图3a为本发明监控AXI总线的方法实施例二的流程图，图3b为本发明监控AXI总线的方法实施例二的结构图一，如图3b所示，本发明实施例提供的监控AXI总线的方法应用于监控AXI总线的装置，在所述监控AXI总线的装置中，一个监控主模块(mon_master)通过自定义串行接口线与由多个监控从模块(mon_slaver)形成的监控从模块(mon_slaver)队列串行连接，形成由一个监控主模块(mon_master)与多个监控从模块(mon_slaver)组成的闭合环路。
如图3a所示，该方法包括如下步骤：
步骤201、所述监控主模块接收待检测芯片发送的串行协议命令。
监控主模块(mon_master)可以采用简单的串行协议接口线接到待检测芯片的管脚上接收待检测芯片输入/输出(I/O)口发送的串行协议命令(WRITE/READ)。
在本发明的一个具体实施例中，监控主模块(mon_master)可以采用两个来实现；图3c为本发明监控AXI总线的方法实施例二的结构图二，如图3c所示，第一监控主模块(mon_master0)与第二监控主模块(mon_master1)之间通过串行协议接口线串行连接，形成具有开口的监控主模块(mon_master)队列，监控从模块(mon_slaver)之间通过串行协议接口线串行连接，形成具有开口的监控从模块(mon_slaver)队列，具有开口的监控主模块队列与具有开口的监控从模块(mon_slaver)队列通过串行协议接口线串行连接，形成闭合环路。
另外，第一监控主模块(mon_master0)采用简单的串行协议接口线与待检测芯片连接、第二监控主模块(mon_master1)采用简单的串行协议接 口线与中央处理器(Central Processing Unit，CPU)系统连接；两个监控主模块的功能是一样的，都是将接收到的命令转换成内部串行格式命令，差异在于一个接收待检测芯片的串行协议命令，一个接收CPU系统的命令。
第二监控主模块(mon_master1)通过串行协议接口线连接到CPU系统上，在CPU系统是正常情况下，可以借助CPU来发起总线监控的操作；这种结构的优势在于它的便利性，一个CPU调试器就足够完成整个调试，调试员不需要在AXI总线监控接口和CPU调试接口之间来回切换，借用CPU调试系统还能进行一些辅助性的打印或编写小程序来对监控的数据进行提取和分析。
这种方式的调试不依赖于任何内部的CPU系统，即使CPU没有正常工作起来或者CPU因为某种原因挂死，都不影响外部调试和问题定位，保证了稳定性。
步骤202、所述监控主模块将所述串行协议命令转换成自定义串行比特帧命令。
监控主模块(mon_master)将串行协议命令存入内部缓存(buffer)，按照串行比特协议将串行协议命令转换成自定义串行比特帧命令，下面对自定义串行比特帧命令进行具体说明。
图4为本发明监控AXI总线的方法实施例二的自定义串行比特帧命令的结构图，如图4所示，整个自定义串行比特帧命令的结构长度为32；它包括了起始位置、监控主模块ID、读写指示、监控从模块ID、偏移地址、结束位置；其中，
start_bit(1)：1bit起始比特表示帧结构的起始位置，空闲情况下串行比特线处于高电平，第一个低电平表示起始位置；
MID(1)：1bit master ID，指示从哪个master发出，1个bit最多支持2个监控主模块(mon_master)(改变帧结构中MID域的位宽，监控主模块(mon_master)个数可支持的最大值也随之变化，如果只用到一个监控主模块(mon_master)，该域可以删除)；
wr/rd(1)：1bit读写指示，1写，0读；
SID(5)：5bit slave ID，从多个监控从模块(mon_slave)节点中译码出一个，监控从模块(mon_slave)的个数根据实际应用选定，最多可以支持32个监控从模块(mon_slave)(改变帧结构中节点地址域的位宽，监控从模块(mon_slave)个数可支持的最大值也随之变化)；
offset_addr(8)：8bit偏移地址，从被选中监控从模块(mon_slave)节点的多个偏移地址中译码出一个，偏移地址的个数根据实际应用选定，最多可以支持256个监控从模块(mon_slave)(改变帧结构中偏移地址域的位宽，偏移地址寄存器个数可支持的最大值也随之变化)；
data(16)：串行比特线帧结构的数据域，可以根据实际应用进行自定义；
stop_bit(1)：1bit结束比特表示帧结构的结束位置，stop bit为高电平，结束位下一位开始，串行比特线进入空闲状态。
步骤203、所述监控主模块将所述自定义串行比特帧命令发送至所述监控从模块。
监控主模块(mon_master)将自定义串行比特帧命令通过串行比特线发送至监控从模块(mon_slaver)。
步骤204、所述监控从模块将所述自定义串行比特帧命令转换成通用的并行数据读写接口命令。
图5为本发明监控AXI总线的方法实施例二的监控从模块的结构图，如图5所示，监控从模块(mon_slaver)包括了转换单元(s2p_bridge)及监控单元(amti)；监控从模块(mon_slaver)中的转换单元(s2p_bridge)将自定义串行比特帧命令转换成通用的并行数据读写接口命令并下发给监控从模块(mon_slaver)中的监控单元(amti)，该通用的并行数据读写接口命令可以为读写控制信号接口命令，可以是地址线、数据线接口命令，可以是静态随机存取存储器(Static Random Access Memory，SRAM)接口命令，也可以是类似于SRAM接口命令的其他接口命令。
这里需要说明的是，如果监控从模块(mon_slaver)有至少两个的情况时，每个监控从模块(mon_slaver)在接收自定义串行比特帧命令的同时， 会将自定义串行比特帧命令原封不动的传递给下一个节点，每个监控从模块(mon_slaver)都设置有唯一的SID，转换单元(s2p_bridge)在进行串并转换时，会将接收到的SID与分配给自己的SID进行匹配，匹配上的会将自定义串行比特帧命令在本节点保存下来，下发给监控从模块(mon_slaver)中的监控单元(amti)供其使用。
这里需要说明的是，因为监控从模块(mon_slaver)的功能都是相同的，可以将监控从模块(mon_slaver)进行分时复用；因此，在本发明实施例中仅以一个监控从模块(mon_slaver)中的监控单元(amti)的具体组成和具体具有的功能进行说明。
步骤205、所述监控从模块根据所述通用的并行数据读写接口命令对所述待检测芯片的AXI总线进行监控，得到所述AXI总线的状态信息。
监控从模块(mon_slaver)中的监控单元(amti)根据通用的并行数据读写接口命令完成读写控制信息的配置，实现AXI总线的读写通道信号的复用，完成AXI总线的信号的收集和校验，完成AXI总线的状态监控和抓取的设置、启动、记录和清除。
步骤206、所述监控从模块将所述AXI总线的状态信息发送至监控主模块。
步骤207、所述监控主模块根据所述AXI总线的状态信息确定出所述待检测芯片的AXI总线的状态。
具体地，图6为本发明监控AXI总线的方法实施例二的监控从模块中的监控单元的工作状态图，如图6所示，监控单元(amti)中的配置子单元(amti_cfg)配置为根据通用的并行数据读写接口命令完成读写控制信息的配置；监控单元(amti)中的复用子单元(amti_imux)配置为实现AXI总线的读写通道信号的复用；监控单元(amti)中的收集和校验子单元(amti_check)，配置为完成AXI总线的信号的收集和校验；监控单元(amti)中的处理单元子(amti_sample)，配置为完成AXI总线的状态监控和抓取的设置、启动、记录和清除。
例如，监控单元(amti)通过SRAM接口来配置和读取内部寄存器，完成AXI总线的状态监控和数据抓取。
其中，读写控制信息包括：aw、w、b、ar、r五个数据通道的读写控制信息及addr、data、resp三个类别的读写控制信息。
每个类别可以设置不同的的匹配开关，地址通道有addr、id、len、size、burst信息，设计中为addr、id、len、size、burst每一项信息设置了一个独立的匹配开关match_en，这几个匹配开关可以独立打开和关闭，也可以任意组合打开和关闭。
比如，addr项匹配开关打开时，addr信息会作为匹配项，在进行采样之前必须先为addr项设置一个期望值，一旦在地址通道上出现该期望值，表示捕获成功，捕获成功的状态会被记录下来，同时监控单元(amti)会将地址通道对应的id、len、size、burst信息保存下来；其他匹配开关开启的组合情况可以依次类推。
数据通道有data、id、wstrb信息，设计中为data、id、wstrb每一项信息设置了一个独立的匹配开关match_en，这几个匹配开关可以独立打开和关闭，也可以任意组合打开和关闭，工作方式与上面的地址通道类似。
响应通道有resp、id信息，设计中为resp、id每一项信息设置了一个独立的匹配开关match_en，这几个匹配开关可以独立打开和关闭，也可以任意组合打开和关闭，工作方式与上面的地址通道类似。
地址、数据、响应三个通道之间的组合顺序也可以设置，地址通道匹配支持先触发数据通道，数据通道匹配支持先触发地址通道，响应通道匹配支持先触发地址或数据通道。
还可以支持单次触发和多次触发，单次触发记录第一次匹配上的结果，多次触发记录最新匹配结果。
下面以采样aw通道数据，设置addr为匹配项，单次触发为例，以采样w通道数据，设置data为匹配项，多次触发为例，以采样w通道响应，设置resp为匹配项，多次触发为例，分别给出相关寄存器的配置流程。
图7为本发明监控AXI总线的方法实施例二的监控从模块中的监控单元采样ar通道数据、设置addr为匹配项的单次触发的配置流程图，如图7所示(以下流程中每个寄存器的配置和读取都需要监控主模块发起一个相 应的命令来实现)，该流程包括：
步骤301、配置axi_dbg_en开关(8'h00)为1。
这里，打开axi_dbg_en开关，默认情况是关闭的，为了节省功耗。
步骤302、配置axi_rchn_sta_en开关(8'h01)为1。
这里，打开axi_rchn_sta_en开关，读写通道复用硬件资源(采样写通道数据，需要打开axi_wchn_sta_en开关)。
步骤303、配置a_single_trig_en(8'h34)为1。
这里，打开单次触发开关(支持单次、多次触发两种模式)。
步骤304、配置data_trig_off(8'h20)为0。
这里，关闭data_trig_off(支持data寄存器复用于addr存储)。
步骤305、配置id_match_adr_sel(8'h20)为2'b00。
这里，配置id_match_adr_sel选择addr通道(id寄存器供addr、data、resp通道复用)。
步骤306、配置a_time_catch_en(8'h34)为1。
这里，打开抓取时间使能开关。
步骤307、将addr_match_en开关(8'h20)打开。
这里，打开addr匹配使能开关。
步骤308、配置采样匹配值addr_value(8'h21，8'h22)。
这里，在addr寄存器中写入待匹配值。
步骤309、配置采样匹配mask值addr_mask(8'h23，8'h24)。
这里，根据待匹配的addr来写入相应的addr_mask值(支持addr精确匹配和区间匹配，通过配置addr_mask来实现)。
步骤310、对a_catch_ok清零(8'h33)。
这里，所有配置完成后，清零抓取完成标志，一旦抓取成功，该标志会再次置起。
步骤311、读取a_catch_ok状态(8'h33)。
这里，读取a_catch_ok状态信息。
步骤312、判断a_catch_ok是否等于1'b1。
这里，判断a_catch_ok是否等于1'b1，如果不等于1'b1，返回执行步骤311；如果等于1'b1，执行步骤313；即判断循环查询抓取成功标志是否置起，如果一直未置起，表示没有相匹配的addr访问，返回执行步骤311；如果标志置起，执行步骤313。
步骤313、读取相关数据信息。
这里，读取相关的抓取信息(id、len、size、burst)。
图8为本发明监控AXI总线的方法实施例二的监控从模块中的监控单元采样w通道数据、设置data为匹配项的多次触发的配置流程图，如图8所示(以下流程中每个寄存器的配置和读取都需要监控主模块发起一个相应的命令来实现)，该流程包括：
步骤401、配置axi_dbg_en开关(8'h00)为1。
这里，打开axi_dbg_en开关。
步骤402、配置axi_wchn_sta_en开关(8'h02)为1。
这里，打开axi_wchn_sta_en开关，即设置默认模式为多次触发。
步骤403、配置id_match_adr_sel(8'h20)为2'b01。
这里，配置id_match_adr_sel选择data通道。
步骤404、将data_match_en开关(8'h20)打开。
这里，打开data匹配使能开关。
步骤405、配置采样匹配值data_value(8'h2b～8'h32)。
这里，data寄存器写入待匹配值。
步骤406、对a_catch_ok清零(8'h33)。
这里，所有配置完成后，清零抓取完成标志，一旦抓取成功，该标志会再次置起。
步骤407、读取a_catch_ok状态(8'h33)。
这里，读取a_catch_ok状态信息。
步骤408、判断a_catch_ok是否等于1'b1。
这里，判断a_catch_ok是否等于1'b1，如果不等于1'b1，返回执行步骤407；如果等于1'b1，执行步骤409；即判断循环查询抓取成功标志是否置起，如果一直未置起，表示没有相匹配的addr访问，返回执行步骤407；如果标志置起，执行步骤409。
步骤409、读取相关数据信息(id，strb及burst的第几个)。
读取相关数据信息(id，strb及burst的第几个)。
图9为本发明监控AXI总线的方法实施例二的监控从模块中的监控单元采样w通道响应、设置resp为匹配项的多次触发的配置流程图，如图9所示(以下流程中每个寄存器的配置和读取都需要监控主模块发起一个相应的命令来实现)，该流程包括：
步骤501、配置axi_dbg_en开关(8'h00)为1。
这里，打开axi_dbg_en开关。
步骤502、配置axi_wchn_sta_en开关(8'h02)为1。
这里，打开axi_wchn_sta_en开关，，即默认模式为多次触发。
步骤503、配置id_match_adr_sel(8'h20)为2'b10。
这里，配置id_match_adr_sel选择resp通道。
步骤504、将data_match_en开关(8'h20)打开。
这里，打开resp匹配使能开关。
步骤505、配置采样匹配值resp_value(8'h29)。
这里，在resp寄存器中写入待匹配值。
步骤506、对a_catch_ok清零(8'h33)。
这里，所有配置完成后，清零抓取完成标志，一旦抓取成功，该标志会再次置起。
步骤507、读取a_catch_ok状态(8'h33)。
这里，读取a_catch_ok状态信息。
步骤508、判断a_catch_ok是否等于1'b1。
这里，判断a_catch_ok是否等于1'b1，如果不等于1'b1，返回执行步骤507；如果等于1'b1，执行步骤509；即判断循环查询抓取成功标志是否置起，如果一直未置起，表示没有相匹配的addr访问，返回执行步骤507；如果标志置起，执行步骤509。
步骤509、读取相关数据信息(id)。
这里，读取相关数据信息(id)。
其中，读取相关数据信息(id)后，所述监控从模块将所述AXI总线的状态信息发送至监控主模块。
具体地，监控从模块(mon_slaver)中的监控单元(amti)将监控、抓取到的AXI总线的状态信息(相关数据信息)通过自定义串行接口发送至监控主模块(mon_master)。
所述监控主模块根据所述AXI总线的状态信息确定出所述待检测芯片的AXI总线的状态。
监控主模块(mon_master)根据AXI总线的状态信息分析确定出待检测芯片的AXI总线的状态，将状态问题定位出来，或者工作人员通过监控主模块(mon_master)接收到的AXI总线的状态信息分析确定出待检测芯片的AXI总线的状态，将状态问题定位出来；比如待检测芯片模块存储地址的数据被意外改写，通过抓取改写该地址的ID，能准确分析出改写源，再将分析的重心放到改写源，这样就可以很快发现改写的原因，极大降低了问题定位的难度，调试效率可以呈技术级增长。
本发明实施例提供的监控AXI总线的方法，通过监控主模块接收待检测芯片发送的串行协议命令；监控主模块将所述串行协议命令转换成自定义串行比特帧命令；监控主模块将所述自定义串行比特帧命令发送至所述监控从模块；监控从模块将所述自定义串行比特帧命令转换成通用的并行数据读写接口命令；监控从模块根据所述通用的并行数据读写接口命令对所述待检测芯片的AXI总线进行监控，得到所述AXI总线的状态信息；监 控从模块将所述AXI总线的状态信息发送至监控主模块；监控主模块根据所述AXI总线的状态信息确定出所述待检测芯片的AXI总线的状态；实现了对每个监控点的状态进行确定，定位到出现问题的监控点，这样可以将出问题范围缩小，一旦定位到一个小的范围以内，问题定位的难度将会极大降低，调试效率可以呈级数级增长。
图10为本发明监控AXI总线的装置实施例的结构示意图，如图10所示，本发明实施例提供的监控AXI总线的装置010包括：监控主模块101及监控从模块102；其中，所述监控主模块101通过串行协议接口线与所述监控从模块102串行连接，形成由所述监控主模块101与所述监控从模块102组成的闭合环路；
所述监控主模块101，配置为接收待检测芯片发送的串行协议命令，将所述串行协议命令转换成自定义串行比特帧命令，将所述自定义串行比特帧命令发送至所述监控从模块102；
所述监控从模块102，配置为将所述自定义串行比特帧命令转换成通用的并行数据读写接口命令，根据所述通用的并行数据读写接口命令对所述待检测芯片的AXI总线进行监控，得到所述AXI总线的状态信息，将所述AXI总线的状态信息发送至所述监控主模块101；
所述监控主模块101，还配置为根据所述AXI总线的状态信息确定出所述待检测芯片的AXI总线的状态。
在一具体实施例中，所述自定义串行比特帧命令包括：起始位置、所述监控主模块ID、读写指示、所述监控从模块ID、偏移地址、结束位置。
在一具体实施例中，所述监控从模块102，包括：转换单元1021及监控单元1022；其中，
所述转换单元1021，配置为将所述自定义串行比特帧命令转换成通用的并行数据读写接口命令；
所述监控单元1022，包括：配置子单元10221、复用子单元10222、收集和校验子单元10223、处理子单元10224；其中，
所述配置子单元10221，配置为根据所述通用的并行数据读写接口命令 完成读写控制信息的配置；
所述复用子单元10222，配置为实现所述AXI总线的读写通道信号的复用；
所述收集和校验子单元10223，配置为完成所述AXI总线的信号的收集和校验；
所述处理子单元10224，配置为完成所述AXI总线的状态监控和抓取的设置、启动、记录和清除。
在一具体实施例中，所述读写控制信息包括：aw、w、b、ar、r五个数据通道的读写控制信息及addr、data、resp三个类别的读写控制信息。
在一具体实施例中，若所述监控主模块101为一个、所述监控从模块102为至少两个时，所述监控从模块102之间通过所述串行协议接口线串行连接，形成具有开口的监控从模块102队列，所述监控主模块101与所述具有开口的监控从模块102队列通过所述串行协议接口线形成闭合环路；
若所述监控主模块101为至少两个、所述监控从模块102为一个时，所述监控主模块101之间通过所述串行协议接口线串行连接，形成具有开口的监控主模块101队列，所述具有开口的监控主模块101队列与所述监控从模块102通过所述串行协议接口线串行连接，形成闭合环路；
若所述监控主模块101为至少两个、所述监控从模块102为至少两个时，所述监控主模块101之间通过所述串行协议接口线串行连接，形成具有开口的监控主模块101队列，所述监控从模块102之间通过所述串行协议接口线串行连接，形成具有开口的监控从模块102队列，所述具有开口的监控主模块101队列与所述具有开口的监控从模块102队列通过所述串行协议接口线串行连接，形成闭合环路。
本实施例的装置，可以配置为执行上述所示方法实施例的技术方案，其实现原理和技术效果类似，此处不再赘述。
在实际应用中，所述监控主模块101、监控从模块102、转换单元1021、监控单元1022、配置子单元10221、复用子单元10222、收集和校验子单元10223、处理子单元10224均可由位于监控AXI总线的装置010中的处理器 比如CPU、微处理器(Micro Processor Unit，MPU)、数字信号处理器(Digital Signal Processor，DSP)或FPGA等实现。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
基于此，本发明实施例还提供了一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现本发明实施例的监控AXI总线的方法的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例提供的方案，通过监控主模块接收待检测芯片发送的串行协议命令，将串行协议命令转换成自定义串行比特帧命令，将自定义串行比特帧命令发送至监控从模块；监控主模块接收监控从模块发送的AXI总线的状态信息；其中，AXI总线的状态信息是通过监控从模块将自定义串行比特帧命令转换成通用的并行数据读写接口命令，根据通用的并行数据读写接口命令对待检测芯片的AXI总线进行监控得到的；监控主模块根据AXI总线的状态信息确定出待检测芯片的AXI总线的状态；实现了对每个监控点的状态进行确定，定位到出现问题的监控点，这样可以将出问题范围缩小，一旦定位到一个小的范围以内，问题定位的难度将会极大降低，调试效率可以呈级数级增长。

Claims (11)

  1. 一种监控高级可扩展接口AXI总线的方法，所述方法应用于监控AXI总线的装置，在所述监控AXI总线的装置中，监控主模块通过串行协议接口线与监控从模块串行连接，形成由所述监控主模块与所述监控从模块组成的闭合环路，所述方法包括：
    所述监控主模块接收待检测芯片发送的串行协议命令；将所述串行协议命令转换成自定义串行比特帧命令；将所述自定义串行比特帧命令发送至所述监控从模块；
    所述监控主模块接收所述监控从模块发送的所述AXI总线的状态信息；其中，所述AXI总线的状态信息是通过所述监控从模块将所述自定义串行比特帧命令转换成通用的并行数据读写接口命令，根据所述通用的并行数据读写接口命令对所述待检测芯片的AXI总线进行监控得到的；
    所述监控主模块根据所述AXI总线的状态信息确定出所述待检测芯片的AXI总线的状态。
  2. 根据权利要求1所述的方法，其中，所述自定义串行比特帧命令包括：起始位置、所述监控主模块标识号ID、读写指示、所述监控从模块标识号ID、偏移地址、结束位置。
  3. 根据权利要求1所述的方法，其中，所述方法还包括：
    所述监控从模块根据所述通用的并行数据读写接口命令完成读写控制信息的配置，实现所述AXI总线的读写通道信号的复用，完成所述AXI总线的信号的收集和校验，完成所述AXI总线的状态监控和抓取的设置、启动、记录和清除。
  4. 根据权利要求3所述的方法，其中，所述读写控制信息包括：aw、w、b、ar、r五个数据通道的读写控制信息及addr、data、resp三个类别的读写控制信息。
  5. 根据权利要求1至4任一项所述的方法，其中，
    若所述监控主模块为一个、所述监控从模块为至少两个时，所述监控 从模块之间通过所述串行协议接口线串行连接，形成具有开口的监控从模块队列，所述监控主模块与所述具有开口的监控从模块队列通过所述串行协议接口线形成闭合环路；
    或者，若所述监控主模块为至少两个、所述监控从模块为一个时，所述监控主模块之间通过所述串行协议接口线串行连接，形成具有开口的监控主模块队列，所述具有开口的监控主模块队列与所述监控从模块通过所述串行协议接口线串行连接，形成闭合环路；
    或者，若所述监控主模块为至少两个、所述监控从模块为至少两个时，所述监控主模块之间通过所述串行协议接口线串行连接，形成具有开口的监控主模块队列，所述监控从模块之间通过所述串行协议接口线串行连接，形成具有开口的监控从模块队列，所述具有开口的监控主模块队列与所述具有开口的监控从模块队列通过所述串行协议接口线串行连接，形成闭合环路。
  6. 一种监控高级可扩展接口AXI总线的装置，所述装置包括：监控主模块及监控从模块；其中，所述监控主模块通过串行协议接口线与所述监控从模块串行连接，形成由所述监控主模块与所述监控从模块组成的闭合环路；
    所述监控主模块，配置为接收待检测芯片发送的串行协议命令，将所述串行协议命令转换成自定义串行比特帧命令，将所述自定义串行比特帧命令发送至所述监控从模块；
    所述监控从模块，配置为将所述自定义串行比特帧命令转换成通用的并行数据读写接口命令，根据所述通用的并行数据读写接口命令对所述待检测芯片的AXI总线进行监控，得到所述AXI总线的状态信息，将所述AXI总线的状态信息发送至所述监控主模块；
    所述监控主模块，还配置为根据所述AXI总线的状态信息确定出所述待检测芯片的AXI总线的状态。
  7. 根据权利要求6所述的装置，其中，所述自定义串行比特帧命令包括：起始位置、所述监控主模块标识号ID、读写指示、所述监控从模块标识号ID、偏移地址、结束位置。
  8. 根据权利要求6所述的装置，其中，所述监控从模块，包括：
    转换单元，配置为将所述自定义串行比特帧命令转换成通用的并行数据读写接口命令；
    监控单元；所述监控单元包括：
    配置子单元，配置为根据所述通用的并行数据读写接口命令完成读写控制信息的配置；
    复用子单元，配置为实现所述AXI总线的读写通道信号的复用；
    收集和校验子单元，配置为完成所述AXI总线的信号的收集和校验；
    处理子单元，配置为完成所述AXI总线的状态监控和抓取的设置、启动、记录和清除。
  9. 根据权利要求8所述的装置，其中，所述读写控制信息包括：aw、w、b、ar、r五个数据通道的读写控制信息及addr、data、resp三个类别的读写控制信息。
  10. 根据权利要求6至9任一项所述的装置，其中，
    若所述监控主模块为一个、所述监控从模块为至少两个时，所述监控从模块之间通过所述串行协议接口线串行连接，形成具有开口的监控从模块队列，所述监控主模块与所述具有开口的监控从模块队列通过所述串行协议接口线形成闭合环路；
    或者，若所述监控主模块为至少两个、所述监控从模块为一个时，所述监控主模块之间通过所述串行协议接口线串行连接，形成具有开口的监控主模块队列，所述具有开口的监控主模块队列与所述监控从模块通过所述串行协议接口线串行连接，形成闭合环路；
    或者，若所述监控主模块为至少两个、所述监控从模块为至少两个时，所述监控主模块之间通过所述串行协议接口线串行连接，形成具有开口的监控主模块队列，所述监控从模块之间通过所述串行协议接口线串行连接，形成具有开口的监控从模块队列，所述具有开口的监控主模块队列与所述具有开口的监控从模块队列通过所述串行协议接口线串行连接，形成闭合环路。
  11. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1至5任一项所述方法的步骤。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110531686A (zh) * 2019-09-28 2019-12-03 徐州可云智能科技有限公司 一种基于单主多从协议实现多主机的装置及其方法
CN112540949A (zh) * 2020-12-17 2021-03-23 北京航天测控技术有限公司 一种数据传输系统
CN114385544A (zh) * 2020-10-20 2022-04-22 Oppo广东移动通信有限公司 Uart芯片及fpga芯片
CN114531371A (zh) * 2022-02-23 2022-05-24 杭州中天微系统有限公司 总线监测网络、片上系统以及总线管理方法
CN116932333A (zh) * 2023-09-14 2023-10-24 武汉凌久微电子有限公司 一种硅后验证的axi总线实时性能监控方法
CN119065930A (zh) * 2024-08-29 2024-12-03 无锡众星微系统技术有限公司 一种片上axi总线监控方法及监控模块

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109471824B (zh) * 2018-11-22 2021-02-05 青岛方寸微电子科技有限公司 基于axi总线的数据传输系统及方法
CN112286746B (zh) * 2020-10-31 2023-01-24 拓维电子科技(上海)有限公司 针对axi从设备接口的通用验证平台及方法
CN112579415B (zh) * 2020-12-10 2024-05-31 北京爱芯科技有限公司 Axi总线的性能计算方法、装置、电子设备及存储介质
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CN113055259B (zh) * 2021-02-08 2022-05-13 西安电子科技大学 一种基于axi总线协议的功能安全保护方法
CN117346220A (zh) * 2022-06-27 2024-01-05 佛山市顺德区美的电子科技有限公司 家电系统及其通讯方法、设备、存储介质
CN116136949A (zh) * 2023-02-22 2023-05-19 篆芯半导体(南京)有限公司 一种多核SoC的调试方法及应用其的调试系统
CN118093235A (zh) * 2023-12-18 2024-05-28 无锡众星微系统技术有限公司 一种芯片cpu异常诊断方法和装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101676887A (zh) * 2008-08-15 2010-03-24 北京北大众志微系统科技有限责任公司 一种基于ahb总线结构的总线监听方法及装置
CN101989242A (zh) * 2010-11-12 2011-03-23 深圳国微技术有限公司 一种提高soc系统安全的总线监视器及其实现方法
US20110225337A1 (en) * 2010-03-12 2011-09-15 Byrne Richard J Transaction performance monitoring in a processor bus bridge
CN103186447A (zh) * 2011-12-27 2013-07-03 安凯(广州)微电子技术有限公司 一种总线读写检测装置
CN103810074A (zh) * 2012-11-14 2014-05-21 华为技术有限公司 一种片上系统芯片及相应的监控方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102231129B (zh) * 2011-07-04 2013-11-13 浙江大学 一种基于串口的多层AHB总线架构SoC监测调试系统与方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101676887A (zh) * 2008-08-15 2010-03-24 北京北大众志微系统科技有限责任公司 一种基于ahb总线结构的总线监听方法及装置
US20110225337A1 (en) * 2010-03-12 2011-09-15 Byrne Richard J Transaction performance monitoring in a processor bus bridge
CN101989242A (zh) * 2010-11-12 2011-03-23 深圳国微技术有限公司 一种提高soc系统安全的总线监视器及其实现方法
CN103186447A (zh) * 2011-12-27 2013-07-03 安凯(广州)微电子技术有限公司 一种总线读写检测装置
CN103810074A (zh) * 2012-11-14 2014-05-21 华为技术有限公司 一种片上系统芯片及相应的监控方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110531686A (zh) * 2019-09-28 2019-12-03 徐州可云智能科技有限公司 一种基于单主多从协议实现多主机的装置及其方法
CN114385544A (zh) * 2020-10-20 2022-04-22 Oppo广东移动通信有限公司 Uart芯片及fpga芯片
CN112540949A (zh) * 2020-12-17 2021-03-23 北京航天测控技术有限公司 一种数据传输系统
CN114531371A (zh) * 2022-02-23 2022-05-24 杭州中天微系统有限公司 总线监测网络、片上系统以及总线管理方法
CN116932333A (zh) * 2023-09-14 2023-10-24 武汉凌久微电子有限公司 一种硅后验证的axi总线实时性能监控方法
CN116932333B (zh) * 2023-09-14 2023-12-26 武汉凌久微电子有限公司 一种硅后验证的axi总线实时性能监控方法
CN119065930A (zh) * 2024-08-29 2024-12-03 无锡众星微系统技术有限公司 一种片上axi总线监控方法及监控模块

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