WO2018076641A1

WO2018076641A1 - Method and apparatus for reducing delay and storage medium

Info

Publication number: WO2018076641A1
Application number: PCT/CN2017/082161
Authority: WO
Inventors: 肖春梅; 余斯擎
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2016-10-28
Filing date: 2017-04-27
Publication date: 2018-05-03
Also published as: CN108011845A

Abstract

Disclosed in the present invention is a method for reducing delay, comprising: firstly acquiring bandwidth information and length of available space of a first-in first-out cache; and stopping scheduling of a received message when the bandwidth information is less than a first preset value or the length of available space of the first-in first-out cache is less than a second preset value. Also disclosed in the present invention are an apparatus for reducing delay and a storage medium.

Description

Method, device and storage medium for reducing time delay

Cross-reference to related applications

The present application is based on a Chinese patent application filed on Jan. 28, 2016, the entire disclosure of which is hereby incorporated by reference.

Technical field

The present invention relates to the field of optical communication networks, and in particular, to a method, an apparatus, and a storage medium for reducing delay.

Background technique

In a communication device, bandwidth is usually set in advance for each user. When the amount of data transmitted by the user is greater than the preset bandwidth, in order to guarantee the quality of service (QoS), high-priority packets need to be transmitted preferentially, and low-priority packets are delayed or discarded. Therefore, in order to guarantee QoS, it is very important to reduce the delay of high priority messages in network devices.

In an Optical Network Unit (ONU), a FIFO for storing messages is usually set to reduce the overhead of media access control (MAC) and multi-mode. Line speed. When congestion occurs, as in the case shown in Figure 1, the low-priority message occupies a large proportion and is stored in the FIFO position of the FIFO, while the high-priority message is stored in The relative tail position of the FIFO cache, when the bandwidth is sufficient, the message is read from the FIFO and sent to the optical line terminal (OLT, Optical Line Terminal); at this time, only the low priority report is sent. A high-priority packet can be sent after the packet is sent out. Or, a higher-priority packet can be scheduled at this time. After all the packets stored in the FIFO cache are sent out, the higher priority packets can be sent; or the FIFO cache is deleted, but in this case, the bandwidth information is obtained and the scheduling is completed. During this time, the network will be idle again, which will waste network resources; and it will not help to reduce the delay of high-priority messages. It can be seen that these three situations will greatly affect QoS.

Therefore, how to reduce the delay in the ONU, especially how to reduce the delay of high-priority messages and improve the QoS of network services in the case of packet congestion is an urgent problem to be solved.

Summary of the invention

In view of this, the embodiments of the present invention are directed to a method, an apparatus, and a storage medium for reducing delay, which can reduce the delay of message scheduling and improve the QoS of network services.

To achieve the above objective, the technical solution of the embodiment of the present invention is implemented as follows:

The embodiment of the invention provides a method for reducing delay, the method comprising:

Get bandwidth information and the length of free space in the FIFO cache;

When the bandwidth information is smaller than the first preset value or the available space length of the FIFO is less than the second preset value, the scheduling of the received packet is stopped.

In the foregoing solution, after the stopping the scheduling of the received packet, the method further includes:

When the bandwidth information is smaller than the first preset value and the total length of the packet buffered by the FIFO is less than the third preset value, the received packet is scheduled, and the FIFO is kept in the FIFO. The total length of the stored packets does not exceed the third preset value.

In the above solution, the method further includes: when the bandwidth information is greater than or equal to the first preset value, the packet is read from the first in first out buffer and sent.

In the above solution, after the stopping the scheduling of the received message, the method further includes: temporarily storing the received message after stopping the scheduling into the memory.

In the foregoing solution, the scheduling the received packet includes: sending a high priority packet Priority storage to the FIFO.

The embodiment of the invention further provides an apparatus for reducing delay, the apparatus comprising: an obtaining module and a scheduling module; wherein

The obtaining module is configured to acquire bandwidth information and a free space length of the first in first out cache;

The scheduling module is configured to stop scheduling the received packet when the bandwidth information is smaller than the first preset value or the available space length of the FIFO is less than a second preset value.

In the above solution, the scheduling module is further configured to: after the stopping the scheduling of the received packet, the bandwidth information is smaller than the first preset value, and the total length of the packet buffered by the FIFO cache When the value is smaller than the third preset value, the received packet is scheduled, and the total length of the packet stored in the FIFO cache does not exceed the third preset value.

In the above solution, the device further includes: a traffic management egress module, configured to: when the bandwidth information is greater than or equal to the first preset value, read the packet from the FIFO cache and send the packet.

In the above solution, the scheduling module is further configured to temporarily store the received message after stopping the scheduling into the memory after stopping the scheduling of the received message.

In the foregoing solution, the scheduling module is configured to preferentially store the high priority packet to the first in first out cache.

The embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the method for reducing delay described above.

The method, device, and storage medium for reducing delay in the embodiment of the present invention acquire bandwidth information and available space length of the first-in first-out cache; the bandwidth information is smaller than the first preset value or the available space of the first-in first-out cache When the length is less than the second preset value, the receiving of the received packet is stopped. Obviously, in the embodiment of the present invention, the packet is scheduled and sent only when the bandwidth or the remaining space of the FIFO buffer is sufficiently large. FIFO; when the bandwidth and the remaining space of the FIFO cache are insufficient, the message will not be dispatched, and the packet in the FIFO cache will not be added. The total length, in this way, according to the available space of the first-in first-out cache and the currently available bandwidth, timely determine and determine whether to schedule the message, send the stored message in the FIFO cache as soon as possible, shorten the transmission time, and make new The waiting time of the scheduled packets is shortened, which effectively reduces the delay of packet scheduling and improves the QoS of network services.

Further, in the embodiment of the present invention, the high-priority packet can be preferentially stored in the FIFO cache, so that when the packet can be scheduled and sent, the high-priority packet can be preferentially processed, thereby enabling congestion. The delay of high-priority messages is reduced, thereby improving the QoS of network services.

DRAWINGS

FIG. 1 is a schematic diagram of the principle of ONU message transmission in the prior art;

2 is a schematic diagram showing the principle of uplink data transmission of a PON in the prior art;

FIG. 3 is a schematic diagram of an implementation process of a method for reducing delay according to an embodiment of the present invention; FIG.

FIG. 4 is a schematic flowchart of a specific implementation process of a method for reducing delay according to an embodiment of the present invention.

FIG. 5 is a schematic structural diagram of a device for reducing delay according to an embodiment of the present invention; FIG.

FIG. 6 is a schematic structural diagram of a device for reducing delay in an embodiment of the present invention.

detailed description

As shown in FIG. 1 and FIG. 2, in the prior art, when an ONU receives a message from a terminal user (Terminal User), in order to improve QoS, the received message is scheduled; The packet is cached in the FIFO buffer. When the ONU determines that the uplink time slot has been allocated, the MAC module will read the packet from the FIFO and perform the encapsulation and other processing to send the packet to the OLT.

Generally, the priority of packets transmitted on the network is different. The voice service priority of the call is relatively high. If there is a large delay or it is discarded and then re-transmitted under bad conditions, the quality of the call will be degraded and the user experience will be affected. This is not tolerable; For example, in the test of the operator, there is a test requirement for this situation. In the case of congestion, three flows of different priorities are sent, and the flow is from small to large in descending order. In this case, even if there is a high-priority packet, the low-priority packet occupies a large amount of the egress buffer, so that the high-priority packet can be processed after the packet is processed, thereby greatly increasing the number of packets. Delay.

In the embodiment of the present invention, the bandwidth information and the available space length of the FIFO are obtained; when the bandwidth information is smaller than the first preset value or the available space length of the FIFO is less than the second preset value, the pair stops. Received packets are scheduled.

The present invention will be further described in detail below with reference to the embodiments.

A method for reducing delay is provided in the embodiment of the present invention. As shown in FIG. 3, the method includes:

Step 301: Acquire bandwidth information and a length of available space of the FIFO cache;

Here, the bandwidth information may be acquired by the MAC module, where the bandwidth information includes the size of the currently available bandwidth.

Step 302: Stop the scheduling of the received message when the bandwidth information is smaller than the first preset value or the available space length of the FIFO is less than the second preset value.

In this step, the bandwidth information may be greater than or equal to the first preset value, and the available space length of the FIFO buffer is greater than or equal to the second preset value as a determination condition. When the determination condition is not met, the receiving is started. The received message is scheduled; otherwise, the received message is stopped.

In this step, the received message is from the end user; since the packet will follow a certain protocol format, each packet has a minimum length. If the current free space of the first in first out cache is less than the shortest length of the packet, The new preset packet can be stored in the FIFO cache. Therefore, the second preset value can be set based on the shortest length of the packet. To prevent the packet from being discarded, the available space length is less than the second preset value. It is necessary to stop scheduling the message.

In practical applications, when the bandwidth information is less than a certain value, it is cached in the FIFO cache. The message will not be sent out or sent very little. If the message is continuously scheduled and stored in the FIFO cache, the amount of data buffered in the FIFO cache will increase; therefore, the first preset needs to be set. The value is used as a trigger condition for stopping the scheduling message. Preferably, the first preset value can be set to zero.

The method for reducing the delay may further include the step 303: if the bandwidth information is greater than or equal to the first preset value, the packet is read from the FIFO cache and sent;

Here, the transmitting is to send the read message to an external device.

In practical applications, step 303 and step 302 do not have a sequence of operations, and step 302 may be run first, and then step 303 may be run; or step 303 may be run first, then step 302 may be run; both may also be run simultaneously. In order to avoid the phenomenon of packet loss, the total number of packets sent in step 303 must not be greater than the bandwidth information.

In the method for reducing the delay provided by the embodiment of the present invention, if the bandwidth information is smaller than the first preset value, the total length of the packet in the FIFO buffer is not increased, and the packet is not read from the FIFO cache. And sending the message to the external device; after a period of time, when the bandwidth information is greater than or equal to the first preset value and the remaining space in the FIFO buffer is sufficient, the message stored in the FIFO buffer can be all in the shortest time. After the transmission is completed, the waiting delay time of the newly scheduled message is shortened, thereby effectively reducing the delay of the newly scheduled message.

In the embodiment of the present invention, after the stopping the scheduling of the received packet, the method further includes: the bandwidth information is smaller than the first preset value, and the total length of the packet buffered by the FIFO is less than The third preset value is used to schedule the received packet, and keep the total length of the packet stored in the FIFO cache not exceeding a third preset value.

In the embodiment of the present invention, it is considered that the third preset value needs to be set to assist in determining whether to schedule and store the packet: in an actual application, a situation may occur in which the bandwidth information is smaller than the first preset value. A packet of a certain length is stored in the FIFO cache. After the bandwidth information is greater than or equal to the first preset value, the packet is scheduled to be sent. For a period of time; if the total length of the packets stored in the FIFO buffer is insufficient, the packets will be read and sent out quickly, and the network will be idle, causing network resources. waste. Therefore, in order to improve the usage rate of the network, a certain length of the message may be stored in the FIFO cache in advance to ensure that the network is fully utilized during the period described above; a threshold may be set according to experience, that is, the third preset. Value to determine if the total length of the message in the FIFO buffer is long enough.

In the embodiment of the present invention, after the stopping the scheduling of the received message, the method further includes temporarily storing the received message after stopping the scheduling into the memory; the memory may be an external memory.

Here, after the packet scheduling is stopped, the newly received packet cannot be stored in the FIFO buffer. To prevent packet loss, a memory can be set to temporarily store the packet received after the scheduling is stopped. Correspondingly, when the received message is scheduled to start in step 302, the received message includes a message stored in the memory, and also includes a message received from the terminal user at this time.

In the embodiment of the present invention, the scheduling of the received packet includes: preferentially storing the high priority packet to the first in first out cache;

Here, high priority messages can be stored in the relative head of the FIFO cache. Therefore, when the bandwidth information is greater than or equal to the first preset value, the high-priority packet can be sent preferentially, which effectively reduces the delay of the high-priority packet; and after the packet stored in the FIFO cache is sent. The packets with the highest priority are scheduled to be sent out and sent, so that the waiting time of the newly scheduled high-priority packets is minimized, which effectively reduces the delay of high-priority packets.

As shown in FIG. 4, the working process of the method for reducing delay is specifically described below:

Step 401: Determine whether there is a message that can be scheduled, if yes, execute step 402; otherwise, end the current processing flow;

Step 402: Determine whether the bandwidth information is greater than or equal to the first preset value, and the FIFO buffer remaining space is greater than or equal to the second preset value. If yes, execute step 403; otherwise, end the current processing flow;

Step 403: Queue the packet, perform processing such as fragmentation and packet modification;

Step 404: The message is stored in the corresponding first-in first-out cache under the current TCONT;

Here, the FIFO cache size is configurable, and the configuration of the maximum slice length needs to be considered at the same time.

Step 405: Read the packet in the FIFO cache according to the bandwidth information, and send the packet, and then end the processing flow.

Step 406: Obtain corresponding bandwidth information from the MAC module; then perform step 402.

An embodiment of the present invention provides a device for reducing delay. As shown in FIG. 5, the device includes a block: a scheduling module 1 and an obtaining module 3;

Obtaining module 3, configured to obtain bandwidth information and a free space length of the first in first out cache;

Here, the obtaining module 3 may be included in a MAC module, and obtains bandwidth information by using a MAC module, where the bandwidth information includes a size of a currently available bandwidth.

The scheduling module 1 is configured to stop scheduling the received message when the bandwidth information is less than the first preset value or the available space length of the FIFO is less than the second preset value.

In the module, the bandwidth information may be greater than or equal to the first preset value, and the available space length of the first-in first-out buffer is greater than or equal to the second preset value as a determination condition, and when the determination condition is not met, the pair is started. The received message is scheduled; otherwise, the received message is stopped.

In the module, the received message is from the end user; since the message will follow a certain protocol format, each message has a shortest length. If the current available space of the first in first out cache is less than the shortest length of the message, It is no longer possible to store new messages in the FIFO cache; therefore, the second preset value can be set based on the minimum length of the message, when the available space length is less than the first To prevent the packet from being discarded, you need to stop scheduling the packet.

In actual applications, when the bandwidth information is less than a certain value, the packets buffered in the FIFO are not sent out or sent very little. If the packets are continuously scheduled and stored in the FIFO cache, the advanced first. The amount of data buffered in the buffer is increased; therefore, the first preset value needs to be set as a trigger condition for stopping the scheduling message. Preferably, the first preset value can be set to zero.

In the embodiment of the present invention, the device further includes a traffic management egress module 2 configured to read and send the packet from the FIFO cache when the bandwidth information is greater than or equal to the first preset value.

Here, the transmitting is to send the read message to an external device.

In the apparatus for reducing delay provided by the embodiment of the present invention, if the bandwidth information is smaller than the first preset value, the total length of the packet in the FIFO buffer is not increased, and the packet is not read from the FIFO cache. And sending the message to the external device; after a period of time, when the bandwidth information is greater than or equal to the first preset value and the remaining space in the FIFO buffer is sufficient, the message stored in the FIFO buffer can be all in the shortest time. After the transmission is completed, the waiting delay time of the newly scheduled message is shortened, thereby effectively reducing the delay of the newly scheduled message.

In the embodiment of the present invention, the scheduling module 1 is further configured to: after the stopping the scheduling of the received packet, the bandwidth information is smaller than the first preset value, and the packet buffered by the first-in first-out cache When the total length is less than the third preset value, the received packet is scheduled, and the total length of the packet stored in the FIFO cache does not exceed the third preset value.

In the embodiment of the present invention, it is considered that the third preset value needs to be set to assist in determining whether to schedule and store the packet: in an actual application, a situation may occur in which the bandwidth information is smaller than the first preset value. A packet of a certain length is stored in the FIFO cache. After the bandwidth information is greater than or equal to the first preset value, the packet is scheduled to be sent out. This process takes a while; during this time, if the storage is performed If the total length of the packets in the FIFO buffer is insufficient, the packets will be read and sent out quickly, and the network will be idle. Waste of network resources. Therefore, in order to improve the usage rate of the network, a certain length of the message may be stored in the FIFO cache in advance to ensure that the network is fully utilized during the period described above; a threshold may be set according to experience, that is, the third preset. Value to determine if the total length of the message in the FIFO buffer is long enough.

In the embodiment of the present invention, the scheduling module 1 is further configured to temporarily store the received message after stopping the scheduling into the memory after stopping the scheduling of the received message; the memory may be an external memory.

Here, after the packet scheduling is stopped, the newly received packet cannot be stored in the FIFO buffer. To prevent packet loss, a memory can be set to temporarily store the received unscheduled packet. Correspondingly, when the scheduling module starts to schedule the received message, the received message includes the message stored in the memory, and also includes the message received from the terminal user at this time.

In the embodiment of the present invention, the scheduling module 1 is configured to preferentially store high priority packets to the first in first out cache.

Here, high priority messages can be stored in the relative head of the FIFO cache. Therefore, when the bandwidth information is greater than or equal to the first preset value, the high-priority packet can be sent preferentially, which effectively reduces the delay of the high-priority packet; and after the packet stored in the FIFO cache is sent. The packets with the highest priority are scheduled to be sent out and sent, so that the waiting time of the newly scheduled high-priority packets is minimized; the delay of high-priority packets is effectively reduced.

A specific implementation manner of the reduced delay device is as shown in FIG. 6 , including a scheduling module 1 , a traffic management exit module 2 , and an obtaining module 3 , where:

The acquiring module 3 is included in the MAC module 4, configured to acquire bandwidth information, and send bandwidth information to the scheduling module 1 and the traffic management exit module 2;

The MAC module 4 is further configured to send the received packet to an external device.

The traffic management exit module 2 includes an egress data cache management module 21 and a first in first out cache 22;

a first-in first-out cache 22 configured to buffer messages;

The egress data cache management module 21 is configured to store the received message in the FIFO cache 22, and configured to: when the bandwidth information is smaller than the first preset value or the available space length of the FIFO is smaller than the second When the preset value is, the back pressure signal is sent to the scheduling module 1; and when the bandwidth information is greater than or equal to the first preset value, the message is read from the first in first out buffer and sent to the MAC module 4;

The scheduling module 1 is configured to stop scheduling the received packet when the bandwidth information is smaller than the first preset value or when receiving the back pressure information; otherwise, the received packet is scheduled and sent to the traffic management exit. Module 2.

In the embodiment of the present invention, the reduced delay device is further provided with a memory 11; and in the scheduling module 1, when the scheduling of the received message is stopped, the received message is temporarily stored in the memory 11. .

In the embodiment of the present invention, after the scheduling of the received packet is stopped, the bandwidth information is smaller than the first preset value, and the total length of the packet buffered by the FIFO is less than The third preset value is used to schedule the received packet, and keep the total length of the packet stored in the FIFO cache not exceeding a third preset value.

In the embodiment of the present invention, in the scheduling module 1, the scheduling of the received packet includes: sending the high priority packet to the traffic management exit module 2 in priority.

The voice information and the data information are taken as an example to describe a working process of the device for reducing the delay. In this embodiment, the initial bandwidth information is assumed to be zero; here, the voice packet belongs to a high priority data packet, and the traffic is compared. Small; data packets are low-priority packets with large traffic.

In the embodiment of the present invention, the working process of the apparatus for reducing delay includes:

Step 1. The acquisition module 3 sends the bandwidth information to the scheduling module 1 and the traffic management exit module 2; since the bandwidth information is smaller than the first preset value, the egress data cache management module 21 will adjust Degree module 1 sends back pressure information; here, the bandwidth information value is zero;

Step 2: The scheduling module 1 receives the back pressure information, stops scheduling the received message, and temporarily stores the received message in the memory 11;

Here, if the remaining space of the memory is used up, the received message is discarded; therefore, the total length of the message stored in the FIFO is not long;

In addition, if the scheduling module 1 is also connected with other modules, the scheduling module 1 also needs to send back pressure information to the modules;

Step 3: When the voice packet and the data packet enter the scheduling module 1, the scheduling module 1 stores the received voice packet and the data packet in the memory 11;

Step 4: If the bandwidth information is greater than or equal to the first preset value, the acquiring module 3 sends the bandwidth information to the scheduling module 1 and the traffic management exit module 2; at this time, since the bandwidth information is greater than the first preset value, the egress data cache management The module 21 reads the message from the FIFO buffer 22, sends it to the MAC module 4, and sends it to the external device by the MAC module 4; and the total length of the remaining space of the FIFO buffer is greater than the second preset value. , so no back pressure information will be sent to the scheduling module 1;

Step 5: The scheduling module 1 starts to schedule the received voice message and the data packet, and because the voice message has a high priority, the voice message is first scheduled and sent to the traffic management exit module 2; After the packets stored in the buffer are sent, the voice packets are sent to the external device through the MAC module 4; in step 2, the total number of packets stored in the FIFO buffer is limited in advance. Length, so the delay of the voice message will be shorter;

Step 6: If the traffic management exit module 2 determines that the remaining space of the FIFO buffer is less than the second preset value, the back pressure signal is sent to the scheduling module 1, and then the state at this time is equivalent to the step 2, and the Perform the operations from step 2 to step 5.

In a practical application, the scheduling module 1, the traffic management exit module 2, and the obtaining module 3 may be a central processing unit (CPU) of the base station server, and a microprocessor. (MPU, Micro Processor Unit), digital signal processor (DSP, Digital Signal Processor), or Field Programmable Gate Array (FPGA).

In the embodiment of the present invention, if the above method for reducing the delay is implemented in the form of a software function module, and is sold or used as a separate product, it may also be stored in a computer readable storage medium. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions. A computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention. The foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.

Correspondingly, the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program, and the computer program is used to execute the method for reducing delay in the embodiment of the present invention.

Those skilled in the art will appreciate that embodiments of the invention may be provided as a method, apparatus, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of a method, apparatus, apparatus, and computer program product according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, a special purpose computer, an embedded processor or other programmable data processing device to produce a machine such that Instructions executed by a processor of a computer or other programmable data processing device generate means for implementing the functions specified in a block or blocks of a flow or a flow and/or a block diagram of the flowchart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Industrial applicability

The method for reducing the delay in the embodiment of the present invention obtains the bandwidth information and the available space length of the FIFO; the bandwidth information is smaller than the first preset value or the available space length of the FIFO is smaller than the second preset. When the value is set, the scheduling of the received message is stopped. According to the above solution, according to the available space of the first-in first-out cache and the currently available bandwidth, it is timely determined and determined whether to schedule the message, and the stored message in the FIFO cache is sent as soon as possible, shortening the sending time, and making the new scheduling The waiting time of the packet is shortened, which effectively reduces the delay of packet scheduling and improves the QoS of the network service.

Claims

A method of reducing latency, the method comprising:

Get bandwidth information and the length of free space in the FIFO cache;

When the bandwidth information is smaller than the first preset value or the available space length of the FIFO is less than the second preset value, the scheduling of the received packet is stopped.
The method of reducing the delay according to claim 1, wherein after the stopping the scheduling of the received message, the method further comprises:

When the bandwidth information is smaller than the first preset value and the total length of the packet buffered by the FIFO is less than the third preset value, the received packet is scheduled, and the FIFO is kept in the FIFO. The total length of the stored packets does not exceed the third preset value.
The method of reducing latency according to claim 1, wherein the method further comprises:

When the bandwidth information is greater than or equal to the first preset value, the packet is read from the FIFO cache and sent.
The method of reducing the delay according to claim 1, wherein after the stopping the scheduling of the received message, the method further comprises:

The message received after stopping the scheduling is temporarily stored in the memory.
The method of reducing delay according to any one of claims 1 to 4, wherein the scheduling of the received message comprises:

High priority messages are stored first in the FIFO cache.
A device for reducing delay, the device comprising: an acquisition module and a scheduling module;

The obtaining module is configured to acquire bandwidth information and a free space length of the first in first out cache;

The scheduling module is configured to stop scheduling the received packet when the bandwidth information is smaller than the first preset value or the available space length of the FIFO is less than a second preset value.
The apparatus for reducing delay according to claim 6, wherein the scheduling module is further configured to: after the stopping scheduling the received message, the bandwidth information is smaller than a first preset value and When the total length of the packet buffered by the FIFO cache is less than the third preset value, the received packet is scheduled, and the total length of the packet stored in the FIFO cache does not exceed the third preset value. .
The apparatus for reducing time delay according to claim 6, wherein the apparatus further comprises:

The traffic management egress module is configured to read and send the packet from the FIFO cache when the bandwidth information is greater than or equal to the first preset value.
The apparatus for reducing delay according to claim 6, wherein the scheduling module is further configured to temporarily store the received message after stopping the scheduling into the memory after stopping the scheduling of the received message.
The apparatus for reducing delay according to claim 6, wherein the scheduling module is configured to preferentially store the high priority message to the FIFO cache.
A computer storage medium having stored therein computer executable instructions for performing the method of reducing latency according to any one of claims 1 to 5.