WO2018076294A1 - 防反接及电流反灌电路 - Google Patents

防反接及电流反灌电路 Download PDF

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Publication number
WO2018076294A1
WO2018076294A1 PCT/CN2016/103827 CN2016103827W WO2018076294A1 WO 2018076294 A1 WO2018076294 A1 WO 2018076294A1 CN 2016103827 W CN2016103827 W CN 2016103827W WO 2018076294 A1 WO2018076294 A1 WO 2018076294A1
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Prior art keywords
circuit
controllable switch
voltage
reverse
control
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Ceased
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PCT/CN2016/103827
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English (en)
French (fr)
Inventor
欧开锋
张生
杨振兴
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Hytera Communications Corp Ltd
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Hytera Communications Corp Ltd
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Priority to PCT/CN2016/103827 priority Critical patent/WO2018076294A1/zh
Publication of WO2018076294A1 publication Critical patent/WO2018076294A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection

Definitions

  • the present invention relates to the field of power supply technologies, and in particular, to an anti-reverse connection and current reverse irrigation circuit.
  • Low-power DC power supplies generally use diodes as anti-reverse or current-reverse circuits to prevent damage to the power supply and back-end circuits due to reverse power supply or current back-up, but as power increases, diode losses increase. , seriously affect the efficiency of the power supply.
  • the high-power power supply basically uses a metal oxide field effect transistor (MOSFET) or an integrated chip as an anti-reverse circuit, and the loss is small, but the cost of the integrated chip is high, and the MOSFET cost is low, but the circuit cannot be timely in the presence of current backflow. Turning off the MOSFET may cause the power supply to work abnormally or even risk the damage.
  • the current backflow of this circuit mainly comes from two aspects.
  • the technical problem to be solved by the present invention is to provide an anti-reverse connection and current reverse irrigation circuit to meet the demand of high-power power supply while reducing the cost and shutting down the circuit in time to prevent damage to the power supply and the back-end circuit.
  • a technical solution adopted by the present invention is to provide an anti-reverse connection and current reverse irrigation circuit, including:
  • a voltage input terminal connected to the first input terminal for receiving an input voltage
  • a voltage output end connected to the back end circuit for outputting a voltage to the back end circuit
  • control circuit connected to the voltage input terminal and the voltage output terminal, for receiving a voltage from the voltage input terminal and outputting a first control signal or a second control signal;
  • a switching circuit connected to the control circuit, the voltage output end and the second input end, for receiving the first control signal or the second control signal from the control circuit, the switch circuit receiving the Turning on when a control signal is turned on, and the switch circuit is turned off when receiving the second control signal;
  • An output circuit connecting the voltage input terminal, the control circuit, the switch circuit, the voltage output terminal and the second input terminal, when the first input terminal is connected to a positive pole of the power source and the second input
  • the control circuit outputs the first control signal to the switch circuit, the switch circuit is turned on, and the power source passes through the output circuit, the switch circuit, and the voltage Outputting an output voltage to the back end circuit; when the first input terminal is connected to a negative pole of the power source and the second input end is connected to a positive pole of the power source or a short circuit of a power source connected to the first and second input terminals
  • the output circuit pulls down the voltage supplied to the control circuit by the voltage input terminal such that the control circuit outputs the second control signal to the switch circuit, the switch circuit is turned off, the second input
  • the voltage at the terminal and the sink current are not supplied to the back end circuit through the switching circuit and the voltage output terminal.
  • the control circuit includes first and second resistors, first and second controllable switches, a first end of the first resistor is connected to the voltage input end, and a second end of the first resistor is connected to the second end a control end of the first controllable switch, a first end of the first controllable switch is connected to the voltage input end, and a second end of the first controllable switch is connected to a second end of the second controllable switch And the switch circuit, the first end of the second controllable switch is connected to the switch circuit and the voltage output end, and the control end of the second controllable switch is connected to the control of the first controllable switch And the first end of the second resistor, the second end of the second resistor is connected to the switch circuit and the voltage output end.
  • the first controllable switch is an NPN-type triode, and the control end, the first end and the second end of the first controllable switch respectively correspond to a base, a collector and an emitter of the NPN-type triode;
  • the second controllable switch is a PNP type transistor, and the control end, the first end and the second end of the second controllable switch respectively correspond to a base, a collector and an emitter of the PNP type transistor.
  • the switch circuit includes a third resistor, a third controllable switch, and a first diode, and the control end of the third controllable switch is connected to the first and second controllable switches via the third resistor
  • the second end of the third controllable switch is connected to the first end of the second controllable switch, the second end of the second resistor, and the voltage output end, the third a first end of the control switch is connected to the second input end, an anode of the first diode is connected to a second end of the third controllable switch, and a cathode of the first diode is connected to the third end The first end of the controllable switch.
  • the third controllable switch is an N-type MOS field effect transistor, and the control end, the first end and the second end of the third controllable switch respectively correspond to gates and drains of the N-type MOS field effect transistor Extreme and source.
  • the output circuit includes a fourth resistor, fourth and fifth controllable switches, second and third diodes, and a first end of the fourth resistor is connected to the voltage input end, and the fourth resistor
  • the second end is connected to the control end of the fourth controllable switch, the first end of the fourth controllable switch is connected to the second end of the first resistor, and the second end of the fourth controllable switch is connected
  • An anode of the second diode, a cathode of the second diode is connected to a second end of the third controllable switch, and a second end of the fifth controllable switch is connected to the fourth resistor a second end and a control end of the fourth controllable switch, the control end of the fifth controllable switch being connected to the first end of the fifth controllable switch and connected to the anode of the third diode
  • the cathode of the third diode is connected to the second input end and the first end of the third controllable switch.
  • the fourth controllable switch is an NPN-type triode, and the control end, the first end and the second end of the fourth controllable switch respectively correspond to a base, a collector and an emitter of the NPN-type triode;
  • the fifth controllable switch is a PNP type triode, and the control end, the first end and the second end of the fifth controllable switch respectively correspond to a base, a collector and an emitter of the PNP type triode.
  • the fourth controllable switch is an NPN-type triode, and the control end, the first end and the second end of the fourth controllable switch respectively correspond to a base, a collector and an emitter of the NPN-type triode;
  • the fifth controllable switch is a PNP type triode, and the control end, the first end and the second end of the fifth controllable switch respectively correspond to a base, an emitter and a collector of the PNP type triode.
  • the output circuit includes a fourth resistor, fourth and fifth controllable switches, second and third diodes, and a first end of the fourth resistor is connected to the voltage input end, and the fourth resistor
  • the second end is connected to the control end of the fourth controllable switch, the control end of the fifth controllable switch, and the first end of the fifth controllable switch, and the first end of the fourth controllable switch Connecting a second end of the first resistor, a second end of the fourth controllable switch is connected to an anode of the second diode, and a cathode of the second diode is connected to the third controllable switch
  • the second end of the fifth controllable switch is connected to the anode of the third diode, the cathode of the third diode is connected to the second input end and the third controllable The first end of the switch.
  • the fourth controllable switch is an NPN-type triode, and the control end, the first end and the second end of the fourth controllable switch respectively correspond to a base, a collector and an emitter of the NPN-type triode;
  • the fifth controllable switch is an NPN type triode, and the control end, the first end and the second end of the fifth controllable switch respectively correspond to a base, a collector and an emitter of the NPN type triode.
  • the fourth controllable switch is an NPN-type triode, and the control end, the first end and the second end of the fourth controllable switch respectively correspond to a base, a collector and an emitter of the NPN-type triode;
  • the fifth controllable switch is an NPN type triode, and the control end, the first end and the second end of the fifth controllable switch respectively correspond to a base, an emitter and a collector of the NPN type triode.
  • the output circuit further includes a fourth diode, an anode of the fourth diode is connected to a second end of the fourth resistor, and a cathode of the fourth diode is connected to the first resistor Second end.
  • the output circuit further includes a first capacitor, the first end of the first capacitor is connected to the voltage input end, and the second end of the first capacitor is connected to the second end of the third controllable switch.
  • the anti-reverse and current sink circuit further includes an auxiliary source, the input end of the auxiliary source is connected to the first input end, and the output end of the auxiliary source is connected to the voltage input end.
  • the anti-reverse and current sink circuit further includes a slow start circuit connected between the first input end and the voltage output end.
  • the anti-reverse connection and current reverse irrigation circuit further includes a DC voltage conversion circuit, and the DC voltage conversion circuit is connected to the slow start circuit.
  • the anti-reverse and current sink circuit further includes a second capacitor connected between the slow start circuit and the DC voltage conversion circuit.
  • the anti-reverse and current sinking circuit of the present invention provides the first and second control signals through the control circuit to control the switching circuit to be turned on or By cutting off, the output circuit is further controlled to provide a voltage to the back-end circuit to meet the demand of the high-power power supply while reducing the cost and shutting down the circuit in time to prevent the power supply from being reversed or the current back-fluxing damage the power supply and the back-end circuit. .
  • FIG. 1 is a circuit diagram of a first embodiment of an anti-reverse and current sink circuit of the present invention
  • Figure 2 is a circuit diagram of a second embodiment of the anti-reverse and current sink circuit of the present invention.
  • Figure 3 is a circuit diagram of a third embodiment of the anti-reverse and current sink circuit of the present invention.
  • Figure 4 is a circuit diagram of a fourth embodiment of the anti-reverse and current sink circuit of the present invention.
  • FIG. 1 is a circuit diagram of a first embodiment of the anti-reverse and current sink circuit of the present invention.
  • the anti-reverse connection and current reverse irrigation circuit includes a voltage input terminal VCC connected to the first input terminal for receiving an input voltage, and a voltage output terminal VOUT connected to the back end circuit for outputting a voltage to the device.
  • the control circuit 10 is connected to the voltage input terminal VCC and the voltage output terminal VOUT for receiving a voltage from the voltage input terminal VCC and outputting a first control signal or a second control signal; the switch circuit 20 Connecting the control circuit 10, the voltage output terminal VOUT, and the second input terminal for receiving the first control signal or the second control signal from the control circuit 10, and the switch circuit 20 receives the When the first control signal is turned on, the switch circuit 20 is turned off when receiving the second control signal; the output circuit 30 is connected to the voltage input terminal VCC, the control circuit 10, the switch circuit 20, the a voltage output terminal VOUT and the second input end, when the first input terminal is connected to the positive pole of the power source and the second input terminal is connected to the negative pole of the power source, the control circuit 10 outputs the first control signal Giving a switching circuit 20, the switching circuit 20 is turned on, the power supply outputs a voltage to the back end circuit through the output circuit 30, the switching circuit 20, and the voltage output terminal VOUT; when the first input When the terminal is connected to the negative pole of the power source
  • the control circuit 10 includes first and second resistors R1 and R2, first and second controllable switches T1 and T2, and a first end of the first resistor R1 is connected to the voltage input terminal VCC.
  • the second end of the first resistor R1 is connected to the control end of the first controllable switch T1, and the first end of the first controllable switch T1 is connected to the voltage input terminal VCC, the first controllable switch T1
  • the second end of the second controllable switch T2 is connected to the switch circuit 20, and the first end of the second controllable switch T2 is connected to the switch circuit 20 and the voltage output terminal VOUT.
  • the control end of the second controllable switch T2 is connected to the control end of the first controllable switch T1 and the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the switch circuit 20 and the voltage output terminal VOUT.
  • the first controllable switch T1 is an NPN-type triode, and the control end, the first end, and the second end of the first controllable switch T1 respectively correspond to a base and a set of the NPN-type triode An electrode and an emitter;
  • the second controllable switch T2 is a PNP type transistor, and the control end, the first end and the second end of the second controllable switch T2 respectively correspond to a base and a collector of the PNP type transistor And the emitter.
  • the switch circuit 20 includes a third resistor R3, a third controllable switch T3, and a first diode D1.
  • the control end of the third controllable switch T3 is connected to the first and the third via the third resistor R3.
  • the second end of the second controllable switch T1 is connected to the second end of the second controllable switch T2, the second end of the second controllable switch T2, and the second end of the second resistor R2 a voltage output terminal VOUT, a first end of the third controllable switch T3 is connected to the second input end, and an anode of the first diode D1 is connected to a second end of the third controllable switch T3.
  • the cathode of the first diode D1 is connected to the first end of the third controllable switch T3.
  • the third controllable switch T3 is an N-type MOS field effect transistor, and the control end, the first end, and the second end of the third controllable switch T3 respectively correspond to the N-type MOS field effect The gate, drain and source of the tube.
  • the first control signal received by the third controllable switch T3 is a high level signal
  • the second control signal received by the third controllable switch T3 is a low level signal.
  • the first diode D1 is a body diode of the third controllable switch T3, and the first diode D1 is packaged with the third controllable switch T3.
  • the output circuit 30 includes a fourth resistor R4, a fourth controllable switch T4, and a fifth controllable switch T5, a second diode D2, and a third diode D3.
  • the first end of the fourth resistor R4 is connected.
  • the second end of the fourth resistor R4 is connected to the control end of the fourth controllable switch T4, and the first end of the fourth controllable switch T4 is connected to the first resistor R1.
  • the second end of the fourth controllable switch T4 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the second of the third controllable switch T3
  • the second end of the fifth controllable switch T5 is connected to the second end of the fourth resistor R4 and the control end of the fourth controllable switch T4, and the control end of the fifth controllable switch T5 is connected.
  • a first end of the fifth controllable switch T5 is connected to an anode of the third diode D3, a cathode of the third diode D3 is connected to the second input end, and the third controllable The first end of the switch T3.
  • the fourth controllable switch T4 is an NPN-type triode, and the control end, the first end, and the second end of the fourth controllable switch T4 respectively correspond to a base and a set of the NPN-type triode An electrode and an emitter;
  • the fifth controllable switch T5 is a PNP type transistor, and the control end, the first end and the second end of the fifth controllable switch T5 respectively correspond to a base and a collector of the PNP type transistor And the emitter.
  • the fourth and fifth controllable switches T4 and T5 are integrated pairs of transistors, which are packaged together, and the second and third diodes D2 and D3 are integrated pairs of diodes, which are packaged together.
  • the output circuit 30 further includes a fourth diode D4, an anode of the fourth diode D4 is connected to a second end of the fourth resistor R4, and a cathode of the fourth diode D4 is connected to the first a second end of the resistor R1; the output circuit 30 further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the voltage input terminal VCC, and a second end of the first capacitor C1 is connected to the second end The second end of the third controllable switch T3.
  • the anti-reverse and current sink circuit further includes an auxiliary source 40, an input end of the auxiliary source 40 is connected to the first input end, and an output end of the auxiliary source 40 is connected to the voltage input terminal VCC;
  • the anti-reverse connection and current reversal circuit further includes a slow start circuit 50 connected between the first input end and the voltage output end VOUT; the anti-reverse connection and current reverse irrigation circuit further
  • the DC voltage conversion circuit 60 is connected to the slow start circuit 50;
  • the anti-reverse and current reverse circuit further includes a second capacitor C2, and the second capacitor C2 is connected to the
  • the startup circuit 50 is connected to the DC voltage conversion circuit 60.
  • the auxiliary source 40 is configured to supply a voltage of 12V to the voltage input terminal VCC
  • the DC voltage conversion circuit 60 is configured to adaptively convert a DC voltage to meet circuit requirements, the slow start circuit 50 and the DC voltage.
  • the conversion circuit 60 is a prior art, and is not described herein again.
  • the first capacitor C1 is a decoupling capacitor
  • the second capacitor C2 is a storage capacitor.
  • the control end of the first controllable switch T1 receives a high level signal.
  • the second controllable switch T2 is turned off, and the voltage input terminal VCC provides an output voltage of the power source (such as a high level signal) through the first controllable switch T1 and the third resistor R3.
  • the third controllable The first terminal voltage of the switch T3 is greater than the voltage of the second terminal thereof, that is, the third controllable switch T3 is a negative voltage drop, and then the voltage input terminal VCC passes the output voltage of the power source through the fourth The resistor R4, the fourth controllable switch T4, the second diode D2, and the voltage output terminal VOUT are provided to the back end circuit, and the fourth controllable switch T4 is forward biased and turned on.
  • the second controllable switch T2 is turned on such that the control terminal of the third controllable switch T3 receives a low level signal,
  • the third controllable switch T3 is turned off, thereby preventing the reverse voltage or the reverse current of the second input terminal from being supplied to the back end circuit through the third controllable switch T3 and the voltage output terminal VOUT, thereby achieving the protection circuit. purpose.
  • FIG. 2 is a circuit diagram of a second embodiment of the anti-reverse and current sink circuit of the present invention.
  • the second embodiment of the anti-reverse and current sink circuit differs from the first embodiment of the anti-reverse and current sink circuit in that: the fourth controllable switch T4 is an NPN-type triode, and the control end, the first end and the second end of the fourth controllable switch T4 respectively correspond to a base, a collector and an emitter of the NPN-type transistor; the fifth controllable switch T5 For the PNP type transistor, the control end, the first end and the second end of the fifth controllable switch T5 respectively correspond to the base, the emitter and the collector of the PNP type transistor.
  • FIG. 3 is a circuit diagram of a third embodiment of the anti-reverse and current sink circuit of the present invention.
  • the third embodiment of the anti-reverse and current sink circuit differs from the first embodiment of the anti-reverse and current sink circuit in that the output circuit 30 includes a fourth resistor R4, a fourth controllable switch T4 and a fifth controllable switch T5, a second diode D2 and a third diode D3, the first end of the fourth resistor R4 is connected to the voltage input terminal VCC, The second end of the fourth resistor R4 is connected to the control end of the fourth controllable switch T4, the control end of the fifth controllable switch T5, and the first end of the fifth controllable switch T5.
  • a first end of the fourth controllable switch T4 is connected to the second end of the first resistor R1, and a second end of the fourth controllable switch T4 is connected to the anode of the second diode D2, the second a cathode of the diode D2 is connected to the second end of the third controllable switch T3, and a second end of the fifth controllable switch T5 is connected to the anode of the third diode D3, the third diode
  • the cathode of the tube D3 is connected to the second input and the first end of the third controllable switch T3.
  • the fourth controllable switch T4 is an NPN-type triode, and the control end, the first end, and the second end of the fourth controllable switch T4 respectively correspond to a base and a set of the NPN-type triode An electrode and an emitter;
  • the fifth controllable switch T5 is an NPN type transistor, and the control end, the first end and the second end of the fifth controllable switch T5 respectively correspond to a base and a collector of the NPN transistor And the emitter.
  • FIG. 4 is a circuit diagram of a fourth embodiment of the anti-reverse and current sink circuit of the present invention.
  • the fourth embodiment of the anti-reverse and current sink circuit is different from the third embodiment of the anti-reverse and current sink circuit in that: the fourth controllable switch T4 is an NPN-type triode, and the control end, the first end and the second end of the fourth controllable switch T4 respectively correspond to a base, a collector and an emitter of the NPN-type transistor; the fifth controllable switch T5 For the NPN type transistor, the control end, the first end and the second end of the fifth controllable switch T5 respectively correspond to the base, the emitter and the collector of the NPN type transistor.
  • the anti-reverse connection and current back-flux circuit provides first and second control signals through the control circuit to control whether the switch circuit is turned on or off, thereby controlling whether the output circuit supplies a voltage to the back-end circuit to satisfy High-power power requirements reduce costs at the same time and can shut down the circuit in time to prevent damage to the power supply and back-end circuits caused by reverse power supply or current back-up.

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Abstract

一种防反接及电流反灌电路，包括电压输入端（VCC）；电压输出端（VOUT）；控制电路（10），输出第一或第二控制信号；开关电路（20），接收第一控制信号导通，接收第二控制信号截止；输出电路（30），当第一输入端连电源的正极且第二输入端连电源的负极时，电源输出电压给后端电路；当第一输入端连电源的负极且第二输入端连电源的正极或电源短路时，电压及反灌电流不会提供给后端电路。

Description

防反接及电流反灌电路
【技术领域】
本发明涉及电源技术领域，特别是涉及一种防反接及电流反灌电路。
【背景技术】
小功率直流电源一般都是用二极管作为防反接或电流反灌电路，来防止电源接反或电流反灌对电源及后端电路的损坏，但随着功率的增加，二极管的损耗会加大，严重影响电源的效率。大功率电源基本使用金属氧化物场效应管（MOSFET）或者集成芯片作为防反接电路，损耗较小，但集成芯片成本较高，MOSFET成本较低但这种电路在出现电流反灌时不能及时关断MOSFET，可能会导致电源工作异常，甚至有损坏的风险，这种电路的电流反灌主要来自两个方面，一个是电源突然短路，输入电容会通过输入端进行快速放电，从而形成电流反灌，在桥式电流同步整流中，可能会造成同步整流MOSFET漏源极电压急剧增大，损坏MOSFET，也有可能损坏电源；另一个是负向浪涌（-48V对电压输入回路浪涌）时可能会出现电流反灌的情形，导致电源掉电。
【发明内容】
本发明主要解决的技术问题是提供一种防反接及电流反灌电路，以满足大功率电源需求的同时降低成本且能及时关断电路，以防止对电源及后端电路造成损坏。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种防反接及电流反灌电路，包括：
电压输入端，连接第一输入端，用于接收输入电压；
电压输出端，连接后端电路，用于输出电压给所述后端电路；
控制电路，连接所述电压输入端及所述电压输出端，用于从所述电压输入端接收电压并输出第一控制信号或第二控制信号；
开关电路，连接所述控制电路、所述电压输出端及第二输入端，用于从所述控制电路接收所述第一控制信号或所述第二控制信号，所述开关电路接收所述第一控制信号时导通，所述开关电路接收所述第二控制信号时截止；
输出电路，连接所述电压输入端、所述控制电路、所述开关电路、所述电压输出端及所述第二输入端，当所述第一输入端连接电源的正极且所述第二输入端连接所述电源的负极时，所述控制电路输出所述第一控制信号给所述开关电路，所述开关电路导通，所述电源通过所述输出电路、所述开关电路及所述电压输出端输出电压给所述后端电路；当所述第一输入端连接电源的负极且所述第二输入端连接所述电源的正极或者与所述第一及第二输入端连接的电源短路时，所述输出电路拉低所述电压输入端提供给所述控制电路的电压使得所述控制电路输出所述第二控制信号给所述开关电路，所述开关电路截止，所述第二输入端的电压及反灌电流不会通过所述开关电路及所述电压输出端提供给所述后端电路。
其中，所述控制电路包括第一及第二电阻、第一及第二可控开关，所述第一电阻的第一端连接所述电压输入端，所述第一电阻的第二端连接所述第一可控开关的控制端，所述第一可控开关的第一端连接所述电压输入端，所述第一可控开关的第二端连接所述第二可控开关的第二端及所述开关电路，所述第二可控开关的第一端连接所述开关电路及所述电压输出端，所述第二可控开关的控制端连接所述第一可控开关的控制端及所述第二电阻的第一端，所述第二电阻的第二端连接所述开关电路及所述电压输出端。
其中，所述第一可控开关为NPN型三极管，所述第一可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第二可控开关为PNP型三极管，所述第二可控开关的控制端、第一端及第二端分别对应所述PNP型三极管的基极、集电极及发射极。
其中，所述开关电路包括第三电阻、第三可控开关及第一二极管，所述第三可控开关的控制端经所述第三电阻连接所述第一及第二可控开关的第二端，所述第三可控开关的第二端连接所述第二可控开关的第一端、所述第二电阻的第二端及所述电压输出端，所述第三可控开关的第一端连接所述第二输入端，所述第一二极管的阳极连接所述第三可控开关的第二端，所述第一二极管的阴极连接所述第三可控开关的第一端。
其中，所述第三可控开关为N型MOS场效应管，所述第三可控开关的控制端、第一端及第二端分别对应所述N型MOS场效应管的栅极、漏极及源极。
其中，所述输出电路包括第四电阻、第四及第五可控开关、第二及第三二极管，所述第四电阻的第一端连接所述电压输入端，所述第四电阻的第二端连接所述第四可控开关的控制端，所述第四可控开关的第一端连接所述第一电阻的第二端，所述第四可控开关的第二端连接所述第二二极管的阳极，所述第二二极管的阴极连接所述第三可控开关的第二端，所述第五可控开关的第二端连接所述第四电阻的第二端及所述第四可控开关的控制端，所述第五可控开关的控制端连接所述第五可控开关的第一端且连接至所述第三二极管的阳极，所述第三二极管的阴极连接所述第二输入端及所述第三可控开关的第一端。
其中，所述第四可控开关为NPN型三极管，所述第四可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关为PNP型三极管，所述第五可控开关的控制端、第一端及第二端分别对应所述PNP型三极管的基极、集电极及发射极。
其中，所述第四可控开关为NPN型三极管，所述第四可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关为PNP型三极管，所述第五可控开关的控制端、第一端及第二端分别对应所述PNP型三极管的基极、发射极及集电极。
其中，所述输出电路包括第四电阻、第四及第五可控开关、第二及第三二极管，所述第四电阻的第一端连接所述电压输入端，所述第四电阻的第二端连接所述第四可控开关的控制端、所述第五可控开关的控制端及所述第五可控开关的第一端，所述第四可控开关的第一端连接所述第一电阻的第二端，所述第四可控开关的第二端连接所述第二二极管的阳极，所述第二二极管的阴极连接所述第三可控开关的第二端，所述第五可控开关的第二端连接所述第三二极管的阳极，所述第三二极管的阴极连接所述第二输入端及所述第三可控开关的第一端。
其中，所述第四可控开关为NPN型三极管，所述第四可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关为NPN型三极管，所述第五可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极。
其中，所述第四可控开关为NPN型三极管，所述第四可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关为NPN型三极管，所述第五可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、发射极及集电极。
其中，所述输出电路还包括第四二极管，所述第四二极管的阳极连接所述第四电阻的第二端，所述第四二极管的阴极连接所述第一电阻的第二端。
其中，所述输出电路还包括第一电容，所述第一电容的第一端连接所述电压输入端，所述第一电容的第二端连接所述第三可控开关的第二端。
其中，所述防反接及电流反灌电路还包括辅助源，所述辅助源的输入端连接所述第一输入端，所述辅助源的输出端连接所述电压输入端。
其中，所述防反接及电流反灌电路还包括缓启动电路，所述缓启动电路连接在所述第一输入端与所述电压输出端之间。
其中，所述防反接及电流反灌电路还包括直流电压转换电路，所述直流电压转换电路连接所述缓启动电路。
其中，所述防反接及电流反灌电路还包括第二电容，所述第二电容连接在所述缓启动电路与所述直流电压转换电路之间。
本发明的有益效果是：区别于现有技术的情况，本发明的所述防反接及电流反灌电路通过所述控制电路提供第一及第二控制信号来控制所述开关电路导通或者截止，进而控制所述输出电路是否提供电压给后端电路，以满足大功率电源需求的同时降低成本且能及时关断电路，以防止电源接反或者电流反灌对电源及后端电路造成损坏。
【附图说明】
图1是本发明的防反接及电流反灌电路的第一实施例的电路图；
图2是本发明的防反接及电流反灌电路的第二实施例的电路图；
图3是本发明的防反接及电流反灌电路的第三实施例的电路图；
图4是本发明的防反接及电流反灌电路的第四实施例的电路图。
【具体实施方式】
请参阅图1，是本发明的防反接及电流反灌电路的第一实施例的电路图。如图1所示，所述防反接及电流反灌电路包括电压输入端VCC，连接第一输入端，用于接收输入电压；电压输出端VOUT，连接后端电路，用于输出电压给所述后端电路；控制电路10，连接所述电压输入端VCC及所述电压输出端VOUT，用于从所述电压输入端VCC接收电压并输出第一控制信号或第二控制信号；开关电路20，连接所述控制电路10、所述电压输出端VOUT及第二输入端，用于从所述控制电路10接收所述第一控制信号或所述第二控制信号，所述开关电路20接收所述第一控制信号时导通，所述开关电路20接收所述第二控制信号时截止；输出电路30，连接所述电压输入端VCC、所述控制电路10、所述开关电路20、所述电压输出端VOUT及所述第二输入端，当所述第一输入端连接电源的正极且所述第二输入端连接所述电源的负极时，所述控制电路10输出所述第一控制信号给所述开关电路20，所述开关电路20导通，所述电源通过所述输出电路30、所述开关电路20及所述电压输出端VOUT输出电压给所述后端电路；当所述第一输入端连接电源的负极且所述第二输入端连接所述电源的正极或者与所述第一及第二输入端连接的电源短路时，所述输出电路30拉低所述电压输入端VCC提供给所述控制电路10的电压使得所述控制电路10输出所述第二控制信号给所述开关电路20，所述开关电路20截止，所述电源不会通过所述开关电路20及所述电压输出端VOUT输出电压给所述后端电路。
具体地，所述控制电路10包括第一及第二电阻R1、R2、第一及第二可控开关T1、T2，所述第一电阻R1的第一端连接所述电压输入端VCC，所述第一电阻R1的第二端连接所述第一可控开关T1的控制端，所述第一可控开关T1的第一端连接所述电压输入端VCC，所述第一可控开关T1的第二端连接所述第二可控开关T2的第二端及所述开关电路20，所述第二可控开关T2的第一端连接所述开关电路20及所述电压输出端VOUT，所述第二可控开关T2的控制端连接所述第一可控开关T1的控制端及所述第二电阻R2的第一端，所述第二电阻R2的第二端连接所述开关电路20及所述电压输出端VOUT。
在本实施例中，所述第一可控开关T1为NPN型三极管，所述第一可控开关T1的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第二可控开关T2为PNP型三极管，所述第二可控开关T2的控制端、第一端及第二端分别对应所述PNP型三极管的基极、集电极及发射极。
所述开关电路20包括第三电阻R3、第三可控开关T3及第一二极管D1，所述第三可控开关T3的控制端经所述第三电阻R3连接所述第一及第二可控开关T1及T2的第二端，所述第三可控开关T3的第二端连接所述第二可控开关T2的第一端、所述第二电阻R2的第二端及所述电压输出端VOUT，所述第三可控开关T3的第一端连接所述第二输入端，所述第一二极管D1的阳极连接所述第三可控开关T3的第二端，所述第一二极管D1的阴极连接所述第三可控开关T3的第一端。
在本实施例中，所述第三可控开关T3为N型MOS场效应管，所述第三可控开关T3的控制端、第一端及第二端分别对应所述N型MOS场效应管的栅极、漏极及源极。其中，所述第三可控开关T3接收到的所述第一控制信号为高电平信号，所述第三可控开关T3接收到的所述第二控制信号为低电平信号。其中，所述第一二极管D1是所述第三可控开关T3的体二极管，所述第一二极管D1与所述第三可控开关T3封装在一起。
所述输出电路30包括第四电阻R4、第四可控开关T4及第五可控开关T5、第二二极管D2及第三二极管D3，所述第四电阻R4的第一端连接所述电压输入端VCC，所述第四电阻R4的第二端连接所述第四可控开关T4的控制端，所述第四可控开关T4的第一端连接所述第一电阻R1的第二端，所述第四可控开关T4的第二端连接所述第二二极管D2的阳极，所述第二二极管D2的阴极连接所述第三可控开关T3的第二端，所述第五可控开关T5的第二端连接所述第四电阻R4的第二端及所述第四可控开关T4的控制端，所述第五可控开关T5的控制端连接所述第五可控开关T5的第一端且连接至所述第三二极管D3的阳极，所述第三二极管D3的阴极连接所述第二输入端及所述第三可控开关T3的第一端。
在本实施例中，所述第四可控开关T4为NPN型三极管，所述第四可控开关T4的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关T5为PNP型三极管，所述第五可控开关T5的控制端、第一端及第二端分别对应所述PNP型三极管的基极、集电极及发射极。其中，所述第四及第五可控开关T4及T5为集成对三极管，其封装在一起，所述第二及第三二极管D2及D3为集成对二极管，其封装在一起。
所述输出电路30还包括第四二极管D4，所述第四二极管D4的阳极连接所述第四电阻R4的第二端，所述第四二极管D4的阴极连接所述第一电阻R1的第二端；所述输出电路30还包括第一电容C1，所述第一电容C1的第一端连接所述电压输入端VCC，所述第一电容C1的第二端连接所述第三可控开关T3的第二端。
所述防反接及电流反灌电路还包括辅助源40，所述辅助源40的输入端连接所述第一输入端，所述辅助源40的输出端连接所述电压输入端VCC；所述防反接及电流反灌电路还包括缓启动电路50，所述缓启动电路50连接在所述第一输入端与所述电压输出端VOUT之间；所述防反接及电流反灌电路还包括直流电压转换电路60，所述直流电压转换电路60连接所述缓启动电路50；所述防反接及电流反灌电路还包括第二电容C2，所述第二电容C2连接在所述缓启动电路50与所述直流电压转换电路60之间。所述辅助源40用于提供12V电压给所述电压输入端VCC，所述直流电压转换电路60用于对直流电压进行适应性转换以满足电路需求，所述缓启动电路50及所述直流电压转换电路60均为现有技术，在此不再赘述，所述第一电容C1为去耦电容，所述第二电容C2为储能电容。
所述防反接及电流反灌电路的工作原理描述如下：
当所述第一输入端连接电源正极且所述第二输入端连接所述电源负极时，即所述电源正常接入时，所述第一可控开关T1的控制端接收高电平信号而导通，所述第二可控开关T2截止，所述电压输入端VCC将所述电源的输出电压（如高电平信号）通过所述第一可控开关T1及所述第三电阻R3提供给所述第三可控开关T3的控制端，所述第三可控开关T3导通，电流从所述第三可控开关T3的第二端流向第一端，因为此时所述第三可控开关T3为正向压降，则所述电压输入端VCC将所述电源的输出电压通过所述第四电阻R4、所述第五可控开关T5、所述第三二极管D3、所述第三可控开关T3及所述电压输出端VOUT提供给后端电路，此时所述第四可控开关T4处以截止或非饱和导通状态，因此所述第三可控开关T3维持电路稳定工作。
当所述第一输入端连接电源负极且所述第二输入端连接所述电源正极时，即所述电源反接时或者有电流反灌（如电源短路）时，则所述第三可控开关T3的第一端电压大于其第二端电压，即所述第三可控开关T3为负向压降，则此时所述电压输入端VCC将所述电源的输出电压通过所述第四电阻R4、所述第四可控开关T4、所述第二二极管D2及所述电压输出端VOUT提供给后端电路，此时所述第四可控开关T4正向偏置导通拉低所述第一及第二可控开关T1及T2的控制端的电压，所述第二可控开关T2导通从而使得所述第三可控开关T3的控制端接收低电平信号，所述第三可控开关T3截止，从而防止所述第二输入端的反接电压或者反灌电流通过所述第三可控开关T3及所述电压输出端VOUT提供给后端电路，进而达到保护电路的目的。
请参阅图2，是本发明的防反接及电流反灌电路的第二实施例的电路图。如图2所示，所述防反接及电流反灌电路的第二实施例与所述防反接及电流反灌电路的第一实施例的区别之处在于：所述第四可控开关T4为NPN型三极管，所述第四可控开关T4的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关T5为PNP型三极管，所述第五可控开关T5的控制端、第一端及第二端分别对应所述PNP型三极管的基极、发射极及集电极。
请参阅图3，是本发明的防反接及电流反灌电路的第三实施例的电路图。如图3所示，所述防反接及电流反灌电路的第三实施例与所述防反接及电流反灌电路的第一实施例的区别之处在于：所述输出电路30包括第四电阻R4、第四可控开关T4及第五可控开关T5、第二二极管D2及第三二极管D3，所述第四电阻R4的第一端连接所述电压输入端VCC，所述第四电阻R4的第二端连接所述第四可控开关T4的控制端、所述第五可控开关T5的控制端及所述第五可控开关T5的第一端，所述第四可控开关T4的第一端连接所述第一电阻R1的第二端，所述第四可控开关T4的第二端连接所述第二二极管D2的阳极，所述第二二极管D2的阴极连接所述第三可控开关T3的第二端，所述第五可控开关T5的第二端连接所述第三二极管D3的阳极，所述第三二极管D3的阴极连接所述第二输入端及所述第三可控开关T3的第一端。
在本实施例中，所述第四可控开关T4为NPN型三极管，所述第四可控开关T4的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关T5为NPN型三极管，所述第五可控开关T5的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极。
请参阅图4，是本发明的防反接及电流反灌电路的第四实施例的电路图。如图4所示，所述防反接及电流反灌电路的第四实施例与所述防反接及电流反灌电路的第三实施例的区别之处在于：所述第四可控开关T4为NPN型三极管，所述第四可控开关T4的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关T5为NPN型三极管，所述第五可控开关T5的控制端、第一端及第二端分别对应所述NPN型三极管的基极、发射极及集电极。
其中，所述防反接及电流反灌电路的第二至第四实施例的工作原理与上述第一实施例的工作原理相同，在此不再一一赘述。
所述防反接及电流反灌电路通过所述控制电路提供第一及第二控制信号来控制所述开关电路导通或者截止，进而控制所述输出电路是否提供电压给后端电路，以满足大功率电源需求的同时降低成本且能及时关断电路，以防止电源接反或者电流反灌对电源及后端电路造成损坏。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种防反接及电流反灌电路，其中，所述防反接及电流反灌电路包括：
    电压输入端，连接第一输入端，用于接收输入电压；
    电压输出端，连接后端电路，用于输出电压给所述后端电路；
    控制电路，连接所述电压输入端及所述电压输出端，用于从所述电压输入端接收电压并输出第一控制信号或第二控制信号；
    开关电路，连接所述控制电路、所述电压输出端及第二输入端，用于从所述控制电路接收所述第一控制信号或所述第二控制信号，所述开关电路接收所述第一控制信号时导通，所述开关电路接收所述第二控制信号时截止；
    输出电路，连接所述电压输入端、所述控制电路、所述开关电路、所述电压输出端及所述第二输入端，当所述第一输入端连接电源的正极且所述第二输入端连接所述电源的负极时，所述控制电路输出所述第一控制信号给所述开关电路，所述开关电路导通，所述电源通过所述输出电路、所述开关电路及所述电压输出端输出电压给所述后端电路；当所述第一输入端连接电源的负极且所述第二输入端连接所述电源的正极或者与所述第一及第二输入端连接的电源短路时，所述输出电路拉低所述电压输入端提供给所述控制电路的电压使得所述控制电路输出所述第二控制信号给所述开关电路，所述开关电路截止，所述第二输入端的电压及反灌电流不会通过所述开关电路及所述电压输出端提供给所述后端电路。
  2. 根据权利要求1所述的防反接及电流反灌电路，其中，所述控制电路包括第一及第二电阻、第一及第二可控开关，所述第一电阻的第一端连接所述电压输入端，所述第一电阻的第二端连接所述第一可控开关的控制端，所述第一可控开关的第一端连接所述电压输入端，所述第一可控开关的第二端连接所述第二可控开关的第二端及所述开关电路，所述第二可控开关的第一端连接所述开关电路及所述电压输出端，所述第二可控开关的控制端连接所述第一可控开关的控制端及所述第二电阻的第一端，所述第二电阻的第二端连接所述开关电路及所述电压输出端。
  3. 根据权利要求2所述的防反接及电流反灌电路，其中，所述第一可控开关为NPN型三极管，所述第一可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第二可控开关为PNP型三极管，所述第二可控开关的控制端、第一端及第二端分别对应所述PNP型三极管的基极、集电极及发射极。
  4. 根据权利要求2所述的防反接及电流反灌电路，其中，所述开关电路包括第三电阻、第三可控开关及第一二极管，所述第三可控开关的控制端经所述第三电阻连接所述第一及第二可控开关的第二端，所述第三可控开关的第二端连接所述第二可控开关的第一端、所述第二电阻的第二端及所述电压输出端，所述第三可控开关的第一端连接所述第二输入端，所述第一二极管的阳极连接所述第三可控开关的第二端，所述第一二极管的阴极连接所述第三可控开关的第一端。
  5. 根据权利要求4所述的防反接及电流反灌电路，其中，所述第三可控开关为N型MOS场效应管，所述第三可控开关的控制端、第一端及第二端分别对应所述N型MOS场效应管的栅极、漏极及源极。
  6. 根据权利要求4所述的防反接及电流反灌电路，其中，所述输出电路包括第四电阻、第四及第五可控开关、第二及第三二极管，所述第四电阻的第一端连接所述电压输入端，所述第四电阻的第二端连接所述第四可控开关的控制端，所述第四可控开关的第一端连接所述第一电阻的第二端，所述第四可控开关的第二端连接所述第二二极管的阳极，所述第二二极管的阴极连接所述第三可控开关的第二端，所述第五可控开关的第二端连接所述第四电阻的第二端及所述第四可控开关的控制端，所述第五可控开关的控制端连接所述第五可控开关的第一端且连接至所述第三二极管的阳极，所述第三二极管的阴极连接所述第二输入端及所述第三可控开关的第一端。
  7. 根据权利要求6所述的防反接及电流反灌电路，其中，所述第四可控开关为NPN型三极管，所述第四可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关为PNP型三极管，所述第五可控开关的控制端、第一端及第二端分别对应所述PNP型三极管的基极、集电极及发射极。
  8. 根据权利要求6所述的防反接及电流反灌电路，其中，所述第四可控开关为NPN型三极管，所述第四可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关为PNP型三极管，所述第五可控开关的控制端、第一端及第二端分别对应所述PNP型三极管的基极、发射极及集电极。
  9. 根据权利要求4所述的防反接及电流反灌电路，其中，所述输出电路包括第四电阻、第四及第五可控开关、第二及第三二极管，所述第四电阻的第一端连接所述电压输入端，所述第四电阻的第二端连接所述第四可控开关的控制端、所述第五可控开关的控制端及所述第五可控开关的第一端，所述第四可控开关的第一端连接所述第一电阻的第二端，所述第四可控开关的第二端连接所述第二二极管的阳极，所述第二二极管的阴极连接所述第三可控开关的第二端，所述第五可控开关的第二端连接所述第三二极管的阳极，所述第三二极管的阴极连接所述第二输入端及所述第三可控开关的第一端。
  10. 根据权利要求9所述的防反接及电流反灌电路，其中，所述第四可控开关为NPN型三极管，所述第四可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关为NPN型三极管，所述第五可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极。
  11. 根据权利要求9所述的防反接及电流反灌电路，其中，所述第四可控开关为NPN型三极管，所述第四可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、集电极及发射极；所述第五可控开关为NPN型三极管，所述第五可控开关的控制端、第一端及第二端分别对应所述NPN型三极管的基极、发射极及集电极。
  12. 根据权利要求6或9所述的防反接及电流反灌电路，其中，所述输出电路还包括第四二极管，所述第四二极管的阳极连接所述第四电阻的第二端，所述第四二极管的阴极连接所述第一电阻的第二端。
  13. 根据权利要求6或9所述的防反接及电流反灌电路，其中，所述输出电路还包括第一电容，所述第一电容的第一端连接所述电压输入端，所述第一电容的第二端连接所述第三可控开关的第二端。
  14. 根据权利要求1所述的防反接及电流反灌电路，其中，所述防反接及电流反灌电路还包括辅助源，所述辅助源的输入端连接所述第一输入端，所述辅助源的输出端连接所述电压输入端。
  15. 根据权利要求1所述的防反接及电流反灌电路，其中，所述防反接及电流反灌电路还包括缓启动电路，所述缓启动电路连接在所述第一输入端与所述电压输出端之间。
  16. 根据权利要求1所述的防反接及电流反灌电路，其中，所述防反接及电流反灌电路还包括直流电压转换电路，所述直流电压转换电路连接所述缓启动电路。
  17. 根据权利要求1所述的防反接及电流反灌电路，其中，所述防反接及电流反灌电路还包括第二电容，所述第二电容连接在所述缓启动电路与所述直流电压转换电路之间。
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