WO2018071143A3 - 3d semiconductor device and structure - Google Patents

3d semiconductor device and structure Download PDF

Info

Publication number
WO2018071143A3
WO2018071143A3 PCT/US2017/052359 US2017052359W WO2018071143A3 WO 2018071143 A3 WO2018071143 A3 WO 2018071143A3 US 2017052359 W US2017052359 W US 2017052359W WO 2018071143 A3 WO2018071143 A3 WO 2018071143A3
Authority
WO
WIPO (PCT)
Prior art keywords
bitlines
bit
cell array
rows
independent
Prior art date
Application number
PCT/US2017/052359
Other languages
French (fr)
Other versions
WO2018071143A2 (en
Inventor
Zvi Or-Bach
Jin-Woo Han
Brian Cronquist
Eli Lusky
Original Assignee
Monolithic 3D Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to CN201780061048.5A priority Critical patent/CN109952643B/en
Priority to US16/337,665 priority patent/US10991675B2/en
Priority to EP17859869.4A priority patent/EP3523825A4/en
Application filed by Monolithic 3D Inc. filed Critical Monolithic 3D Inc.
Publication of WO2018071143A2 publication Critical patent/WO2018071143A2/en
Publication of WO2018071143A3 publication Critical patent/WO2018071143A3/en
Priority to US17/214,883 priority patent/US11107803B2/en
Priority to US17/372,476 priority patent/US11158598B1/en
Priority to US17/485,504 priority patent/US11251149B2/en
Priority to US17/567,049 priority patent/US11329059B1/en
Priority to US17/712,875 priority patent/US11482541B2/en
Priority to US17/949,988 priority patent/US11621240B2/en
Priority to US18/105,856 priority patent/US11711928B2/en
Priority to US18/206,040 priority patent/US11812620B2/en
Priority to US18/239,117 priority patent/US11869591B2/en
Priority to US18/388,840 priority patent/US11930648B1/en
Priority to US18/431,177 priority patent/US12041791B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A 3D device, the device comprising: a first stratum comprising a first bit-cell array, the first bit-cell array includes three independent first rows; a second stratum including a second bit-cell array, the second bitcell array includes three independent second rows, where the second stratum overlays the first stratum; and at least three vertical bitlines each connected to respective three horizontal first bitlines and three horizontal second bitlines, where the three horizontal first bitlines include control of the first bit-cell array, where the three horizontal second bitlines include control of the second bit-cell array, and where each of the three vertical bitlines could be used to control a different one of the three independent first rows, or control a different one of the three independent second rows
PCT/US2017/052359 2016-10-10 2017-09-19 3d semiconductor device and structure WO2018071143A2 (en)

Priority Applications (14)

Application Number Priority Date Filing Date Title
CN201780061048.5A CN109952643B (en) 2016-10-10 2017-09-19 3D semiconductor device and structure
US16/337,665 US10991675B2 (en) 2016-10-10 2017-09-19 3D semiconductor device and structure
EP17859869.4A EP3523825A4 (en) 2016-10-10 2017-09-19 3d semiconductor device and structure
US17/214,883 US11107803B2 (en) 2016-10-10 2021-03-28 Method to construct 3D devices and systems
US17/372,476 US11158598B1 (en) 2016-10-10 2021-07-11 Method to construct 3D devices and systems
US17/485,504 US11251149B2 (en) 2016-10-10 2021-09-27 3D memory device and structure
US17/567,049 US11329059B1 (en) 2016-10-10 2021-12-31 3D memory devices and structures with thinned single crystal substrates
US17/712,875 US11482541B2 (en) 2016-10-10 2022-04-04 3D memory devices and structures with multiple memory levels
US17/949,988 US11621240B2 (en) 2016-10-10 2022-09-21 3D memory devices and structures with control circuits
US18/105,856 US11711928B2 (en) 2016-10-10 2023-02-05 3D memory devices and structures with control circuits
US18/206,040 US11812620B2 (en) 2016-10-10 2023-06-05 3D DRAM memory devices and structures with control circuits
US18/239,117 US11869591B2 (en) 2016-10-10 2023-08-28 3D memory devices and structures with control circuits
US18/388,840 US11930648B1 (en) 2016-10-10 2023-11-12 3D memory devices and structures with metal layers
US18/431,177 US12041791B2 (en) 2016-10-10 2024-02-02 3D memory devices and structures with memory arrays and metal layers

Applications Claiming Priority (26)

Application Number Priority Date Filing Date Title
US201662406376P 2016-10-10 2016-10-10
US62/406,376 2016-10-10
US201662432575P 2016-12-11 2016-12-11
US62/432,575 2016-12-11
US201662440720P 2016-12-30 2016-12-30
US62/440,720 2016-12-30
US201762457838P 2017-02-11 2017-02-11
US62/457,838 2017-02-11
US201762460989P 2017-02-20 2017-02-20
US62/460,989 2017-02-20
US201762471963P 2017-03-16 2017-03-16
US62/471,963 2017-03-16
US201762480529P 2017-04-02 2017-04-02
US62/480,529 2017-04-02
US201762484398P 2017-04-12 2017-04-12
US62/484,398 2017-04-12
US201762488821P 2017-04-23 2017-04-23
US62/488,821 2017-04-23
US201762517152P 2017-06-08 2017-06-08
US62/517,152 2017-06-08
US201762530173P 2017-07-08 2017-07-08
US62/530,173 2017-07-08
US201762535265P 2017-07-21 2017-07-21
US62/535,265 2017-07-21
US201762549952P 2017-08-24 2017-08-24
US62/549,952 2017-08-24

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US62406376 Continuation-In-Part 2016-10-10

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US16/337,665 A-371-Of-International US10991675B2 (en) 2016-10-10 2017-09-19 3D semiconductor device and structure
US17/214,883 Continuation-In-Part US11107803B2 (en) 2016-10-10 2021-03-28 Method to construct 3D devices and systems

Publications (2)

Publication Number Publication Date
WO2018071143A2 WO2018071143A2 (en) 2018-04-19
WO2018071143A3 true WO2018071143A3 (en) 2018-07-26

Family

ID=61905833

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2017/052359 WO2018071143A2 (en) 2016-10-10 2017-09-19 3d semiconductor device and structure

Country Status (3)

Country Link
EP (1) EP3523825A4 (en)
CN (1) CN109952643B (en)
WO (1) WO2018071143A2 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10839872B2 (en) * 2018-07-03 2020-11-17 Ememory Technology Inc. Random bit cell using an initial state of a latch to generate a random bit
US10847236B2 (en) * 2018-10-17 2020-11-24 Ememory Technology Inc. Memory cell with a sensing control circuit
KR102683652B1 (en) * 2018-11-09 2024-07-11 에스케이하이닉스 주식회사 Vertical memory device and method for manufacturing the same
US10861722B2 (en) * 2018-11-13 2020-12-08 Applied Materials, Inc. Integrated semiconductor processing
US10741535B1 (en) * 2019-02-14 2020-08-11 Sandisk Technologies Llc Bonded assembly containing multiple memory dies sharing peripheral circuitry on a support die and methods for making the same
CN110024126B (en) * 2019-02-26 2020-06-26 长江存储科技有限责任公司 Three-dimensional memory device and method of forming the same
KR20210119509A (en) * 2019-04-30 2021-10-05 양쯔 메모리 테크놀로지스 씨오., 엘티디. 3D memory device with embedded dynamic random access memory
CN110530969B (en) * 2019-08-14 2021-05-25 江苏大学 Preparation process of graphene resonant gas sensor based on doped metal atoms
CN113451269B (en) * 2020-03-25 2022-07-22 长鑫存储技术有限公司 Word line structure and semiconductor memory
US11856781B2 (en) * 2020-07-22 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
US11704271B2 (en) * 2020-08-20 2023-07-18 Alibaba Group Holding Limited Scalable system-in-package architectures
US11232824B1 (en) 2020-12-11 2022-01-25 International Business Machines Corporation Non-volatile analog resistive memory cells implementing ferroelectric select transistors
CN112687522B (en) * 2020-12-24 2024-08-30 上海集成电路研发中心有限公司 Amorphous germanium-silicon film structure, integrated structure and manufacturing method
US11545220B2 (en) * 2020-12-29 2023-01-03 Micron Technology, Inc. Split-gate memory cells
EP4024222A1 (en) 2021-01-04 2022-07-06 Imec VZW An integrated circuit with 3d partitioning
CN112768366B (en) * 2021-01-22 2024-02-23 长江存储科技有限责任公司 Semiconductor structure and preparation method thereof
KR20220150552A (en) * 2021-05-04 2022-11-11 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof
CN113782461B (en) * 2021-08-20 2024-04-09 长江存储科技有限责任公司 Method for testing semiconductor structure and test sample
JP2023041280A (en) * 2021-09-13 2023-03-24 キオクシア株式会社 Storage device
KR20230085675A (en) * 2021-12-07 2023-06-14 삼성전자주식회사 Semiconductor memory device and method for fabricating the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100259960A1 (en) * 2009-04-08 2010-10-14 George Samachisa Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines
US8581349B1 (en) * 2011-05-02 2013-11-12 Monolithic 3D Inc. 3D memory semiconductor device and structure
US20150076668A1 (en) * 2013-09-17 2015-03-19 Macronix International Co., Ltd. Conductor with a plurality of vertical extensions for a 3d device
US20150162311A1 (en) * 2013-12-05 2015-06-11 International Business Machines Corporation Multiple active vertically aligned cores for three-dimensional chip stack
US20160218046A1 (en) * 2013-03-12 2016-07-28 Monolithic 3D Inc. Semiconductor device and structure

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7291878B2 (en) * 2003-06-03 2007-11-06 Hitachi Global Storage Technologies Netherlands B.V. Ultra low-cost solid-state memory
DE102007008530B4 (en) * 2007-02-21 2015-11-12 Infineon Technologies Ag A method of manufacturing a nonvolatile memory device, a nonvolatile memory device, a memory card having a nonvolatile memory device, and an electrical device having a memory card
US7897431B2 (en) * 2008-02-01 2011-03-01 Promos Technologies, Inc. Stacked semiconductor device and method
US8754533B2 (en) * 2009-04-14 2014-06-17 Monolithic 3D Inc. Monolithic three-dimensional semiconductor device and structure
EP2599112A4 (en) * 2010-07-30 2017-07-26 MonolithIC 3D S.A. Semiconductor device and structure
US8630114B2 (en) * 2011-01-19 2014-01-14 Macronix International Co., Ltd. Memory architecture of 3D NOR array
US8724393B2 (en) * 2011-05-02 2014-05-13 Macronix International Co., Ltd. Thermally assisted flash memory with diode strapping
US8574929B1 (en) * 2012-11-16 2013-11-05 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US9023688B1 (en) * 2013-06-09 2015-05-05 Monolithic 3D Inc. Method of processing a semiconductor device
KR102192539B1 (en) * 2014-05-21 2020-12-18 삼성전자주식회사 Semiconductor Device and program method of the same
KR102275540B1 (en) * 2014-12-18 2021-07-13 삼성전자주식회사 Variable Resistance memory device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100259960A1 (en) * 2009-04-08 2010-10-14 George Samachisa Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines
US8581349B1 (en) * 2011-05-02 2013-11-12 Monolithic 3D Inc. 3D memory semiconductor device and structure
US20160218046A1 (en) * 2013-03-12 2016-07-28 Monolithic 3D Inc. Semiconductor device and structure
US20150076668A1 (en) * 2013-09-17 2015-03-19 Macronix International Co., Ltd. Conductor with a plurality of vertical extensions for a 3d device
US20150162311A1 (en) * 2013-12-05 2015-06-11 International Business Machines Corporation Multiple active vertically aligned cores for three-dimensional chip stack

Also Published As

Publication number Publication date
CN109952643A (en) 2019-06-28
CN109952643B (en) 2024-05-31
WO2018071143A2 (en) 2018-04-19
EP3523825A4 (en) 2020-09-09
EP3523825A2 (en) 2019-08-14

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