WO2018066662A1 - Method for producing silicon carbide semiconductor device - Google Patents

Abstract

When a portion of a p-type SiC layer (50) for forming a p-type deep layer (5), said portion being formed above the surface of an n⁺-type source region (4), is removed, a sacrificial layer (60) having fluidity is formed on the p-type SiC layer (50). Since the surface of the sacrificial layer (60) is in a flat state due to the fluidity, the p-type SiC layer (50) is etched back together with the sacrificial layer (60) so that the etching selectivity thereof is 1. Consequently, the p-type SiC layer (50) is able to be removed so as to have a flat surface. Consequently, a method for producing an SiC semiconductor device according to the present invention is capable of enabling the n⁺-type source region (4) and the p-type deep layer (5) to have flat surfaces after the etching back step by a simpler process.

Description

Method for manufacturing silicon carbide semiconductor device Cross-reference to related applications

This application is based on Japanese Patent Application No. 2016-197414 filed on October 5, 2016 and Japanese Patent Application No. 2017-179442 filed on September 19, 2017, the contents of which are described herein. Is incorporated by reference.

The present disclosure relates to a method for manufacturing a silicon carbide (hereinafter referred to as SiC) semiconductor device.

Conventionally, there is an SiC semiconductor device having a structure in which a trench is formed in a base layer made of SiC and then a SiC layer is embedded only in the trench. As a manufacturing method of such a structure, in Non-Patent Document 1, after performing buried epitaxial growth so that the trench formed in the underlayer is filled with the SiC layer, it is further formed on the surface of the underlayer of the SiC layer. There has been proposed a method of removing the uneven portion and flattening. More specifically, the surface of the SiC layer is planarized by the following manufacturing method.

First, after forming a trench in the base layer, buried epitaxial growth is performed so as to fill the trench with a SiC layer. At this time, the surface of the SiC layer has a concave-convex shape that is recessed at a position corresponding to the portion embedded in the trench and protrudes at a portion where the trench is not formed. Therefore, if the SiC layer is simply etched back to remove the portion of the SiC layer formed above the surface of the underlying layer, surface irregularities remain, and the surface of the SiC layer becomes flat. I can't plan.

For this reason, LTO (abbreviation of Low-Temperature Oxidation) is formed so as to cover the surface of the SiC layer, and further, a polymer film is formed so as to cover the surface of the LTO. That is, even if the LTO is formed so as to cover the surface of the SiC layer, the surface unevenness remains, so that the LTO is further covered with a polymer film having a flat surface.

After forming the polymer film and the LTO film in this way, the polymer film and the LTO film are etched back so that the etching selectivity is 1, that is, the polymer film and the LTO are etched at the same rate. Thereby, the polymer film and the LTO are etched back at the same rate, that is, the surfaces of the polymer film and the LTO are kept flat regardless of the unevenness of the surface of the LTO. Subsequently, when the polymer film is removed, the etching conditions such as the etching gas are switched, and the LTO and the SiC layer are etched back so that their etching selection ratio becomes 1. As a result, the LTO and SiC layers are etched back at the same rate while the surface remains flat. Then, etch back of the LTO and SiC layers is continued until the underlayer is exposed.

Such a manufacturing method makes it possible to manufacture an SiC single crystal device having a structure in which an SiC layer is left only in a trench formed in an underlayer.

However, the above manufacturing method requires a step of manufacturing a polymer film in addition to LTO on the SiC layer. Also, a two-stage etch back process is required in which the polymer film and LTO are etched back so that the etching selectivity is 1, and then the LTO and SiC layer are etched back so that the etching selectivity is 1. become. Therefore, the manufacturing method becomes complicated, and as a result, the manufacturing cost increases.

Note that here, as an example of performing etch back for planarization when unevenness is formed on the surface, a structure in which a SiC layer is left in the trench has been described as an example. However, other structures may be used as the structure for flattening when irregularities are formed on the surface. For example, unevenness based on step bunching is formed when epitaxial growth is performed on an off-substrate having an off angle, or unevenness based on step bunching is formed by activation annealing after ion implantation of impurities. There is a case. In these cases as well, the above becomes a problem.

A first object of the present disclosure is to provide a manufacturing method capable of making the surface of a SiC layer flat more simply in a SiC semiconductor device having a structure in which a SiC layer is embedded in a trench formed in a base layer. . Further, a second object of the present invention is to provide a manufacturing method capable of making the surface of the SiC layer flattened more simply when flattening the uneven surface on which the surface of the SiC layer is formed in the SiC semiconductor device. To do.

In the method of manufacturing a SiC semiconductor device according to the first aspect of the present disclosure, a semiconductor substrate made of SiC and having a base layer formed thereon is prepared, a trench is formed in the base layer, and the trench is formed in the trench. The SiC layer is epitaxially grown so as to be formed on the surface of the underlayer while being buried, a sacrificial layer is formed on the surface of the SiC layer, and after the sacrificial layer is formed, the sacrificial layer is formed by reflow. And planarizing and sacrificing the SiC layer together with the sacrificial layer after the planarization by dry etching under an etching condition in which the etching selectivity between the sacrificial layer and the SiC layer is 1.

Thus, when removing the portion of the SiC layer formed above the surface of the underlayer, a fluid sacrificial layer is formed on the SiC layer. Since the surface of the sacrificial layer is in a flat state due to the fluidity, the surface of the SiC layer is flattened by etching back the SiC layer together with the sacrificial layer so that the etching selectivity is 1. Can be removed. Therefore, it is possible to more simply provide a method for manufacturing a SiC semiconductor device in which the surface of the base layer and the SiC layer after the etch back can be made flat.

In the method of manufacturing a SiC semiconductor device according to the second aspect of the present disclosure, a semiconductor substrate made of SiC and having a main surface and an off-substrate having an off angle is prepared. A SiC layer is epitaxially grown on the surface, a sacrificial layer is formed on the surface of the epitaxially grown SiC layer and has unevenness based on step bunching, and the sacrificial layer is formed. After that, the sacrificial layer is planarized by reflow, and the SiC layer together with the planarized sacrificial layer is etched back by dry etching under an etching condition in which the etching selectivity between the sacrificial layer and the SiC layer is 1. , Including.

Thus, when the uneven surface of the epitaxially grown SiC layer is flattened, a fluid sacrificial layer is formed on the SiC layer. Also in this case, the SiC layer can be removed so that the surface becomes flat by etching back the SiC layer together with the sacrificial layer so that the etching selectivity is 1. Therefore, it becomes possible to provide a method of manufacturing a SiC semiconductor device that can make the surface of the SiC layer after the etch back flattened more simply.

In the method of manufacturing a SiC semiconductor device according to the third aspect of the present disclosure, a semiconductor substrate made of SiC and having a main surface and an off substrate having an off angle is prepared. An SiC layer is epitaxially grown on the surface, and after impurity implantation is performed on the surface of the epitaxially grown SiC layer, an activation annealing process is performed to form an impurity layer, and an activation annealing process is performed. Forming a sacrificial layer on the surface of the SiC layer including the impurity layer and having irregularities based on step bunching, and forming the sacrificial layer, and then planarizing the sacrificial layer by reflow And the impurity layer and the SiC layer together with the sacrificial layer after planarization under an etching condition in which the etching selectivity between the sacrificial layer and the SiC layer is 1. And it includes a etched back, a by dry etching.

As described above, when the uneven surface formed when the impurity layer is formed by performing ion implantation and activation annealing on the SiC layer, a sacrificial layer having fluidity is formed on the SiC layer. Forming. Also in this case, the SiC layer and the impurity layer can be removed so as to have a flat surface by etching back the SiC layer together with the sacrifice layer so that the etching selectivity is 1. Therefore, it is possible to more simply provide a method for manufacturing an SiC semiconductor device in which the surfaces of the SiC layer and the impurity layer after the etch back can be made flat.

It is sectional drawing of the vertical MOSFET with which the SiC semiconductor device concerning 1st Embodiment is equipped. FIG. 6 is a cross-sectional view showing a manufacturing process of the vertical MOSFET shown in FIG. 1. It is sectional drawing which shows the manufacturing process of the vertical MOSFET following FIG. 2A. FIG. 3B is a cross-sectional view showing the vertical MOSFET manufacturing process following FIG. 2B. FIG. 2D is a cross-sectional view showing the vertical MOSFET manufacturing process following FIG. 2C. It is sectional drawing which shows the manufacturing process of the vertical MOSFET following FIG. 2D. It is sectional drawing which shows the manufacturing process of the vertical MOSFET following FIG. 2E. It is sectional drawing which shows the manufacturing process of the vertical MOSFET following FIG. 2F. It is sectional drawing which shows the manufacturing process of the vertical MOSFET following FIG. 2G. It is sectional drawing which shows the manufacturing process of the vertical MOSFET shown in FIG. 1 in the position which produces an alignment key. It is sectional drawing which shows the manufacturing process of the vertical MOSFET following FIG. 3A. FIG. 3B is a cross-sectional view showing the vertical MOSFET manufacturing process following FIG. 3B. FIG. 3D is a cross-sectional view showing the vertical MOSFET manufacturing process following FIG. 3C. It is the figure which showed the same process as FIG. 3A by another cross section. It is the figure which showed the same process as FIG. 3B by another cross section. It is the figure which showed the same process as FIG. 3C by another cross section. It is the figure which showed the same process as FIG. 3D by another cross section. It is a top view of an alignment key. It is a top view of an alignment key. It is sectional drawing of JBS with which the SiC semiconductor device concerning 2nd Embodiment is equipped. It is sectional drawing which shows the manufacturing process of JBS shown in FIG. It is sectional drawing which shows the manufacturing process of JBS following FIG. 7A. It is sectional drawing which shows the manufacturing process of JBS following FIG. 7B. FIG. 7D is a cross-sectional view showing the manufacturing process of JBS following FIG. 7C. It is sectional drawing to which one part in the manufacturing process of the vertical MOSFET demonstrated in 3rd Embodiment was expanded. It is sectional drawing which shows the manufacturing process of the vertical MOSFET following FIG. 8A. FIG. 9A is a cross-sectional view showing the vertical MOSFET manufacturing process following FIG. 8B. FIG. 8D is a cross-sectional view showing the vertical MOSFET manufacturing process following FIG. 8C. It is sectional drawing of JBS with which the SiC semiconductor device concerning 4th Embodiment is equipped. FIG. 10 is an enlarged cross-sectional view of a part of the vertical MOSFET shown in FIG. 9 during the manufacturing process. FIG. 10B is a cross-sectional view showing the vertical MOSFET manufacturing process following FIG. 10A. FIG. 10B is a cross-sectional view showing the vertical MOSFET manufacturing process following FIG. 10B. FIG. 10D is a cross-sectional view showing the vertical MOSFET manufacturing process following FIG. 10C.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described. As shown in FIG. 1, the SiC semiconductor device according to the present embodiment has a vertical MOSFET formed as a semiconductor element. The vertical MOSFET is formed in the cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming the outer peripheral breakdown voltage structure so as to surround the cell region. Only shown. In the following description, the horizontal direction in FIG. 1 is the width direction, and the vertical direction is the thickness direction or depth direction.

In the SiC semiconductor device, an n ⁺ type substrate 1 made of SiC is used as a semiconductor substrate. In the case of the present embodiment, the normal direction of the paper surface of FIG. 1 is matched with the off direction. As the n ⁺ type substrate 1, an off substrate having a (0001) Si surface and a predetermined off angle is used. For example, the off direction is <11-20>. The N ⁺ type substrate 1 has an N type impurity concentration of, for example, 1.0 × 10 ¹⁹ / cm ³ .

On the main surface of the n ⁺ type substrate 1, an n ⁻ type drift layer 2 made of SiC, a p type base region 3 and an n ⁺ type source region 4 are epitaxially grown in this order. For example, the n ⁻ -type drift layer 2 has an n-type impurity concentration of 0.5 to 2.0 × 10 ¹⁶ / cm ³ and a thickness of 5 to 14 μm. The p-type base region 3 is a portion where a channel region is formed, and has a p-type impurity concentration of, for example, about 2.0 × 10 ¹⁷ / cm ³ and a thickness of 0.5 to 2 μm. The n ⁺ -type source region 4 has a higher impurity concentration than the n ⁻ -type drift layer 2, and the n-type impurity concentration in the surface layer portion is, for example, 2.5 × 10 ¹⁸ to 1.0 × 10 ¹⁹ / cm ³ and has a thickness. It is composed of about 0.5 to 2 μm.

A p-type deep layer 5 is formed so as to penetrate the n ⁺ -type source region 4 and the p-type base region 3 and reach the n ⁻ -type drift layer 2. The p-type deep layer 5 is configured by, for example, embedding a trench 5 a having a width of 1 μm or less and an aspect ratio of 2 or more with a SiC layer by buried epitaxial growth. Also, the p-type impurity concentration is increased. Specifically, a plurality of p-type deep layers 5 are arranged at equal intervals on the n ⁻ -type drift layer 2 and are spaced apart from each other so that the top surface layout is striped. For example, each p-type deep layer 5 has a p-type impurity concentration of, for example, 1.0 × 10 ¹⁷ to 1.0 × 10 ¹⁹ / cm ³ , a width of 0.7 μm, and a depth of p-type base region 3 and n ⁺ -type. It is configured to be deeper than the total film thickness of the source region 4 by 0.4 μm or more.

Further, for example, the width is 0.8 μm and the depth is the p-type base region 3 and the n ⁺ -type source region so as to penetrate the p-type base region 3 and the n ⁺ -type source region 4 and reach the n ⁻ -type drift layer 2. A gate trench 6 that is deeper by 0.2 to 0.4 μm than the total thickness of 4 is formed. The p-type base region 3 and the n ⁺ -type source region 4 described above are arranged so as to be in contact with the side surface of the gate trench 6. The gate trench 6 is formed in a line-shaped layout in which the horizontal direction in FIG. 1 is the width direction, the normal direction to the longitudinal direction is the longitudinal direction, and the vertical direction is the depth direction. Although only one gate trench 6 is shown in FIG. 1, a plurality of gate trenches 6 are arranged at equal intervals in the left-right direction on the paper surface, and are arranged so as to be sandwiched between p-type deep layers 5 respectively. It is made into a shape.

A portion of the p-type base region 3 located on the side surface of the gate trench 6 is a channel region that connects the n ⁺ -type source region 4 and the n ⁻ -type drift layer 2 when the vertical MOSFET is operated. A gate insulating film 7 is formed on the inner wall surface of the gate trench 6 including the channel region. A gate electrode 8 made of doped Poly-Si is formed on the surface of the gate insulating film 7, and the gate trench 6 is completely filled with the gate insulating film 7 and the gate electrode 8.

A source electrode 9 and a gate wiring layer are formed on the surface of the n ⁺ -type source region 4 and the p-type deep layer 5 and on the gate electrode 8 via an interlayer insulating film 10. The source electrode 9 and the gate wiring layer are made of a plurality of metals such as Ni / Al. Of the plurality of metals, at least the n-type SiC, specifically, the n ⁺ -type source region 4 and the portion in contact with the gate electrode 8 in the case of n-type doping are made of a metal capable of ohmic contact with the n-type SiC. Yes. Further, at least a portion of the plurality of metals that contacts the p-type SiC, specifically, the p-type deep layer 5, is made of a metal that can make ohmic contact with the p-type SiC. The source electrode 9 is electrically insulated by being formed on the interlayer insulating film 10. The source electrode 9 is in electrical contact with the n ⁺ -type source region 4 and the p-type deep layer 5 through a contact hole formed in the interlayer insulating film 10.

Further, on the back side of the n ⁺ -type substrate 1 n ⁺ -type substrate 1 and electrically connected to the drain electrode 11 is formed. With such a structure, an n-channel type inverted MOSFET having a trench gate structure is formed. A cell region is configured by arranging a plurality of such vertical MOSFETs. An SiC semiconductor device is configured by forming an outer peripheral breakdown voltage structure such as a guard ring (not shown) so as to surround a cell region where such a vertical MOSFET is formed.

In the SiC semiconductor device configured as described above, the n ⁺ -type source region 4, the p-type base region 3 and the n ⁻ -type drift layer 2 are used as a base layer, and the p-type deep layer 5 corresponding to the SiC layer is entered into the trench 5 a. It is formed by buried epitaxial growth. When the p-type base region 3 is formed, a portion of the p-type deep layer 5 that has been epitaxially grown in the buried epitaxial layer 5 is removed by a manufacturing process that will be described later. For this reason, the surfaces of the n ⁺ -type source region 4 and the p-type deep layer 5 are flat surfaces with few damage layers. Since the trench gate structure is formed on such a flat surface with few damage layers, the gate insulating film 7 is also formed with good film quality. Therefore, the SiC semiconductor device is capable of suppressing a reduction in gate life.

Next, a manufacturing method of the SiC semiconductor device including the vertical MOSFET according to the present embodiment will be described with reference to FIGS. 2A to 2H, FIGS. 3A to 3D, FIGS. 4A to 4D, FIGS. 5A and 5B. To do. 2A to 2H are cross-sectional views in a manufacturing process at a position corresponding to the vertical MOSFET shown in FIG. 3A to 3D and FIGS. 4A to 4D are cross-sectional views different from those in FIG. 1, and directions perpendicular to the direction parallel to <11-20>, which is the off direction at the position where the alignment key is created, respectively. FIG. 2 shows a part of a cross-sectional view during the manufacturing process. 5A and 5B are layout diagrams when FIG. 3A and FIG. 4A and FIG. 3B and FIG. 4B are viewed from the upper side of the drawing. 3A corresponds to the IIIA-IIIA section in FIG. 5A, and FIG. 4A corresponds to the IVA-IVA section in FIG. 5A. 3B corresponds to the IIIB-IIIB cross section in FIG. 5B, and FIG. 4B corresponds to the IVB-IVB cross section in FIG. 5B. 3C, FIG. 3D, FIG. 4C, and FIG. 4D do not show layout views when viewed from above, but FIG. 3C and FIG. 3D are cross-sectional views at the same positions as FIG. 3A and FIG. FIG. 4D shows a cross section at the same position as in FIGS. 4A and 4B.

[Step shown in FIG. 2A]
First, a wafer-like n ⁺ type substrate 1 is prepared as a semiconductor substrate. Then, an n ⁻ type drift layer 2 made of SiC, a p type base region 3 and an n ⁺ type source region 4 are epitaxially grown in this order on the main surface of the n ⁺ type substrate 1 with a desired film thickness.

[Step shown in FIG. 2B]
Next, a mask (not shown) is arranged on the surface of the n ⁺ -type source region 4, and a region where the p-type deep layer 5 is to be formed in the mask is opened. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using the mask to form a trench 5a having a depth of, for example, a width of 1 μm or less and an aspect ratio of 2 or more.

At this time, as shown in FIGS. 3A and 4A, an alignment trench 5b is formed at a position different from the trench 5a. For example, the alignment trench 5b as an alignment key is formed in a portion of the wafer that is different from a portion constituting the SiC semiconductor device or a portion that does not affect the vertical MOSFET in the chip. Here, as shown in FIG. 5A, the alignment trench 5b has a cross shape in which one of the two orthogonal sides extends in the <11-20> direction, but may have another shape.

[Step shown in FIG. 2C]
After removing the mask, a p-type SiC layer 50 is formed. At this time, the p-type SiC layer 50 is buried in the trench 5a by buried epitaxial growth. However, since the trench 5a is formed in a narrow line shape, the p-type SiC layer 50 is formed in the trench 5a. Can be securely embedded.

However, the thickness of the portion of the p-type SiC layer 50 located above the surfaces of the trench 5a and the n ⁺ -type source region 4 corresponds to the trench 5a because the portion embedded in the trench 5a is generated. It becomes thin in the part to do. For this reason, the surface of the p-type SiC layer 50 has a concavo-convex shape which is recessed at a position corresponding to the portion embedded in the trench 5a and protrudes at a portion where the trench 5a is not formed.

Further, as shown in FIGS. 3B, 4B, and 5B, the p-type SiC layer 50 has a recessed shape at a position corresponding to the alignment trench 5b, and as shown in FIG. 3B, the epitaxial growth depends on the plane orientation. The facet 50a resulting from the property is formed. Specifically, facet 50a inclined along the off direction is formed on the surface of p-type SiC layer 50 at a position corresponding to one surface of alignment trench 5b whose normal direction is the <11-20> direction. It is formed. As shown in FIG. 5B, when the alignment trench 5b has a cross shape, the facet 50a is not formed on the upstream side in the off direction, that is, on the side opposite to the direction in which the facet 50a extends. For this reason, in the cross section shown in FIG. 4B, the p-type SiC layers 50 formed on both side surfaces of the alignment trench 5b have a symmetrical shape, and the facets 50a are not formed.

[Step shown in FIG. 2D]
After the sacrificial layer 60 is formed so as to cover the surface of the p-type SiC layer 50, the sacrificial layer 60 is flowed by reflowing at 950 to 1100 ° C. in an inert gas atmosphere such as a nitrogen gas atmosphere to flatten the surface. Turn into. As the sacrificial layer 60, PSG (abbreviation of phospho silicate glass), BPSG (abbreviation of Boro-phospho silicate glass) or SOG (abbreviation of Spin on glass) which becomes a fluid oxide film can be used. Since these materials are fluid materials that easily flow by reflow, the surface of the sacrificial layer 60 becomes a flat surface by performing reflow. For example, the level difference due to the unevenness on the surface of the sacrificial layer 60 after reflow is 0.1 μm or less.

At this time, as shown in FIG. 3C and FIG. 4C, the sacrificial layer 60 is formed so that the recessed portion of the p-type SiC layer 50 at the position corresponding to the alignment trench 5b is buried. When the reflow is performed, the surface of the sacrificial layer 60 becomes a flat surface in the recessed portion as well as the outside of the recessed portion regardless of the presence or absence of the facet 50a.

[Step shown in FIG. 2E]
Etchback is performed so that a portion of the p-type SiC layer 50 formed above the surface of the n ⁺ -type source region 4 is removed together with the sacrificial layer 60 by dry etching. Thereby, p-type SiC layer 50 remains only in trench 5a, and p-type deep layer 5 is formed.

At this time, etching back is performed so that the etching selection ratio between the sacrificial layer 60 and the p-type SiC layer 50 is 1, that is, the sacrificial layer 60 and the p-type SiC layer 50 are etched at the same rate. The etching conditions are arbitrary. For example, a mixed gas of SF ₆ and argon is used. The RF power in the etching apparatus is 1200 W, the atmospheric pressure is 0.5 Pa, the flow rate of SF ₆ is 3.7 sccm, argon The flow rate is 500 sccm. In such dry etching, the p-type SiC layer 50 is chemically etched with SF ₆ and the sacrificial layer 60 is physically etched with argon, so that the etching selectivity can be 1.

Thereby, regardless of the unevenness of the surface of p-type SiC layer 50, sacrificial layer 60 and p-type SiC layer 50 are etched back at the same rate, that is, their surfaces are kept flat. Therefore, when the sacrificial layer 60 and the p-type SiC layer 50 are etched back until a portion formed above the surface of the n ⁺ -type source region 4 is removed, the n ⁺ -type source region 4 and the p-type deep layer 5 are removed. The surface of can be made flat.

Further, as shown in FIGS. 3D and 4D, since the p-type SiC layer 50 is etched back together with the sacrificial layer 60, the surface after removal is also removed at the position serving as the alignment key. Can be flat. In the position serving as the alignment key, the facet 50a is formed. However, when the sacrificial layer 60 and the p-type SiC layer 50 are etched back so that the etching selection ratio becomes 1 as described above, Facet 50a can be removed.

That is, the facet 50a remains when the p-type SiC layer 50 is etched back without forming the sacrificial layer 60, but the facet 50a does not remain by etching back the p-type SiC layer 50 together with the sacrificial layer 60. You can Even if the sacrificial layer 60 is not formed, the surface without the facets 50a can be obtained by removing the p-type SiC layer 50 by grinding, but in the case of grinding, the surface is rough and unevenness remains. Therefore, it is not preferable. On the other hand, according to the etch back method of this embodiment, the surface state is good and the facet 50a can be removed.

In the subsequent process, when the alignment is recognized, the outer edge of the alignment trench 5b, that is, the boundary between the p-type deep layer 5 and the n ⁺ -type source region 4 is used as an alignment key. If the facet 50a remains, when the alignment is recognized, the boundary between the facet 50a and the non-facet 50a may be erroneously recognized instead of the alignment key to be recognized. For this reason, it is possible to suppress the occurrence of misalignment by preventing the facet 50a from remaining.

Since the sacrificial layer 60 is etched back with the p-type SiC layer 50 at a selection ratio of 1, the sacrificial layer 60 still remains in the alignment trench 5b when the etch-back of the p-type SiC layer 50 is completed. It becomes a state. For this reason, after the p-type SiC layer 50 is etched back, the sacrificial layer 60 in the alignment trench 5b is removed by switching to a condition in which only the sacrificial layer 60 is etched, so that it can be used as an alignment key thereafter. Become.

[Step shown in FIG. 2F]
After forming a mask (not shown) on the n ⁺ -type source region 4 and the like, a region where the gate trench 6 is to be formed in the mask is opened. Then, the gate trench 6 is formed by performing anisotropic etching such as RIE using a mask. For example, the etching is performed with the depth of the gate trench 6 set to be 0.2 to 0.4 μm deeper than the total film thickness of the p-type base region 3 and the n ⁺ -type source region 4. Thereby, the protruding amount of the gate trench 6 from the bottom of the p-type base region 3 is set to 0.2 to 0.4 μm.

At this time, mask alignment when forming the gate trench 6 is performed using the alignment key as a reference. However, since the facet 50a does not remain as described above, the alignment key can be prevented from being erroneously recognized. Can be formed at an accurate position.

[Step shown in FIG. 2G]
After removing the mask, the gate insulating film 7 is formed by performing, for example, thermal oxidation, and the gate insulating film 7 covers the inner wall surface of the gate trench 6 and the surface of the n + type source region 4. Then, after depositing Poly-Si doped with p-type impurities or n-type impurities, this is etched back to leave the Poly-Si at least in the gate trench 6 to form the gate electrode 8.

[Step shown in FIG. 2H]
An interlayer insulating film 10 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 8 and the gate insulating film 7. Then, after forming a mask (not shown) on the surface of the interlayer insulating film 10, a portion of the mask located between the gate electrodes 8, that is, a portion corresponding to the p-type deep layer 5 and its vicinity are opened. Thereafter, the interlayer insulating film 10 is patterned using a mask to form a contact hole exposing the p-type deep layer 5 and the n ⁺ -type source region 4.

Although the subsequent steps are not shown, an electrode material composed of, for example, a laminated structure of a plurality of metals is formed on the surface of the interlayer insulating film 10. Then, the source electrode 9 is formed by patterning the electrode material. Further, by performing a process such as forming the drain electrode 11 on the back surface side of the n ⁺ type substrate 1, the SiC semiconductor device having the vertical MOSFET according to the present embodiment shown in FIG. 1 is completed.

As described above, when the portion of the p-type SiC layer 50 for forming the p-type deep layer 5 formed above the surface of the n ⁺ -type source region 4 is removed, the p-type SiC layer 50 A fluid sacrificial layer 60 is formed thereon. Since the surface of the sacrificial layer 60 is in a flat state due to the fluidity, the p-type SiC layer 50 is etched back together with the sacrificial layer 60 so that the etching selectivity is 1, whereby the p-type SiC is obtained. The layer 50 can be removed so that the surface is flat. Therefore, it is possible to provide a method of manufacturing an SiC semiconductor device that can make the surfaces of n ⁺ -type source region 4 and p-type deep layer 5 after etch back flattened more simply. In addition, since the manufacturing method of the SiC semiconductor device can be simplified, it is possible to reduce the manufacturing cost of the SiC semiconductor device.

(Second Embodiment)
A second embodiment will be described. In the present embodiment, a junction barrier Schottky diode (hereinafter referred to as JBS) is provided instead of a vertical MOSFET as a semiconductor element as compared with the first embodiment. Others are the same as those in the first embodiment, and therefore only the parts different from the first embodiment will be described.

The JBS is formed in the cell portion of the SiC semiconductor device, and the SiC semiconductor device is configured by forming an outer peripheral breakdown voltage structure such as a guard ring so as to surround the cell region. Is mainly described.

As shown in FIG. 6, an n ⁻ type drift layer 102 made of SiC having an n type impurity concentration lower than that of the n ⁺ type substrate 101 is formed on an n ⁺ type substrate 101 made of SiC. . In the cell region, a striped p-type deep layer 103 is formed on the surface portion of the n ⁻ -type drift layer 102, and although not shown, the p-type layer is formed so as to surround the periphery thereof. An outer pressure-resistant structure such as a guard ring is provided.

The p-type deep layer 103 is arranged in a stripe-shaped trench 103a in which a plurality of n ^- type drift layers 102 are arranged at equal intervals, and is constituted by a p-type epitaxial film formed by buried epitaxial growth. The trench 103a corresponds to a deep trench, and has a width of 1 μm or less and an aspect ratio of 2 or more, for example.

On the n ⁻ -type drift layer 102 and the p-type deep layer 103, a Schottky electrode 104 in contact with these surfaces is formed. Furthermore, an ohmic electrode 105 is formed on the back side of the n ⁺ type substrate 101.

Thus, even in a SiC semiconductor device including JBS as a semiconductor element, the p-type deep layer 103 is formed by buried epitaxial growth in the trench 103a. The etch back method similar to that of the first embodiment can also be applied when forming the p-type deep layer 103. Specifically, a method for manufacturing the SiC semiconductor device according to the present embodiment will be described with reference to FIGS. 7A to 7D.

[Step shown in FIG. 7A]
First, a wafer-like n ⁺ type substrate 101 is prepared as a semiconductor substrate. Then, an n ⁻ type drift layer 102 made of SiC is epitaxially grown on the main surface of the n ⁺ type substrate 101 with a desired film thickness.

Next, a mask (not shown) is arranged on the surface of the n ⁻ -type drift layer 102, and a region where the p-type deep layer 103 is to be formed in the mask is opened. Then, by performing anisotropic etching such as RIE using a mask, a trench 103a having a depth of, for example, a width of 1 μm or less and an aspect ratio of 2 or more is formed.

[Step shown in FIG. 7B]
After removing the mask, a p-type SiC layer 110 is formed. At this time, the p-type SiC layer 110 is buried in the trench 103a by buried epi, but since the trench 103a is formed in a narrow line shape, the p-type SiC layer 110 is formed in the trench 103a. Can be securely embedded.

However, the thickness of the portion of the p-type SiC layer 110 located above the surfaces of the trench 103a and the n ⁻ -type drift layer 102 corresponds to that of the trench 103a because the portion embedded in the trench 103a is generated. It becomes thin in the part to do. For this reason, the surface of the p-type SiC layer 110 has a concavo-convex shape that is recessed at a position corresponding to the portion embedded in the trench 103a and protrudes at a portion where the trench 103a is not formed.

[Step shown in FIG. 7C]
After the sacrificial layer 120 is formed so as to cover the surface of the p-type SiC layer 110, the sacrificial layer 120 is flowed by performing reflow to flatten the surface. The material of the sacrificial layer 120 and the reflow conditions are the same as in the first embodiment.

[Step shown in FIG. 7D]
Etchback is performed so that a portion of the p-type SiC layer 110 formed above the surface of the n ⁻ -type drift layer 102 is removed together with the sacrificial layer 120 by dry etching. The etch back method at this time is also the same as in the first embodiment. Thereby, p-type SiC layer 110 remains only in trench 103a, and p-type deep layer 5 is formed. That is, since the sacrificial layer 120 and the p-type SiC layer 110 are etched back at the same rate regardless of the surface irregularities of the p-type SiC layer 50, the surfaces of the n ⁻ -type drift layer 102 and the p-type deep layer 103 are It can be a flat surface.

Although the subsequent steps are not shown, the Schottky electrode 104 is formed on the front surface side of the n ⁻ type drift layer 102 and the p type deep layer 103, and the ohmic electrode 105 is formed on the back surface side of the n ⁺ type substrate 101. And so on. Thereby, the SiC semiconductor device according to the present embodiment is completed.

As described above, the same etch-back method as in the first embodiment can also be applied to a SiC semiconductor device having JBS formed by buried epitaxial growth of the p-type deep layer 103 in the trench 103a. Thereby, it is possible to obtain the same effect as in the first embodiment.

(Third embodiment)
A third embodiment will be described. In the present embodiment, the same processes as those in the first and second embodiments are performed when flattening unevenness caused by step bunching that occurs during epitaxial growth.

For example, the SiC semiconductor device shown in FIG. 1 described in the first embodiment has a desired n ⁻ type drift layer 2 made of SiC on the main surface of the n ⁺ type substrate 1 as shown in FIG. 2A. Epitaxial growth with film thickness. At this time, since unevenness due to step bunching can be formed, it is flattened. Specifically, the steps shown in FIGS. 8A to 8D are performed.

First, as shown in FIG. 8A, an n ⁺ type substrate 1 is prepared. Then, as shown in FIG. 8B, an n ⁻ type drift layer 2 made of SiC is epitaxially grown on the main surface of the n ⁺ type substrate 1. At this time, since the n ⁺ type substrate 1 is an off substrate having an off angle, the surface of the n ⁻ type drift layer 2 formed thereon has an uneven surface on which unevenness due to step bunching is formed. 2a.

For this reason, as shown in FIG. 8C, after the sacrificial layer 60 is formed so as to cover the uneven surface 2a of the n ⁻ type drift layer 2, it is 950 to 1100 ° C. in an inert gas atmosphere such as a nitrogen gas atmosphere. The sacrificial layer 60 is caused to flow by reflow to flatten the surface. For the sacrificial layer 60, PSG, BPSG, SOG, or the like, which becomes a fluid oxide film, can be used as in the first embodiment.

Then, as shown in FIG. 8D, the sacrificial layer 60 and the n ⁻ -type drift layer 2 are etched back by dry etching so as to partially remove the uneven surface 2a side. At this time, etching back is performed so that the etching selection ratio between the sacrificial layer 60 and the n ⁻ -type drift layer 2 is 1, that is, the sacrificial layer 60 and the n ⁻ -type drift layer 2 are etched at the same rate. The etching conditions can be the same as those in the first embodiment, for example. Thereby, the surface of the n ⁻ -type drift layer 2 can be made flat.

As described above, when the n ⁻ type drift layer 2 made of SiC is formed on the main surface of the n ⁺ type substrate 1, even when irregularities are formed by step bunching, the sacrificial layer 60 is formed, The sacrificial layer 60 and the n ⁻ type drift layer 2 are etched back so that the selection ratio becomes 1. As a result, irregularities on the surface of the n ⁻ type drift layer 2 can be removed, and the surface can be planarized.

Although the case where the surface of the n ⁻ -type drift layer 2 is planarized has been described here, the planarization of the p-type base region 3 and the n ⁺ -type source region 4 formed on the n ⁻ -type drift layer 2 is explained. Also in the case of performing the etching, an etch-back with a selection ratio of 1 using the sacrificial layer 60 may be performed. Further, only one of the n ⁻ type drift layer 2, the p type base region 3, and the n ⁺ type source region 4 may be planarized, or any one of a plurality of planarizations may be performed. good.

(Fourth embodiment)
A fourth embodiment will be described. In the present embodiment, the same process as in the first and second embodiments is performed when flattening irregularities by step bunching that occurs when an activation annealing process is performed after ion implantation of impurities. . Here, as an example, JBS will be described as an example.

As shown in FIG. 9, the SiC semiconductor device according to the present embodiment is also provided with a JBS as in the second embodiment. The JBS is formed using an n ⁺ type substrate 101. On the n ⁺ -type substrate 101, n is an n-type impurity concentration than the ^{n +} -type substrate 101 made of low been SiC ^- -type drift layer 102 is formed. The JBS is formed in the cell portion of the SiC semiconductor substrate constituted by the n ⁺ -type substrate 1 and the n ⁻ -type drift layer 102, and the termination structure (not shown) is formed in the outer peripheral region thereof. An SiC semiconductor device is configured.

Specifically, a plurality of p-type deep layers 103 are arranged at equal intervals on the surface layer portion of the n ⁻ -type drift layer 102 to form a stripe shape. A Schottky electrode 104 made of, for example, Mo (molybdenum) is formed on the surfaces of the n ⁻ -type drift layer 102 and the p-type deep layer 103. Schottky electrode 104 is in Schottky contact with n ⁻ type drift layer 102. An insulating film 106 made of, for example, a silicon oxide film is formed on the surface of the n ⁻ type drift layer 102, and the Schottky electrode 104 is formed on the insulating film 106. The Schottky electrode 104 is brought into contact with the surfaces of the n ⁻ -type drift layer 102 and the p-type deep layer 103 through an opening 106 a partially formed in the cell portion of the insulating film 106.

Further, a p-type RESURF layer 107 is formed along the outer edge of the opening 106a. The p-type RESURF layer 107 is further provided with a guard ring (not shown) on the outer periphery, thereby providing an outer peripheral withstand voltage structure. Then, an ohmic electrode 105 made of, for example, Ni (nickel), Ti (titanium), Mo, Au (gold), or the like is formed so as to be in contact with the back surface of the n ⁺ type substrate 101, thereby providing a JBS. An SiC semiconductor device is configured.

In the SiC semiconductor device configured as described above, for example, after the n ⁻ type drift layer 102 is epitaxially grown on the n ⁺ type substrate 101, ion implantation is performed and activation annealing treatment is performed, whereby a p type deep layer is formed. 103 and the p-type RESURF layer 107 can be formed. At this time, since unevenness due to step bunching can be formed, it is flattened. Specifically, the steps shown in FIGS. 10A to 10D are performed.

First, as shown in FIG. 10A, After preparing ^{n +} -type substrate 101, made of SiC on the main surface of the ^{n +} -type substrate 101 n ^- -type drift layer 102 is epitaxially grown. Further, a p-type impurity is ion-implanted into a region where the p-type deep layer 103 is to be formed using a mask (not shown). Only the p-type deep layer 103 is shown here, but at this time, p-type impurities are also ion-implanted into a region where the p-type RESURF layer 107 is to be formed. Then, an activation annealing process is performed. In this case, n ⁺ -type substrate 1 has been turned off substrate having an off angle, n formed thereon ^- it also -type drift layer 102 is taken over. Therefore, as shown in FIG. 10B, the unevenness caused by the step bunching is formed on the surface of the n ⁻ type drift layer 102 including the surfaces of the p-type deep layer 103 and the p-type RESURF layer 107 by the annealing process. A surface 102a is formed.

For this reason, as shown in FIG. 10C, the sacrificial layer 60 is formed so as to cover the uneven surface 102a of the n ⁻ type drift layer 102 including the surface of the p type deep layer 103, and then, for example, a nitrogen gas atmosphere is not used. The sacrificial layer 60 is made to flow by reflowing at 950 to 1100 ° C. in an active gas atmosphere to flatten the surface. For the sacrificial layer 60, PSG, BPSG, SOG, or the like, which becomes a fluid oxide film, can be used as in the first embodiment.

Then, as shown in FIG. 10D, etch back is performed by dry etching so as to partially remove the uneven surface 102a side of the n ⁻ type drift layer 102 including the surface of the p-type deep layer 103 and the like together with the sacrificial layer 60. . At this time, the etching selection ratio between the sacrificial layer 60 and the n ⁻ type drift layer 102 and the p-type deep layer 103 is set to 1, that is, the sacrificial layer 60 and the n ⁻ type drift layer 102 and the p-type deep layer 103 and the like. Etch back so that and are etched at an equal rate. The etching conditions can be the same as those in the first embodiment, for example. As a result, the surfaces of the n ⁻ -type drift layer 102 and the p-type deep layer 103 can be made flat.

As described above, even when the activation annealing treatment is performed after the ion implantation and unevenness due to step bunching is formed, the sacrificial layer 60 is formed, and then the n ⁻ -type drift layer 102 and the p ^{− are} formed together with the sacrificial layer 60. The mold deep layer 103 and the like are etched back with a selection ratio of 1. As a result, surface irregularities such as the n ⁻ type drift layer 102 and the p type deep layer 103 can be removed, and the surfaces can be planarized.

(Other embodiments)
Although the present disclosure has been described based on the above-described embodiment, the present disclosure is not limited to the embodiment, and includes various modifications and modifications within an equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

For example, in the first embodiment, the structure in which the n ⁻ type drift layer 2, the p type base region 3, and the n ⁺ type source region 4 are formed on the n ⁺ type substrate 1 as the base layer is taken as an example. Similarly, in the second embodiment, the structure in which the n ⁻ type drift layer 102 is formed on the n ⁺ type substrate 101 as the base layer is taken as an example. However, this is merely an example. After forming a trench in the underlying layer, a SiC layer is buried and epitaxially grown in the trench, and a portion of the SiC layer above the surface of the underlying layer is formed. Other structures may be used as long as they are configured to etch back.

In the first and second embodiments, the structure in which the SiC layer remains only in the trench formed in the base layer when the SiC layer is etched back together with the sacrificial layer has been described. However, this is only an example, and a structure in which a part of the SiC layer remains on the surface of the underlayer may be used. Even in such a structure, the surface of the SiC layer can be made flat by applying the above-described etch back method.

In the third and fourth embodiments, when a semiconductor substrate composed of an off-substrate having an off-angle is used, the uneven surface of the surface of the SiC layer epitaxially grown thereon, or An example of the flattening of the uneven surface on which the impurity layer is formed by ion implantation is shown. However, these are only examples, and may be applied to a method of manufacturing an SiC semiconductor device in which a similar uneven surface is formed.

In the first and third embodiments, the vertical MOSFET has been described as an example of the semiconductor element provided in the SiC semiconductor device. However, the semiconductor element is not limited to the vertical MOSFET, and other semiconductor elements are formed. May be. Further, the n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example, but a p-channel type MOSFET in which the conductivity type of each component is inverted may be used. good. In the above description, the MOSFET has been described as an example of the semiconductor element. However, the present disclosure can be applied to an IGBT having a similar structure. The IGBT only changes the conductivity type of the n ⁺ type substrate 1 from the n-type to the p-type with respect to the above-described embodiments, and the other structures and manufacturing methods are the same as those in the above-described embodiments. Further, the vertical MOSFET having the trench gate structure has been described as an example. However, the vertical MOSFET is not limited to the trench gate structure but may be a planar type.

It should be noted that when indicating the orientation of a crystal, a bar (-) should be attached on a desired number, but there is a limitation in terms of expression based on an electronic application. A bar shall be placed in front of the number.

Claims (8)

1. Preparing a semiconductor substrate (1, 101) made of silicon carbide and having an underlayer (2-4, 102) formed thereon;
   Forming trenches (5a, 103a) in the base layer;
   Epitaxially growing a silicon carbide layer (50, 110) so as to be formed on the surface of the underlayer while being embedded in the trench;
   Forming a sacrificial layer (60, 120) on the surface of the silicon carbide layer;
   After depositing the sacrificial layer, planarizing the sacrificial layer by reflow;
   Etching the silicon carbide layer together with the sacrificial layer after planarization by dry-etching the silicon carbide layer under an etching condition in which an etching selectivity between the sacrificial layer and the silicon carbide layer is 1 A method for manufacturing a semiconductor device.
2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the etch back, the surface of the base layer is exposed by the etch back, and the silicon carbide layer is left only in the trench.
3. 3. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein forming the sacrificial layer includes forming any one of PSG, BPSG, and SOG as the sacrificial layer.
4. Forming the trench includes forming an alignment trench (5b) at a position different from the trench with respect to the foundation layer,
   In the epitaxial growth of the silicon carbide layer, the silicon carbide layer is also grown in the alignment trench,
   In forming the sacrificial layer, the sacrificial layer is also formed on the silicon carbide layer formed to fill the alignment trench,
   The etching back is performed until the facet (50a) included in a recess formed at a position corresponding to the alignment trench in the surface of the silicon carbide layer is removed. The manufacturing method of the silicon carbide semiconductor device as described in any one.
5. In preparing a semiconductor substrate on which the underlayer is formed, a silicon carbide substrate (1) of the first or second conductivity type is used as the semiconductor substrate, and the silicon carbide substrate is used as the underlayer. A first conductivity type drift layer (2) made of silicon carbide having a lower impurity concentration than the silicon carbide substrate, and a second conductivity type base region (3) made of silicon carbide; And a first conductivity type source region (4) composed of silicon carbide having a higher impurity concentration than the drift layer is prepared in order,
   In the etch back, a deep layer (5) of the second conductivity type is formed in the trench (5a) by performing the etch back until the surface of the source region is exposed.
   After forming the deep layer, a gate trench (6) deeper than the base region from the surface of the source region, a gate insulating film (7) formed on the inner wall surface of the gate trench, and the gate insulating film Forming a trench gate structure comprising a gate electrode (8) formed thereon;
   Forming a source electrode (9) electrically connected to the source region and the deep layer;
   The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising: forming a drain electrode (11) on a back surface side of the semiconductor substrate.
6. In preparing the semiconductor substrate on which the foundation layer is formed, a silicon carbide substrate (101) of the first conductivity type is used as the semiconductor substrate, and the silicon carbide is formed on the silicon carbide substrate as the foundation layer. Preparing a first conductivity type drift layer (102) formed of silicon carbide having a lower impurity concentration than the substrate;
   In the etch back, a second conductive type deep layer (103) is formed in the trench (103a) by performing the etch back until the surface of the drift layer is exposed.
   Forming a Schottky electrode (104) electrically connected to the drift layer and the deep layer;
   The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising: forming an ohmic electrode (105) on a back surface side of the semiconductor substrate.
7. Providing a semiconductor substrate (1) made of silicon carbide and having a main surface and an off-substrate having an off angle;
   Epitaxially growing a silicon carbide layer (2) on the main surface of the semiconductor substrate;
   Depositing a sacrificial layer (60) on the surface of the epitaxially grown silicon carbide layer on the uneven surface (2a) having unevenness based on step bunching;
   After depositing the sacrificial layer, planarizing the sacrificial layer by reflow;
   Etching the silicon carbide layer together with the sacrificial layer after planarization by dry-etching the silicon carbide layer under an etching condition in which an etching selectivity between the sacrificial layer and the silicon carbide layer is 1 A method for manufacturing a semiconductor device.
8. Providing a semiconductor substrate (101) made of silicon carbide and having a main surface and an off-substrate having an off angle;
   Epitaxially growing a silicon carbide layer (102) on the main surface of the semiconductor substrate;
   Forming an impurity layer (103, 107) by ion-implanting impurities into the surface of the epitaxially grown silicon carbide layer and then performing an activation annealing treatment;
   Depositing a sacrificial layer (120) on the surface of the silicon carbide layer including the impurity layer that has been subjected to the activation annealing process and on the uneven surface (102a) having unevenness based on step bunching;
   After depositing the sacrificial layer, planarizing the sacrificial layer by reflow;
   Etching back the silicon carbide layer including the impurity layer together with the sacrificial layer after planarization by dry etching under an etching condition in which an etching selectivity between the sacrificial layer and the silicon carbide layer is 1. A method for manufacturing a silicon carbide semiconductor device.

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