WO2018062852A1 - Semiconductor light emitting element - Google Patents

Semiconductor light emitting element Download PDF

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Publication number
WO2018062852A1
WO2018062852A1 PCT/KR2017/010728 KR2017010728W WO2018062852A1 WO 2018062852 A1 WO2018062852 A1 WO 2018062852A1 KR 2017010728 W KR2017010728 W KR 2017010728W WO 2018062852 A1 WO2018062852 A1 WO 2018062852A1
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Prior art keywords
electrode
layer
light emitting
semiconductor
film
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PCT/KR2017/010728
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French (fr)
Korean (ko)
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진근모
이성기
정연호
박준천
이성규
설대수
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주식회사 세미콘라이트
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Priority claimed from KR1020160124002A external-priority patent/KR101766329B1/en
Priority claimed from KR1020160176550A external-priority patent/KR101895227B1/en
Application filed by 주식회사 세미콘라이트 filed Critical 주식회사 세미콘라이트
Publication of WO2018062852A1 publication Critical patent/WO2018062852A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58Optical field-shaping elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58Optical field-shaping elements
    • H01L33/60Reflective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to a semiconductor light emitting device as a whole, and more particularly to a semiconductor light emitting device having improved light emission efficiency.
  • the present disclosure relates to a semiconductor light emitting device as a whole, and more particularly, to a semiconductor light emitting device that reduces light absorption loss due to metal and improves heat dissipation efficiency.
  • the semiconductor light emitting device refers to a semiconductor optical device that generates light through recombination of electrons and holes, for example, a group III nitride semiconductor light emitting device.
  • GaAs type semiconductor light emitting elements used for red light emission, etc. are mentioned.
  • FIG. 1 is a view illustrating an example of a semiconductor light emitting device disclosed in Korean Patent Publication No. 10-1611480.
  • the semiconductor light emitting device includes a substrate 110, a plurality of semiconductor layers 130, 140, 150, a buffer layer 120, a light absorption prevention film 141, a current diffusion conductive film 160, a non-conductive reflecting film 191, and a first electrode 175. , A second electrode 185, a first electrical connection 173, a second electrical connection 183, a first lower electrode 171, and a second lower electrode 181.
  • the refractive index of the air layer is large so that the light cannot be reflected from the non-conductive reflecting film 191 to the air layer.
  • the light hitting the first electrode 175 and the second electrode 185 is reflected by light, but part of the light is absorbed and thus the reflection efficiency is lower than the reflection in the air layer.
  • the size of the first electrode 175 and the second electrode 185 is reduced to make the area where the air layer and the non-conductive reflective film 191 touch.
  • FIG. 2 is a diagram illustrating an example of a semiconductor light emitting device disclosed in Korean Laid-Open Patent Publication No. 10-2011-0031099.
  • FIG. 2A is a plan view of the light emitting device 201
  • FIG. 2B is a sectional view taken along the line A-A in FIG. 2A
  • FIG. 2C is a sectional view taken along the line B-B in FIG.
  • the light emitting device 201 is provided with a transparent conductive layer 230 provided on the p-side contact layer 228 and a plurality of p electrodes 240 provided in a part of the region on the transparent conductive layer 230.
  • the light emitting device 201 includes a plurality of n electrodes provided on the n-side contact layer 222 exposed by a plurality of vias formed from the p-side contact layer 228 to at least the surface of the n-side contact layer 222.
  • a lower insulating layer 250 provided on the inner surface of the via and the transparent conductive layer 230, and a reflective layer 260 provided inside the lower insulating layer 250 are provided.
  • the reflective layer 260 is provided at portions except the upper portions of the p electrode 240 and the n electrode 242.
  • the lower insulating layer 250 in contact with the transparent conductive layer 230 includes a via 250a extending in the vertical direction on each p electrode 240 and a via 250b extending in the vertical direction on each n electrode 242.
  • the p wiring 270 and the n wiring 272 are provided on the lower insulating layer 250 in the light emitting device 201.
  • the p-wire 270 may include a second planar conductive part 2700 extending in a planar direction on the lower insulating layer 250, and a plurality of second electrically connected to the respective p electrodes 240 through the via 250a. It has a vertical conductive portion 2702.
  • the n wiring 272 may include a first planar conductive part 2720 extending in the planar direction on the lower insulating layer 250, a via 250b of the lower insulating layer 250, and a via formed in the semiconductor stack structure. It has a plurality of first vertical conductive portions 2722 electrically connected to the respective n electrodes 242 through.
  • the light emitting device 201 includes an upper insulating layer 280 provided on the lower insulating layer 250 in contact with the p wiring 270, the n wiring 272, and the transparent conductive layer 230, and an upper insulating layer.
  • P-side junction electrode 290 electrically connected to p-line 270 through p-side opening 280a provided in layer 280 and n-side opening 280b provided in upper insulating layer 280.
  • An n-side junction electrode 292 electrically connected to the wiring 272 is provided.
  • Some of the light emitted from the emission layer 225 may be emitted toward the p-side cladding 226 layer.
  • Light emitted to the p-side cladding 226 layer strikes the n-wiring 272 and the p-wiring 270, partly reflected and partially absorbed. For this reason, in order to prevent absorption of the emitted light as much as possible, the widths of the n wiring 272 and the p wiring 270 are formed thin.
  • FIG. 15 is a view illustrating an example of a semiconductor light emitting device disclosed in US Patent No. 7,262,436.
  • the semiconductor light emitting device may include a substrate 100, an n-type semiconductor layer 300 grown on the substrate 100, an active layer 400 grown on the n-type semiconductor layer 300, and p grown on the active layer 400.
  • a chip having such a structure that is, a chip in which both the electrodes 901, 902, 903 and the electrode 800 are formed on one side of the substrate 100, and the electrodes 901, 902, 903 function as a reflective film is called a flip chip.
  • the electrodes 901, 902 and 903 may include a high reflectance electrode 901 (eg Ag), an electrode 903 (eg Au) for bonding, and an electrode 902 for preventing diffusion between the electrode 901 material and the electrode 903 material; Example: Ni).
  • This metal reflective film structure has a high reflectance and has an advantage in current spreading, but has a disadvantage of light absorption by metal.
  • 16 is a diagram illustrating an example of a semiconductor light emitting device disclosed in Japanese Laid-Open Patent Publication No. 2006-20913.
  • the semiconductor light emitting device includes a substrate 100, a buffer layer 200 grown on the substrate 100, an n-type semiconductor layer 300 grown on the buffer layer 200, and an active layer 400 grown on the n-type semiconductor layer 300.
  • the bonding pad 700 and the n-side bonding pad 800 are formed on the etched and exposed n-type semiconductor layer 300.
  • the distributed Bragg reflector 900 DBR: Distributed Bragg Reflector
  • the metal reflecting film 904 are provided on the transparent conductive film 600. According to this configuration, the light absorption by the metal reflective film 904 is reduced, but there is a disadvantage in that current spreading is not smoother than using the electrodes 901, 902, 903.
  • FIG. 23 is a view showing an example of a conventional Group III nitride semiconductor light emitting device.
  • the group III nitride semiconductor light emitting device includes a substrate 10 (eg, a sapphire substrate), a buffer layer 20 grown on the substrate 10, an n-type group III nitride semiconductor layer 30 grown on the buffer layer 20, and an n-type 3
  • An active layer 40 grown on the group nitride semiconductor layer 30, a p-type group III nitride semiconductor layer 50 grown on the active layer 40, and a current diffusion electrode formed on the p-type group III nitride semiconductor layer 50 ( 60), the n-type III-nitride semiconductor in which the p-side pad electrode 70, the p-type III-nitride semiconductor layer 50, and the active layer 40 formed on the current diffusion electrode 60 are mesa-etched and exposed. And an n-side pad electrode 80 and a passivation layer 90 formed on the layer 30.
  • the current spreading electrode 60 is provided so that the current is well supplied to the entire p-type group III nitride semiconductor layer 50.
  • the current spreading electrode 60 is formed over almost the entire surface of the p-type group III nitride semiconductor layer, for example, formed of a transmissive conductive film using ITO or Ni and Au, or as a reflective conductive film using Ag. Can be formed.
  • the p-side pad electrode 70 and the n-side pad electrode 80 are metal electrodes for supplying current and wire bonding to the outside, for example, nickel, gold, silver, chromium, titanium, platinum, palladium, and rhodium. And iridium, aluminum, tin, indium, tantalum, copper, cobalt, iron, ruthenium, zirconium, tungsten, molybdenum, or any combination thereof.
  • the passivation layer 90 is formed of a material such as silicon dioxide and may be omitted.
  • branch electrodes and a plurality of electrodes are introduced to smoothly spread current in the semiconductor light emitting device.
  • branch electrodes are provided at the p-side pad electrode 70 and the n-side pad electrode 80.
  • current spreading is improved, and in addition, a plurality of p-side pad electrodes 70 and n-side pad electrodes 80 may be provided for sufficient current supply.
  • Metal-like electrodes such as the p-side pad electrode 70 and the n-side pad electrode 80 have a thick thickness and a large light absorption loss, thereby degrading light extraction efficiency of the light emitting device.
  • the group III nitride semiconductor light emitting device includes a substrate 10 (eg, a sapphire substrate), a buffer layer 20 grown on the substrate 10, an n-type group III nitride semiconductor layer 30 grown on the buffer layer 20, and an n-type 3 Current diffusion conductive film formed on the active layer 40 grown on the group nitride semiconductor layer 30, the p-type group III nitride semiconductor layer 50 grown on the active layer 40, and the p-type group III nitride semiconductor layer 50.
  • a substrate 10 eg, a sapphire substrate
  • a buffer layer 20 grown on the substrate 10
  • an n-type group III nitride semiconductor layer 30 grown on the buffer layer 20
  • an n-type 3 Current diffusion conductive film formed on the active layer 40 grown on the group nitride semiconductor layer 30, the p-type group III nitride semiconductor layer 50 grown on the active layer 40, and the p-type group III nitride semiconductor layer 50 is a substrate 10
  • n-side bonding pad 70 formed on the current diffusion conductive film 60, the p-side bonding pad 70 formed on the current diffusion conductive film 60, the n-type III-nitride semiconductor layer exposed by the mesa-etched p-type III-nitride semiconductor layer 50 and the active layer 40 And an n-side bonding pad 80 and a passivation layer 90 formed over the 30.
  • the buffer layer 20 is to overcome the difference in lattice constant and thermal expansion coefficient between the substrate 10 and the n-type group III nitride semiconductor layer 30.
  • US Pat. No. 5,122,845 discloses a sapphire substrate at 380 ⁇ to 800 ⁇ . A technique for growing an AlN buffer layer having a thickness of 100 kPa to 500 kPa at a temperature is described.
  • U.S. Patent No. 5,290,393 describes Al (x) Ga (T) having a thickness of 10 kPa to 5000 kPa at a temperature of 200 to 900C on a sapphire substrate.
  • a technique for growing a 1-x) N (0 ⁇ x ⁇ 1) buffer layer is described, and US Patent Publication No.
  • 2006/154454 discloses growing a SiC buffer layer (seed layer) at a temperature of 600 ° C. to 990 ° C. Techniques for growing an In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer thereon have been described. Preferably, the undoped GaN layer is grown prior to the growth of the n-type Group III nitride semiconductor layer 30, which may be viewed as part of the buffer layer 20 or as part of the n-type Group III nitride semiconductor layer 30. .
  • the current spreading conductive film 60 is provided so that the current is well supplied to the entire p-type group III nitride semiconductor layer 50.
  • the current spreading conductive film 60 is formed over almost the entire surface of the p-type group III nitride semiconductor layer 50, and is formed of a translucent conductive film using, for example, ITO, ZnO or Ni and Au, or using Ag. It can be formed into a reflective conductive film.
  • the p-side bonding pad 70 and the n-side bonding pad 80 are metal electrodes for supplying current and wire bonding to the outside, for example, nickel, gold, silver, chromium, titanium, platinum, palladium, and rhodium. And iridium, aluminum, tin, indium, tantalum, copper, cobalt, iron, ruthenium, zirconium, tungsten, molybdenum, or any combination thereof.
  • the passivation layer 90 is formed of a material such as silicon dioxide and may be omitted.
  • FIG. 29 is a view showing an example of serially connected LEDs A and B disclosed in US Patent No. 6,547,249. Due to various advantages, as shown in FIG. 29, a plurality of LEDs A and B are used in series. For example, connecting a plurality of LEDs A and B in series reduces the number of external circuits and wire connections, and reduces the light absorption loss due to the wires. In addition, since the operating voltage of the series-connected LEDs A and B all increases, the power supply circuit can be further simplified.
  • an interconnector 34 is deposited to connect the p-side electrode 32 and the n-side electrode 32 of the neighboring LEDs (A, B).
  • a plurality of semiconductor layers must be etched to expose the sapphire substrate 20 in an isolation process that electrically insulates the plurality of LEDs (A, B), because the etching depth is long and takes a long time and a large step is large. It is difficult to form the interconnector 34.
  • the interconnector 34 is formed to have a gentle inclination as shown in FIG. 29 by using the insulator 30, there is a problem in that the integration between the LEDs A and B is increased.
  • FIG. 30 is a view showing another example of a series-connected LED disclosed in US Patent No. 6,547,249.
  • Another method of isolating the plurality of LEDs (A, B) is ion implantation without etching the lower semiconductor layer 22 (for example, n-type nitride semiconductor layer) between the plurality of LEDs (A, B). Insulation between the plurality of LEDs A and B by ion implantation reduces the level of the interconnector 34.
  • it is difficult to implant ions deeply into the lower semiconductor layer 22 and a long process time is a problem.
  • FIG. 31 is a diagram illustrating an example of an LED array disclosed in US Patent No. 7,417,259, in which a two-dimensional LED array is formed on an insulating substrate for driving a high drive voltage and a low current.
  • a sapphire monolithically substrate was used, and two LED arrays were connected in parallel in a reverse direction on the substrate. Therefore, AC power can be used as the direct drive power.
  • 32 is a diagram illustrating an example of a semiconductor light emitting device disclosed in Korean Laid-Open Patent Publication No. 10-2011-0031099.
  • FIG. 32A is a plan view of the light emitting device 201
  • FIG. 32B is a sectional view taken along the line A-A of FIG. 32A
  • FIG. 32C is a sectional view taken along the line B-B of FIG.
  • the light emitting device 201 is provided with a transparent conductive layer 230 provided on the p-side contact layer 228 and a plurality of p electrodes 240 provided in a part of the region on the transparent conductive layer 230.
  • the light emitting device 201 includes a plurality of n electrodes provided on the n-side contact layer 222 exposed by a plurality of vias formed from the p-side contact layer 228 to at least the surface of the n-side contact layer 222.
  • a lower insulating layer 250 provided on the inner surface of the via and the transparent conductive layer 230, and a reflective layer 260 provided inside the lower insulating layer 250 are provided.
  • the reflective layer 260 is provided at portions except the upper portions of the p electrode 240 and the n electrode 242.
  • the lower insulating layer 250 in contact with the transparent conductive layer 230 may include a via 250a extending in the vertical direction on each p electrode 240 and a via 250b extending in the vertical direction on each n electrode 242.
  • the p wiring 270 and the n wiring 272 are provided on the lower insulating layer 250 in the light emitting device 201.
  • the p-wire 270 may include a second planar conductive part 2700 extending in a planar direction on the lower insulating layer 250, and a plurality of second electrically connected to the respective p electrodes 240 through the via 250a. It has a vertical conductive portion 2702.
  • the n wiring 272 may include a first planar conductive part 2720 extending in the planar direction on the lower insulating layer 250, a via 250b of the lower insulating layer 250, and a via formed in the semiconductor stack structure. It has a plurality of first vertical conductive portions 2722 electrically connected to the respective n electrodes 242 through.
  • the light emitting device 201 includes an upper insulating layer 280 provided on the lower insulating layer 250 in contact with the p wiring 270, the n wiring 272, and the transparent conductive layer 230, and an upper insulating layer.
  • P-side junction electrode 290 electrically connected to p-line 270 through p-side opening 280a provided in layer 280 and n-side opening 280b provided in upper insulating layer 280.
  • An n-side junction electrode 292 electrically connected to the wiring 272 is provided.
  • a semiconductor light emitting device including an electrode display unit interposed between a nonconductive reflective film and an insulating layer is provided.
  • a semiconductor light emitting element thicker than the second thickness is provided.
  • a light absorption blocking layer interposed between the light absorption prevention layer and the transparent conductive layer, wherein the light absorption prevention layer and the light absorption blocking layer are formed of different materials.
  • a first light emitting part and a second light emitting part formed in a longitudinal direction, the first semiconductor layer having a first conductivity, A first light emitting unit and a second light emitting unit including a plurality of semiconductor layers sequentially stacked with an active layer that generates light through recombination of electrons and holes, and a second semiconductor layer having a second conductivity different from the first conductivity; A connection electrode formed in a long direction and electrically connecting the first light emitting part and the second light emitting part; A reflective layer formed to cover the first light emitting part, the second light emitting part, and the connection electrode, and reflecting light generated by the active layer; A first electrode part provided to be in electrical communication with the first semiconductor layer of the first light emitting part and supplying one of electrons and holes; And a second electrode part provided to be in electrical communication with the second semiconductor layer of the second light emitting part and supplying the other one of electrons and holes, wherein the connection electrode is partially connected to
  • 1 is a view showing an example of a conventional semiconductor light emitting device chip (Lateral Chip),
  • FIG. 2 is a view showing another example of a flip chip of the semiconductor light emitting device chip disclosed in US Patent No. 7,262,436;
  • FIG. 3 is a view for explaining an example of a semiconductor light emitting device according to the present disclosure.
  • FIGS. 4 to 7 are views for explaining an example of a method of manufacturing a semiconductor light emitting device according to the present disclosure
  • FIGS. 8 to 10 are views for explaining another example of the semiconductor light emitting device according to the present disclosure.
  • 11 and 12 are views for explaining an example of a semiconductor light emitting device according to the present disclosure.
  • FIG. 13 is a view for explaining an example of a method of manufacturing a semiconductor light emitting device according to the present disclosure
  • FIG. 14 is a view for explaining an example of a method of manufacturing a semiconductor light emitting device according to the present disclosure
  • 16 is a view showing an example of a semiconductor light emitting device disclosed in Japanese Laid-Open Patent Publication No. 2006-20913;
  • FIG. 17 illustrates an example of a semiconductor light emitting device according to the present disclosure
  • FIG. 19 illustrates another example of a semiconductor light emitting device according to the present disclosure
  • FIG. 20 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • 21 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • FIG. 22 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • 23 is a view showing an example of a conventional Group III nitride semiconductor light emitting device
  • 26 illustrates another example of a semiconductor light emitting device according to the present disclosure
  • FIG. 27 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • FIG. 28 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • 29 is a view showing an example of a series-connected LED disclosed in US Pat. No. 6,547,249;
  • 31 is a view showing an example of an LED array disclosed in US Patent No. 7,417,259;
  • 32 is a view showing an example of a semiconductor light emitting device disclosed in Korean Laid-Open Patent Publication No. 10-2011-0031099;
  • 33 is a view for explaining an example of a semiconductor light emitting device according to the present disclosure.
  • FIG. 34 is a view for explaining an example of a cut plane taken along the line A-A of FIG. 33;
  • connection electrode 35 is a view for explaining an example of a connection electrode
  • 36 is a view for explaining another example of the semiconductor light emitting device according to the present disclosure.
  • FIG. 37 is a view for explaining another example of a semiconductor light emitting device according to the present disclosure.
  • FIG 3 is a view for explaining an example of the semiconductor light emitting device 1 according to the present disclosure.
  • FIG. 3A is a perspective view and FIG. 3B is a cross-sectional view taken along AA ′.
  • the semiconductor light emitting device 1 may include a substrate 10, a plurality of semiconductor layers 20, 30, 40, and 50, an electrode display unit 100, a reflective layer 91, a first connection electrode 71, and a second connection electrode ( 75, a first electrode 81, and a second electrode 85.
  • the group III nitride semiconductor light emitting element will be described as an example.
  • Sapphire, SiC, Si, GaN and the like are mainly used as the substrate 10, and the substrate 10 may be finally removed.
  • the plurality of semiconductor layers 20, 30, 40, and 50 may include a buffer layer 20 formed on the substrate 10, a first semiconductor layer 30 having a first conductivity (eg, Si-doped GaN), and different from the first conductivity.
  • An active layer 40 eg, an InGaN / (In) GaN multi-quantum well structure.
  • Each of the plurality of semiconductor layers 30, 40, and 50 may be formed in multiple layers, and the buffer layer 20 may be omitted.
  • the electrode display unit 100 displays the polarity of the first electrode 81 and the second electrode 85.
  • the first electrode 81 is connected to the first semiconductor layer 30 (eg, Si-doped GaN) having a first conductivity, that is, an n-type polarity
  • the second electrode 85 is connected to the second conductivity. That is, the second semiconductor layer 50 (eg, Mg-doped GaN) having a p-type polarity is connected.
  • the electrode display portion 100 when viewed from the side of the substrate 10, the electrode display portion 100 indicates that the first electrode 81 has an n-type polarity and the second electrode 85 has a p-type polarity. This can be confirmed by the diode symbol of. In contrast, the polarities of the first electrode 81 and the second electrode 85 may be reversed.
  • grooves or notches have been formed in the edges of opposing first and second electrodes to identify the polarity of the electrodes. Therefore, when observing from the substrate side, it is difficult to distinguish the polarity of the electrode, and it is difficult to identify the presence or absence of grooves or notches.
  • the electrode display unit 100 is formed between the plurality of semiconductor layers 30, 40, 50 and the reflective layer 91, when viewed from the side of the substrate 10, the first electrode 81 and the second electrode ( The polarity of 85 may be easily confirmed through the electrode display unit 100.
  • the electrode display unit 100 may be represented by a diode symbol.
  • the present invention is not limited thereto, and the polarity of the first electrode 81 and the second electrode 85 may be represented by a symbol capable of displaying the polarity thereof.
  • the electrode display unit 100 may be formed to have a thickness and a size that do not affect the semiconductor light emitting device 1.
  • the electrode display part 100 may be formed to a thickness of about 5 ⁇ m or less and a size of about 100 ⁇ m or less.
  • the electrode display unit 100 has a thickness of 2 ⁇ m and a size of 8 ⁇ m.
  • the electrode display unit 100 is made of the same material as the first electrode 81 and the second electrode 85.
  • the electrode display unit 100 is positioned between the plurality of semiconductor layers 30, 40, 50 and the reflective layer 91 in which the first electrode 81 and the second electrode 85 are not formed. That is, the electrode display unit 100 does not overlap the first electrode 81 and the second electrode 85.
  • the reflective layer 91 reflects light from the active layer 40 toward the plurality of semiconductor layers 30, 40, and 50.
  • the reflective layer 91 is formed of a non-conductive reflective film to reduce light absorption by the metal reflective film.
  • the reflective layer 91 includes, for example, a distributed Bragg reflector 91a, a dielectric film 91b and a clad film 91c.
  • the dielectric film 91b or the clad film 91c may be omitted.
  • the entirety of the dielectric film 91b, the distributed Bragg reflector 91a and the clad film 91c function as the nonconductive reflecting film 91.
  • the distribution Bragg reflector 91a reflects the light from the active layer 40 toward the substrate 10 side.
  • the distribution Bragg reflector 91a is preferably formed of a light transmitting material (eg, SiO 2 / TiO 2) to prevent absorption of light.
  • the dielectric film 91b is positioned between the plurality of semiconductor layers 30, 40, and 50 and the distribution Bragg reflector 91a, and the dielectric film 91b is formed of a dielectric (for example, SiO2) having a refractive index smaller than the effective refractive index of the distribution Bragg reflector 91a.
  • the effective refractive index refers to the equivalent refractive index of light that can travel in a waveguide made of materials having different refractive indices.
  • the dielectric film 91b may also help reflection of light, and may also function as an insulating film electrically blocking the first connection electrode 71 from the second semiconductor layer 50 and the active layer 40.
  • the clad film 91c is formed on the distributed Bragg reflector 91a, and the clad film 91c may also be made of a material having a lower refractive index than that of the distributed Bragg reflector 91a (eg, Al2O3, SiO2, SiON, MgF, CaF). have.
  • the relationship between the dielectric film 91b, the distributed Bragg reflector 91a, and the clad film 91c can be described in terms of an optical waveguide.
  • the optical waveguide is a structure that guides the light by using total reflection by surrounding the light propagation part with a material having a lower refractive index.
  • the dielectric film 91b and the clad film 91c surround the propagation section and can be viewed as part of the optical waveguide.
  • At least one first opening 63, a plurality of second openings 5 and 7, and a plurality of third openings 65 are formed in the reflective layer 91.
  • the plurality of first openings 63 are formed to the reflective layer 91, the second semiconductor layer 50, the active layer 40, and a part of the first semiconductor layer 30.
  • a plurality of second openings 5 and 7 are formed through the reflective layer 91, and a plurality of third openings 65 are formed near the edges.
  • the plurality of second openings 5, 7 comprises an internal opening 5 and at least two peripheral openings 7 positioned around the internal opening.
  • the plurality of second openings 5, 7 in this example comprises one inner opening 5 and four peripheral openings 7.
  • the inner opening 5 and the peripheral opening 7 are passageways for hole supply.
  • the inner opening 5 is located approximately in the center of the semiconductor light emitting element 1, and is located between the first electrode 81 and the second electrode 85.
  • the first connection electrode 71 and the second connection electrode 75 are formed on the reflective layer 91, for example, on the clad film 91c.
  • the first connection electrode 71 extends into the plurality of first openings 63 to be electrically connected to the first semiconductor layer 30.
  • the second connection electrode 75 is electrically connected to the second semiconductor layer 50 through the plurality of second openings 5 and 7.
  • the inner opening 5 and the plurality of peripheral openings 7 are electrically connected by the second connection electrode 75.
  • the second connection electrode 75 has a quadrangular plate shape and covers the inner opening 5 and the plurality of peripheral openings 7.
  • the first connection electrode 71 is formed in a closed loop shape to surround the second connection electrode 75.
  • the semiconductor light emitting device 1 includes a third connection electrode 73.
  • the third connection electrode 73 supplies holes to the second semiconductor layer 50 through the third opening 65.
  • the third connection electrode 73 is positioned outside the second connection electrode 75 to connect the plurality of third openings 65 in a closed loop shape.
  • the semiconductor light emitting device 1 includes a conductive film 60 between a plurality of semiconductor layers 30, 40, 50 and a reflective layer 91, for example, between a second semiconductor layer 50 and a dielectric film 91b. It may include.
  • the conductive layer 60 may be formed of a current diffusion electrode (ITO, etc.), an ohmic metal layer (Cr, Ti, etc.), a reflective metal layer (Al, Ag, etc.), or a combination thereof.
  • the conductive film 60 is preferably made of a light transmissive conductive material (eg, ITO).
  • the second connection electrode 75 and the third connection electrode 73 are respectively connected to the conductive layer 60 by being connected to the plurality of second openings 5 and 7 and the plurality of third openings 65.
  • the dielectric film 91b extends between the conductive film 60 and the distributed Bragg reflector 91a to the inner surface of the first opening 63, thereby connecting the first connection electrode 71 to the second semiconductor layer 50.
  • the active layer 40 and the second connection electrode 75 may be formed between the dielectric film 91b and the conductive film 60.
  • the inner opening 5 of the plurality of second openings 5, 7 functions to further increase the light emission as compared to the case where there is no inner opening 5 in the local area in which the inner opening 5 is located.
  • the number, spacing, and arrangement of the first openings 63, the second openings 5, 7, and the third openings 65 are used for the size of the semiconductor light emitting device, the current spreading and the uniform current supply, and the uniformity of the light emission. Can be adjusted appropriately.
  • at least one inner opening 5 may be formed.
  • the plurality of peripheral openings 7, the plurality of first openings 63, and the plurality of third openings 65 are formed symmetrically with respect to the inner opening 5.
  • a current is supplied through the plurality of first openings 63 and the plurality of second openings 5, 7, and when the current is nonuniform, a portion of the first openings 63 and the second openings 5, 7 is supplied. This can be biased, which can lead to deterioration in locations where current is biased in the long run.
  • the first connection electrode 71 is formed in a closed loop shape to surround the second connection electrode 75, and the third connection electrode 73 also surrounds the second connection electrode 75 and has a closed loop shape.
  • the closed loop shape is not limited to the complete closed loop shape, but may include a closed loop shape in which a part is broken.
  • the closed loop shape may have a shape along the outer shape of the light emitting surface of the semiconductor light emitting device to improve the uniformity of the current distribution.
  • the electrical opening to the inner opening 5 may be difficult or other complicated designs may have to be taken into account in this example, so that the inner opening 5 may be considered.
  • the plurality of peripheral openings 7 become currents having the same polarity, that is, hole supply passages. As described above, when both the inner opening 5 and the plurality of peripheral openings 7 become the hole supply passages, in view of electron supply, the plurality of semiconductor layers 30, 40, 50 under the second connection electrode 75. ) Is expected to be smaller than the electron density in the plurality of semiconductor layers 30, 40, 50 outside the second connection electrode 75.
  • the present disclosure confirmed that the light emission increased in the plurality of semiconductor layers 30, 40, and 50 under the second connection electrode 75 as compared with the case where there was no internal opening 5.
  • the semiconductor layers 30, 40, and 50 under the second connection electrode 75 holes having a relatively high density due to the internal opening 5 attract electrons in a region having a relatively low hole density. It is assumed that this is caused by an increase in the recombination rate of the holes.
  • the inner opening 5 inside the second connection electrode 75 while the second openings 5, 7 and the plurality of third openings 65 achieve an improved uniform current distribution in a closed loop shaped arrangement and a symmetrical arrangement. ) May be maintained or increased.
  • a suitable value of the area of the second connection electrode 75 or the distance between the inner opening 5 and the peripheral opening 7 can be found. For example, as the distance between the inner opening 5 and the peripheral opening 7 increases, the area of the second connection electrode 75 increases and the area of which the hole density is relatively high increases. If the area of the second connection electrode 75 is increased, the hole supply can be made larger. In order to maintain the light emission performance of the semiconductor light emitting element 1, it is preferable that the temperature difference between the positions on the light emitting surface is small. If the area of the second connection electrode 75 is increased, the number of electrical connections with the second electrode 85 to be described later may be further increased, and may be more advantageous for heat dissipation through the second electrode 85.
  • the area of the second connection electrode 75 when the area of the second connection electrode 75 is increased, a region having a relatively high hole density on the light emitting surface increases, which may not be good in terms of uniformity.
  • the extent to which the holes attract electrons to emit light may be influenced by the area of the second connection electrode 75 or the distance and number of the inner opening 5 and the peripheral opening 7. Therefore, it is possible to determine the area of the second connection electrode 75 or the distance and the number of the peripheral opening 7 and the area of the second connection electrode 75 by selecting which advantage to select in the design of the semiconductor light emitting device.
  • the semiconductor light emitting device 1 includes an insulating layer 95 covering the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73 on the reflective layer 91. At least one fourth opening 67, at least one fifth opening 68, and at least one sixth opening 69 are formed in the insulating layer 95.
  • the insulating layer 95 may be made of SiO 2.
  • the first electrode 81 and the second electrode 85 are formed on the insulating layer 95.
  • the first electrode 81 is electrically connected to the first connection electrode 71 through at least one fourth opening 67 to supply electrons to the first semiconductor layer 30.
  • the second electrode 85 is electrically connected to the second connection electrode 75 through the fifth opening 68, and is electrically connected to the third connection electrode 73 through the sixth opening 69. Holes are supplied to the semiconductor layer 50.
  • the first electrode 81 and the second electrode 85 may be electrodes for eutectic bonding.
  • the semiconductor light emitting device 1 reduces the light absorption by using the non-conductive reflecting film 91 including the distribution Bragg reflector 91a instead of the metal reflecting film.
  • a plurality of first openings 63, a plurality of second openings 5 and 7, and a plurality of third openings 65 are formed to facilitate current diffusion into the plurality of semiconductor layers 30, 40, and 50. Let's do it.
  • the inner opening 5 covered by the innermost second connection electrode 75 is formed to maintain or increase light emission in the inner region.
  • 4 to 7 illustrate an example of a method of manufacturing the semiconductor light emitting device 1 according to the present disclosure.
  • a plurality of semiconductor layers 30, 40, 50 are grown on the substrate 10.
  • a buffer layer eg, an AlN or GaN buffer layer
  • an undoped semiconductor layer eg, an un-doped GaN
  • a first layer are formed on the substrate 10 (eg, Al 2 O 3, Si, SiC).
  • a first semiconductor layer 30 having a conductivity e.g., Si doped GaN
  • an active layer 40 that generates light through recombination of electrons and holes InGaN / (In) GaN multi-quantum well structure
  • a second semiconductor layer 50 eg, Mg doped GaN having another second conductivity is grown.
  • the buffer layer 20 may be omitted, and each of the plurality of semiconductor layers 30, 40, and 50 may be formed in multiple layers.
  • the first semiconductor layer 30 and the second semiconductor layer 50 may be formed with opposite conductivity, but are not preferable in the case of a group III nitride semiconductor light emitting device.
  • the conductive film 60 is formed on the second semiconductor layer 50.
  • the conductive layer 60 may be formed of a light transmissive conductor (eg, ITO) to reduce light absorption. Although the conductive film 60 may be omitted, it is generally provided to spread the current to the second semiconductor layer 50.
  • a light transmissive conductor eg, ITO
  • the electrode display unit 100 is formed on the conductive film 60.
  • the electrode display unit 100 is positioned between the semiconductor layers 30, 40, 50 and the reflective layer 91 in which the first electrode 81 and the second electrode 85 are not formed. That is, the electrode display unit 100 does not overlap the first electrode 81 and the second electrode 85.
  • the reflective layer 91 is formed on the conductive film 60.
  • the dielectric film 91b, the distributed Bragg reflector 91a, and the clad film 91c covering the conductive film 60 are formed.
  • the dielectric film 91b or the clad film 91c may be omitted.
  • the distributed Bragg reflector 91a is formed by stacking a pair of SiO 2 and TiO 2 a plurality of times, for example.
  • the distribution Bragg reflector 91a may be formed of a combination of a high refractive index material such as Ta 2 O 5, HfO, ZrO, and SiN, and a dielectric thin film (typically SiO 2) having a lower refractive index.
  • a high refractive index material such as Ta 2 O 5, HfO, ZrO, and SiN
  • a dielectric thin film typically SiO 2
  • the thickness of each layer does not have to obey an optical thickness of 1/4 of the wavelength.
  • the number of combinations is suitable for 4 to 20 pairs.
  • the effective refractive index of the distribution Bragg reflector 91a is larger than the refractive index of the dielectric film 91b for the reflection and guide of light.
  • the distributed Bragg reflector 91a is composed of SiO 2 / TiO 2
  • the effective refractive index of the distributed Bragg reflector has a value between 1.46 and 2.4.
  • the dielectric film 91b may be made of SiO2, and the thickness thereof is appropriately 0.2um to 1.0um. Prior to the deposition of the distributed Bragg reflector 91a requiring precision, by forming the dielectric film 91b having a predetermined thickness, the distributed Bragg reflector 91a can be stably manufactured and can also help reflection of light. .
  • the clad film 91c may be made of a metal oxide such as Al2O3, a dielectric film 91b such as SiO2, SiON, MgF, CaF, or the like.
  • the clad film 91c may also be formed of SiO 2 having a refractive index of 1.46 smaller than the effective refractive index of the distribution Bragg reflector 91a.
  • the clad film 91c is located below the distributed Bragg reflector 91a. It is preferable to be thicker than [lambda] / 4n so as to be distinguished from the uppermost layer.
  • the clad film 91c is not only burdened with the subsequent steps of forming the plurality of first openings 63 and the plurality of second openings 5, 7 but also because the increase in thickness does not contribute to the improvement of efficiency and only the material cost can be increased. ) Is not too thick beyond 3.0um.
  • the maximum value of the clad film 91c is formed within 1 ⁇ m to 3 ⁇ m. It will be advisable to be. However, in some cases, it is not impossible to form more than 3.0um.
  • the distribution Bragg reflector 91a and the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73 are in direct contact with each other, a part of the light traveling through the distribution Bragg reflector 91a Absorption may occur by the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73. Therefore, by introducing the clad film 91c and the dielectric film 91b having a lower refractive index than the distribution Bragg reflector 91a as described above, the amount of light absorption can be greatly reduced.
  • the dielectric film 91b is omitted may be considered, it is not preferable from the viewpoint of the optical wave guide, but from the viewpoint of the overall technical idea of the present disclosure, it is composed of the distributed Bragg reflector 91a and the clad film 91c. There is no reason to rule out this.
  • the distribution Bragg reflector 91a instead of the distribution Bragg reflector 91a, one may consider the case where the dielectric film 91b made of TiO2 is used as the dielectric material. In the case where the distribution Bragg reflector 91a is provided with an SiO2 layer at the top, the case where the clad film 91c is omitted may also be considered.
  • the dielectric film 91b, the distributed Bragg reflector 91a, and the clad film 91c serve as an optical waveguide as a non-conductive reflecting film, and preferably have a total thickness of 1 to 8 um.
  • the plurality of first openings 63 and the plurality of second openings 5 in the reflective layer 91 by dry etching or wet etching, or a combination thereof. , 7) and a plurality of third openings 65 are formed.
  • the first opening 63 is formed to the reflective layer 91, the second semiconductor layer 50, the active layer 40, and a portion of the first semiconductor layer 30.
  • the second openings 5 and 7 and the third opening 65 are formed to penetrate the reflective layer 91 to expose a portion of the conductive film 60.
  • the first opening 63, the second openings 5, 7 and the third opening 65 may be formed after the formation of the reflective layer 91, but alternatively, before the conductive film 60 is formed or the conductive film 60.
  • the first openings 63 are partially formed in the plurality of semiconductor layers 30, 40, and 50, and the reflective layers 91 are formed to cover the first openings 63, and then penetrate the reflective layers 91.
  • the first opening 63 can be formed through the process of, and the second openings 5, 7 and the third opening 65 can be formed simultaneously with the further process or in another process.
  • the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73 are formed on the reflective layer 91.
  • the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73 may be deposited using sputtering equipment, E-beam equipment, or the like.
  • the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73 may be formed using Cr, Ti, Ni, or a combination thereof for stable electrical contact.
  • the same reflective metal layer may be included.
  • the first connection electrode 71 may be formed to contact the first semiconductor layer 30 through the plurality of first openings 63, and the second connection electrode 75 may be the plurality of second openings 5 and 7. ),
  • the third connection electrode 73 may be formed to contact the conductive layer 60 through the plurality of third openings 65.
  • an insulating layer 95 is formed to cover the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73.
  • Representative material of the insulating layer 95 is SiO 2, but is not limited thereto, and SiN, TiO 2, Al 2 O 3, Su-8, or the like may be used.
  • at least one fourth opening 67, at least one fifth opening 68, and at least one sixth opening 69 are formed in the insulating layer 95.
  • the first electrode 81 and the second electrode 85 may be deposited on the insulating layer 95 using sputtering equipment, E-beam equipment, or the like.
  • the first electrode 81 is connected to the first connection electrode 71 through at least one fourth opening 67
  • the second electrode 85 is at least one fifth opening 68 and at least one agent. It is connected to the second connection electrode 75 and the third connection electrode 73 through the six opening 69.
  • the first electrode 81 and the second electrode 85 are displayed with their polarities by the electrode display unit 100, and do not overlap with the electrode display unit 100.
  • the first electrode 81 and the second electrode 85 may be electrically connected to electrodes provided outside (package, COB, submount, etc.) by a method such as stud bump, conductive paste, and eutectic bonding.
  • a method such as stud bump, conductive paste, and eutectic bonding.
  • the semiconductor light emitting device 1 according to the present example since the first electrode 81 and the second electrode 85 can be formed on the insulating layer 95 by the same process, there is almost no height difference between the two electrodes. Thus there is an advantage in the case of eutectic bonding.
  • the uppermost portions of the first electrode 81 and the second electrode 85 are eutectic bonding such as Au / Sn alloy and Au / Sn / Cu alloy. It can be formed of a material.
  • FIG. 8 is a view for explaining another example of the semiconductor light emitting device according to the present disclosure.
  • the semiconductor light emitting element 11 illustrates a flip chip.
  • the semiconductor light emitting device 11 is not limited to such a flip chip, and a lateral chip or a vertical chip may also be applied.
  • the semiconductor light emitting device 11 may include a substrate 10, a plurality of semiconductor layers 30, 40, and 50, an electrode display unit 100, a light reflection layer R, a first electrode 80, and a second electrode 70. It includes.
  • sapphire, SiC, Si, GaN, and the like may be used as the substrate 10 as a group III nitride semiconductor light emitting device, and the substrate 10 may be finally removed.
  • the plurality of semiconductor layers 30, 40, and 50 may include a buffer layer (not shown) formed on the substrate 10, a first semiconductor layer 30 having a first conductivity (eg, Si-doped GaN), and different from the first conductivity.
  • An active layer 40 eg, an InGaN / (In) GaN multi-quantum well structure).
  • Each of the semiconductor layers 30, 40, and 50 may be formed in multiple layers, and the buffer layer may be omitted.
  • the positions of the first semiconductor layer 30 and the second semiconductor layer 50 may be changed, and are mainly made of GaN in the group III nitride semiconductor light emitting device.
  • the first electrode 80 is in electrical communication with the first semiconductor layer 30 to supply electrons.
  • the first electrode 80 has a first conductivity, that is, an n-type polarity.
  • the second electrode 70 is in electrical communication with the second semiconductor layer 50 to supply holes.
  • the second electrode 70 has a second conductivity, that is, a p-type polarity.
  • a light reflection layer R is interposed between the second semiconductor layer 50 and the first and second electrodes 80 and 70, and the light reflection layer R is an insulating layer such as SiO 2, a distributed bragg reflector (DBR), or an ODR. It may have a multilayer structure including an omni-directional reflector.
  • DBR distributed bragg reflector
  • the electrode display unit 100 is interposed between the second semiconductor layer 50 and the light reflection layer R on which the first electrode 80 and the second electrode 70 are not formed, and the first electrode 80 and the second electrode. It is located between the electrodes 70. That is, the electrode display unit 100 does not overlap the first electrode 80 and the second electrode 70.
  • the polarity of the first electrode 80 and the second electrode 70 is displayed.
  • the electrode display unit 100 may be represented by a diode symbol, but is not limited thereto.
  • the electrode display unit 100 may be represented by a symbol capable of displaying polarities of the first electrode 80 and the second electrode 70. .
  • the diode symbol of the electrode display portion 100 indicates that the first electrode 80 has an n-type polarity and the second electrode 70 has a p-type polarity. You can check it through
  • FIG. 9 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • a metal reflective film R is provided on the second semiconductor layer 50, a second electrode 70 is provided on the metal reflective film R, and the first semiconductor layer 30 exposed by mesa etching. ) May be different from the first electrode 80.
  • a transparent conductive film (not shown) may be interposed between the second semiconductor layer 50 and the light reflection layer R.
  • the electrode display unit 100 is interposed between the second semiconductor layer 50 and the light reflection layer R on which the first electrode 80 and the second electrode 70 are not formed, and the first electrode 80 and the second electrode. It is located between the electrodes 70. That is, the electrode display unit 100 does not overlap the first electrode 80 and the second electrode 70.
  • the polarity of the first electrode 80 and the second electrode 70 is displayed.
  • the electrode display unit 100 may be represented by a diode symbol, but is not limited thereto.
  • the electrode display unit 100 may be represented by a symbol capable of displaying polarities of the first electrode 80 and the second electrode 70. .
  • the diode symbol of the electrode display portion 100 indicates that the first electrode 80 has an n-type polarity and the second electrode 70 has a p-type polarity. You can check it through
  • FIG. 10 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • the semiconductor light emitting device shown in FIG. 10 is substantially the same as the semiconductor light emitting device described in FIG. 9 except for the formation position of the electrode display unit 100. Therefore, duplicate description is omitted.
  • the electrode display unit 100 is interposed between the second semiconductor layer 50 and the light reflection layer R on which the first electrode 80 and the second electrode 70 are not formed, and the first electrode 80 and the second electrode. It does not overlap with the electrode 70.
  • the first electrode 80 is positioned on the first surface, that is, the upper surface thereof, or as shown in FIG. 10 (b), the first electrode 80. It may be located on the second surface, that is, the lower surface opposite to the first surface of the).
  • the present invention is not limited thereto and may be interposed between the second semiconductor layer 50 and the light reflection layer R which do not overlap the first electrode 80 and the second electrode 70.
  • FIG. 11 is a diagram illustrating an example of a semiconductor light emitting device according to the present disclosure
  • FIG. 12 is a diagram illustrating an example of a cross section taken along line A-A in FIG. 11.
  • the semiconductor light emitting device 1 may include a substrate 10, a plurality of semiconductor layers 30, 40, and 50, a non-conductive reflective film 91, an insulating layer 95, and a first electrode part. 80, a second electrode portion 70, and an electrode display portion 100.
  • the group III nitride semiconductor light emitting element will be described as an example.
  • Sapphire, SiC, Si, GaN and the like are mainly used as the substrate 10, and the substrate 10 may be finally removed.
  • the plurality of semiconductor layers 30, 40, and 50 may include a first semiconductor layer 30, an active layer 40, and a second semiconductor layer 50 sequentially stacked.
  • the positions of the first semiconductor layer 30 and the second semiconductor layer 50 may be changed, and are mainly made of GaN in the group III nitride semiconductor light emitting device.
  • the plurality of semiconductor layers 30, 40, and 50 may include a buffer layer 20 formed on the substrate 10, a first semiconductor layer 30 having a first conductivity (eg, Si-doped GaN), and a second different from the first conductivity.
  • a conductive second semiconductor layer 50 eg, Mg-doped GaN
  • an active layer interposed between the first semiconductor layer 30 and the second semiconductor layer 50 to generate light through recombination of electrons and holes ( 40; e.g., InGaN / (In) GaN multi-quantum well structure).
  • Each of the plurality of semiconductor layers 30, 40, and 50 may be formed in multiple layers, and the buffer layer 20 may be omitted.
  • the active layer 40 is formed between the first semiconductor layer 30 and the second semiconductor layer 50 and generates light.
  • the semiconductor light emitting device 1 includes a light-transmissive conductive film between the plurality of semiconductor layers 30, 40, 50 and the nonconductive reflecting film 91, for example, between the second semiconductor layer 50 and the nonconductive reflecting film 91. 60).
  • the transparent conductive film 60 may be omitted.
  • the transparent conductive layer 60 may be formed of a transparent conductive material (eg, ITO), an ohmic metal layer (Cr, Ti, etc.), a reflective metal layer (Al, Ag, etc.), or a combination thereof.
  • the light transmissive conductive film 60 is preferably made of a light transmissive conductive material (eg, ITO).
  • the non-conductive reflective film 91 may be formed on the plurality of semiconductor layers 130, 140, and 150 to reflect the light generated by the active layer 40 toward the first semiconductor layer 30, and may be formed of a dielectric material. In the present disclosure, the nonconductive reflective film 91 is formed to cover the transparent conductive film 60, the first and second ohmic electrodes 81 and 71, and the plurality of semiconductor layers 30, 40, and 50.
  • the non-conductive reflecting film 91 is insulative and is connected to the plurality of semiconductor layers 30, 40, 50 by an electrical connection 82, 72 passing through the non-conductive reflecting film 91. It is a flip chip in electrical communication.
  • the non-conductive reflecting film 91 is formed of an insulating material at least the side of the light reflecting of the non-conductive reflecting film 91 to reduce the light absorption by the metal reflecting film, preferably DBR (Distributed Bragg Reflector) or ODR It may be a multilayer structure including an omni-directional reflector. Insulating means that the non-conductive reflecting film 91 is not used as a means of electrical conduction, and does not necessarily mean that the entire non-conductive reflecting film 91 should be made of only a non-conductive material.
  • An example of the multilayer structure includes a dielectric film 91b, a distributed Bragg reflector 91a, and a clad film 91c.
  • the dielectric film 91b may reduce the height difference to stably manufacture the distributed Bragg reflector 91a and may also help to reflect light.
  • SiO 2 is a suitable material for the dielectric film 91b.
  • the distributed Bragg reflector 91a is formed on the dielectric film 91b.
  • the distribution Bragg reflector 91a may consist of repeated stacking of materials with different reflectances, for example, SiO 2 / TiO 2 , SiO 2 / Ta 2 O 2 , or SiO 2 / HfO, and for blue light SiO 2 / TiO 2 has a good reflection efficiency, and for UV light, SiO 2 / Ta 2 O 2 , or SiO 2 / HfO will have a good reflection efficiency.
  • the clad film 91c may be made of a metal oxide such as Al 2 O 3 , a dielectric film 91b such as SiO 2 , SiON, MgF, CaF, or the like.
  • the distributed Bragg reflector 91a has a higher reflectance as light closer to the vertical direction reflects approximately 99% or more.
  • each material layer of a multilayer structure must be formed to a specially designed thickness.
  • the non-conductive reflecting layer 91 has portions where height differences occur in the non-conductive reflecting layer 91 due to the following structures (for example, ohmic electrodes and trenches between the light emitting parts). Due to this height difference, there is an area in which each material layer of the nonconductive reflecting film 91 is hard to be formed to a designed thickness, and in this area, the reflection efficiency may decrease. The reflection efficiency may be lower than that of other parts between the light emitting parts. Therefore, forming as few metal layers between the light emitting portions as possible is preferable to reduce the light absorption loss by the metal.
  • the insulating layer 95 is formed on the nonconductive reflecting film 91.
  • the insulating layer 95 is formed to cover the first and second connection electrodes 83 and 73 and the nonconductive reflective film 91.
  • the insulating layer 95 may be made of SiO 2 .
  • the insulating layer 95 is not limited thereto, and SiN, TiO 2 , Al 2 O 3 , Su-8, or the like may be used.
  • the refractive index of the insulating layer 95 covering the non-conductive reflective film 91 is similar to that of the non-conductive reflective film 91, so it is not reflected and transmits well. Therefore, some of the light that is not reflected by the non-conductive reflecting film 91 exits to the insulating layer 95 and has a problem in that light efficiency is inferior. Therefore, the first and second connection electrodes 83 and 73 cover the light exiting to the insulating layer 95 entirely on the non-conductive reflecting film 91 to reflect the light exiting to the insulating layer 95. do.
  • the first electrode portion 80 and the second electrode portion 70 are the ohmic electrodes 81 and 71, the connection electrodes 83 and 73, the electrical connections 82, 84, 72 and 74, and the pad electrodes 85 and 75. Each).
  • the first electrode portion 80 and the second electrode portion 70 are symmetrically arranged around the connecting electrodes 83 and 73 for current spreading and equal current supply. Therefore, it has a very symmetrical structure and is a good structure for improving uniformity.
  • the first electrode part 80 is provided to be in electrical communication with the first semiconductor layer 30, and supplies one of electrons and holes, and the second electrode part 70 is electrically connected to the second semiconductor layer 50. It is provided to communicate, and supplies the other one of the electron and the hole.
  • the first connection electrode 83 and the second connection electrode 73 are formed on the nonconductive reflective film 191.
  • the first connection electrode 83 penetrates the non-conductive reflecting film 91, is electrically connected to the first semiconductor layer 30 through the first electrical connection 82, and the second connection electrode 73.
  • the light penetrates the non-conductive reflecting layer 91 and is electrically connected to the second semiconductor layer 50 through the second electrical connection 72.
  • first connection electrode 83 and the second connection electrode 73 are formed on the non-conductive reflecting film 91 in a wide manner. This is because the first connection electrode 83 and the second connection electrode 73 may absorb shocks on the nonconductive reflective film 91 to prevent cracking or breaking of the nonconductive reflective film 91.
  • first connection electrode 83 and the second connection electrode 73 are made of metal, the first connection electrode 83 and the second connection electrode 73 may also absorb light, so that the first connection electrode 83 and the second connection electrode 73 may be formed to be narrow. I think that it is a method to raise brightness.
  • the first connection electrode 83 and the second connection electrode 73 may be formed of metal.
  • the first ohmic electrode 81 is formed between the first electrical connection 82 and the first semiconductor layer 30 to reduce contact resistance and provide stable electrical connection
  • the second ohmic electrode 71 is formed of the second electrical connection ( It is formed between the 72 and the second semiconductor layer 50 for reducing contact resistance and stable electrical connection.
  • Ohmic metal may be used for the first ohmic electrode 81 and the second ohmic electrode 71.
  • the first ohmic electrode 81 and the second ohmic electrode 71 are formed of an island type electrode made of a dot, a circle, a polygon, and the like, and generally mean a shape that does not extend to one side.
  • the operating voltage of the semiconductor light emitting device 1 is lowered due to the first ohmic electrode 81 and the second ohmic electrode 71.
  • heights of the first and second ohmic electrodes 81 and 71 may be minimized to increase the reflectance of the non-conductive reflecting film 91.
  • the distortion of the non-conductive reflecting film 91 may be reduced, thereby decreasing the reflectance.
  • the third electrical connection 84 and the fourth electrical connection 74 penetrate through the insulating layer 95, and the first pad electrode 85 and the second pad electrode 75, the first connection electrode 83, and the first connection electrode 83 and the first connection electrode 83 and the first connection electrode 83 and the first connection electrode 83, respectively.
  • the two connecting electrodes 73 are electrically connected to each other.
  • the third electrical connection 84 is in electrical communication with the first pad electrode 85 and the first connection electrode 83
  • the fourth electrical connection 74 is connected with the second pad electrode 75 and the second.
  • the connection electrode 73 is in electrical communication.
  • a plurality of third electrical connections 84 and fourth electrical connections 74 may be formed. For example, the number of the third electrical connection 84 and the fourth electrical connection 74 may be greater than the number of the first electrical connection 82 and the second electrical connection 72.
  • the first pad electrode 85 is electrically connected to the first connection electrode 83 through the third electrical connection 84 to supply electrons to the first semiconductor layer 30.
  • the second pad electrode 75 is electrically connected to the second connection electrode 73 through the fourth electrical connection 74 to supply holes to the second semiconductor layer 50.
  • the first pad electrode 85 and the second pad electrode 75 are electrodes for electrical connection with the external electrode, and may be eutectic bonded, soldered or wire bonded with the external electrode.
  • the external electrode may be a conductive part provided in the sub-mount, a lead frame of the package, an electrical pattern formed on the PCB, and the like, and the external electrode may not be particularly limited in form.
  • the first pad electrode 85 and the second pad electrode 75 are formed to have an area to some extent, so that they become heat dissipation passages.
  • first ohmic electrode 81, the second ohmic electrode 71, the first connection electrode 83, the second connection electrode 73, and the like are formed in the semiconductor light emitting device.
  • the lowermost layer should have high bonding strength and bonding strength, and materials such as Cr and Ti may be mainly used, and Ni, Ti, TiW, and the like may also be used.
  • Au is used for wire bonding or for connection with external electrodes. In order to reduce the amount of Au and compensate for the relatively soft Au properties, Ni, Ti, TiW, W, or the like is used between the lowermost layer and the uppermost layer depending on the required specification, or when a high reflectance is required. , Al, Ag and the like are used.
  • the electrode display unit 100 When the electrode display unit 100 is interposed between the non-conductive reflecting film 91 and the insulating layer 95, the electrode display unit 100 displays the polarity of the first pad electrode 85 and the second pad electrode 75.
  • the electrode display unit 100 is positioned below at least one pad electrode of the first pad electrode 85 and the second pad electrode 75, and corresponds to the selected first pad electrode 85 and the second pad electrode 75. It is positioned on the same layer as the first connection electrode 83 or the second connection electrode 73. In this case, the electrode display unit 100 does not overlap the first connection electrode 83 or the second connection electrode 73.
  • the electrode display unit 100 corresponds to the second pad electrode 75, and the same layer as the second connection electrode 73 without overlapping the second connection electrode 73 under the second pad electrode 75. It can be located at On the contrary, the electrode display unit 100 does not overlap the first connection electrode 83 under the first pad electrode 85 in correspondence with the first pad electrode 85, and is the same layer as the first connection electrode 83. It can be located at
  • the electrode display unit 100 may include at least one hole, and may be formed in an island type shape including a dot, a circle, a rectangle, and a polygon. In the present disclosure, the electrode display unit 100 is illustrated to have a circular shape when it has three holes, but is not limited thereto.
  • the electrode display unit 100 may be formed to have a thickness and a size that do not affect the semiconductor light emitting device 1.
  • the size of the electrode display unit 100 is greater than the opening size of the second electrical connection 84 and the fourth electrical connection 74, the thickness of the electrode display unit 100 is the first connection electrode 83 and the first electrode. It is preferable to have the same thickness as the thickness of the two connection electrode 73.
  • the electrode display unit 100 is made of the same material as the first connection electrode 83 and the second connection electrode 73.
  • the first pad electrode 85 is connected to the first semiconductor layer 30 having a first conductivity, that is, an n-type polarity (eg, Si-doped GaN), and the second pad electrode 75 is formed of a first pad electrode 75. It is connected to the second semiconductor layer 50 (eg, Mg-doped GaN) having a second conductivity, that is, a p-type polarity.
  • a first conductivity that is, an n-type polarity (eg, Si-doped GaN)
  • the second pad electrode 75 is formed of a first pad electrode 75. It is connected to the second semiconductor layer 50 (eg, Mg-doped GaN) having a second conductivity, that is, a p-type polarity.
  • the first pad electrode 85 and the second pad electrode 75 are provided on opposite sides of the plurality of semiconductor layers 30, 40, and 50 with respect to the non-conductive reflective film 91. Since the electrode display part 100 is positioned on the same layer as the second connection electrode 73 under the second pad electrode 75 when viewed in the direction of the substrate 10, the first pad electrode 85 has an n-type polarity. It can be confirmed that the second pad electrode 75 has a p-type polarity through the electrode display unit 100. In contrast, the polarities of the first pad electrode 85 and the second electrode 75 may be reversed.
  • grooves or notches have been formed in the edges of opposing first and second pad electrodes to identify the polarity of the electrodes. Therefore, when observing from the substrate side, it is difficult to distinguish the polarity of the electrode, and it is difficult to identify the presence or absence of grooves or notches.
  • the electrode display unit 100 when the electrode display unit 100 is formed on the non-conductive reflecting film 91, when viewed from the side of the substrate 10, the polarity of the first pad electrode 85 and the second electrode 75 has the electrode display unit ( 100) can be easily checked.
  • the first semiconductor layer 30, the active layer 40, the second semiconductor layer 50, the current diffusion electrode 60 on the substrate 10 Eg, ITO is formed and mesa-etched to expose a portion of the first semiconductor layer 30 corresponding to the first electrical connection 73.
  • Mesa etching may be performed before or after the current diffusion electrode 60 is formed.
  • the current spreading electrode 60 can be omitted.
  • ohmic electrodes 71 and 81 are formed on the current diffusion electrode 60 and the exposed first semiconductor layer 30, respectively. Although the ohmic electrodes 71 and 81 may be omitted, the ohmic electrodes 71 and 81 may be provided to suppress an increase in operating voltage and to provide stable electrical contact.
  • the current diffusion electrode 60 may be considered to form a light absorption prevention film on the second semiconductor layer 50 corresponding to the ohmic electrode 81.
  • a non-conductive reflecting film 91 is formed on the current spreading electrode 60.
  • the dielectric film 91b, the distributed Bragg reflector 91a, and the clad film 91c covering the conductive film 60 are formed.
  • the dielectric film 91b or the clad film 91c may be omitted.
  • a first electrical connection 82 and a second electrical connection 72 formed of openings in the non-conductive reflective film 91 are formed by dry etching or wet etching, or a combination thereof.
  • the first electrical connection 82 and the second electrical connection 72 are formed to contact the first ohmic electrode 81 and the second ohmic electrode 71, respectively.
  • the first electrical connection 82 is formed up to the non-conductive reflective film 91, the second semiconductor layer 50, the active layer 40, and a portion of the first semiconductor layer 30.
  • the second electrical connection 72 is formed to penetrate the non-conductive reflecting film 91 to expose a portion of the current spreading electrode 60.
  • the first electrical connection 82 and the second electrical connection 72 may be formed after the formation of the nonconductive reflecting film 91, but alternatively, a plurality of the first and second electrical connections 82 and 72 may be formed before or after the formation of the nonconductive reflecting film 91.
  • the non-conductive reflective film 91 is formed to cover the first electrical connection 82, and then the non-conductive reflective film 91 is formed.
  • the first electrical connection 82 may be formed through additional processing therethrough, and the second electrical connection 72 may be formed concurrently or with another process.
  • the first connection electrode 83 and the second connection electrode 73 are formed on the nonconductive reflecting film 91.
  • the first connection electrode 83 and the second connection electrode 73 may be deposited using sputtering equipment, E-beam equipment, or the like.
  • the first connection electrode 83 and the second connection electrode 73 may be formed using Cr, Ti, Ni, or an alloy thereof for stable electrical contact, and may include a reflective metal layer such as Al or Ag. .
  • the first connection electrode 83 may be formed to contact the first semiconductor layer 30 through the plurality of first electrical connections 82, and the second connection electrode 73 may connect the second electrical connection 72. It may be formed to contact the current diffusion electrode 60 through.
  • the electrode display unit 100 is formed on the nonconductive reflecting film 91 corresponding to the pad electrodes 85 and 75.
  • the electrode display unit 100 is formed on the non-conductive reflective film 91 in which the first connection electrode 83 and the second connection electrode 73 are not formed corresponding to the pad electrodes 85 and 75. That is, the electrode display unit 100 does not overlap with the first connection electrode 83 and the second connection electrode 73.
  • it may be formed inside the second connection electrode 73 as shown in FIG. 13 (a) or may be formed outside the first connection electrode 83 as shown in FIG. 13 (b). have.
  • the present invention is not limited thereto, and the electrode display unit 100 may be positioned anywhere on the non-conductive reflective film 91 that does not overlap the first connection electrode 83 or the second connection electrode 73.
  • the electrode display unit 100 may be formed before forming the first connection electrode 83 and the second connection electrode 73.
  • it may be formed inside the second connection electrode 73 as shown in FIG. 14 (a) or may be formed outside the first connection electrode 83 as shown in FIG. 14 (b). have.
  • the present invention is not limited thereto, and the electrode display unit 100 may be positioned anywhere on the non-conductive reflective film 91 that does not overlap the first connection electrode 83 or the second connection electrode 73.
  • an insulating layer 95 is formed to cover the electrode display unit 100, the first connection electrode 83, and the second connection electrode 73.
  • Representative material of the insulating layer 95 is SiO 2 , without being limited thereto, SiN, TiO 2 , Al 2 O 3 , Su-8 and the like may be used.
  • a third electrical connection 84 and a fourth electrical connection 74 formed of openings in the insulating layer 95 are formed by dry etching or wet etching, or a combination thereof.
  • the third electrical connection 84 and the fourth electrical connection 74 are formed to contact the first connection electrode 83 and the second connection electrode 73, respectively.
  • the third electrical connection 84 and the fourth electrical connection 74 may be formed after the insulating layer 95 is formed, or alternatively, may be formed before the insulating layer 95 is formed.
  • the first pad electrode 85 and the second pad electrode 75 may be electrically connected to an external electrode (package, COB, submount, etc.) by a method such as stud bump, conductive paste, and eutectic bonding. have.
  • a method such as stud bump, conductive paste, and eutectic bonding.
  • the semiconductor light emitting device according to the present example since the first pad electrode 85 and the second pad electrode 75 can be formed on the insulating layer 95 by the same process, there is almost no height difference between the two electrodes. Thus there is an advantage in the case of eutectic bonding.
  • the uppermost portions of the first pad electrode 85 and the second pad electrode 75 are Ute such as Au / Sn alloy and Au / Sn / Cu alloy. It may be formed of a tick bonding material.
  • FIG. 17 is a diagram illustrating an example of a semiconductor light emitting device according to the present disclosure.
  • the semiconductor light emitting device 100 may include a substrate 110, a plurality of semiconductor layers 130, 140, and 150, a transparent conductive film 160, a first pad electrode 180, and a second pad electrode 170.
  • the buffer layer 120, the first semiconductor layer 130, the active layer 140, and the second semiconductor layer 150 are sequentially formed on the substrate 110.
  • semiconductor layers epitaxially grown on the substrate 110 are mainly grown by organometallic vapor phase growth (MOCVD), and each layer may further include sublayers as needed.
  • MOCVD organometallic vapor phase growth
  • the substrate 110 is mainly sapphire, SiC, Si, GaN, etc., but may be in any form as long as the group III nitride semiconductor layer can be grown. The substrate 110 may be finally removed.
  • the plurality of semiconductor layers 130, 140, and 150 may include a buffer layer 120 formed on the substrate 10, a first semiconductor layer 130 having a first conductivity (eg, Si-doped GaN), and a second different from the first conductivity.
  • a conductive second semiconductor layer 150 eg, Mg-doped GaN
  • an active layer interposed between the first semiconductor layer 130 and the second semiconductor layer 150 to generate light through recombination of electrons and holes ( 140; for example, InGaN / (In) GaN multi-quantum well structure).
  • Each of the semiconductor layers 130, 140, and 150 may be formed in multiple layers, and the buffer layer 20 may be omitted.
  • the first semiconductor layer 130 and the second semiconductor layer 150 are provided to have different conductivity, and their positions may be changed.
  • the first semiconductor layer 130 is an n-type nitride semiconductor layer 130 (eg, an n-type GaN layer)
  • the second semiconductor layer 150 is a p-type nitride semiconductor layer 150 (eg, p-type GaN layer), for example.
  • the second semiconductor layer 150 and the active layer 140 are mesa-etched to expose a portion of the first semiconductor layer 130.
  • the order of mesa etching may be changed.
  • the transparent conductive film 160 performs a function of diffusing current to the second pad electrode 170 to improve uniformity of light.
  • the transmissive conductive layer 160 is formed to cover most of the second semiconductor layer 150 except for the first pad electrode 180 formed through the mesa etching process.
  • the transparent conductive film 160 is preferably formed.
  • the transparent conductive film is formed of one layer having the same thickness on the second semiconductor layer.
  • the driving voltage increases due to the current diffusion, and when the light-transmissive conductive film is formed too thick, the light extraction efficiency can be reduced by low transmittance, though it has a low sheet resistance.
  • the thickness of the light-transmitting doser film 160 may be differently formed so that current diffusion is easy and the light transmittance is improved regardless of the driving voltage. That is, the thickness of the transparent conductive film 160 positioned corresponding to the second pad electrode 170 may be greater than the thickness of the transparent conductive film 160 positioned on the second semiconductor layer 150.
  • an area where the second pad electrode 170 is located is described as a first area A, and a remaining area where the second pad electrode 170 is not located is described as a second area B.
  • the thickness T2 of the transparent conductive film 160 positioned in the first region A corresponding to the second pad electrode 170 may be formed on the second pad electrode 170 except for the first region A.
  • the thickness T1 of the second region B may be It is preferably about 600 GPa, and the thickness T2 of the first region A is preferably about 1200 to 1800 GPa.
  • the transparent conductive layer 160 includes a first conductive layer 161 positioned on the second semiconductor layer 150 and a second conductive layer 162 positioned on the first conductive layer 161.
  • the first conductive layer 161 is entirely located in the first region A and the second region B and is formed of one layer.
  • the second conductive layer 162 is partially positioned only in the first region A, and is formed between the first conductive layer 161 and the second pad electrode 170.
  • first conductive film 161 and the second conductive film 162 be made of the same material.
  • first conductive layer 161 and the second conductive layer 162 may be formed of the same material as ITO and Ni / Au.
  • the thickness T1 of the first conductive film 161 preferably has the same thickness as the thickness T2 of the second conductive film 162, the thickness T2 of the second conductive film 162 is not limited thereto. It may have a larger or smaller thickness.
  • the thicknesses T1 and T2 of the first conductive film 161 and the second conductive film 162 are preferably about 600 kPa to 1200 kPa, respectively.
  • the width W2 of the second conductive layer 162 may be smaller than the width W1 of the first conductive layer 161 and may be the same as or wider than the width of the second pad electrode 170.
  • the first pad electrode 180 is formed on the first semiconductor layer 130 exposed by mesa etching, and the second pad electrode 170 is formed on the transparent conductive layer 160.
  • the first pad electrode 180 is an n-side pad electrode 180 electrically connected to the first semiconductor layer 130, and the second pad electrode 170 is connected to the second semiconductor layer 150.
  • the n-side pad electrode 170 will be described.
  • the first pad electrode 180 may correspond to the first electrode in the above description, and the second pad electrode 170 may correspond to the second electrode in the above description.
  • the first pad electrode 180 may correspond to the first electrode in the above description, and the second pad electrode 170 may correspond to the first electrode in the above description.
  • the first pad electrode 180 and the second pad electrode 170 may be formed by stacking nickel, chromium, and gold.
  • the first buffer layer 120, the first semiconductor layer 130, the active layer 140, and the second semiconductor layer 150 are formed on the substrate 110.
  • the second semiconductor layer 150 and the active layer 140 are etched in a mesa form to expose the first semiconductor layer 130.
  • a dry etching method for example, an inductively coupled plasma (ICP) may be used.
  • the first conductive layer 161 is formed on the entire surface of the second semiconductor layer 150 by using a sputtering method, an E-beam evaporation method, a thermal evaporation method, or the like.
  • the first conductive layer 161 corresponding to the portion where the second pad electrode 170 is to be formed is formed by using a sputtering method, an E-beam evaporation method, a thermal evaporation method, or the like.
  • the second conductive film 162 is partially formed.
  • the second conductive layer 162 may be formed of the same material and the same thickness as the first conductive layer 161, but is not limited thereto.
  • the first pad electrode 180 and the second pad electrode 170 are formed by using a method such as a sputtering method, an electron beam evaporation method, a thermal evaporation method, or the like.
  • the first region A corresponding to a portion where the second pad electrode 170 is to be formed through a separate etching process. ) Can only be located.
  • the light-transmissive conductive layer 160 is formed on the entire surface of the second semiconductor layer 150 to have the same thickness as the sum of the first conductive layer 161 and the second conductive layer 162.
  • a portion of the transparent conductive film 160 except for the portion corresponding to the second pad electrode 170 may be exposed. Accordingly, the thickness of the transparent conductive layer 160 exposed by etching may be smaller than the thickness of the transparent conductive layer 160 corresponding to the second pad electrode 170.
  • the order of the manufacturing method of the semiconductor light emitting device according to the present disclosure may be included in the scope of the present disclosure in a range that can be easily changed by those skilled in the art.
  • FIG 18 illustrates another example of the semiconductor light emitting device according to the present disclosure.
  • the semiconductor light emitting device 200 includes a protective film 201.
  • the passivation layer 201 may include side and top surfaces of the semiconductor layers 230, 240, and 250, and the transparent conductive layer 260 and the first and second pad electrodes 280 and 270 to protect the semiconductor light emitting device 200. It is formed to cover a portion of the top surface.
  • the protective film 201 does not necessarily cover all regions on the first semiconductor layer 230 and the second semiconductor layer 250.
  • the light-transmissive conductive film 260 includes a first conductive film 261 positioned on the second semiconductor layer 250 and a second conductive film 262 positioned on the first conductive film 261.
  • the protective film 201 may be formed of a material such as SiO 2 , TiO 2 , SiNx, DBR, or the like, and may be omitted.
  • the protective film 201 may be formed simultaneously with the second conductive film 262 of the transparent conductive film 260.
  • the order of the manufacturing method of the semiconductor light emitting device according to the present disclosure may be included in the scope of the present disclosure in a range that can be easily changed by those skilled in the art.
  • the semiconductor light emitting device 100 has the same characteristics as the semiconductor light emitting device 100 of FIG. 17.
  • FIG. 19 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • the semiconductor light emitting device 300 includes a light absorption prevention film 390.
  • the transparent conductive film 360 covers the light absorption prevention film 390 and performs a function of diffusing current to the second pad electrode 370 to improve uniformity of light.
  • the translucent conductive film 360 may include the first conductive film 361 disposed on the second semiconductor layer 350 and the light absorption prevention film 390, and the second conductive film 362 disposed on the first conductive film 361. ).
  • the light absorption prevention layer 390 is interposed between the first conductive layer 361 and the second semiconductor layer 350 of the transparent conductive layer 360.
  • the light absorption prevention layer 390 is formed on a position corresponding to the second pad electrode 370, that is, on the second semiconductor layer 350 in the first region A.
  • the light absorption prevention layer 390 reflects some or all of the light generated from the active layer 340 to prevent light absorption from the transparent conductive layer 360.
  • the light absorption prevention layer 390 may have a function of preventing current from flowing directly under the second pad electrode 370.
  • the light absorption prevention layer 390 may be omitted.
  • the light absorption prevention layer 390 is a single layer (eg, SiO 2 ), a multilayer (eg, Si0 2 / TiO 2 / SiO 2 ), a distributed Bragg reflector, or a single layer made of a light transmissive material having a lower refractive index than the second semiconductor layer 350. Or a combination of a layer and a distributed Bragg reflector.
  • the light absorption prevention layer 390 may be made of a non-conductive material (eg, a dielectric film such as SiOx or TiOx).
  • the semiconductor light emitting diode 100 has the same characteristics as the semiconductor light emitting device 100 illustrated in FIG. 17.
  • FIG. 20 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • the semiconductor light emitting device 400 may include a light absorption prevention layer 490 and a light absorption blocking layer 492.
  • the transparent conductive film 460 covers the light absorption prevention film 490 and the light absorption blocking film 492, and performs a function of diffusing current to the second pad electrode 470 to improve uniformity of light.
  • the transparent conductive film 460 is positioned on the first conductive film 461 and the first conductive film 461 positioned on the second semiconductor layer 450, the light absorption prevention film 490, and the light absorption blocking film 492.
  • the second conductive film 462 is included.
  • the light absorption prevention film 490 and the light absorption blocking film 492 are interposed between the first conductive film 461 and the second semiconductor layer 450.
  • the light absorption prevention film 490 is interposed between the first conductive film 461 and the second semiconductor layer 450.
  • the light absorption prevention layer 490 is formed on the position corresponding to the second pad electrode 470, that is, on the second semiconductor layer 450 in the first region A.
  • the light absorption blocking film 492 is interposed between the first conductive film 461 and the light absorption prevention film 490.
  • the light absorption blocking layer 492 is formed on a position corresponding to the second pad electrode 470, that is, on the light absorption prevention layer 490 in the first region A.
  • the light absorption blocking layer 492 blocks light that is not reflected by the light absorption prevention layer 490 and passes through the light absorption prevention layer 490.
  • the light absorption blocking film 492 may also function as a branch electrode.
  • the light absorption blocking film 492 is disposed between the first conductive film 461 and the light absorption preventing film 490 to block light absorption generated from the transparent conductive film 460 to extract light from the semiconductor light emitting device. It is possible to improve the extraction efficiency.
  • the light absorption barrier layer 492 may be formed of a material different from that of the light absorption barrier layer 490.
  • the light absorption barrier layer 492 has a high reflectivity and a high reflectivity and a good electrical contact.
  • the metallic material may be silver (Ag), aluminum (Al), or distributed Bragg reflector (DBR). Bragg Reflector), highly reflective white reflector, and the like.
  • DBR distributed Bragg reflector
  • Al aluminum
  • the manufacturing cost can be reduced while increasing the bonding force.
  • the thickness T3 of the light absorption prevention film 490 and the thickness T4 of the light absorption blocking film 492 are preferably formed to be the same. However, the present invention is not limited thereto, and the thickness T3 of the light absorption prevention layer 490 may be larger or smaller than the thickness T4 of the light absorption blocking layer 492.
  • the thickness T3 of the light absorption prevention film 490 and the thickness T4 of the light absorption blocking film 492 are preferably about 1000 GPa or more and about 6000 GPa or less.
  • the thicknesses T3 and T4 of the light absorption prevention film 490 and the light absorption blocking film 492 are 1000 ⁇ or less, the thickness is too thin to prevent the light absorption and blocking function smoothly, and the light absorption prevention film 490 And when the thickness (T3, T4) of the light absorption blocking film 492 is 6000 ⁇ or more, it may be difficult to deposit the transparent conductive film 460 deposited on the light absorption blocking film 492.
  • the light absorption prevention film 490 and the light absorption blocking film 492 are formed to correspond to the second pad electrode 470.
  • the light absorption prevention layer 490 and the light absorption blocking layer 492 may be formed in an island shape under the second pad electrode 470, but are not limited thereto.
  • the light absorption prevention layer 490 may have a width W3 equal to or wider than that of the second pad electrode 470.
  • the width W4 of the light absorption blocking film 492 may be the same as or smaller than the width W3 of the light absorption blocking film 490.
  • the width W4 of the light absorption blocking layer 492 may be the same as or wider than the width of the second pad electrode 470.
  • the widths W3 and W4 of the light absorption prevention film 490 and the light absorption blocking film 492 are formed to be wider than the width of the second pad electrode 470, a region in which current is blocked may become too large to reduce the efficiency of the device.
  • light generated by the active layer 440 and incident on the light absorption prevention layer 490 and the light absorption blocking layer 492 may be reflected back toward the plurality of semiconductor layers more than necessary.
  • the widths W3 and W4 of the light absorption prevention film 490 and the light absorption blocking film 492 are smaller than the width of the second pad electrode 470, the light incident to the second pad electrode 470 is emitted. It does not reflect effectively. Accordingly, the widths W3 and W4 of the light absorption prevention film 490 and the light absorption blocking film 492 may be the same as or wider than the width of the second pad electrode 470.
  • the semiconductor light emitting device 100 has the same characteristics as the semiconductor light emitting device 100 illustrated in FIG. 17.
  • 21 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • the semiconductor light emitting device 500 includes a light absorption blocking layer 590 and a light absorption blocking layer 592 including a metal layer 5920 and a non-conductive layer 5921.
  • the light absorption prevention layer 590 is positioned on the second semiconductor layer 550, and the light absorption blocking layer 592 is positioned between the light absorption prevention layer 590 and the light transmission conductive layer 560.
  • the transparent conductive film 560 is positioned on the first conductive film 561 and the first conductive film 561 on the second semiconductor layer 550, the light absorption prevention film 590, and the light absorption blocking film 592.
  • a second conductive film 562 is included.
  • the metal layer 5920 is positioned on an upper surface of the light absorption prevention layer 590, and may be formed of a metallic material having high reflectance and excellent electrical contact to block light absorption while increasing bonding force with the light absorption prevention layer 590.
  • the metal layer 5920 may be made of silver (Ag), aluminum (Al), a distributed Bragg reflector (DBR), a highly reflective white reflector, or the like.
  • DBR distributed Bragg reflector
  • aluminum (Al) is preferred in view of cost and efficiency.
  • the metal layer 5920 may be formed on the light absorption prevention layer 590 by using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, e-beam evaporation, thermal evaportation, or the like.
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • sputtering e-beam evaporation
  • thermal evaportation or the like.
  • the non-conductor layer 5921 is positioned on the metal layer 5920, that is, interposed between the metal layer 5920 and the first conductive film 561 of the transparent conductive film 560.
  • the nonconductive layer 5921 may be formed by anodizing the surface of the metal layer 5920 or by depositing an insulating material on the surface of the metal layer 5920.
  • the nonconductive layer 5921 may be made of an aluminum oxide film (Al 2 O 3 ).
  • the insulator layer 5921 may be any one of SiO 2 , TiO 2 , SiN, SiON, Al 2 O 3, and Ta 2 O 5 films formed through deposition.
  • the nonconductive layer 5921 is positioned between the metal layer 5920 and the first conductive film 561 of the transparent conductive film 560 to electrically insulate the transparent conductive film 560 to maintain a stable insulating state.
  • the insulator layer 5921 may improve current spreading while maintaining a stable state of insulation between the metal layer 5920 and the transparent conductive film 560.
  • FIG 22 illustrates another example of the semiconductor light emitting device according to the present disclosure.
  • the semiconductor light emitting device 600 includes a nonconductive reflecting film 602.
  • the non-conductive reflecting film 602 is a side surface and an upper surface of the etched and exposed semiconductor layers 630, 640, 650, and the first conductive film 661 and the second conductive film 662 of the transparent conductive film 660.
  • the first and second pad electrodes 680 and 670 may be formed to cover portions of the top surface of the first and second pad electrodes 680 and 670.
  • the non-conductive reflecting film 602 does not necessarily cover all regions on the first semiconductor layer 630 and the second semiconductor layer 650.
  • the non-conductive reflecting film 602 functions as a reflecting film but is preferably formed of a light transmitting material to prevent absorption of light.
  • the nonconductive reflecting film 602 may be made of a single dielectric layer (eg, a transparent dielectric material such as SiOx, TiOx, Ta 2 O 5 , MgF 2 ), or may have a multilayer structure.
  • the non-conductive reflective film 602 may include a dielectric film sequentially stacked, a distributed Bragg reflector (eg, a DBR made of a combination of SiO 2 and TiO 2 ) and a clad film.
  • the non-conductive reflecting film 602 is made of SiOx, since the non-conductive reflecting film 602 has a lower refractive index than the second semiconductor layer 650 (for example, GaN), light having an incident angle greater than or equal to a critical angle is provided in the plurality of semiconductor layers 630, 640, and 650. Some reflections can be made to the side.
  • the second semiconductor layer 650 for example, GaN
  • the non-conductive reflecting film 91 is made of a distributed Bragg reflector (DBR: DBR made of a combination of SiO 2 and TiO 2 ), a greater amount of light may be applied to the plurality of semiconductor layers 630, 640, and the like. 650) to the side.
  • DBR distributed Bragg reflector
  • non-conductive reflecting film 602 shown in FIG. 22 has the same characteristics as the semiconductor light emitting device 100 shown in FIG.
  • 24 and 25 illustrate an example of a semiconductor light emitting device according to the present disclosure.
  • FIG. 24 is a plan view
  • FIG. 25A is a sectional view taken along AA ′
  • FIG. 25B is a detailed sectional view of A.
  • the semiconductor light emitting device 100 may include a substrate 110, a plurality of semiconductor layers 130, 140, and 150, a light absorption prevention film 190, a light absorption blocking film 192, a transparent conductive film 160, and a first pad electrode ( 180 and a second pad electrode 170.
  • a group III nitride semiconductor light emitting element will be described as an example.
  • Means a light emitting device such as a light emitting diode including a semiconductor layer, and additionally excludes the inclusion of a material consisting of elements of other groups such as SiC, SiN, SiCN, CN or a semiconductor layer made of these materials. no.
  • the buffer layer 120, the first semiconductor layer 130, the active layer 140, and the second semiconductor layer 150 are sequentially formed on the substrate 110.
  • semiconductor layers epitaxially grown on the substrate 110 are mainly grown by organometallic vapor phase growth (MOCVD), and each layer may further include sublayers as needed.
  • MOCVD organometallic vapor phase growth
  • the substrate 110 is mainly sapphire, SiC, Si, GaN, etc., but may be in any form as long as the group III nitride semiconductor layer can be grown. The substrate 110 may be finally removed.
  • the plurality of semiconductor layers 130, 140, and 150 may include a buffer layer 120 formed on the substrate 10, a first semiconductor layer 130 having a first conductivity (eg, Si-doped GaN), and a second different from the first conductivity.
  • a conductive second semiconductor layer 150 eg, Mg-doped GaN
  • an active layer interposed between the first semiconductor layer 130 and the second semiconductor layer 150 to generate light through recombination of electrons and holes ( 140; for example, InGaN / (In) GaN multi-quantum well structure).
  • Each of the semiconductor layers 130, 140, and 150 may be formed in multiple layers, and the buffer layer 20 may be omitted.
  • the first semiconductor layer 130 and the second semiconductor layer 150 are provided to have different conductivity, and their positions may be changed.
  • the first semiconductor layer 130 is an n-type nitride semiconductor layer 130 (eg, an n-type GaN layer)
  • the second semiconductor layer 150 is a p-type nitride semiconductor layer 150 (eg, p-type GaN layer), for example.
  • the second semiconductor layer 150 and the active layer 140 are mesa-etched to expose a portion of the first semiconductor layer 130.
  • the order of mesa etching can be changed.
  • the transparent conductive layer 160 covers the light absorption barrier layer 190 and the light absorption barrier layer 192 and improves the uniformity of light by performing a function of diffusing current to the second pad electrode 170.
  • the transmissive conductive layer 160 is formed to cover most of the second semiconductor layer 150 except for the first pad electrode 180 formed through the mesa etching process. Therefore, the light absorption prevention film 190 and the light absorption blocking film 192 are interposed between the transparent conductive film 160 and the second semiconductor layer 150.
  • the transparent conductive film 160 is preferably formed.
  • the transparent conductive layer 160 may be formed of a material such as ITO or Ni / Au.
  • the driving voltage is increased due to the current diffusion, and when the light-transmissive conductive layer 160 is formed too thick, light extraction efficiency may be reduced due to light absorption.
  • the first pad electrode 180 is formed on the first semiconductor layer 130 exposed by mesa etching, and the second pad electrode 170 is formed on the transparent conductive layer 160.
  • the first pad electrode 180 is an n-side pad electrode 180 electrically connected to the first semiconductor layer 130, and the second pad electrode 170 is connected to the second semiconductor layer 150.
  • the n-side pad electrode 170 will be described.
  • the first pad electrode 180 and the second pad electrode 170 may be formed by stacking nickel, chromium, and gold.
  • the light absorption prevention layer 190 is formed on the second semiconductor layer 150 corresponding to the second pad electrode 170.
  • the light absorption prevention layer 190 reflects some or all of the light generated from the active layer 140 to prevent light absorption from the transmissive conductive layer 160.
  • the light absorption prevention layer 190 may have a function of preventing current from flowing directly under the second pad electrode 170.
  • the light absorption prevention layer 190 may be omitted.
  • the light absorption prevention layer 190 may be formed of a single layer (eg, SiO 2 ), a multilayer (eg, Si0 2 / TiO 2 / SiO 2 ), a distributed Bragg reflector, or a single layer of a light transmissive material having a lower refractive index than the second semiconductor layer 150. Or a combination of a layer and a distributed Bragg reflector.
  • the light absorption prevention layer 190 may be made of a non-conductive material (eg, a dielectric film such as SiOx or TiOx).
  • the light absorption blocking layer 192 is formed on the light absorption prevention layer 190 in correspondence with the second pad electrode 170. That is, it is positioned between the transparent conductive film 160 and the light absorption prevention film 190.
  • the light absorption blocking layer 192 blocks light that is not reflected by the light absorption prevention layer 190 and passes through the light absorption prevention layer 190. Meanwhile, the light absorption blocking layer 192 may also function as a branch electrode.
  • the light absorption prevention film is positioned between the transparent conductive film and the plurality of semiconductor layers. Some of the light generated from the active layer is reflected by the anti-reflective film, and the remaining non-reflected light is first absorbed by the transmissive conductive film through the anti-reflective film, and the remaining light is primarily reflected back by the pad electrode. After the second absorption in the light-transmissive conductive film is passed through the light absorption prevention film and re-incident into a plurality of semiconductor layers. Accordingly, light efficiency extraction could be reduced.
  • the light absorption blocking layer 192 is disposed between the light transmissive conductive layer 160 and the light absorption prevention layer 190, thereby blocking light absorption generated from the light transmissive conductive layer 160 to thereby extract light efficiency of the semiconductor light emitting device. (extraction efficiency) can be improved.
  • the light absorption blocking layer 192 may be formed of a material different from that of the light absorption blocking layer 190.
  • the light absorption blocking layer 192 has a high reflectivity and is highly reflective and has excellent electrical contact.
  • the metallic material may be silver (Ag), aluminum (Al), or distributed Bragg reflector (DBR). Bragg Reflector), highly reflective white reflector, and the like.
  • DBR distributed Bragg reflector
  • Al aluminum
  • the manufacturing cost may be reduced while increasing the bonding force.
  • the light absorption prevention layer 190 is formed to have a first thickness T1
  • the light absorption blocking layer 192 is formed to have a second thickness T2.
  • the first thickness T1 of the light absorption prevention film 190 and the second thickness T2 of the light absorption blocking film 192 are preferably formed to be the same.
  • the present invention is not limited thereto, and the first thickness T1 of the light absorption prevention layer 190 may be larger or smaller than the second thickness T2 of the light absorption blocking layer 192.
  • the first thickness T1 of the light absorption prevention film 190 and the second thickness T2 of the light absorption blocking film 192 are preferably about 1000 kPa or more and about 6000 kPa or less.
  • the thickness is too thin to prevent the function of preventing and blocking light absorption, and when the first and second thicknesses T1 and T2 are 6000 ⁇ s or more. Deposition of the transparent conductive film 160 deposited on the light absorption blocking layer 192 may be difficult.
  • the light absorption prevention layer 190 and the light absorption blocking layer 192 are formed to correspond to the second pad electrode 170.
  • the light absorption prevention layer 190 and the light absorption blocking layer 192 may be formed in an island shape under the second pad electrode 170, but are not limited thereto.
  • the light absorption prevention layer 190 may be formed to have a first width W1 and may be formed to be the same as or wider than the width of the second pad electrode 170.
  • the light absorption blocking layer 192 may be formed to have a second width W1, and may be formed to be the same as or smaller than the first width W1 of the light absorption prevention layer 190. In addition, the light absorption blocking layer 192 may be formed to be the same as or wider than the width of the second pad electrode 170.
  • the first and second widths W1 and W2 of the light absorption prevention film 190 and the light absorption blocking film 192 are formed to be wider than the width of the second pad electrode 170, the area where the current is cut off becomes too large. Efficiency may be reduced, and light generated in the active layer 140 and incident on the light absorption prevention layer 190 and the light absorption blocking layer 192 may be reflected back toward the plurality of semiconductor layers more than necessary.
  • the first and second widths W1 and W2 of the light absorption prevention layer 190 and the light absorption blocking layer 192 are smaller than the width of the second pad electrode 170, the second pad electrode 170 may be formed. It does not reflect light incident to it effectively. Accordingly, the first and second widths W1 and W2 of the light absorption blocking layer 190 and the light absorption blocking layer 192 may be the same as or wider than the width of the second pad electrode 170.
  • the first buffer layer 120, the first semiconductor layer 130, the active layer 140, and the second semiconductor layer 150 are formed on the substrate 110.
  • the second semiconductor layer 150 and the active layer 140 are etched in a mesa form to expose the first semiconductor layer 130.
  • a dry etching method for example, an inductively coupled plasma (ICP) may be used.
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • sputtering e-beam evaporation
  • thermal evaportation thermal evaportation, or the like.
  • the light absorption prevention layer 190 is formed on a portion of the semiconductor layer 150.
  • a light absorption blocking layer 192 is formed on the light absorption prevention layer 190 by using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, e-beam evaporation, and thermal evaportation. .
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • sputtering e-beam evaporation
  • thermal evaportation thermal evaportation
  • the light absorption prevention layer 190 and the light absorption blocking layer 192 may be formed at the same time.
  • the first pad electrode 180 and the second pad electrode 170 are formed by using a method such as a sputtering method, an electron beam evaporation method, a thermal evaporation method, or the like.
  • 26 illustrates another example of the semiconductor light emitting device according to the present disclosure.
  • the semiconductor light emitting device 200 includes a protective film 201.
  • the passivation layer 201 may include side and top surfaces of the semiconductor layers 230, 240, and 250, and the transparent conductive layer 260 and the first and second pad electrodes 280 and 270 to protect the semiconductor light emitting device 200. It is formed to cover a portion of the top surface.
  • the protective film 201 does not necessarily cover all regions on the first semiconductor layer 230 and the second semiconductor layer 250.
  • the protective film 201 may be formed of a material such as SiO 2 , TiO 2 , SiNx, DBR, or the like, and may be omitted.
  • the protective film 201 may be formed simultaneously with the transparent conductive film 260.
  • the order of the manufacturing method of the semiconductor light emitting device according to the present disclosure may be included in the scope of the present disclosure in a range that can be easily changed by those skilled in the art.
  • FIG. 27 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • the semiconductor light emitting device 300 includes a light absorption blocking layer 392 including a metal layer 3920 and a non-conductive layer 3921.
  • the metal layer 3920 is positioned on an upper surface of the light absorption prevention layer 390, and may be formed of a metallic material having high reflectance and excellent electrical contact to block light absorption while increasing bonding strength with the light absorption prevention layer 390.
  • the metal layer 392 may be made of silver (Ag), aluminum (Al), a distributed Bragg reflector (DBR), a highly reflective white reflector, or the like.
  • silver (Ag) is preferred in view of cost and efficiency.
  • the metal layer 3920 may be formed on the light absorption prevention layer 390 using Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), sputtering, E-beam evaporation, thermal evaportation, or the like.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • sputtering E-beam evaporation
  • thermal evaportation or the like.
  • the insulator layer 3921 is positioned on the metal layer 3920, that is, interposed between the metal layer 3920 and the transparent conductive film 360.
  • the nonconductive layer 3921 may be formed by anodizing the surface of the metal layer 3920 or by depositing an insulating material on the surface of the metal layer 3920.
  • the nonconductive layer 3921 may be made of aluminum oxide film (Al 2 O 3).
  • the insulator layer 3921 may be any one of SiO 2 , TiO 2 , SiN, SiON, Al 2 O 3, and Ta 2 O 5 films formed through deposition.
  • the nonconductive layer 3921 is positioned between the metal layer 3920 and the transparent conductive film 360 to electrically insulate the transparent conductive film 360 to maintain a stable insulating state.
  • the insulator layer 3921 may improve current spreading while maintaining a stable state of insulation between the metal layer 3920 and the transparent conductive film 360.
  • the semiconductor light emitting device 100 has the same characteristics as the semiconductor light emitting device 100 illustrated in FIGS. 24 and 25.
  • the semiconductor light emitting device 400 includes a nonconductive reflecting film 402.
  • the non-conductive reflecting layer 402 is formed on side surfaces and top surfaces of the plurality of etched and exposed semiconductor layers 430, 440, and 450, and a portion of the upper surface of the transparent conductive layer 460 and the first and second pad electrodes 480 and 470. It is formed to cover.
  • the non-conductive reflective film 402 does not necessarily cover all regions on the first semiconductor layer 430 and the second semiconductor layer 450.
  • the non-conductive reflecting film 402 functions as a reflecting film but is preferably formed of a light transmitting material to prevent absorption of light.
  • the nonconductive reflective film 402 may be made of a single dielectric layer (eg, a transparent dielectric material such as SiOx, TiOx, Ta 2 O 5 , MgF 2 ), or may have a multilayer structure.
  • the non-conductive reflective film 402 may include a dielectric film sequentially stacked, a distributed Bragg reflector (eg, a DBR made of a combination of SiO 2 and TiO 2 ) and a clad film.
  • the non-conductive reflective film 402 is made of SiOx, since the non-conductive reflective film 402 has a lower refractive index than the second semiconductor layer 450 (for example, GaN), light having an incident angle greater than or equal to a critical angle is provided in the plurality of semiconductor layers 430, 440, and 450. Some reflections can be made to the side.
  • the second semiconductor layer 450 for example, GaN
  • the non-conductive reflecting film 91 is made of a distributed Bragg reflector (DBR: DBR of a combination of SiO 2 and TiO 2 ), a greater amount of light may be applied to the plurality of semiconductor layers 430, 440, and the like. 450) can be reflected to the side.
  • DBR distributed Bragg reflector
  • non-conductive reflecting film 402 shown in FIG. 28 has the same characteristics as the semiconductor light emitting device 100 shown in FIGS.
  • FIG. 33 is a view for explaining an example of a semiconductor light emitting device according to the present disclosure
  • FIG. 34 is a view for explaining an example of a cut plane taken along line A-A of FIG. 33.
  • the semiconductor light emitting device may include a first light emitting part 101 and a second light emitting part 102, a connection electrode 92, a reflective layer 91, a first electrode 80, and a second electrode formed to face each other on a substrate 10. 70, a first electrical connection 71, and a second electrical connection 81.
  • the first light emitting unit 101 and the second light emitting unit 102 each include a plurality of semiconductor layers in which the first semiconductor layer 30, the active layer 40, and the second semiconductor layer 50 are sequentially stacked.
  • the reflective layer 91 is formed to cover the first light emitting part 101, the second light emitting part 102, and the first light emitting part 101 and the second light emitting part 102. Reflect the generated light.
  • the first electrode 80 is provided to be in electrical communication with the first semiconductor layer 30 of the first light emitting part 101, and supplies one of electrons and holes.
  • the second electrode 70 is provided to be in electrical communication with the second semiconductor layer 50 of the second light emitting part 102, and supplies the other one of electrons and holes.
  • the first electrical connection 71 and the second electrical connection 81 pass through the reflective layer 91 and are in electrical communication with the plurality of semiconductor layers.
  • the first electrical connection 81 is in electrical communication with the first semiconductor layer 30, and the second electrical connection 71 is in electrical communication with the second semiconductor layer 50.
  • connection electrode 92 extends over the reflective layer 91 and electrically connects the first light emitting part 101 and the second light emitting part 102.
  • group III nitride semiconductor light emitting element will be described as an example.
  • Sapphire, SiC, Si, GaN and the like are mainly used as the substrate 10, and the substrate 10 may be finally removed.
  • the positions of the first semiconductor layer 30 and the second semiconductor layer 50 may be changed, and are mainly made of GaN in the group III nitride semiconductor light emitting device.
  • the plurality of semiconductor layers 30, 40, and 50 may include a buffer layer 20 formed on the substrate 10, a first semiconductor layer 30 having a first conductivity (eg, Si-doped GaN), and a second different from the first conductivity.
  • a conductive second semiconductor layer 50 eg, Mg-doped GaN
  • an active layer interposed between the first semiconductor layer 30 and the second semiconductor layer 50 to generate light through recombination of electrons and holes ( 40; e.g., InGaN / (In) GaN multi-quantum well structure).
  • Each of the plurality of semiconductor layers 30, 40, and 50 may be formed in multiple layers, and the buffer layer 20 may be omitted.
  • the semiconductor light emitting device may include a plurality of light emitting parts.
  • the semiconductor light emitting element includes a first light emitting portion 101 and a second light emitting portion 102.
  • each of the first light emitting part 101 and the second light emitting part 102 has a rectangular shape having a long side formed in the long direction (x direction) and a short side formed in the short direction (y direction), for example, a rectangular shape.
  • Have The long sides of each of the first light emitting units 101 and the second light emitting units 102 are arranged in one direction (y direction) to face each other. Therefore, the semiconductor light emitting device has a shape substantially similar in width and length as a whole.
  • the reflective layer 91 is formed to cover the plurality of semiconductor layers 30, 40, and 50, the first light emitting part 101, the second light emitting part 102, and the connection electrode 92.
  • the reflective layer 91 is insulative, and at least one of the first electrode 80 and the second electrode 70 is opposite to the plurality of semiconductor layers 30, 40, and 50 based on the reflective layer 91.
  • a flip chip provided at the side and electrically connected to the plurality of semiconductor layers by an electrical connection passing through the reflective layer 91.
  • the reflective layer 91 may be formed of an insulating material to reduce light absorption by the metal reflective film, and may preferably have a multilayer structure including a distributed bragg reflector (DBR) or an omni-directional reflector (ODR).
  • DBR distributed bragg reflector
  • ODR omni-directional reflector
  • An example of the multilayer structure includes a dielectric film 91b, a distributed Bragg reflector 91a, and a clad film 91c.
  • the dielectric film 91b may reduce the height difference to stably manufacture the distributed Bragg reflector 91a and may also help to reflect light.
  • SiO 2 is a suitable material for the dielectric film 91b.
  • the distributed Bragg reflector 91a is formed on the dielectric film 91b.
  • the distribution Bragg reflector 91a may be composed of repeated stacking of materials having different reflectances, for example, SiO 2 / TiO 2 , SiO 2 / Ta 2 O 2 , or SiO 2 / HfO.
  • SiO 2 / TiO 2 has good reflection efficiency, and for UV light, SiO 2 / Ta 2 O 2 , or SiO 2 / HfO will have good reflection efficiency.
  • the clad film 91c may be made of a metal oxide such as Al 2 O 3 , a dielectric film 91b such as SiO 2 , SiON, MgF, CaF, or the like.
  • the distributed Bragg reflector 91a has a higher reflectance as light closer to the vertical direction reflects approximately 99% or more.
  • each material layer having a multilayer structure must be formed to a specially designed thickness.
  • the reflective layer 91 has portions where height differences occur in the reflective layer 91 due to the following structures (eg, ohmic electrodes, trenches between the light emitting parts, etc.). Due to the height difference, there is an area in which each material layer of the reflective layer 91 is hard to be formed in the designed thickness, and the reflection efficiency may be reduced in this area. The reflection efficiency may be lower than that of other parts between the light emitting parts. Therefore, forming as few metal layers between the light emitting portions as possible is preferable to reduce the light absorption loss by the metal.
  • connection electrode 92 electrically connects the first light emitting part 101 and the second light emitting part 102 that face each other in the long direction (x direction). Part of the connection electrode 92 overlaps with each other between the first light emitting part 101 and the second light emitting part 102. That is, the first light emitting part 101 and the second light emitting part 102 are electrically connected to each other by the connection electrode 92.
  • connection electrode 92 is in electrical communication with the second semiconductor layer 50 between the second semiconductor layer 50 and the reflective layer 91, and the other end of the connection electrode 92 is the second semiconductor.
  • the layer 50 and the active layer 40 are etched and in electrical communication with the exposed first semiconductor layer 30.
  • connection electrode 92 Since the connection electrode 92 is provided on the opposite side of the plurality of semiconductor layers 30, 40, and 50 with respect to the reflective layer 91, the reflective layer before the light generated in the active layer 40 impinges on the connection electrode 92. In (91) it can almost be reflected.
  • the width of the connection electrode 92 may be smaller than the width of the first light emitting part 101 and the second light emitting part 102, but is not limited thereto.
  • the width of the connection electrode 92 is smaller than the width of the first light emitting part 101 and the second light emitting part 102, and between the first light emitting part 101 and the second light emitting part 102. It is preferable to form larger than the interval of. Therefore, since the distance between the first light emitting part 101 and the second light emitting part 102 can be minimized, the size of the semiconductor light emitting device can be reduced.
  • each of the first light emitting part 101 and the second light emitting part 102 may face each other and minimize the distance from each other, thereby improving the uniformity of current spreading.
  • connection electrode 92 may have the same length as that of the first light emitting part 101 and the second light emitting part 102, but is not limited thereto. In this example, the connection electrode 92 is illustrated to have a length shorter than the length of the first light emitting part 101 and the second light emitting part 102.
  • connection electrode 92 is formed to be elongated in the longitudinal direction (x direction) corresponding to the long sides of each of the first light emitting part 101 and the second light emitting part 102, thereby forming the first light emitting part 101 and
  • the connection stability between the second light emitting units 102 may be further improved.
  • the first light emitting part 101 and the second light emitting part 102 are connected in parallel in the long direction (x direction) by the connecting electrode 92 and are driven at a higher voltage than one light emitting part. .
  • Each of the first electrode 80 and the second electrode 70 is formed on the reflective layer 91 in correspondence with the first light emitting part 101 and the second light emitting part 102.
  • the first electrode 80 is connected to the first electrical connection 81 of the first light emitting part 101
  • the second electrode 70 is connected to the second electrical connection 71 of the second light emitting part 102. do.
  • the first electrical connection 81 penetrates the reflective layer 91 to electrically connect the first electrode 80 and the first semiconductor layer 30.
  • the first ohmic electrode 82 may be interposed between the first electrical connection 81 and the first semiconductor layer 30 to reduce contact resistance and provide stable electrical connection.
  • a current diffusion electrode 60 eg, ITO, Ni / Au
  • the current spreading electrode 60 can be omitted.
  • the second electrical connection 71 penetrates the reflective layer 91 to electrically connect the second electrode 70 and the second semiconductor layer 50.
  • the second ohmic electrode 72 may be interposed to reduce contact resistance and to provide stable electrical connection between the second electrical connection 71 and the second semiconductor layer 50.
  • the first electrode 80 and the second electrode 70 are electrodes for electrical connection with the external electrode, and may also be eutectic bonded, soldered, or wire bonded with the external electrode.
  • the external electrode may be a conductive part provided in the submount, a lead frame of the package, an electrical pattern formed on the PCB, and the like, and the external electrode may be any type of conductive wire independently of the semiconductor light emitting device.
  • the first electrode 80 and the second electrode 70 are formed to have a certain area to be a heat dissipation passage.
  • Mesa etching may be performed before or after the current diffusion electrode 60 is formed.
  • the current spreading electrode 60 can be omitted.
  • a process of electrically insulating the plurality of light emitting parts together with or separately from the mesa etching process may be performed so that each light emitting part may be electrically insulated from each other by a trench exposing the growth substrate 10.
  • ohmic electrodes 72 and 82 are formed on the current diffusion electrode 60 and the exposed first semiconductor layer 30, respectively.
  • the ohmic electrodes 72 and 82 may be omitted, but are preferably provided for suppressing an increase in operating voltage and for stable electrical contact.
  • the connection electrode 92 is formed together with or separately from the formation of the ohmic electrodes 72 and 82.
  • the current diffusion electrode 60 may be considered to form a light absorption prevention film on the second semiconductor layer 50 corresponding to the ohmic electrode 72.
  • the reflective layer 91 is formed on the current spreading electrode 60. Thereafter, an opening is formed in the reflective layer 91, and the first electrical connection 81 and the second electrical connection 71 penetrate through the opening to contact the first ohmic electrode 82 and the second ohmic electrode 72, respectively. Is formed.
  • first electrode 80 and the second electrode 70 are formed to be connected to the first electrical connection 81 and the second electrical connection 71, respectively.
  • the first and second electrical connections 81 and 70 and the first and second electrodes 80 and 70 may be formed separately, but may be integrally formed in one process.
  • the semiconductor light emitting device including the plurality of light emitting parts is manufactured by cutting the individual semiconductor light emitting devices including the plurality of light emitting parts on the wafer. In cutting, the scribing and / or breaking process may proceed, and a chemical etching process may be added.
  • connection electrode 35 is a diagram for explaining an example of a connection electrode.
  • connection electrode 92 is formed in plural and includes a first connection electrode 92a, a second connection electrode 92b, and a third connection electrode 92c which are spaced apart in the longitudinal direction (x direction).
  • connection electrodes 92 are limited to three spaced apart locations, but the embodiment is not limited thereto.
  • the first connection electrode 92a, the second connection electrode 92b, and the third connection electrode 92c each have a first light emitting portion 101 and a second light emitting portion 102 facing each other in the long direction (x direction). Connect electrically. As such, the first light emitting part 101 and the second light emitting part 102 are connected in parallel in the long direction (x direction) by the connecting electrode 92 and are driven at a higher voltage than one light emitting part. do.
  • the semiconductor light emitting element includes a light absorption prevention film 41.
  • the light absorption prevention layer 41 may be provided between the second semiconductor layer 50 and the current diffusion electrode 60.
  • the light absorption prevention layer 41 may be formed of SiO 2, TiO 2, or the like, and may have only a function of reflecting some or all of the light generated in the active layer 40, and may be configured to directly flow down from the second ohmic electrode 72. It may have only a function to prevent the flow of or may have both functions.
  • the semiconductor light emitting element includes an insulating layer 35.
  • the insulating layer 35 may include the side surfaces of the first semiconductor layer 30 of the second light emitting unit 102, the exposed substrate 10, and the plurality of semiconductor layers 30, 40, and 50 of the first light emitting unit 101. Is formed on the side.
  • the insulating layer 35 is a passivation layer having transparency, and is deposited on the etching portions 21 and 25 by using materials such as SiO 2 , TiO 2 , and Al 2 O 3 .
  • the thickness of the deposition can be, for example, thousands of millimeters, but of course the thickness can be varied.
  • the edges 21 and 25 of the first light emitting part 101 and the second light emitting part 102 face each other between the first light emitting part 101 and the second light emitting part 102.
  • a plurality of light emitting portions are formed at high-voltage because the distance between the first light emitting portion 101 and the second light emitting portion 102 is narrow, as described above.
  • the insulating layer 35 may be formed to the etching portion 25 of the edge of the first light emitting portion 101 and the second light emitting portion 102 to further improve the reliability of electrical insulation.
  • the insulating layer 35 is formed on the second semiconductor layer 50 of the second light emitting part 102 in correspondence with the second ohmic electrode 72, and corresponds to the connection electrode 92. 1 may be formed on the second semiconductor layer 50 of the light emitting unit 101. Accordingly, the insulating layer 35 also functions as a light absorption prevention film. Of course, it may be considered to form a light absorption prevention film in a separate process from the insulating layer 35, in which case it is also possible to form a thicker insulating layer 35.
  • connection electrode 92 intersects the insulating layer 35 between the first light emitting part 101 and the second light emitting part 102, and electrically connects the first light emitting part 101 and the second light emitting part 102.
  • the first light emitting part 101 and the second light emitting part 102 are trenched or removed as the plurality of semiconductor layers 30, 40, and 50 are removed (eg, mesa etching). ) Is formed.
  • the semiconductor layers 30, 40, and 50 may be removed from the etching portions 21 and 25 to expose the substrate 10, the semiconductor layers 30, 40, and 50 may be exposed between the plurality of semiconductor layers 30, 40, and 50. Additional layers may be exposed.
  • a plurality of semiconductor light emitting devices formed on the wafer are separated from the etching part 25 of the outer edges of the first light emitting part 101 and the second light emitting part 102 to be manufactured as individual semiconductor light emitting devices.
  • the first light emitting portion 101 and the second light emitting portion 102 have a substantially rectangular shape and are provided so that the edges face each other.
  • a plurality of semiconductor layers 30, 40, and 50 are removed between the first light emitting part 101 and the second light emitting part 102 and the edges of the first light emitting part 101 and the second light emitting part 102.
  • Etch portions 21 and 25 may be exposed and the substrate 10 may be exposed.
  • the etching parts 21 and 25 are electrically isolated or insulated by themselves. Since the plurality of semiconductor layers 30, 40, and 50 become light emitting regions, it is desirable to reduce the reduction of the plurality of semiconductor layers 30, 40, and 50 due to the etching portions 21 and 25. For the etch portion 25 of the rim needs a certain width.
  • the width of the etching portion 21 between the first light emitting portion 101 and the second light emitting portion 102 is the etching portion 25 of the edge of the first light emitting portion 101 and the second light emitting portion 102. It is formed to be narrower than the width of), and the reduction of the plurality of semiconductor layers 30, 40, 50 is suppressed while securing margins of the edges.
  • the width of the edge portion of the edge may mean the width of the edge portion of the plurality of semiconductor light emitting elements on the wafer, or may mean the edge portion 25 of the edge of the semiconductor light emitting element separated into individual elements.
  • the semiconductor light emitting device has the same characteristics as the semiconductor light emitting device shown in FIG.
  • the semiconductor light emitting device includes the first light emitting part 103 and the second light emitting part 104, the connection electrode 192, the reflective layer 191, the insulating layer 195, and the first light emitting part 103 formed to face each other on the substrate 110.
  • the insulating layer 195, the first intermediate connection layer 180, the second electrical connection 183, the first pad electrode 184, the second intermediate connection layer 170, and the first intermediate connection layer 180 disposed on the reflective layer 191 are formed.
  • the semiconductor light emitting device has the same characteristics as the semiconductor light emitting device illustrated in FIG. 34.
  • the first light emitting unit 103 and the second light emitting unit 104 are positioned on the reflective layer 191, and the first electrical connection 181, the third electrical connection 171, and the connection electrode 192 are disposed. Covering insulating layer 195.
  • the insulating layer 195 may be made of SiO 2 .
  • the first electrical connection 181 passes through the reflective layer 191 and is in electrical communication with the exposed first semiconductor layer 130.
  • the third electrical connection 171 passes through the reflective layer 191 and is in electrical communication with the second semiconductor layer 150.
  • the first ohmic electrode 182 may be interposed between the first electrical connection 181 and the first semiconductor layer 130 to reduce contact resistance and provide stable electrical connection, and the third electrical connection 171 and the second semiconductor may be interposed therebetween.
  • the second ohmic electrode 172 may be interposed between the layers 150 to reduce contact resistance and provide stable electrical connection.
  • connection electrode 192 is in electrical communication with the second semiconductor layer 150 between the second semiconductor layer 150 and the reflective layer 191, and the other end of the connection electrode 192 is the second semiconductor.
  • the layer 150 and the active layer 140 are etched in electrical communication with the exposed first semiconductor layer 130.
  • Each of the first pad electrode 184 and the second pad electrode 174 is formed on the insulating layer 195 corresponding to the first light emitting part 103 and the second light emitting part 104.
  • the first pad electrode 184 penetrates through the insulating layer 195 and is electrically connected to the first electrical connection 181 through the second electrical connection 183 to supply electrons to the first semiconductor layer 130.
  • the first intermediate connection layer 180 may be interposed between the second electrical connection 183 and the first electrical connection 181 to reduce contact resistance and provide stable electrical connection.
  • the second pad electrode 174 penetrates through the insulating layer 195 and is electrically connected to the third electrical connection 171 through the fourth electrical connection 173 to supply holes to the second semiconductor layer 150.
  • the second intermediate connection layer 170 may be interposed between the fourth electrical connection 173 and the second electrical connection 171 to reduce contact resistance and provide stable electrical connection.
  • a semiconductor light emitting device comprising: a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and interposed between the first semiconductor layer and the second semiconductor layer and having electrons and holes
  • a plurality of semiconductor layers having an active layer that generates light through recombination of the semiconductors;
  • a reflection film formed on the plurality of semiconductor layers to reflect light generated in the active layer toward the first semiconductor layer;
  • a first electrode part electrically connected to the first semiconductor layer and supplying one of electrons and holes;
  • a second electrode part electrically connected to the second semiconductor layer and supplying the other one of electrons and holes;
  • an electrode display unit interposed between the plurality of semiconductor layers and the reflective film.
  • the electrode display unit is a semiconductor light emitting element located between the first electrode portion and the second electrode portion.
  • the semiconductor light emitting device comprising the same material as at least one of the first electrode portion and the second electrode portion.
  • the semiconductor light emitting element having a size of the electrode display portion of 100 ⁇ m or less.
  • the semiconductor light emitting element having a thickness of 5 ⁇ m or less of the electrode display portion.
  • each of the first electrode portion and the second electrode portion includes a connecting electrode positioned between the reflective film and the insulating layer;
  • Semiconductor light emitting device comprising a.
  • a semiconductor light emitting element comprising a distributed Bragg reflector (DBR) as a non-conductive reflecting film.
  • DBR distributed Bragg reflector
  • a semiconductor light emitting device comprising: a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and interposed between the first semiconductor layer and the second semiconductor layer and having electrons and holes A plurality of semiconductor layers having an active layer that generates light through recombination of the semiconductors; A non-conductive reflecting film formed over the plurality of semiconductor layers to reflect light generated in the active layer toward the first semiconductor layer; An insulating layer formed on the nonconductive reflecting film; A first electrode part electrically connected to the first semiconductor layer and supplying one of electrons and holes; A second electrode part electrically connected to the second semiconductor layer and supplying the other one of electrons and holes; And an electrode display disposed between the nonconductive reflecting film and the insulating layer.
  • At least one of the first electrode portion and the second electrode portion includes: a connection electrode formed on the nonconductive reflecting film; A first electrical connection penetrating the non-conductive reflective film to electrically connect the connection electrode and the plurality of semiconductor layers; A pad electrode formed on the insulating reflective layer; And a second electrical connection connecting the pad electrode and the connection electrode to penetrate through the insulating reflective layer.
  • a semiconductor light emitting element wherein the electrode display portion is positioned under at least one pad electrode of a pad electrode of the first electrode portion and a pad electrode of the second electrode portion.
  • a semiconductor light emitting device comprising electrode holes in a plurality of holes.
  • a semiconductor light emitting element in which the electrode display portion is made of islands such as circles, triangles, squares, and the like.
  • a semiconductor light emitting element wherein the first electrode portion and the second electrode portion are formed symmetrically with each other.
  • the first electrode portion and the second electrode portion are symmetrically arranged around the connection electrode.
  • DBR distributed Bragg reflector
  • a semiconductor light emitting device comprising: a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and interposed between the first semiconductor layer and the second semiconductor layer and having electrons and holes
  • a plurality of semiconductor layers having an active layer for generating light through recombination of and grown using a growth substrate;
  • a first electrode and a second electrode supplying electrons and holes, comprising: a first electrode electrically connected to the first semiconductor layer and a second electrode electrically connected to the second semiconductor layer;
  • a light-transmissive conductive film positioned on the second semiconductor layer, wherein the first thickness of the light-transmissive conductive film located in the first region corresponding to the second electrode is equal to that of the light-transmissive conductive film positioned in the second region except the first region.
  • a semiconductor light emitting element thicker than the second thickness.
  • a semiconductor light emitting device wherein the first thickness of the first region has a thickness of at least two times or more than the second thickness of the second region.
  • the light-transmissive conductive film includes: a first conductive film which is entirely formed in the first region and the second region and formed of one layer; And a second conductive film partially positioned in the second region and formed between the second electrode and the first conductive film.
  • a semiconductor light emitting element wherein the first conductive film and the second conductive film are formed of the same material and the same thickness.
  • the width of the second conductive film is smaller than the width of the first conductive film.
  • the light absorption prevention film and the light absorption blocking film are semiconductor light emitting devices made of different materials.
  • a semiconductor light emitting device comprising: a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and interposed between the first semiconductor layer and the second semiconductor layer and having electrons and holes
  • a plurality of semiconductor layers having an active layer for generating light through recombination of and grown using a growth substrate;
  • a first electrode and a second electrode supplying electrons and holes, comprising: a first electrode electrically connected to the first semiconductor layer and a second electrode electrically connected to the second semiconductor layer;
  • a light absorption prevention film interposed between the second semiconductor layer and the transparent conductive film;
  • a light absorption blocking layer interposed between the light absorption prevention film and the light-transmitting conductive film, wherein the light absorption prevention film and the light absorption blocking film are made of different materials.
  • the first electrode may correspond to the first pad electrode in the above description, and the second electrode may correspond to the second pad electrode in the above description.
  • the first pad electrode may correspond to the first electrode in the above description, and the second pad electrode may correspond to the first electrode in the above description.
  • the light absorption barrier may also function as a branch electrode.
  • the light absorption prevention film is a semiconductor light emitting element comprising at least one of SiO 2 , SiN, AlO x , SiON, and TiO 2 .
  • the light absorption blocking film is a semiconductor light emitting device comprising at least one of aluminum (Al), silver (Ag), a distributed Bragg reflector (DBR) and a highly reflective white reflecting material.
  • the semiconductor light emitting device having a thickness of light absorption preventing film and light absorption blocking film of about 1000 GPa or more.
  • a semiconductor light emitting device wherein the light absorption prevention film and the light absorption blocking film are positioned corresponding to the second electrode.
  • the light absorption blocking film is a semiconductor light emitting device which is formed to be equal to or wider than the width of the second electrode.
  • the light absorption prevention film is a semiconductor light emitting element formed with the same or wider width of the light absorption blocking film.
  • the light absorption prevention film and the light absorption blocking film are formed in an island shape.
  • the light absorption blocking film further comprises a non-conductive layer on the surface in contact with the second electrode.
  • a semiconductor light emitting device comprising: a first light emitting portion and a second light emitting portion formed in a longitudinal direction, a first semiconductor layer having a first conductivity, an active layer for generating light through recombination of electrons and holes, and a first conductivity A plurality of semiconductor layers in which a second semiconductor layer having a second conductivity different from the first semiconductor layer is sequentially stacked; A connection electrode formed in a long direction and electrically connecting the first light emitting part and the second light emitting part; A reflective layer formed to cover the first light emitting part, the second light emitting part, and the connection electrode, and reflecting light generated by the active layer; A first electrode part provided to be in electrical communication with the first semiconductor layer of the first light emitting part and supplying one of electrons and holes; And a second electrode part provided to be in electrical communication with the second semiconductor layer of the second light emitting part and supplying the other one of electrons and holes, wherein the connection electrode is partially connected to the first light emitting part and the second light emitting part.
  • connection electrode has a length equal to or shorter than a length of at least one of the first light emitting part and the second light emitting part.
  • a semiconductor light emitting device comprising a plurality of connection electrodes, wherein the plurality of connection electrodes have a length shorter than at least one of the first and second light emitting parts, and are spaced apart from each other in the longitudinal direction.
  • the connecting electrode electrically connects the first semiconductor layer and the second semiconductor layer of the first light emitting part and the second light emitting part to face each other.
  • the semiconductor light emitting element is a flip chip, wherein the first electrode portion comprises: a first electrode formed on the reflective layer of the first light emitting portion; And a first electrical connection penetrating the reflective layer to electrically connect the first semiconductor layer and the first electrode of the first light emitting part, wherein the second electrode part comprises: a second electrode formed on the reflective layer of the second light emitting part; And a second electrical connection penetrating the reflective layer to electrically connect the second semiconductor layer and the second electrode of the second light emitting unit.
  • the first electrode part comprises: a first intermediate connection layer formed on the reflective layer of the first light emitting part; A first electrical connection penetrating the reflective layer to electrically communicate the first semiconductor layer and the first intermediate connection layer of the first light emitting part; A first pad electrode formed on the insulating layer of the first light emitting part; And a second electrical connection penetrating the insulating layer to electrically connect the first intermediate connection layer and the first pad electrode.
  • a second intermediate connecting layer formed on the reflective layer of the second light emitting part; A third electrical connection penetrating the reflective layer to electrically connect the second semiconductor layer and the second intermediate connection layer of the second light emitting part; A second pad electrode formed on the insulating layer of the second light emitting part; And a fourth electrical connection penetrating through the insulating layer to electrically connect the second intermediate connection layer and the second pad electrode.
  • a semiconductor light emitting device wherein the insulating layer comprises SiO 2 , and the reflective layer is insulating and includes one of a distributed Bragg reflector and an Omni-Directional Reflector (ODR).
  • ODR Omni-Directional Reflector
  • the polarity of each electrode may be easily displayed using a separate electrode display unit without forming a groove or notch to display the polarity of the electrode.
  • the process can be simplified by forming an island type electrode display unit in the shape of the connection electrode without providing a separate electrode display unit.
  • the thickness of the transparent conductive film positioned in correspondence with the electrode is made thicker than the thickness of other portions, so that the current spreading can be smoothly performed without reducing the extraction efficiency.
  • a light absorption prevention film having different materials from each other into a double layer, it is possible to prevent light from being absorbed to the pad electrode side, thereby reducing the light absorption amount.
  • the non-conductive layer is positioned between the pad electrode and the light absorption prevention film, it is possible to maintain the insulating state stably and improve current spreading.
  • the stability of the connection can be improved.
  • the uniformity of current spreading can be further improved.

Abstract

The present disclosure relates to a semiconductor light emitting device comprising: a plurality of semiconductor layers including a first semiconductor layer having first conductivity, a second semiconductor layer having second conductivity different from the first conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer and generating light through hole-electron recombination; a reflective film formed on the plurality of semiconductor layers so as to reflect the light generated in the active layer toward the first semiconductor layer; a first electrode part electrically connected to the first semiconductor layer and supplying one of an electron and a hole; a second electrode part electrically connected to the second semiconductor layer and supplying the remaining one of the electron and the hole; and an electrode display part interposed between the plurality of semiconductor layers and the reflective film.

Description

반도체 발광소자Semiconductor light emitting device
본 개시(Disclosure)는 전체적으로 반도체 발광소자에 관한 것으로, 특히 발광 효율을 높인 반도체 발광소자에 관한 것이다.The present disclosure relates to a semiconductor light emitting device as a whole, and more particularly to a semiconductor light emitting device having improved light emission efficiency.
본 개시(Disclosure)는 전체적으로 반도체 발광소자에 관한 것으로, 특히 금속에 의한 광흡수 손실을 줄이고 방열 효율을 향상한 반도체 발광소자에 관한 것이다.The present disclosure relates to a semiconductor light emitting device as a whole, and more particularly, to a semiconductor light emitting device that reduces light absorption loss due to metal and improves heat dissipation efficiency.
여기서, 반도체 발광소자는 전자와 정공의 재결합을 통해 빛을 생성하는 반도체 광소자를 의미하며, 3족 질화물 반도체 발광소자를 예로 들 수 있다. 3족 질화물 반도체는 Al(x)Ga(y)In(1-x-y)N (0=x=1, 0=y=1, 0=x+y=1)로 된 화합물로 이루어진다. 이외에도 적색 발광에 사용되는 GaAs계 반도체 발광소자 등을 예로 들 수 있다.Here, the semiconductor light emitting device refers to a semiconductor optical device that generates light through recombination of electrons and holes, for example, a group III nitride semiconductor light emitting device. The group III nitride semiconductor consists of a compound of Al (x) Ga (y) In (1-x-y) N (0 = x = 1, 0 = y = 1, 0 = x + y = 1). In addition, GaAs type semiconductor light emitting elements used for red light emission, etc. are mentioned.
도 1은 한국 등록특허공보 제10-1611480호에 제시된 반도체 발광소자의 일 예를 나타내는 도면이다.1 is a view illustrating an example of a semiconductor light emitting device disclosed in Korean Patent Publication No. 10-1611480.
반도체 발광소자는 기판(110), 복수의 반도체층(130,140,150), 버퍼층(120), 빛 흡수 방지막(141), 전류확산 도전막(160), 비도전성 반사막(191), 제1 전극(175), 제2 전극(185), 제1 전기적 연결(173), 제2 전기적 연결(183), 제1 하부전극(171), 및 제2 하부전극(181)을 포함한다.The semiconductor light emitting device includes a substrate 110, a plurality of semiconductor layers 130, 140, 150, a buffer layer 120, a light absorption prevention film 141, a current diffusion conductive film 160, a non-conductive reflecting film 191, and a first electrode 175. , A second electrode 185, a first electrical connection 173, a second electrical connection 183, a first lower electrode 171, and a second lower electrode 181.
비도전성 반사막(191) 위에 전극이 형성된 경우에서, 빛은 비도전성 반사막(191)에서 공기층으로 나갈 때, 공기층의 굴절률이 커서 비도전성 반사막(191)에서 공기층으로 빛이 나가지 못하고 반사가 된다. 하지만, 제1 전극(175), 제2 전극(185)에 닿은 빛은 빛이 반사도 되지만, 일부는 흡수되어 공기층에서의 반사보다 반사효율이 떨어졌다. 그 결과 제1 전극(175), 제2 전극(185)의 크기를 작게 하여 공기층과 비도전성 반사막(191)이 닿는 부위를 넓게 만들도록 하였다.In the case where an electrode is formed on the non-conductive reflecting film 191, when the light exits from the non-conductive reflecting film 191 to the air layer, the refractive index of the air layer is large so that the light cannot be reflected from the non-conductive reflecting film 191 to the air layer. However, the light hitting the first electrode 175 and the second electrode 185 is reflected by light, but part of the light is absorbed and thus the reflection efficiency is lower than the reflection in the air layer. As a result, the size of the first electrode 175 and the second electrode 185 is reduced to make the area where the air layer and the non-conductive reflective film 191 touch.
도 2는 한국 공개특허공보 제10-2011-0031099호에 제시된 반도체 발광소자의 일 예를 나타내는 도면이다.2 is a diagram illustrating an example of a semiconductor light emitting device disclosed in Korean Laid-Open Patent Publication No. 10-2011-0031099.
도 2(a)는 발광 소자(201)의 평면도이며, 도 2(b)는 도 2(a)의 A-A단면도이며, 도 2(c)는 도 2(a)의 B-B 단면도이다. 발광 소자(201)에는 p측 접촉층(228) 위에 제공된 투명 도전층(230)과, 투명 도전층(230) 상의 일부의 영역에 제공된 복수의 p 전극(240)이 제공된다. 또한, 발광 소자(201)에는 p측 접촉층(228)으로부터 적어도 n측 접촉층(222)의 표면까지 형성된 복수의 비어에 의해 노출된 n측 접촉층(222) 상에 제공된 복수의 n 전극(242)과, 비어의 내면 및 투명 도전층(230) 위에 제공된 하부 절연층(250)과, 하부 절연층(250)의 내부에 제공된 반사층(260)이 제공된다. 반사층(260)은 p 전극(240) 및 n 전극(242)의 상방을 제외한 부분에 제공된다. 투명 도전층(230)에 접촉하는 하부 절연층(250)은, 각 p 전극(240)상에서 수직 방향으로 연장되는 비어(250a)와, 각 n 전극(242) 상에서 수직 방향으로 연장되는 비어(250b)를 가진다. 또한, p 배선(270)과 n 배선(272)이 발광 소자(201) 내의 하부 절연층(250) 상에 제공된다. p 배선(270)은 하부 절연층(250) 상에서 평면 방향으로 연장되는 제2 평면 도전부(2700)와, 비어(250a)를 통해서 각각의 p 전극(240)에 전기적으로 접속된 복수의 제2 수직 도전부(2702)를 가진다. 또한, n 배선(272)은, 하부 절연층(250) 상에서 평면 방향으로 연장되는 제1 평면 도전부(2720)와, 하부 절연층(250)의 비어(250b) 및 반도체 적층 구조에 형성된 비어를 통해서 각각의 n 전극(242)에 전기적으로 접속된 복수의 제1 수직 도전부(2722)를 가진다. 또한, 발광 소자(201)에는, p 배선(270), n 배선(272), 및 투명 도전층(230)에 접촉하는 하부 절연층(250) 상에 제공된 상부 절연층(280)과, 상부 절연층(280)에 제공된 p측 개구(280a)를 통해서 p 배선(270)에 전기적으로 접속되는 p측 접합 전극(290)과, 상부 절연층(280)에 제공된 n측 개구(280b)를 통해서 n 배선(272)에 전기적으로 접속된 n측 접합 전극(292)이 제공된다.FIG. 2A is a plan view of the light emitting device 201, FIG. 2B is a sectional view taken along the line A-A in FIG. 2A, and FIG. 2C is a sectional view taken along the line B-B in FIG. The light emitting device 201 is provided with a transparent conductive layer 230 provided on the p-side contact layer 228 and a plurality of p electrodes 240 provided in a part of the region on the transparent conductive layer 230. Further, the light emitting device 201 includes a plurality of n electrodes provided on the n-side contact layer 222 exposed by a plurality of vias formed from the p-side contact layer 228 to at least the surface of the n-side contact layer 222. 242, a lower insulating layer 250 provided on the inner surface of the via and the transparent conductive layer 230, and a reflective layer 260 provided inside the lower insulating layer 250 are provided. The reflective layer 260 is provided at portions except the upper portions of the p electrode 240 and the n electrode 242. The lower insulating layer 250 in contact with the transparent conductive layer 230 includes a via 250a extending in the vertical direction on each p electrode 240 and a via 250b extending in the vertical direction on each n electrode 242. ) In addition, the p wiring 270 and the n wiring 272 are provided on the lower insulating layer 250 in the light emitting device 201. The p-wire 270 may include a second planar conductive part 2700 extending in a planar direction on the lower insulating layer 250, and a plurality of second electrically connected to the respective p electrodes 240 through the via 250a. It has a vertical conductive portion 2702. In addition, the n wiring 272 may include a first planar conductive part 2720 extending in the planar direction on the lower insulating layer 250, a via 250b of the lower insulating layer 250, and a via formed in the semiconductor stack structure. It has a plurality of first vertical conductive portions 2722 electrically connected to the respective n electrodes 242 through. In addition, the light emitting device 201 includes an upper insulating layer 280 provided on the lower insulating layer 250 in contact with the p wiring 270, the n wiring 272, and the transparent conductive layer 230, and an upper insulating layer. P-side junction electrode 290 electrically connected to p-line 270 through p-side opening 280a provided in layer 280 and n-side opening 280b provided in upper insulating layer 280. An n-side junction electrode 292 electrically connected to the wiring 272 is provided.
발광층(225)에서 발광한 빛 중 일부는 p측 클래드(226)층 측으로 발광될 수 있다. p측 클래드(226)층 측으로 발광된 빛은 n 배선(272) 및 p 배선(270)에 부딪혀 일부는 반사되고 일부는 흡수된다. 이로 인해, 발광되는 빛의 흡수를 최대한 막기 위해 n 배선(272) 및 p 배선(270)의 너비를 얇게 형성하였다.Some of the light emitted from the emission layer 225 may be emitted toward the p-side cladding 226 layer. Light emitted to the p-side cladding 226 layer strikes the n-wiring 272 and the p-wiring 270, partly reflected and partially absorbed. For this reason, in order to prevent absorption of the emitted light as much as possible, the widths of the n wiring 272 and the p wiring 270 are formed thin.
도 15는 미국 등록특허공보 제7,262,436호에 개시된 반도체 발광소자의 일 예를 나타내는 도면이다.15 is a view illustrating an example of a semiconductor light emitting device disclosed in US Patent No. 7,262,436.
반도체 발광소자는 기판(100), 기판(100) 위에 성장되는 위에 성장되는 n형 반도체층(300), n형 반도체층(300) 위에 성장되는 활성층(400), 활성층(400) 위에 성장되는 p형 반도체층(500), p형 반도체층(500) 위에 형성되는 반사막으로 기능하는 전극(901,902,903) 그리고 식각되어 노출된 n형 반도체층(300) 위에 형성되는 n측 본딩 패드(800)를 포함한다.The semiconductor light emitting device may include a substrate 100, an n-type semiconductor layer 300 grown on the substrate 100, an active layer 400 grown on the n-type semiconductor layer 300, and p grown on the active layer 400. Type semiconductor layer 500, electrodes 901, 902 and 903 serving as reflective films formed on the p-type semiconductor layer 500, and n-side bonding pads 800 formed on the etched and exposed n-type semiconductor layer 300. .
이러한 구조의 칩, 즉 기판(100)의 일측에 전극(901,902,903) 및 전극(800) 모두가 형성되어 있고, 전극(901,902,903)이 반사막으로 기능하는 형태의 칩을 플립 칩(filp chip)이라 한다. 전극(901,902,903)은 반사율이 높은 전극(901; 예: Ag), 본딩을 위한 전극(903; 예: Au) 그리고 전극(901) 물질과 전극(903) 물질사이의 확산을 방지하는 전극(902; 예: Ni)으로 이루어진다. 이러한 금속 반사막 구조는 반사율이 높고, 전류 확산에 이점을 가지지만, 금속에 의한 빛 흡수라는 단점을 가진다.A chip having such a structure, that is, a chip in which both the electrodes 901, 902, 903 and the electrode 800 are formed on one side of the substrate 100, and the electrodes 901, 902, 903 function as a reflective film is called a flip chip. The electrodes 901, 902 and 903 may include a high reflectance electrode 901 (eg Ag), an electrode 903 (eg Au) for bonding, and an electrode 902 for preventing diffusion between the electrode 901 material and the electrode 903 material; Example: Ni). This metal reflective film structure has a high reflectance and has an advantage in current spreading, but has a disadvantage of light absorption by metal.
도 16은 일본 공개특허공보 제2006-20913호에 개시된 반도체 발광소자의 일 예를 나타내는 도면이다.16 is a diagram illustrating an example of a semiconductor light emitting device disclosed in Japanese Laid-Open Patent Publication No. 2006-20913.
반도체 발광소자는 기판(100), 기판(100) 위에 성장되는 버퍼층(200), 버퍼층(200) 위에 성장되는 n형 반도체층(300), n형 반도체층(300) 위에 성장되는 활성층(400), 활성층(400) 위에 성장되는 p형 반도체층(500), p형 반도체층(500) 위에 형성되며, 전류 확산 기능을 하는 투광성 도전막(600), 투광성 도전막(600) 위에 형성되는 p측 본딩 패드(700) 그리고 식각되어 노출된 n형 반도체층(300) 위에 형성되는 n측 본딩 패드(800)를 포함한다. 그리고 투광성 도전막(600) 위에는 분포 브래그 리플렉터(900; DBR: Distributed Bragg Reflector)와 금속 반사막(904)이 구비되어 있다. 이러한 구성에 의하면, 금속 반사막(904)에 의한 빛흡수를 감소하지만, 전극(901,902,903)을 이용하는 것보다 상대적으로 전류 확산이 원활치 못한 단점이 있다.The semiconductor light emitting device includes a substrate 100, a buffer layer 200 grown on the substrate 100, an n-type semiconductor layer 300 grown on the buffer layer 200, and an active layer 400 grown on the n-type semiconductor layer 300. On the p-type semiconductor layer 500 and the p-type semiconductor layer 500 grown on the active layer 400, and the p-side formed on the light-transmissive conductive film 600 and the light-transmissive conductive film 600. The bonding pad 700 and the n-side bonding pad 800 are formed on the etched and exposed n-type semiconductor layer 300. The distributed Bragg reflector 900 (DBR: Distributed Bragg Reflector) and the metal reflecting film 904 are provided on the transparent conductive film 600. According to this configuration, the light absorption by the metal reflective film 904 is reduced, but there is a disadvantage in that current spreading is not smoother than using the electrodes 901, 902, 903.
도 23은 종래의 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면이다.23 is a view showing an example of a conventional Group III nitride semiconductor light emitting device.
3족 질화물 반도체 발광소자는 기판(10; 예; 사파이어 기판), 기판(10) 위에 성장되는 버퍼층(20), 버퍼층(20) 위에 성장되는 n형 3족 질화물 반도체층(30), n형 3족 질화물 반도체층(30) 위에 성장되는 활성층(40), 활성층(40) 위에 성장되는 p형 3족 질화물반도체층(50), p형 3족 질화물 반도체층(50) 위에 형성되는 전류확산 전극(60), 전류확산 전극(60) 위에 형성되는 p측 패드 전극(70), p형 3족 질화물 반도체층(50)과 활성층(40)이 메사(mesa) 식각되어 노출된 n형 3족 질화물 반도체층(30) 위에 형성되는 n측 패드 전극(80), 그리고 보호막(90)을 포함한다.The group III nitride semiconductor light emitting device includes a substrate 10 (eg, a sapphire substrate), a buffer layer 20 grown on the substrate 10, an n-type group III nitride semiconductor layer 30 grown on the buffer layer 20, and an n-type 3 An active layer 40 grown on the group nitride semiconductor layer 30, a p-type group III nitride semiconductor layer 50 grown on the active layer 40, and a current diffusion electrode formed on the p-type group III nitride semiconductor layer 50 ( 60), the n-type III-nitride semiconductor in which the p-side pad electrode 70, the p-type III-nitride semiconductor layer 50, and the active layer 40 formed on the current diffusion electrode 60 are mesa-etched and exposed. And an n-side pad electrode 80 and a passivation layer 90 formed on the layer 30.
전류확산 전극(60)은 p형 3족 질화물 반도체층(50) 전체로 전류가 잘 공급되도록 하기 위해 구비된다. 전류확산 전극(60)은 p형 3족 질화물 반도체층의 거의 전면에 걸쳐서 형성되며, 예를 들어, ITO 또는 Ni 및 Au를 사용하여 투광성 전도막으로 형성되거나, Ag를 사용하여 반사형 전도막으로 형성될 수 있다.The current spreading electrode 60 is provided so that the current is well supplied to the entire p-type group III nitride semiconductor layer 50. The current spreading electrode 60 is formed over almost the entire surface of the p-type group III nitride semiconductor layer, for example, formed of a transmissive conductive film using ITO or Ni and Au, or as a reflective conductive film using Ag. Can be formed.
p측 패드 전극(70)과 n측 패드 전극(80)은 전류의 공급과 외부로의 와이어 본딩을 위한 메탈 전극으로서, 예를 들어, 니켈, 금, 은, 크롬, 티타늄, 백금, 팔라듐, 로듐, 이리듐, 알루미늄, 주석, 인듐, 탄탈륨, 구리, 코발트, 철, 루테늄, 지르코늄, 텅스텐, 몰리브덴으로 이루어진 군으로부터 선택된 어느 하나 또는 이들의 조합을 사용하여 형성될 수 있다.The p-side pad electrode 70 and the n-side pad electrode 80 are metal electrodes for supplying current and wire bonding to the outside, for example, nickel, gold, silver, chromium, titanium, platinum, palladium, and rhodium. And iridium, aluminum, tin, indium, tantalum, copper, cobalt, iron, ruthenium, zirconium, tungsten, molybdenum, or any combination thereof.
보호막(90)은 이산화규소와 같은 물질로 형성되며, 생략될 수도 있다.The passivation layer 90 is formed of a material such as silicon dioxide and may be omitted.
반도체 발광소자의 대면적화 및 고전력 소모에 따라, 반도체 발광소자 내에서 원활한 전류확산을 위해 가지 전극과 복수 개의 전극이 도입되고 있다. 예를 들어, 3족 질화물 반도체 발광소자가 대면적화됨(예를 들어, 가로/세로가 1000um/1000um)에 따라, p측 패드 전극(70)과 n측 패드 전극(80)에 가지 전극을 구비함으로써, 전류확산을 개선하고 있으며, 더하여 충분한 전류 공급을 위해 p측 패드 전극(70)과 n측 패드 전극(80)이 각각 복수 개가 마련되기도 한다.As the semiconductor light emitting device becomes larger in size and consumes higher power, branch electrodes and a plurality of electrodes are introduced to smoothly spread current in the semiconductor light emitting device. For example, according to the Group III nitride semiconductor light emitting device having a large area (eg, 1000 μm / 1000 μm in width and length), branch electrodes are provided at the p-side pad electrode 70 and the n-side pad electrode 80. As a result, current spreading is improved, and in addition, a plurality of p-side pad electrodes 70 and n-side pad electrodes 80 may be provided for sufficient current supply.
p측 패드 전극(70) 및 n측 패드 전극(80)과 같은 금속재질의 전극은 두께가 두껍고, 광흡수 손실(Light Absorption Loss)이 크기 때문에 발광소자의 광 추출 효율을 저하하는 문제점이 있다.Metal-like electrodes such as the p-side pad electrode 70 and the n-side pad electrode 80 have a thick thickness and a large light absorption loss, thereby degrading light extraction efficiency of the light emitting device.
도 23은 종래의 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면이다. 3족 질화물 반도체 발광소자는 기판(10; 예; 사파이어 기판), 기판(10) 위에 성장되는 버퍼층(20), 버퍼층(20) 위에 성장되는 n형 3족 질화물 반도체층(30), n형 3족 질화물 반도체층(30) 위에 성장되는 활성층(40), 활성층(40) 위에 성장되는 p형 3족 질화물 반도체층(50), p형 3족 질화물 반도체층(50) 위에 형성되는 전류확산 전도막(60), 전류확산 전도막(60) 위에 형성되는 p측 본딩 패드(70), p형 3족 질화물 반도체층(50)과 활성층(40)이 메사 식각되어 노출된 n형 3족 질화물 반도체층(30) 위에 형성되는 n측 본딩 패드(80), 그리고 보호막(90)을 포함한다.23 is a view showing an example of a conventional Group III nitride semiconductor light emitting device. The group III nitride semiconductor light emitting device includes a substrate 10 (eg, a sapphire substrate), a buffer layer 20 grown on the substrate 10, an n-type group III nitride semiconductor layer 30 grown on the buffer layer 20, and an n-type 3 Current diffusion conductive film formed on the active layer 40 grown on the group nitride semiconductor layer 30, the p-type group III nitride semiconductor layer 50 grown on the active layer 40, and the p-type group III nitride semiconductor layer 50. 60, the p-side bonding pad 70 formed on the current diffusion conductive film 60, the n-type III-nitride semiconductor layer exposed by the mesa-etched p-type III-nitride semiconductor layer 50 and the active layer 40 And an n-side bonding pad 80 and a passivation layer 90 formed over the 30.
버퍼층(20)은 기판(10)과 n형 3족 질화물 반도체층(30) 사이의 격자상수 및 열팽창계수의 차이를 극복하기 위한 것이며, 미국특허 제5,122,845호에는 사파이어 기판 위에 380℃에서 800℃의 온도에서 100Å에서 500Å의 두께를 가지는 AlN 버퍼층을 성장시키는 기술이 기재되어 있으며, 미국특허 제5,290,393호에는 사파이어 기판 위에 200℃에서 900℃의 온도에서 10Å에서 5000Å의 두께를 가지는 Al(x)Ga(1-x)N (0≤x<1) 버퍼층을 성장시키는 기술이 기재되어 있고, 미국공개특허공보 제2006/154454호에는 600℃에서 990℃의 온도에서 SiC 버퍼층(씨앗층)을 성장시킨 다음 그 위에 In(x)Ga(1-x)N (0<x≤1) 층을 성장시키는 기술이 기재되어 있다. 바람직하게는 n형 3족 질화물 반도체층(30)의 성장에 앞서 도핑되지 않는 GaN층이 성장되며, 이는 버퍼층(20)의 일부로 보아도 좋고, n형 3족 질화물 반도체층(30)의 일부로 보아도 좋다.The buffer layer 20 is to overcome the difference in lattice constant and thermal expansion coefficient between the substrate 10 and the n-type group III nitride semiconductor layer 30. US Pat. No. 5,122,845 discloses a sapphire substrate at 380 캜 to 800 캜. A technique for growing an AlN buffer layer having a thickness of 100 kPa to 500 kPa at a temperature is described. U.S. Patent No. 5,290,393 describes Al (x) Ga (T) having a thickness of 10 kPa to 5000 kPa at a temperature of 200 to 900C on a sapphire substrate. A technique for growing a 1-x) N (0 ≦ x <1) buffer layer is described, and US Patent Publication No. 2006/154454 discloses growing a SiC buffer layer (seed layer) at a temperature of 600 ° C. to 990 ° C. Techniques for growing an In (x) Ga (1-x) N (0 <x≤1) layer thereon have been described. Preferably, the undoped GaN layer is grown prior to the growth of the n-type Group III nitride semiconductor layer 30, which may be viewed as part of the buffer layer 20 or as part of the n-type Group III nitride semiconductor layer 30. .
전류확산 전도막(60)은 p형 3족 질화물 반도체층(50) 전체로 전류가 잘 공급되도록 하기 위해 구비된다. 전류확산 전도막(60)은 p형 3족 질화물 반도체층(50)의 거의 전면에 걸쳐서 형성되며, 예를 들어, ITO, ZnO 또는 Ni 및 Au를 사용하여 투광성 전도막으로 형성되거나, Ag를 사용하여 반사형 전도막으로 형성될 수 있다.The current spreading conductive film 60 is provided so that the current is well supplied to the entire p-type group III nitride semiconductor layer 50. The current spreading conductive film 60 is formed over almost the entire surface of the p-type group III nitride semiconductor layer 50, and is formed of a translucent conductive film using, for example, ITO, ZnO or Ni and Au, or using Ag. It can be formed into a reflective conductive film.
p측 본딩 패드(70)와 n측 본딩 패드(80)는 전류의 공급과 외부로의 와이어 본딩을 위한 메탈 전극으로서, 예를 들어, 니켈, 금, 은, 크롬, 티타늄, 백금, 팔라듐, 로듐, 이리듐, 알루미늄, 주석, 인듐, 탄탈륨, 구리, 코발트, 철, 루테늄, 지르코늄, 텅스텐, 몰리브덴으로 이루어진 군으로부터 선택된 어느 하나 또는 이들의 조합을 사용하여 형성될 수 있다.The p-side bonding pad 70 and the n-side bonding pad 80 are metal electrodes for supplying current and wire bonding to the outside, for example, nickel, gold, silver, chromium, titanium, platinum, palladium, and rhodium. And iridium, aluminum, tin, indium, tantalum, copper, cobalt, iron, ruthenium, zirconium, tungsten, molybdenum, or any combination thereof.
보호막(90)은 이산화규소와 같은 물질로 형성되며, 생략될 수도 있다.The passivation layer 90 is formed of a material such as silicon dioxide and may be omitted.
도 29는 미국 등록특허공보 제6,547,249호에 개시된 직렬연결된 LED(A, B)의 일 예를 나타내는 도면이다. 여러 가지 장점 때문에 도 29에 도시된 것과 같이 복수의 LED(A, B)가 직렬연결되어 사용된다. 예를 들어, 복수의 LED(A, B)를 직렬연결하면 외부 회로와 와이어 연결의 개수가 감소하며, 와이어로 인한 광흡수 손실이 감소된다. 또한, 직렬연결된 LED(A, B) 전체의 동작전압이 상승하기 때문에 전원 공급 회로가 보다 단순화될 수 있다. 단일 기판 위에 복수의 LED(A, B)가 직렬로 연결되는 경우, 개별적인 반도체 발광소자를 직렬로 연결하는 것과 비교했을 때, 점유하는 면적이 작아 설치 밀도를 향상시킬 수 있고, 따라서, 반도체 발광소자를 포함하는 조명 장치 등을 구성할 때 소형화가 가능하다.FIG. 29 is a view showing an example of serially connected LEDs A and B disclosed in US Patent No. 6,547,249. Due to various advantages, as shown in FIG. 29, a plurality of LEDs A and B are used in series. For example, connecting a plurality of LEDs A and B in series reduces the number of external circuits and wire connections, and reduces the light absorption loss due to the wires. In addition, since the operating voltage of the series-connected LEDs A and B all increases, the power supply circuit can be further simplified. When a plurality of LEDs (A, B) are connected in series on a single substrate, compared to connecting individual semiconductor light emitting devices in series, the area occupied is small, so that the installation density can be improved, and therefore, the semiconductor light emitting devices Miniaturization is possible when configuring a lighting device including the.
한편, 복수의 LED(A, B)를 직렬연결하기 위해서 인터커넥터(34)를 증착하여 이웃한 LED(A, B)의 p측 전극(32)과 n측 전극(32)을 연결한다. 그러나 복수의 LED (A, B)를 전기적으로 절연하는 분리(isolation) 공정에서 사파이어 기판(20)이 노출되도록 복수의 반도체층을 식각해야 하는데, 그 식각 깊이가 깊어서 시간이 오래 걸리고 단차가 크기 때문에 인터커넥터(34)를 형성하기가 어렵다. 절연체(30)를 사용하여 도 29에 도시된 것과 같이 인터커넥터(34)를 완만한 경사를 이루도록 형성하는 경우 LED(A, B)들 사이 간격이 증가하여 집적도 향상에 문제가 있다.In order to connect a plurality of LEDs (A, B) in series, an interconnector 34 is deposited to connect the p-side electrode 32 and the n-side electrode 32 of the neighboring LEDs (A, B). However, a plurality of semiconductor layers must be etched to expose the sapphire substrate 20 in an isolation process that electrically insulates the plurality of LEDs (A, B), because the etching depth is long and takes a long time and a large step is large. It is difficult to form the interconnector 34. When the interconnector 34 is formed to have a gentle inclination as shown in FIG. 29 by using the insulator 30, there is a problem in that the integration between the LEDs A and B is increased.
도 30은 미국 등록특허공보 제6,547,249호에 개시된 직렬연결된 LED의 다른 예를 나타내는 도면이다. 복수의 LED(A, B)를 절연(isolation)하는 다른 방법으로 복수의 LED(A, B) 사이의 하부 반도체층(22; 예를 들어, n형 질화물 반도체층)을 식각하지 않고 이온 주입(ion implantation)을 하여 복수의 LED(A, B) 사이를 절연하면 인터커넥터(34)의 단차가 감소된다. 그러나 하부 반도체층(22)에 깊게 이온 주입하는 것이 어렵고 공정 시간이 길어서 문제가 된다.30 is a view showing another example of a series-connected LED disclosed in US Patent No. 6,547,249. Another method of isolating the plurality of LEDs (A, B) is ion implantation without etching the lower semiconductor layer 22 (for example, n-type nitride semiconductor layer) between the plurality of LEDs (A, B). Insulation between the plurality of LEDs A and B by ion implantation reduces the level of the interconnector 34. However, it is difficult to implant ions deeply into the lower semiconductor layer 22 and a long process time is a problem.
도 31은 미국 등록특허공보 제7,417,259호에 개시된 엘이디 어레이의 일 예를 나타내는 도면으로서, 고전압(high drive voltage), 저전류 구동을 위해 절연기판 위에 2차원 배열된 엘이디 어레이가 형성되어 있다. 절연기판은 사파이어 모노리식(monolithically) 기판이 사용되었고, 기판 위에 2개의 엘이디 어레이가 역방향으로 병렬 연결되어 있다. 따라서, AC 전원이 직접 구동전원으로 사용될 수 있다.FIG. 31 is a diagram illustrating an example of an LED array disclosed in US Patent No. 7,417,259, in which a two-dimensional LED array is formed on an insulating substrate for driving a high drive voltage and a low current. As the insulating substrate, a sapphire monolithically substrate was used, and two LED arrays were connected in parallel in a reverse direction on the substrate. Therefore, AC power can be used as the direct drive power.
도 32는 한국 공개특허공보 제10-2011-0031099호에 제시된 반도체 발광소자의 일 예를 나타내는 도면이다.32 is a diagram illustrating an example of a semiconductor light emitting device disclosed in Korean Laid-Open Patent Publication No. 10-2011-0031099.
도 32(a)는 발광 소자(201)의 평면도이며, 도 32(b)는 도 32(a)의 A-A 단면도이며, 도 32(c)는 도 32(a)의 B-B 단면도이다. 발광 소자(201)에는 p측 접촉층(228) 위에 제공된 투명 도전층(230)과, 투명 도전층(230) 상의 일부의 영역에 제공된 복수의 p 전극(240)이 제공된다. 또한, 발광 소자(201)에는 p측 접촉층(228)으로부터 적어도 n측 접촉층(222)의 표면까지 형성된 복수의 비어에 의해 노출된 n측 접촉층(222) 상에 제공된 복수의 n 전극(242)과, 비어의 내면 및 투명 도전층(230) 위에 제공된 하부 절연층(250)과, 하부 절연층(250)의 내부에 제공된 반사층(260)이 제공된다. 반사층(260)은 p 전극(240) 및 n 전극(242)의 상방을 제외한 부분에 제공된다. 투명 도전층(230)에 접촉하는 하부 절연층(250)은, 각 p 전극(240) 상에서 수직 방향으로 연장되는 비어(250a)와, 각 n 전극(242) 상에서 수직 방향으로 연장되는 비어(250b)를 가진다. 또한, p 배선(270)과 n 배선(272)이 발광 소자(201) 내의 하부 절연층(250) 상에 제공된다. p 배선(270)은 하부 절연층(250) 상에서 평면 방향으로 연장되는 제2 평면 도전부(2700)와, 비어(250a)를 통해서 각각의 p 전극(240)에 전기적으로 접속된 복수의 제2 수직 도전부(2702)를 가진다. 또한, n 배선(272)은, 하부 절연층(250) 상에서 평면 방향으로 연장되는 제1 평면 도전부(2720)와, 하부 절연층(250)의 비어(250b) 및 반도체 적층 구조에 형성된 비어를 통해서 각각의 n 전극(242)에 전기적으로 접속된 복수의 제1 수직 도전부(2722)를 가진다. 또한, 발광 소자(201)에는, p 배선(270), n 배선(272), 및 투명 도전층(230)에 접촉하는 하부 절연층(250) 상에 제공된 상부 절연층(280)과, 상부 절연층(280)에 제공된 p측 개구(280a)를 통해서 p 배선(270)에 전기적으로 접속되는 p측 접합 전극(290)과, 상부 절연층(280)에 제공된 n측 개구(280b)를 통해서 n 배선(272)에 전기적으로 접속된 n측 접합 전극(292)이 제공된다.FIG. 32A is a plan view of the light emitting device 201, FIG. 32B is a sectional view taken along the line A-A of FIG. 32A, and FIG. 32C is a sectional view taken along the line B-B of FIG. The light emitting device 201 is provided with a transparent conductive layer 230 provided on the p-side contact layer 228 and a plurality of p electrodes 240 provided in a part of the region on the transparent conductive layer 230. Further, the light emitting device 201 includes a plurality of n electrodes provided on the n-side contact layer 222 exposed by a plurality of vias formed from the p-side contact layer 228 to at least the surface of the n-side contact layer 222. 242, a lower insulating layer 250 provided on the inner surface of the via and the transparent conductive layer 230, and a reflective layer 260 provided inside the lower insulating layer 250 are provided. The reflective layer 260 is provided at portions except the upper portions of the p electrode 240 and the n electrode 242. The lower insulating layer 250 in contact with the transparent conductive layer 230 may include a via 250a extending in the vertical direction on each p electrode 240 and a via 250b extending in the vertical direction on each n electrode 242. ) In addition, the p wiring 270 and the n wiring 272 are provided on the lower insulating layer 250 in the light emitting device 201. The p-wire 270 may include a second planar conductive part 2700 extending in a planar direction on the lower insulating layer 250, and a plurality of second electrically connected to the respective p electrodes 240 through the via 250a. It has a vertical conductive portion 2702. In addition, the n wiring 272 may include a first planar conductive part 2720 extending in the planar direction on the lower insulating layer 250, a via 250b of the lower insulating layer 250, and a via formed in the semiconductor stack structure. It has a plurality of first vertical conductive portions 2722 electrically connected to the respective n electrodes 242 through. In addition, the light emitting device 201 includes an upper insulating layer 280 provided on the lower insulating layer 250 in contact with the p wiring 270, the n wiring 272, and the transparent conductive layer 230, and an upper insulating layer. P-side junction electrode 290 electrically connected to p-line 270 through p-side opening 280a provided in layer 280 and n-side opening 280b provided in upper insulating layer 280. An n-side junction electrode 292 electrically connected to the wiring 272 is provided.
이에 대하여 '발명의 실시를 위한 구체적인 내용'의 후단에 기술한다.This is described later in the section titled 'Details of the Invention.'
여기서는, 본 개시의 전체적인 요약(Summary)이 제공되며, 이것이 본 개시의 외연을 제한하는 것으로 이해되어서는 아니 된다(This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all, provided that this is a summary of the disclosure. of its features).
본 개시에 따른 일 태양에 의하면(According to one aspect of the present disclosure), 반도체 발광소자에 있어서, 제1 도전성을 가지는 제1 반도체층, 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층 및 제1 반도체층과 제2 반도체층 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 가지는 복수의 반도체층; 활성층에서 생성된 빛을 제1 반도체층 측으로 반사하도록 복수의 반도체층 위에 형성된 반사막; 제1 반도체층과 전기적으로 연결되며 전자와 정공 중 하나를 공급하는 제1 전극부; 제2 반도체층과 전기적으로 연결되며 전자와 정공 중 나머지 하나를 공급하는 제2 전극부; 그리고 복수의 반도체층과 반사막 사이에 개재되는 전극 표시부를 포함하는 것을 특징으로 하는 반도체 발광소자가 제공된다.According to one aspect of the present disclosure, in a semiconductor light emitting device, a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and A plurality of semiconductor layers interposed between the first semiconductor layer and the second semiconductor layer and having an active layer that generates light through recombination of electrons and holes; A reflection film formed on the plurality of semiconductor layers to reflect light generated in the active layer toward the first semiconductor layer; A first electrode part electrically connected to the first semiconductor layer and supplying one of electrons and holes; A second electrode part electrically connected to the second semiconductor layer and supplying the other one of electrons and holes; And an electrode display unit interposed between the plurality of semiconductor layers and the reflective film.
본 개시에 따른 다른 태양에 의하면(According to another aspect of the present disclosure), 반도체 발광소자에 있어서, 제1 도전성을 가지는 제1 반도체층, 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층 및 제1 반도체층과 제2 반도체층 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 가지는 복수의 반도체층; 활성층에서 생성된 빛을 제1 반도체층 측으로 반사하도록 복수의 반도체층 위에 형성된 비도전성 반사막; 비도전성 반사막의 위에 형성된 절연층; 제1 반도체층과 전기적으로 연결되며 전자와 정공 중 하나를 공급하는 제1 전극부; 제2 반도체층과 전기적으로 연결되며 전자와 정공 중 나머지 하나를 공급하는 제2 전극부; 그리고 비도전성 반사막과 절연층 사이에 개재되는 전극 표시부를 포함하는 반도체 발광소자가 제공된다.According to another aspect of the present disclosure, in a semiconductor light emitting device, a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and A plurality of semiconductor layers interposed between the first semiconductor layer and the second semiconductor layer and having an active layer that generates light through recombination of electrons and holes; A non-conductive reflecting film formed over the plurality of semiconductor layers to reflect light generated in the active layer toward the first semiconductor layer; An insulating layer formed on the nonconductive reflecting film; A first electrode part electrically connected to the first semiconductor layer and supplying one of electrons and holes; A second electrode part electrically connected to the second semiconductor layer and supplying the other one of electrons and holes; In addition, a semiconductor light emitting device including an electrode display unit interposed between a nonconductive reflective film and an insulating layer is provided.
본 개시에 따른 다른 태양에 의하면(According to another aspect of the present disclosure), 반도체 발광소자에 있어서, 제1 도전성을 가지는 제1 반도체층, 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층, 제1 반도체층과 제2 반도체층 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 구비하며, 성장 기판을 이용하여 성장되는 복수의 반도체층; 전자와 정공을 공급하는 제1 전극 및 제2 전극;으로서, 제1 반도체층과 전기적으로 연결된 제1 전극 및 제2 반도체층과 전기적으로 연결된 제2 전극; 그리고 제2 반도체층 위에 위치하는 투광성 도전막;을 포함하고, 제2 전극에 대응하는 제1 영역에 위치하는 투광성 도전막의 제1 두께는 제1 영역을 제외한 나머지 제2 영역에 위치하는 투광성 도전막의 제2 두께보다 두꺼운 반도체 발광소자가 제공된다.According to another aspect of the present disclosure, in a semiconductor light emitting device, a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, A plurality of semiconductor layers interposed between the first semiconductor layer and the second semiconductor layer, the active layers generating light through recombination of electrons and holes, and grown using a growth substrate; A first electrode and a second electrode supplying electrons and holes, comprising: a first electrode electrically connected to the first semiconductor layer and a second electrode electrically connected to the second semiconductor layer; And a light-transmissive conductive film positioned on the second semiconductor layer, wherein the first thickness of the light-transmissive conductive film located in the first region corresponding to the second electrode is equal to that of the light-transmissive conductive film positioned in the second region except for the first region. A semiconductor light emitting element thicker than the second thickness is provided.
본 개시에 따른 다른 태양에 의하면(According to another aspect of the present disclosure), 반도체 발광소자에 있어서, 제1 도전성을 가지는 제1 반도체층, 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층, 제1 반도체층과 제2 반도체층 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 구비하며, 성장 기판을 이용하여 성장되는 복수의 반도체층; 전자와 정공을 공급하는 제1 전극 및 제2 전극;으로서, 제1 반도체층과 전기적으로 연결된 제1 전극 및 제2 반도체층과 전기적으로 연결된 제2 전극; 제2 반도체층 위에 위치하는 투광성 도전막; 제2 반도체층과 투광성 도전막 사이에 개재되는 빛흡수 방지막; 빛흡수 방지막과 투광성 도전막 사이에 개재되는 빛흡수 차단막;을 포함하고, 빛흡수 방지막과 빛흡수 차단막은 서로 다른 물질로 이루어지는 반도체 발광소자가 제공된다.According to another aspect of the present disclosure, in a semiconductor light emitting device, a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, A plurality of semiconductor layers interposed between the first semiconductor layer and the second semiconductor layer, the active layers generating light through recombination of electrons and holes, and grown using a growth substrate; A first electrode and a second electrode supplying electrons and holes, comprising: a first electrode electrically connected to the first semiconductor layer and a second electrode electrically connected to the second semiconductor layer; A translucent conductive film on the second semiconductor layer; A light absorption prevention film interposed between the second semiconductor layer and the transparent conductive film; And a light absorption blocking layer interposed between the light absorption prevention layer and the transparent conductive layer, wherein the light absorption prevention layer and the light absorption blocking layer are formed of different materials.
본 개시에 따른 다른 태양에 의하면(According to another aspect of the present disclosure), 반도체 발광소자에 있어서, 장방향으로 형성된 제1 발광부 및 제2 발광부로서, 제1 도전성을 가지는 제1 반도체층, 전자와 정공의 재결합을 통해 빛을 생성하는 활성층 및 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층이 순차로 적층된 복수의 반도체층;을 포함하는 제1 발광부 및 제2 발광부; 장방향으로 형성되며, 제1 발광부 및 제2 발광부를 전기적으로 연결하는 연결 전극; 제1 발광부, 제2 발광부 및 연결 전극을 덮도록 형성되며, 활성층에서 생성된 빛을 반사하는 반사층; 제1 발광부의 제1 반도체층과 전기적으로 연통하도록 구비되며, 전자와 정공 중 하나를 공급하는 제1 전극부; 그리고, 제2 발광부의 제2 반도체층과 전기적으로 연통하도록 구비되며, 전자와 정공 중 나머지 하나를 공급하는 제2 전극부;를 포함하고, 연결 전극은 제1 발광부 및 제2 발광부와 일부 중첩되어 위치하는 반도체 발광소자가 제공된다.According to an aspect according to the present disclosure, in a semiconductor light emitting device, a first light emitting part and a second light emitting part formed in a longitudinal direction, the first semiconductor layer having a first conductivity, A first light emitting unit and a second light emitting unit including a plurality of semiconductor layers sequentially stacked with an active layer that generates light through recombination of electrons and holes, and a second semiconductor layer having a second conductivity different from the first conductivity; A connection electrode formed in a long direction and electrically connecting the first light emitting part and the second light emitting part; A reflective layer formed to cover the first light emitting part, the second light emitting part, and the connection electrode, and reflecting light generated by the active layer; A first electrode part provided to be in electrical communication with the first semiconductor layer of the first light emitting part and supplying one of electrons and holes; And a second electrode part provided to be in electrical communication with the second semiconductor layer of the second light emitting part and supplying the other one of electrons and holes, wherein the connection electrode is partially connected to the first light emitting part and the second light emitting part. There is provided a semiconductor light emitting device which is positioned in an overlapping manner.
이에 대하여 '발명의 실시를 위한 구체적인 내용'의 후단에 기술한다.This is described later in the section titled 'Details of the Invention.'
도 1은 종래의 반도체 발광소자 칩의 일 예(Lateral Chip)를 나타내는 도면,1 is a view showing an example of a conventional semiconductor light emitting device chip (Lateral Chip),
도 2는 미국 등록특허공보 제7,262,436호에 제시된 반도체 발광소자 칩의 다른 예(Flip Chip)를 나타내는 도면,FIG. 2 is a view showing another example of a flip chip of the semiconductor light emitting device chip disclosed in US Patent No. 7,262,436;
도 3은 본 개시에 따른 반도체 발광소자의 일 예를 설명하기 위한 도면,3 is a view for explaining an example of a semiconductor light emitting device according to the present disclosure;
도 4 내지 도 7은 본 개시에 따른 반도체 발광소자의 제조방법의 일 예를 설명하기 위한 도면,4 to 7 are views for explaining an example of a method of manufacturing a semiconductor light emitting device according to the present disclosure;
도 8 내지 도 10은 본 개시에 따른 반도체 발광소자의 다른 예를 설명하기 위한 도면,8 to 10 are views for explaining another example of the semiconductor light emitting device according to the present disclosure;
도 11 및 도 12는 본 개시에 따른 반도체 발광소자의 일 예를 설명하기 위한 도면,11 and 12 are views for explaining an example of a semiconductor light emitting device according to the present disclosure;
도 13은 본 개시에 따른 반도체 발광소자의 제조방법의 일 예를 설명하기 위한 도면,13 is a view for explaining an example of a method of manufacturing a semiconductor light emitting device according to the present disclosure;
도 14는 본 개시에 따른 반도체 발광소자의 제조방법의 일 예를 설명하기 위한 도면,14 is a view for explaining an example of a method of manufacturing a semiconductor light emitting device according to the present disclosure;
도 15는 미국 등록특허공보 제7,262,436호에 개시된 반도체 발광소자의 일 예를 나타내는 도면,15 is a view showing an example of a semiconductor light emitting device disclosed in US Patent No. 7,262,436;
도 16은 일본 공개특허공보 제2006-20913호에 제시된 반도체 발광소자의 일 예를 나타내는 도면,16 is a view showing an example of a semiconductor light emitting device disclosed in Japanese Laid-Open Patent Publication No. 2006-20913;
도 17은 본 개시에 따른 반도체 발광소자의 일 예를 보여주는 도면,17 illustrates an example of a semiconductor light emitting device according to the present disclosure;
도 18은 본 개시에 따른 반도체 발광소자의 다른 일 예를 보여주는 도면,18 illustrates another example of a semiconductor light emitting device according to the present disclosure;
도 19는 본 개시에 따른 반도체 발광소자의 또 다른 일 예를 보여주는 도면,19 illustrates another example of a semiconductor light emitting device according to the present disclosure;
도 20은 본 개시에 따른 반도체 발광소자의 또 다른 일 예를 보여주는 도면,20 is a view showing another example of a semiconductor light emitting device according to the present disclosure;
도 21은 본 개시에 따른 반도체 발광소자의 또 다른 일 예를 보여주는 도면,21 is a view showing another example of a semiconductor light emitting device according to the present disclosure;
도 22는 본 개시에 따른 반도체 발광소자의 또 다른 일 예를 보여주는 도면,22 is a view showing another example of a semiconductor light emitting device according to the present disclosure;
도 23은 종래의 3족 질화물 반도체 발광소자의 일 예를 나타내는 도면,23 is a view showing an example of a conventional Group III nitride semiconductor light emitting device;
도 24 및 도 25는 본 개시에 따른 반도체 발광소자의 일 예를 보여주는 도면,24 and 25 illustrate an example of a semiconductor light emitting device according to the present disclosure;
도 26은 본 개시에 따른 반도체 발광소자의 다른 일 예를 보여주는 도면,26 illustrates another example of a semiconductor light emitting device according to the present disclosure;
도 27은 본 개시에 따른 반도체 발광소자의 또 다른 일 예를 보여주는 도면,27 is a view showing another example of a semiconductor light emitting device according to the present disclosure;
도 28은 본 개시에 따른 반도체 발광소자의 또 다른 일 예를 보여주는 도면,28 is a view showing another example of a semiconductor light emitting device according to the present disclosure;
도 29는 미국 특허 제6,547,249호에 개시된 직렬연결된 LED의 일 예를 나타내는 도면,29 is a view showing an example of a series-connected LED disclosed in US Pat. No. 6,547,249;
도 30은 미국 특허 제6,547,249호에 개시된 직렬연결된 LED의 다른 예를 나타내는 도면,30 shows another example of a series connected LED disclosed in US Pat. No. 6,547,249;
도 31은 미국 등록특허공보 제7,417,259호에 개시된 엘이디 어레이의 일 예를 나타내는 도면,31 is a view showing an example of an LED array disclosed in US Patent No. 7,417,259;
도 32는 한국 공개특허공보 제10-2011-0031099호에 제시된 반도체 발광소자의 일 예를 나타내는 도면,32 is a view showing an example of a semiconductor light emitting device disclosed in Korean Laid-Open Patent Publication No. 10-2011-0031099;
도 33은 본 개시에 따른 반도체 발광소자의 일 예를 설명하기 위한 도면,33 is a view for explaining an example of a semiconductor light emitting device according to the present disclosure;
도 34는 도 33의 A-A 선을 따라 취한 절단면의 일 예를 설명하는 도면,FIG. 34 is a view for explaining an example of a cut plane taken along the line A-A of FIG. 33;
도 35는 연결 전극의 일 예를 설명하기 위한 도면,35 is a view for explaining an example of a connection electrode;
도 36은 본 개시에 따른 반도체 발광소자의 다른 예를 설명하기 위한 도면,36 is a view for explaining another example of the semiconductor light emitting device according to the present disclosure;
도 37은 본 개시에 따른 반도체 발광소자의 또 다른 예를 설명하기 위한 도면,37 is a view for explaining another example of a semiconductor light emitting device according to the present disclosure;
도 38은 본 개시에 따른 반도체 발광소자의 또 다른 예를 설명하기 위한 도면.38 illustrates another example of the semiconductor light emitting device according to the present disclosure.
이하, 본 개시를 첨부된 도면을 참고로 하여 자세하게 설명한다(The present disclosure will now be described in detail with reference to the accompanying drawing(s)).The present disclosure will now be described in detail with reference to the accompanying drawing (s).
도 3은 본 개시에 따른 반도체 발광소자(1)의 일 예를 설명하기 위한 도면이다.3 is a view for explaining an example of the semiconductor light emitting device 1 according to the present disclosure.
도 3(a)는 사시도이고, 도 3(b)는 AA`를 따라 자른 단면도이다.FIG. 3A is a perspective view and FIG. 3B is a cross-sectional view taken along AA ′.
반도체 발광소자(1)는 기판(10), 복수의 반도체층(20, 30, 40, 50), 전극 표시부(100), 반사층(91), 제1 연결 전극(71), 제2 연결 전극(75), 제1 전극(81) 및 제2 전극(85)을 포함한다. 이하, 3족 질화물 반도체 발광소자를 예로 하여 설명한다.The semiconductor light emitting device 1 may include a substrate 10, a plurality of semiconductor layers 20, 30, 40, and 50, an electrode display unit 100, a reflective layer 91, a first connection electrode 71, and a second connection electrode ( 75, a first electrode 81, and a second electrode 85. Hereinafter, the group III nitride semiconductor light emitting element will be described as an example.
기판(10)으로 주로 사파이어, SiC, Si, GaN 등이 이용되며, 기판(10)은 최종적으로 제거될 수 있다.Sapphire, SiC, Si, GaN and the like are mainly used as the substrate 10, and the substrate 10 may be finally removed.
복수의 반도체층(20, 30, 40, 50)은 기판(10) 위에 형성된 버퍼층(20), 제1 도전성을 가지는 제1 반도체층(30; 예: Si 도핑된 GaN), 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층(50; 예: Mg 도핑된 GaN) 및 제1 반도체층(30)과 제2 반도체층(50) 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층(40; 예: InGaN/(In)GaN 다중양자우물구조)을 포함한다. 복수의 반도체층(30, 40, 50) 각각은 다층으로 이루어질 수 있고, 버퍼층(20)은 생략될 수 있다.The plurality of semiconductor layers 20, 30, 40, and 50 may include a buffer layer 20 formed on the substrate 10, a first semiconductor layer 30 having a first conductivity (eg, Si-doped GaN), and different from the first conductivity. A second semiconductor layer 50 having a second conductivity (for example, Mg doped GaN) and interposed between the first semiconductor layer 30 and the second semiconductor layer 50 to generate light through recombination of electrons and holes An active layer 40 (eg, an InGaN / (In) GaN multi-quantum well structure). Each of the plurality of semiconductor layers 30, 40, and 50 may be formed in multiple layers, and the buffer layer 20 may be omitted.
전극 표시부(100)는 제1 전극(81) 및 제2 전극(85)이 갖고 있는 극성을 표시한다.The electrode display unit 100 displays the polarity of the first electrode 81 and the second electrode 85.
본 예에서, 제1 전극(81)은 제1 도전성 즉, n형의 극성을 갖는 제1 반도체층(30; 예: Si 도핑된 GaN)과 연결되고, 제2 전극(85)은 제2 도전성 즉, p형의 극성을 갖는 제2 반도체층(50; 예: Mg 도핑된 GaN)과 연결된다.In this example, the first electrode 81 is connected to the first semiconductor layer 30 (eg, Si-doped GaN) having a first conductivity, that is, an n-type polarity, and the second electrode 85 is connected to the second conductivity. That is, the second semiconductor layer 50 (eg, Mg-doped GaN) having a p-type polarity is connected.
이에 따라, 본 예에서, 기판(10) 측면에서 관찰할 때, 제1 전극(81)이 n형의 극성을 갖고, 제2 전극(85)이 p형의 극성을 갖는 것을 전극 표시부(100)의 다이오드 기호를 통해 확인할 수 있다. 이와 달리, 제1 전극(81) 및 제2 전극(85)의 극성은 반대로 바뀔 수 있다.Accordingly, in the present example, when viewed from the side of the substrate 10, the electrode display portion 100 indicates that the first electrode 81 has an n-type polarity and the second electrode 85 has a p-type polarity. This can be confirmed by the diode symbol of. In contrast, the polarities of the first electrode 81 and the second electrode 85 may be reversed.
종래에는 전극의 극성을 식별하기 위해 마주보는 제1 전극 및 제2 전극의 에지에 홈 또는 노치를 형성하였다. 따라서, 기판 측면에서 관찰하는 경우, 전극의 극성의 구별이 어렵고, 홈 또는 노치의 유무의 식별이 어려웠다.Conventionally, grooves or notches have been formed in the edges of opposing first and second electrodes to identify the polarity of the electrodes. Therefore, when observing from the substrate side, it is difficult to distinguish the polarity of the electrode, and it is difficult to identify the presence or absence of grooves or notches.
하지만, 복수의 반도체층(30, 40, 50)과 반사층(91) 사이에 전극 표시부(100)를 형성함으로써, 기판(10) 측면에서 관찰하는 경우, 제1 전극(81) 및 제2 전극(85)이 갖고 있는 극성을 전극 표시부(100)를 통해 손쉽게 확인 할 수 있다.However, when the electrode display unit 100 is formed between the plurality of semiconductor layers 30, 40, 50 and the reflective layer 91, when viewed from the side of the substrate 10, the first electrode 81 and the second electrode ( The polarity of 85 may be easily confirmed through the electrode display unit 100.
본 예에서, 전극 표시부(100)는 다이오드 기호로 표시될 수 있다. 하지만 이에 한정되지 않고, 제1 전극(81) 및 제2 전극(85)에 대한 극성을 표시할 수 있는 기호로 표시될 수 있다.In this example, the electrode display unit 100 may be represented by a diode symbol. However, the present invention is not limited thereto, and the polarity of the first electrode 81 and the second electrode 85 may be represented by a symbol capable of displaying the polarity thereof.
전극 표시부(100)는 반도체 발광소자(1)에 영향을 주지 않는 두께 및 크기로 형성되는 것이 바람직하다. 본 예에서, 전극 표시부(100)는 약 5㎛ 이하의 두께 및 약 100㎛ 이하의 크기로 형성될 수 있다. 예를 들어, 전극 표시부(100)는 2㎛의 두께 및 8㎛의 크기로 형성된다.The electrode display unit 100 may be formed to have a thickness and a size that do not affect the semiconductor light emitting device 1. In this example, the electrode display part 100 may be formed to a thickness of about 5 μm or less and a size of about 100 μm or less. For example, the electrode display unit 100 has a thickness of 2 μm and a size of 8 μm.
전극 표시부(100)는 제1 전극(81) 및 제2 전극(85)과 동일한 물질로 이루어진다.The electrode display unit 100 is made of the same material as the first electrode 81 and the second electrode 85.
본 예에서, 전극 표시부(100)는 제1 전극(81) 및 제2 전극(85)이 형성되지 않는 복수의 반도체층(30, 40, 50)과 반사층(91) 사이에 위치한다. 즉, 전극 표시부(100)는 제1 전극(81) 및 제2 전극(85)과 중첩되어 위치하지 않는다.In this example, the electrode display unit 100 is positioned between the plurality of semiconductor layers 30, 40, 50 and the reflective layer 91 in which the first electrode 81 and the second electrode 85 are not formed. That is, the electrode display unit 100 does not overlap the first electrode 81 and the second electrode 85.
반사층(91)은 활성층(40)으로부터의 빛을 복수의 반도체층(30, 40, 50) 측으로 반사한다. 본 예에서 반사층(91)은 금속 반사막에 의한 빛 흡수 감소를 위해 비도전성 반사막으로 형성된다.The reflective layer 91 reflects light from the active layer 40 toward the plurality of semiconductor layers 30, 40, and 50. In this example, the reflective layer 91 is formed of a non-conductive reflective film to reduce light absorption by the metal reflective film.
반사층(91)은, 예를 들어, 분포 브래그 리플렉터(91a; Distributed Bragg Reflector), 유전체 막(91b) 및 클래드 막(91c)을 포함한다. 유전체 막(91b) 또는 클래드 막(91c)은 생략될 수 있다. 분포 브래그 리플렉터(91a)가 비도전성인 경우, 유전체 막(91b), 분포 브래그 리플렉터(91a) 및 클래드 막(91c) 전체가 비도전성 반사막(91)으로 기능한다.The reflective layer 91 includes, for example, a distributed Bragg reflector 91a, a dielectric film 91b and a clad film 91c. The dielectric film 91b or the clad film 91c may be omitted. In the case where the distributed Bragg reflector 91a is nonconductive, the entirety of the dielectric film 91b, the distributed Bragg reflector 91a and the clad film 91c function as the nonconductive reflecting film 91.
분포 브래그 리플렉터(91a)는 활성층(40)으로부터의 빛을 기판(10)측으로 반사한다. 분포 브래그 리플렉터(91a)는 빛의 흡수를 방지하도록 투광성 물질(예: SiO2/TiO2)로 형성되는 것이 바람직하다.The distribution Bragg reflector 91a reflects the light from the active layer 40 toward the substrate 10 side. The distribution Bragg reflector 91a is preferably formed of a light transmitting material (eg, SiO 2 / TiO 2) to prevent absorption of light.
유전체 막(91b)은 복수의 반도체층(30, 40, 50)과 분포 브래그 리플렉터(91a)의 사이에 위치하며, 굴절률이 분포 브래그 리플렉터(91a)의 유효 굴절률보다 작은 유전체(예: SiO2)로 이루어질 수 있다. 여기서, 유효 굴절률은 서로 다른 굴절률을 가진 물질들로 이루어진 도파로에서 진행할 수 있는 빛이 가지는 등가 굴절률을 의미한다. 유전체 막(91b)은 빛의 반사에도 도움을 줄 수 있으며, 제2 반도체층(50) 및 활성층(40)으로부터 제1 연결 전극(71)을 전기적으로 차단하는 절연막으로도 기능할 수 있다.The dielectric film 91b is positioned between the plurality of semiconductor layers 30, 40, and 50 and the distribution Bragg reflector 91a, and the dielectric film 91b is formed of a dielectric (for example, SiO2) having a refractive index smaller than the effective refractive index of the distribution Bragg reflector 91a. Can be done. Here, the effective refractive index refers to the equivalent refractive index of light that can travel in a waveguide made of materials having different refractive indices. The dielectric film 91b may also help reflection of light, and may also function as an insulating film electrically blocking the first connection electrode 71 from the second semiconductor layer 50 and the active layer 40.
클래드 막(91c)은 분포 브래그 리플렉터(91a) 위에 형성되며, 클래드 막(91c) 또한 분포 브래그 리플렉터(91a)의 유효 굴절률보다 낮은 물질(예: Al2O3, SiO2, SiON, MgF, CaF)로 이루어질 수 있다.The clad film 91c is formed on the distributed Bragg reflector 91a, and the clad film 91c may also be made of a material having a lower refractive index than that of the distributed Bragg reflector 91a (eg, Al2O3, SiO2, SiON, MgF, CaF). have.
활성층(40)에서 발생한 빛은 많은 부분이 유전체 막(91b)과 분포 브래그 리플렉터(91a)에 의해 제1 반도체층(30) 측으로 반사된다. 유전체 막(91b), 분포 브래그 리플렉터(91a) 및 클래드 막(91c)의 관계가 광 웨이브가이드(optical waveguide)의 관점에서 설명될 수 있다. 광 웨이브가이드는 빛의 전파부를 그 보다 굴절률이 낮은 물질로 둘러싸서, 전반사를 이용하여, 빛을 안내하는 구조물이다.A large portion of light generated in the active layer 40 is reflected by the dielectric film 91b and the distributed Bragg reflector 91a toward the first semiconductor layer 30. The relationship between the dielectric film 91b, the distributed Bragg reflector 91a, and the clad film 91c can be described in terms of an optical waveguide. The optical waveguide is a structure that guides the light by using total reflection by surrounding the light propagation part with a material having a lower refractive index.
이러한 관점에서, 분포 브래그 리플렉터(91a)를 전파부로 보면, 유전체 막(91b)과 클래드 막(91c)은 전파부를 둘러싸는 구성으로서 광 웨이브가이드의 일부로 볼 수 있다.From this point of view, when the distributed Bragg reflector 91a is viewed as the propagation section, the dielectric film 91b and the clad film 91c surround the propagation section and can be viewed as part of the optical waveguide.
반사층(91)에는 전기적 연결 통로로 사용되는 적어도 하나의 제1 개구(63), 복수의 제2 개구(5, 7) 및 복수의 제3 개구(65)가 형성되어 있다. 본 예에서는 복수의 제1 개구(63)가 반사층(91), 제2 반도체층(50), 활성층(40) 및 제1 반도체층(30)의 일부까지 형성된다. 도 3(b)를 참조하면, 복수의 제2 개구(5, 7)가 반사층(91)을 관통하여 형성되며, 가장자리 근처에 복수의 제3 개구(65)가 형성된다.At least one first opening 63, a plurality of second openings 5 and 7, and a plurality of third openings 65 are formed in the reflective layer 91. In the present example, the plurality of first openings 63 are formed to the reflective layer 91, the second semiconductor layer 50, the active layer 40, and a part of the first semiconductor layer 30. Referring to FIG. 3B, a plurality of second openings 5 and 7 are formed through the reflective layer 91, and a plurality of third openings 65 are formed near the edges.
복수의 제2 개구(5, 7)는 내부 개구(5; internal opening)와, 내부 개구 주위에 위치하는 적어도 2개의 주변 개구(7; peripheral openings)들을 포함한다. 본 예에서 복수의 제2 개구(5, 7)는 1개의 내부 개구(5)와 4개의 주변 개구(7)들을 포함한다. 본 예에서 내부 개구(5)와 주변 개구(7)는 정공 공급의 통로이다. 평면상으로 관찰할 때, 내부 개구(5)는 대략 반도체 발광소자(1)의 가운데에 위치하며, 제1 전극(81)과 제2 전극(85)의 사이에 위치한다.The plurality of second openings 5, 7 comprises an internal opening 5 and at least two peripheral openings 7 positioned around the internal opening. The plurality of second openings 5, 7 in this example comprises one inner opening 5 and four peripheral openings 7. In this example, the inner opening 5 and the peripheral opening 7 are passageways for hole supply. When viewed in plan view, the inner opening 5 is located approximately in the center of the semiconductor light emitting element 1, and is located between the first electrode 81 and the second electrode 85.
제1 연결 전극(71) 및 제2 연결 전극(75)은 반사층(91) 위에, 예를 들어, 클래드 막(91c) 위에 형성된다.The first connection electrode 71 and the second connection electrode 75 are formed on the reflective layer 91, for example, on the clad film 91c.
제1 연결 전극(71)은 복수의 제1 개구(63)로 이어져 제1 반도체층(30)과 전기적으로 연결된다.The first connection electrode 71 extends into the plurality of first openings 63 to be electrically connected to the first semiconductor layer 30.
제2 연결 전극(75)은 복수의 제2 개구(5, 7)를 통해 제2 반도체층(50)과 전기적으로 연결된다. 내부 개구(5) 및 복수의 주변 개구(7)는 제2 연결 전극(75)에 의해 전기적으로 연결된다.The second connection electrode 75 is electrically connected to the second semiconductor layer 50 through the plurality of second openings 5 and 7. The inner opening 5 and the plurality of peripheral openings 7 are electrically connected by the second connection electrode 75.
본 예에서 제2연결 전극(75)은 4각 판 형상을 가지며 내부 개구(5) 및 복수의 주변 개구(7)를 덮고 있다.In this example, the second connection electrode 75 has a quadrangular plate shape and covers the inner opening 5 and the plurality of peripheral openings 7.
본 예에서 제1 연결 전극(71)은 제2 연결 전극(75)을 둘러싸도록 폐루프 형상으로 형성된다. 본 예에서 반도체 발광소자(1)는 제3 연결 전극(73)을 포함한다.In this example, the first connection electrode 71 is formed in a closed loop shape to surround the second connection electrode 75. In this example, the semiconductor light emitting device 1 includes a third connection electrode 73.
제3 연결 전극(73)은 제3 개구(65)를 통해 제2 반도체층(50)에 정공을 공급한다.The third connection electrode 73 supplies holes to the second semiconductor layer 50 through the third opening 65.
제3 연결 전극(73)은 제2 연결 전극(75)의 바깥에 위치하여 폐루프 형상으로 복수의 제3 개구(65)를 연결한다.The third connection electrode 73 is positioned outside the second connection electrode 75 to connect the plurality of third openings 65 in a closed loop shape.
반도체 발광소자(1)는 복수의 반도체층(30, 40, 50)과 반사층(91) 사이, 예를 들어, 제2 반도체층(50)과 유전체 막(91b)의 사이에 도전막(60)을 포함할 수 있다. 도전막(60)은 전류 확산 전극(ITO 등), 오믹 금속층(Cr, Ti 등), 반사 금속층(Al, Ag, 등) 등으로 형성될 수 있으며, 이들의 조합으로 이루어질 수도 있다.The semiconductor light emitting device 1 includes a conductive film 60 between a plurality of semiconductor layers 30, 40, 50 and a reflective layer 91, for example, between a second semiconductor layer 50 and a dielectric film 91b. It may include. The conductive layer 60 may be formed of a current diffusion electrode (ITO, etc.), an ohmic metal layer (Cr, Ti, etc.), a reflective metal layer (Al, Ag, etc.), or a combination thereof.
금속층에 의한 빛 흡수를 감소하기 위해 도전막(60)은 투광성 도전성 물질(예: ITO)로 이루어지는 것이 바람직하다.In order to reduce light absorption by the metal layer, the conductive film 60 is preferably made of a light transmissive conductive material (eg, ITO).
제2 연결 전극(75) 및 제3 연결 전극(73)은 각각 복수의 제2 개구(5, 7) 및 복수의 제3 개구(65)로 이어져 도전막(60)과 전기적으로 연결된다. 본 예에서 유전체 막(91b)은 도전막(60)과 분포 브래그 리플렉터(91a)의 사이로부터 제1 개구(63)의 내측면으로 이어져, 제1 연결 전극(71)을 제2 반도체층(50), 활성층(40) 및 제2 연결 전극(75)으로부터 절연한다. 이와 다르게 유전체 막(91b)과 도전막(60) 사이에 다른 별도의 절연막이 형성될 수도 있다.The second connection electrode 75 and the third connection electrode 73 are respectively connected to the conductive layer 60 by being connected to the plurality of second openings 5 and 7 and the plurality of third openings 65. In this example, the dielectric film 91b extends between the conductive film 60 and the distributed Bragg reflector 91a to the inner surface of the first opening 63, thereby connecting the first connection electrode 71 to the second semiconductor layer 50. ) And the active layer 40 and the second connection electrode 75. Alternatively, another separate insulating film may be formed between the dielectric film 91b and the conductive film 60.
본 예에서는 복수의 반도체층(30, 40, 50)에 전류 확산을 위해 또는, 균일한 전류 공급을 위해, 전술된 것과 같이, 복수의 제1 개구(63), 복수의 제2 개구(5, 7) 및 복수의 제3 개구(65)가 형성된다. 복수의 제2 개구(5, 7) 중 내부 개구(5)는 내부 개구(5)가 위치한 국부적인 영역에서 내부 개구(5)가 없는 경우에 비하여 발광을 더 증가시키는 기능을 한다.In the present example, the plurality of first openings 63 and the plurality of second openings 5, as described above, for current diffusion to the plurality of semiconductor layers 30, 40, 50 or for uniform current supply. 7) and a plurality of third openings 65 are formed. The inner opening 5 of the plurality of second openings 5, 7 functions to further increase the light emission as compared to the case where there is no inner opening 5 in the local area in which the inner opening 5 is located.
제1 개구(63), 제2 개구(5, 7) 및 제3 개구(65)의 개수와 간격과 배열 형태는 반도체 발광소자의 사이즈, 전류 확산과 균일한 전류 공급 및 발광의 균일성을 위해 적절히 조절될 수 있다. 도 3(b)에 도시한 바와 달리 내부 개구(5)는 하나 이상이 형성될 수도 있다. 본 예에서 내부 개구(5)를 기준으로 복수의 주변 개구(7), 복수의 제1 개구(63) 및 복수의 제3 개구(65)가 대칭적(symmetrically)으로 형성되어 있다.The number, spacing, and arrangement of the first openings 63, the second openings 5, 7, and the third openings 65 are used for the size of the semiconductor light emitting device, the current spreading and the uniform current supply, and the uniformity of the light emission. Can be adjusted appropriately. Unlike in FIG. 3B, at least one inner opening 5 may be formed. In this example, the plurality of peripheral openings 7, the plurality of first openings 63, and the plurality of third openings 65 are formed symmetrically with respect to the inner opening 5.
복수의 제1 개구(63) 및 복수의 제2 개구(5, 7)를 통해 전류가 공급되는데, 전류가 불균일하면 일부의 제1 개구(63) 및 제2 개구(5, 7)에 전류가 편중될 수 있고, 이로 인해 장기적으로 전류가 편중된 위치에서 열화(deterioration)가 발생될 수 있다.A current is supplied through the plurality of first openings 63 and the plurality of second openings 5, 7, and when the current is nonuniform, a portion of the first openings 63 and the second openings 5, 7 is supplied. This can be biased, which can lead to deterioration in locations where current is biased in the long run.
본 개시에서 제1 연결 전극(71)은 제2 연결 전극(75)을 둘러싸도록 폐루프 형상으로 형성되며, 제3 연결 전극(73)도 제2 연결 전극(75)을 둘러싸며 폐루프 형상으로 형성되어 있다. 여기서, 폐루프 형상은 완전한 폐루프 형상에 한정되지 않고 일부가 끊어진 폐루프 형상을 포함할 수도 있다.In the present disclosure, the first connection electrode 71 is formed in a closed loop shape to surround the second connection electrode 75, and the third connection electrode 73 also surrounds the second connection electrode 75 and has a closed loop shape. Formed. Here, the closed loop shape is not limited to the complete closed loop shape, but may include a closed loop shape in which a part is broken.
이와 같이 연결 전극들 및 개구들을 통해 균등한 전류를 공급하면서, 기하학적으로 대칭적이므로 전류 공급의 균일성, 결과적으로 발광면에서 전류 밀도의 균일성을 향상시키는 데에 매우 유리하다. 폐루프 형상이 반도체 발광소자의 발광면의 외곽 형상을 따른 형상을 가지는 것이 전류 분포의 균일성 향상을 위해 더 좋을 것이다.As such, while supplying an equal current through the connecting electrodes and the openings, it is geometrically symmetrical, which is very advantageous for improving the uniformity of the current supply and consequently the uniformity of the current density in the light emitting surface. It may be better for the closed loop shape to have a shape along the outer shape of the light emitting surface of the semiconductor light emitting device to improve the uniformity of the current distribution.
내부 개구(5)가 복수의 주변 개구(7)와 다른 극성의 전류 통로가 되는 경우 내부 개구(5)로의 전기적 연결이 곤란하거나 다른 복잡한 설계를 고려해야 할 수 있기 때문에 본 예에서는 내부 개구(5) 및 복수의 주변 개구(7)는 모두 동일 극성의 전류, 즉 정공 공급 통로가 된다. 이와 같이, 내부 개구(5) 및 복수의 주변 개구(7)가 모두 정공 공급 통로가 되는 경우, 전자 공급의 관점에서, 제2 연결 전극(75) 아래의 복수의 반도체층(30, 40, 50)에서 전자밀도는 제2 연결 전극(75) 외측의 복수의 반도체층(30, 40, 50)에서의 전자밀도보다 작을 것으로 예측된다. 그러나 이와 같은 예측과는 반대로 본 개시에서는 내부 개구(5)가 없는 경우에 비하여 제2연결 전극(75) 아래의 복수의 반도체층(30, 40, 50)에서 발광이 더 증가하는 것을 확인하였다. 이는 제2 연결 전극(75) 아래의 복수의 반도체층(30, 40, 50)에서 내부 개구(5)로 인한 상대적으로 높은 밀도의 정공이 상대적으로 정공 밀도가 낮은 영역의 전자를 끌어당겨서 전자와 정공의 재결합률이 증가함으로써 발생 된 것으로 추측된다.If the inner opening 5 becomes a current path of a different polarity from the plurality of peripheral openings 7, the electrical opening to the inner opening 5 may be difficult or other complicated designs may have to be taken into account in this example, so that the inner opening 5 may be considered. And the plurality of peripheral openings 7 become currents having the same polarity, that is, hole supply passages. As described above, when both the inner opening 5 and the plurality of peripheral openings 7 become the hole supply passages, in view of electron supply, the plurality of semiconductor layers 30, 40, 50 under the second connection electrode 75. ) Is expected to be smaller than the electron density in the plurality of semiconductor layers 30, 40, 50 outside the second connection electrode 75. Contrary to this prediction, however, the present disclosure confirmed that the light emission increased in the plurality of semiconductor layers 30, 40, and 50 under the second connection electrode 75 as compared with the case where there was no internal opening 5. In the semiconductor layers 30, 40, and 50 under the second connection electrode 75, holes having a relatively high density due to the internal opening 5 attract electrons in a region having a relatively low hole density. It is assumed that this is caused by an increase in the recombination rate of the holes.
이와 같이, 제2 연결 전극(75)의 외측 영역에서는 제1 연결 전극(71), 제2 연결 전극(75) 및 제3 연결 전극(73)과, 복수의 제1 개구(63), 복수의 제2 개구(5,7) 및 복수의 제3 개구(65)가 폐루프 형상 배열 및 대칭적 배열로 향상된 균일한 전류 분포를 달성하면서, 제2 연결 전극(75)의 내측에는 내부 개구(5)를 구비하여 발광을 유지 또는 증가시킬 수 있다.As described above, the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73, the plurality of first openings 63, and the plurality of first connection electrodes 71, in the outer region of the second connection electrode 75. The inner opening 5 inside the second connection electrode 75 while the second openings 5, 7 and the plurality of third openings 65 achieve an improved uniform current distribution in a closed loop shaped arrangement and a symmetrical arrangement. ) May be maintained or increased.
발광효율 향상을 위해 제2 연결 전극(75)의 면적 또는 내부 개구(5)와 주변 개구(7) 사이의 거리의 적합한 값을 찾을 수 있다. 예를 들어, 내부 개구(5)와 주변 개구(7) 사이의 거리가 증가하면 제2 연결 전극(75)의 면적이 증가하고 정공 밀도가 상대적으로 높은 영역이 증가한다. 제2 연결 전극(75)의 면적이 증가하면 정공 공급을 더 넓은 면적으로 할 수 있다. 반도체 발광소자(1)의 발광 성능을 유지하는 데에는 발광면에서 위치 간에 온도차가 작은 것이 바람직하다. 제2 연결 전극(75)의 면적이 증가하면 후술된 제2 전극(85)과의 전기적 연결의 개수를 더 증가시킬 수 있고, 제2 전극(85)을 통한 방열에 더 유리할 수 있다.In order to improve the luminous efficiency, a suitable value of the area of the second connection electrode 75 or the distance between the inner opening 5 and the peripheral opening 7 can be found. For example, as the distance between the inner opening 5 and the peripheral opening 7 increases, the area of the second connection electrode 75 increases and the area of which the hole density is relatively high increases. If the area of the second connection electrode 75 is increased, the hole supply can be made larger. In order to maintain the light emission performance of the semiconductor light emitting element 1, it is preferable that the temperature difference between the positions on the light emitting surface is small. If the area of the second connection electrode 75 is increased, the number of electrical connections with the second electrode 85 to be described later may be further increased, and may be more advantageous for heat dissipation through the second electrode 85.
한편, 제2 연결 전극(75)의 면적이 증가하면 발광면 전체적으로 상대적으로 정공 밀도가 높은 영역이 증가하므로 균일성 측면에서는 좋지 않을 수 있다. 정공이 전자를 끌어당겨 발광이 이루어지는 정도는 제2 연결 전극(75)의 면적 또는 내부 개구(5)와 주변 개구(7) 사이의 거리 및 개수에 영향을 받을 수 있다. 따라서 반도체 발광소자의 설계에 있어서 어떤 장점을 선택할 것인지 정하여 제2 연결 전극(75)의 면적 또는 내부 개구(5)와 주변 개구(7) 사이의 거리 및 개수를 정할 수 있다.On the other hand, when the area of the second connection electrode 75 is increased, a region having a relatively high hole density on the light emitting surface increases, which may not be good in terms of uniformity. The extent to which the holes attract electrons to emit light may be influenced by the area of the second connection electrode 75 or the distance and number of the inner opening 5 and the peripheral opening 7. Therefore, it is possible to determine the area of the second connection electrode 75 or the distance and the number of the peripheral opening 7 and the area of the second connection electrode 75 by selecting which advantage to select in the design of the semiconductor light emitting device.
본 예에서, 반도체 발광소자(1)는 반사층(91) 위에서 제1 연결 전극(71), 제2 연결 전극(75) 및 제3 연결 전극(73)을 덮는 절연층(95)을 포함한다. 절연층(95)에는 적어도 하나의 제4 개구(67), 적어도 하나의 제5 개구(68) 및 적어도 하나의 제6 개구(69)가 형성되어 있다. 절연층(95)은 SiO2로 이루어질 수 있다.In this example, the semiconductor light emitting device 1 includes an insulating layer 95 covering the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73 on the reflective layer 91. At least one fourth opening 67, at least one fifth opening 68, and at least one sixth opening 69 are formed in the insulating layer 95. The insulating layer 95 may be made of SiO 2.
제1 전극(81) 및 제2 전극(85)은 절연층(95) 위에 형성된다.The first electrode 81 and the second electrode 85 are formed on the insulating layer 95.
제1 전극(81)은 적어도 하나의 제4 개구(67)를 통해 제1 연결 전극(71)과 전기적으로 연결되어 제1 반도체층(30)에 전자를 공급한다.The first electrode 81 is electrically connected to the first connection electrode 71 through at least one fourth opening 67 to supply electrons to the first semiconductor layer 30.
제2 전극(85)은 제5 개구(68)를 통해 제2 연결 전극(75)과 전기적으로 연결되고, 제6 개구(69)를 통해 제3 연결 전극(73)와 전기적으로 연결되어 제2 반도체층(50)에 정공을 공급한다.The second electrode 85 is electrically connected to the second connection electrode 75 through the fifth opening 68, and is electrically connected to the third connection electrode 73 through the sixth opening 69. Holes are supplied to the semiconductor layer 50.
제1 전극(81) 및 제2 전극(85)은 유테틱 본딩용 전극일 수 있다.The first electrode 81 and the second electrode 85 may be electrodes for eutectic bonding.
반도체 발광소자(1)는 금속 반사막 대신 분포 브래그 리플렉터(91a)를 포함하는 비도전성 반사막(91)을 사용하여 빛 흡수를 감소시킨다.The semiconductor light emitting device 1 reduces the light absorption by using the non-conductive reflecting film 91 including the distribution Bragg reflector 91a instead of the metal reflecting film.
또한, 복수의 제1 개구(63), 복수의 제2 개구(5, 7) 및 복수의 제3 개구(65)를 형성하여 복수의 반도체층(30, 40, 50)으로의 전류 확산을 용이하게 한다.In addition, a plurality of first openings 63, a plurality of second openings 5 and 7, and a plurality of third openings 65 are formed to facilitate current diffusion into the plurality of semiconductor layers 30, 40, and 50. Let's do it.
또한, 폐루프 형상의 제1 연결 전극(71) 또는 제3 연결 전극(73)으로 전류가 더 균등하게 공급되게 하여 전류 편중에 의한 열화를 방지한다.In addition, current is supplied to the first connection electrode 71 or the third connection electrode 73 in the closed loop shape more evenly, thereby preventing deterioration due to current bias.
그리고, 가장 내측의 제2 연결 전극(75)에 의해 덮인 내부 개구(5)를 형성함으로써 내측 영역에서 발광을 유지 또는 증가시킨다.Then, the inner opening 5 covered by the innermost second connection electrode 75 is formed to maintain or increase light emission in the inner region.
도 4 내지 도 7은 본 개시에 따른 반도체 발광소자(1)의 제조방법의 일 예를 설명하는 도면이다.4 to 7 illustrate an example of a method of manufacturing the semiconductor light emitting device 1 according to the present disclosure.
먼저, 기판(10) 위에 복수의 반도체층(30, 40, 50)이 성장된다. 예를 들어, 도 4에 도시된 것과 같이, 기판(10; 예: Al2O3, Si, SiC) 위에 버퍼층(예: AlN 또는 GaN 버퍼층)과 도핑 되지 않은 반도체층(예: un-doped GaN), 제1 도전성을 가지는 제1 반도체층(30; 예: Si 도핑된 GaN), 전자와 정공의 재결합을 통해 빛을 생성하는 활성층(40; InGaN/(In)GaN 다중양자우물구조), 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층(50; 예: Mg 도핑된 GaN)이 성장된다. 여기서, 버퍼층(20)은 생략될 수 있으며, 복수의 반도체층(30, 40, 50) 각각은 다층으로 이루어질 수 있다. 제1 반도체층(30)과 제2 반도체층(50)은 도전성을 반대로 하여 형성될 수 있지만, 3족 질화물 반도체 발광소자의 경우에는 바람직하지는 않다.First, a plurality of semiconductor layers 30, 40, 50 are grown on the substrate 10. For example, as shown in FIG. 4, a buffer layer (eg, an AlN or GaN buffer layer) and an undoped semiconductor layer (eg, an un-doped GaN), a first layer are formed on the substrate 10 (eg, Al 2 O 3, Si, SiC). A first semiconductor layer 30 having a conductivity (e.g., Si doped GaN), an active layer 40 that generates light through recombination of electrons and holes (InGaN / (In) GaN multi-quantum well structure), and a first conductivity A second semiconductor layer 50 (eg, Mg doped GaN) having another second conductivity is grown. Here, the buffer layer 20 may be omitted, and each of the plurality of semiconductor layers 30, 40, and 50 may be formed in multiple layers. The first semiconductor layer 30 and the second semiconductor layer 50 may be formed with opposite conductivity, but are not preferable in the case of a group III nitride semiconductor light emitting device.
다음으로, 제2 반도체층(50) 위에 도전막(60)이 형성된다.Next, the conductive film 60 is formed on the second semiconductor layer 50.
여기서, 도전막(60)은 빛 흡수 감소를 위해 투광성 도전체(예: ITO)로 형성될 수 있다. 도전막(60)은 생략될 수 있지만, 제2 반도체층(50)으로의 전류확산을 위해 구비되는 것이 일반적이다.The conductive layer 60 may be formed of a light transmissive conductor (eg, ITO) to reduce light absorption. Although the conductive film 60 may be omitted, it is generally provided to spread the current to the second semiconductor layer 50.
다음으로, 도전막(60) 위에 전극 표시부(100)가 형성된다.Next, the electrode display unit 100 is formed on the conductive film 60.
전극 표시부(100)는 제1 전극(81) 및 제2 전극(85)이 형성되지 않는 복수의 반도체층(30, 40, 50)과 반사층(91) 사이에 위치한다. 즉, 전극 표시부(100)는 제1 전극(81) 및 제2 전극(85)과 중첩되어 위치하지 않는다.The electrode display unit 100 is positioned between the semiconductor layers 30, 40, 50 and the reflective layer 91 in which the first electrode 81 and the second electrode 85 are not formed. That is, the electrode display unit 100 does not overlap the first electrode 81 and the second electrode 85.
다음으로, 도전막(60) 위에 반사층(91)이 형성된다. 예를 들어, 도전막(60)을 덮는 유전체 막(91b), 분포 브래그 리플렉터(91a) 및 클래드 막(91c)이 형성된다. 유전체 막(91b) 또는 클래드 막(91c)은 생략될 수 있다.Next, the reflective layer 91 is formed on the conductive film 60. For example, the dielectric film 91b, the distributed Bragg reflector 91a, and the clad film 91c covering the conductive film 60 are formed. The dielectric film 91b or the clad film 91c may be omitted.
분포 브래그 리플렉터(91a)는, 예를 들어, SiO2와 TiO2의 쌍이 복수 회 적층되어 이루어진다. 이 외에도 분포 브래그 리플렉터(91a)는 Ta2O5, HfO, ZrO, SiN 등 고 굴절률 물질과 이보다 굴절률이 낮은 유전체 박막(대표적으로 SiO2)등의 조합으로 이루어질 수 있다. 분포 브래그 리플렉터(91a)가 TiO2/SiO2로 구성되는 경우 활성층으로부터 나오는 빛의 파장의 1/4의 광학 두께를 기본으로 입사 각도와 파장에 따른 반사율 등을 고려해서 최적화 공정을 거치는 것이 바람직하며, 반드시 각 층의 두께가 파장의 1/4의 광학 두께를 지켜야 하는 것은 아니다. 그 조합의 수는 4 ~ 20 페어(pairs)가 적합하다.The distributed Bragg reflector 91a is formed by stacking a pair of SiO 2 and TiO 2 a plurality of times, for example. In addition, the distribution Bragg reflector 91a may be formed of a combination of a high refractive index material such as Ta 2 O 5, HfO, ZrO, and SiN, and a dielectric thin film (typically SiO 2) having a lower refractive index. When the distribution Bragg reflector 91a is made of TiO 2 / SiO 2, it is desirable to perform an optimization process in consideration of the incident angle and the reflectance according to the wavelength based on an optical thickness of 1/4 of the wavelength of the light emitted from the active layer. The thickness of each layer does not have to obey an optical thickness of 1/4 of the wavelength. The number of combinations is suitable for 4 to 20 pairs.
빛의 반사 및 가이드를 위해 분포 브래그 리플렉터(91a)의 유효 굴절률이 유전체 막(91b)의 굴절률보다 큰 것이 바람직하다. 분포 브래그 리플렉터(91a)가 SiO2/TiO2로 구성되는 경우에, SiO2의 굴절률이 1.46이고, TiO2의 굴절률이 2.4이므로, 분포 브래그 리플렉터의 유효 굴절률은 1.46과 2.4 사이의 값을 가진다.It is preferable that the effective refractive index of the distribution Bragg reflector 91a is larger than the refractive index of the dielectric film 91b for the reflection and guide of light. In the case where the distributed Bragg reflector 91a is composed of SiO 2 / TiO 2, since the refractive index of SiO 2 is 1.46 and the refractive index of TiO 2 is 2.4, the effective refractive index of the distributed Bragg reflector has a value between 1.46 and 2.4.
따라서, 유전체 막(91b)이 SiO2로 이루어질 수 있으며, 그 두께는 0.2um ~ 1.0um가 적당하다. 정밀성을 요하는 분포 브래그 리플렉터(91a)의 증착에 앞서, 일정 두께의 유전체 막(91b)을 형성함으로써, 분포 브래그 리플렉터(91a)가 안정적으로 제조될 수 있으며, 빛의 반사에도 도움을 줄 수 있다.Therefore, the dielectric film 91b may be made of SiO2, and the thickness thereof is appropriately 0.2um to 1.0um. Prior to the deposition of the distributed Bragg reflector 91a requiring precision, by forming the dielectric film 91b having a predetermined thickness, the distributed Bragg reflector 91a can be stably manufactured and can also help reflection of light. .
클래드 막(91c)은 Al2O3와 같은 금속 산화물, SiO2, SiON와 같은 유전체 막(91b), MgF, CaF, 등의 물질로 이루어질 수 있다. 클래드 막(91c)도 분포 브래그 리플렉터(91a)의 유효굴절률보다 작은 1.46의 굴절률을 가지는 SiO2로 형성 될 수 있다. 클래드 막(91c)은 λ/4n 내지 3.0um의 두께를 가지는 것이 바람직하다. 여기서 λ는 활성층(40)에서 생성된 빛의 파장이고, n은 클래드 막(91c)을 이루는 물질의 굴절률이다. λ가 450nm(4500A)인 경우에, 4500/4*1.46 =771A 이상의 두께로 형성될 수 있다.The clad film 91c may be made of a metal oxide such as Al2O3, a dielectric film 91b such as SiO2, SiON, MgF, CaF, or the like. The clad film 91c may also be formed of SiO 2 having a refractive index of 1.46 smaller than the effective refractive index of the distribution Bragg reflector 91a. The clad film 91c preferably has a thickness of? / 4n to 3.0 um. Where? Is the wavelength of light generated in the active layer 40 and n is the refractive index of the material forming the clad film 91c. When λ is 450 nm (4500 A), it can be formed to a thickness of 4500/4 * 1.46 = 771 A or more.
다수 쌍의 SiO2/TiO2로 이루어지는 분포 브래그 리플렉터(91a)의 최상층이 λ/4n의 두께를 가지는 SiO2층으로 이루어질 수 있다는 것을 고려하여, 클래드 막(91c)은 아래에 위치하게 되는 분포 브래그 리플렉터(91a)의 최상층과 차별되도록 λ/4n보다 두꺼운 것이 바람직하다. 그러나 후속하는 복수의 제1 개구(63) 및 복수의 제2 개구(5,7) 형성공정에 부담이 될 뿐만 아니라 두께 증가가 효율 향상에 기여하지 못하고 재료비만 증가시킬 수 있기 때문에 클래드 막(91c)은 3.0um 이상으로 너무 두꺼운 것은 바람직하지 않다. 후속될 복수의 제1 개구(63), 복수의 제2 개구(5, 7) 및 복수의 제3 개구 형성공정에 부담을 주지 않기 위해, 클래드 막(91c) 두께의 최대치는 1um ~ 3um 이내로 형성되는 것이 적당할 것이다. 그러나 경우에 따라 3.0um 이상으로 형성되는 것이 불가능한 것은 아니다.Considering that the uppermost layer of the distributed Bragg reflector 91a composed of a plurality of pairs of SiO2 / TiO2 may be made of an SiO2 layer having a thickness of λ / 4n, the clad film 91c is located below the distributed Bragg reflector 91a. It is preferable to be thicker than [lambda] / 4n so as to be distinguished from the uppermost layer. However, the clad film 91c is not only burdened with the subsequent steps of forming the plurality of first openings 63 and the plurality of second openings 5, 7 but also because the increase in thickness does not contribute to the improvement of efficiency and only the material cost can be increased. ) Is not too thick beyond 3.0um. In order not to burden the plurality of first openings 63, the plurality of second openings 5, 7 and the plurality of third opening forming processes, the maximum value of the clad film 91c is formed within 1 μm to 3 μm. It will be advisable to be. However, in some cases, it is not impossible to form more than 3.0um.
분포 브래그 리플렉터(91a)와 제1 연결 전극(71), 제2 연결 전극(75) 및 제3 연결 전극(73)이 직접 접촉하는 경우에는 분포 브래그 리플렉터(91a)를 통해서 진행하는 빛의 일부가 제1 연결 전극(71), 제2 연결 전극(75) 및 제3 연결 전극(73)에 의해 흡수가 일어날 수 있다. 따라서, 전술된 것과 같이 분포 브래그 리플렉터(91a)보다 낮은 굴절률을 가지는 클래드 막(91c) 및 유전체 막(91b)을 도입하면 빛 흡수량을 많이 감소할 수 있다.When the distribution Bragg reflector 91a and the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73 are in direct contact with each other, a part of the light traveling through the distribution Bragg reflector 91a Absorption may occur by the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73. Therefore, by introducing the clad film 91c and the dielectric film 91b having a lower refractive index than the distribution Bragg reflector 91a as described above, the amount of light absorption can be greatly reduced.
유전체 막(91b)이 생략되는 경우를 생각해 볼 수 있으며, 광 웨이브 가이드의 관점에서는 바람직하지 않지만, 본 개시의 전체 기술사상의 관점에서, 분포 브래그 리플렉터(91a)와 클래드 막(91c)으로 된 구성을 배제할 이유는 없다.Although the case where the dielectric film 91b is omitted may be considered, it is not preferable from the viewpoint of the optical wave guide, but from the viewpoint of the overall technical idea of the present disclosure, it is composed of the distributed Bragg reflector 91a and the clad film 91c. There is no reason to rule out this.
분포 브래그 리플렉터(91a) 대신에 유전체인 TiO2 재질의 유전체 막(91b)을 포함하는 경우를 생각해 볼 수도 있을 것이다. 분포 브래그 리플렉터(91a)가 가장 위층에 SiO2 층을 구비하는 경우, 클래드 막(91c)을 생략하는 경우 또한 생각해 볼 수 있을 것이다.Instead of the distribution Bragg reflector 91a, one may consider the case where the dielectric film 91b made of TiO2 is used as the dielectric material. In the case where the distribution Bragg reflector 91a is provided with an SiO2 layer at the top, the case where the clad film 91c is omitted may also be considered.
이와 같이, 유전체 막(91b), 분포 브래그 리플렉터(91a) 및 클래드 막(91c)은 비도전성 반사막으로서 광 웨이브가이드의 역할을 수행하며, 전체 두께가 1 ~ 8um인 것이 바람직하다.As such, the dielectric film 91b, the distributed Bragg reflector 91a, and the clad film 91c serve as an optical waveguide as a non-conductive reflecting film, and preferably have a total thickness of 1 to 8 um.
계속해서, 도 5 및 도 6에 도시된 것과 같이, 예를 들어, 건식 식각 또는 습식 식각 또는 이들의 조합에 의해 반사층(91)에 복수의 제1 개구(63), 복수의 제2 개구(5, 7) 및 복수의 제3 개구(65)가 형성된다.Subsequently, as shown in FIGS. 5 and 6, for example, the plurality of first openings 63 and the plurality of second openings 5 in the reflective layer 91 by dry etching or wet etching, or a combination thereof. , 7) and a plurality of third openings 65 are formed.
제1 개구(63)는 반사층(91), 제2 반도체층(50), 활성층(40) 및 제1 반도체층(30) 일부까지 형성된다. 제2 개구(5, 7) 및 제3 개구(65)는 반사층(91)을 관통하여 도전막(60)의 일부를 노출하도록 형성된다. 제1 개구(63), 제2 개구(5,7) 및 제3 개구(65)는 반사층(91) 형성후에 형성될 수도 있지만, 이와 다르게, 도전막(60) 형성 전에 또는 도전막(60) 형성 후에 복수의 반도체층(30, 40, 50)에 제1 개구(63)가 일부 형성되고, 반사층(91)이 제1 개구(63)를 덮도록 형성된 후에, 반사층(91)을 관통하는 추가의 공정을 통해 제1 개구(63)가 형성되고, 추가의 공정과 동시에 또는 다른 공정으로 제2 개구(5, 7) 및 제3 개구(65)가 형성될 수 있다.The first opening 63 is formed to the reflective layer 91, the second semiconductor layer 50, the active layer 40, and a portion of the first semiconductor layer 30. The second openings 5 and 7 and the third opening 65 are formed to penetrate the reflective layer 91 to expose a portion of the conductive film 60. The first opening 63, the second openings 5, 7 and the third opening 65 may be formed after the formation of the reflective layer 91, but alternatively, before the conductive film 60 is formed or the conductive film 60. After the formation, the first openings 63 are partially formed in the plurality of semiconductor layers 30, 40, and 50, and the reflective layers 91 are formed to cover the first openings 63, and then penetrate the reflective layers 91. The first opening 63 can be formed through the process of, and the second openings 5, 7 and the third opening 65 can be formed simultaneously with the further process or in another process.
계속해서, 도 7에 도시된 것과 같이, 반사층(91) 위에 제1 연결 전극(71) 및 제2 연결 전극(75) 및 제3 연결 전극(73)이 형성된다. 예를 들어, 제1 연결 전극(71) 및 제2 연결 전극(75) 및 제3 연결 전극(73)은 스퍼터링 장비, E-빔 장비 등을 이용하여 증착 될 수 있다. 제1 연결 전극(71) 및 제2 연결 전극(75) 및 제3 연결 전극(73)은 안정적 전기적 접촉을 위해 Cr, Ti, Ni 또는 이들의 합급을 사용하여 형성될 수 있으며, Al 또는 Ag와 같은 반사 금속층을 포함할 수도 있다.Subsequently, as illustrated in FIG. 7, the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73 are formed on the reflective layer 91. For example, the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73 may be deposited using sputtering equipment, E-beam equipment, or the like. The first connection electrode 71, the second connection electrode 75, and the third connection electrode 73 may be formed using Cr, Ti, Ni, or a combination thereof for stable electrical contact. The same reflective metal layer may be included.
제1 연결 전극(71)은 복수의 제1 개구(63)를 통해 제1 반도체층(30)과 접촉하도록 형성될 수 있고, 제2 연결 전극(75)은 복수의 제2 개구(5, 7)를 통해, 제3 연결 전극(73)은 복수의 제3 개구(65)를 통해 도전막(60)에 접하도록 형성될 수 있다.The first connection electrode 71 may be formed to contact the first semiconductor layer 30 through the plurality of first openings 63, and the second connection electrode 75 may be the plurality of second openings 5 and 7. ), The third connection electrode 73 may be formed to contact the conductive layer 60 through the plurality of third openings 65.
다음으로, 제1 연결 전극(71) 및 제2 연결 전극(75) 및 제3 연결 전극(73)을 덮는 절연층(95)이 형성된다. 절연층(95)의 대표적인 물질은 SiO2이며, 이에 제한되지 않고 SiN, TiO2, Al2O3, Su-8 등이 사용될 수도 있다. 이후, 절연층(95)에 적어도 하나의 제4 개구(67), 적어도 하나의 제5 개구(68) 및 적어도 하나의 제6 개구(69)가 형성된다.Next, an insulating layer 95 is formed to cover the first connection electrode 71, the second connection electrode 75, and the third connection electrode 73. Representative material of the insulating layer 95 is SiO 2, but is not limited thereto, and SiN, TiO 2, Al 2 O 3, Su-8, or the like may be used. Thereafter, at least one fourth opening 67, at least one fifth opening 68, and at least one sixth opening 69 are formed in the insulating layer 95.
다음으로, 예를 들어, 스퍼터링 장비, E-빔 장비 등을 이용하여 절연층(95) 위에 제1 전극(81) 및 제2 전극(85)이 증착 될 수 있다. 제1 전극(81)은 적어도 하나의 제4 개구(67)를 통해 제1 연결 전극(71)에 연결되며, 제2 전극(85)은 적어도 하나의 제5 개구(68) 및 적어도 하나의 제6 개구(69)를 통해 제2 연결 전극(75) 및 제3 연결 전극(73)에 연결된다. 본 예에서, 제1 전극(81) 및 제2 전극(85)은 전극 표시부(100)에 의해서 각각의 극성이 표시되며, 전극 표시부(100)과 중첩되어 위치하지 않는다.Next, for example, the first electrode 81 and the second electrode 85 may be deposited on the insulating layer 95 using sputtering equipment, E-beam equipment, or the like. The first electrode 81 is connected to the first connection electrode 71 through at least one fourth opening 67, and the second electrode 85 is at least one fifth opening 68 and at least one agent. It is connected to the second connection electrode 75 and the third connection electrode 73 through the six opening 69. In this example, the first electrode 81 and the second electrode 85 are displayed with their polarities by the electrode display unit 100, and do not overlap with the electrode display unit 100.
제1 전극(81) 및 제2 전극(85)은 스터드 범프, 도전성 페이스트, 유테틱 본딩 등의 방법으로 외부(패키지, COB, 서브마운트 등)에 마련된 전극과 전기적으로 연결될 수 있다. 유테틱 본딩의 경우에, 제1 전극(81) 및 제2 전극(85)의 높이 차가 크게 나지 않는 것이 중요하다. 본 예에 따른 반도체 발광소자(1)에 의하면 제1 전극(81) 및 제2 전극(85)이 절연층(95) 위에 동일한 공정에 의해 형성될 수 있으므로 양 전극의 높이 차가 거의 없다. 따라서 유테틱 본딩의 경우에 이점을 가진다. 반도체 발광소자가 유테틱 본딩을 통해 외부와 전기적으로 연결되는 경우에, 제1 전극(81) 및 제2 전극(85)의 최상부는 Au/Sn 합금, Au/Sn/Cu 합금과 같은 유테틱 본딩 물질로 형성될 수 있다.The first electrode 81 and the second electrode 85 may be electrically connected to electrodes provided outside (package, COB, submount, etc.) by a method such as stud bump, conductive paste, and eutectic bonding. In the case of eutectic bonding, it is important that the height difference between the first electrode 81 and the second electrode 85 is not large. According to the semiconductor light emitting device 1 according to the present example, since the first electrode 81 and the second electrode 85 can be formed on the insulating layer 95 by the same process, there is almost no height difference between the two electrodes. Thus there is an advantage in the case of eutectic bonding. In the case where the semiconductor light emitting device is electrically connected to the outside through the eutectic bonding, the uppermost portions of the first electrode 81 and the second electrode 85 are eutectic bonding such as Au / Sn alloy and Au / Sn / Cu alloy. It can be formed of a material.
도 8은 본 개시에 따른 반도체 발광소자의 다른 예를 설명하는 도면이다.8 is a view for explaining another example of the semiconductor light emitting device according to the present disclosure.
도 8을 참조하면, 반도체 발광소자(11)는 플립 칩을 설명하고 있다. 본 개시에서 반도체 발광소자(11)은 이러한 플립 칩에 한정되지 않으며, 레터럴 칩(lateral chip)이나 수직형 칩(vertical chip)도 적용 가능하다.Referring to FIG. 8, the semiconductor light emitting element 11 illustrates a flip chip. In the present disclosure, the semiconductor light emitting device 11 is not limited to such a flip chip, and a lateral chip or a vertical chip may also be applied.
반도체 발광소자(11)는 기판(10), 복수의 반도체층(30, 40, 50), 전극 표시부(100), 광반사층(R), 제1 전극(80), 및 제2 전극(70)을 포함한다.The semiconductor light emitting device 11 may include a substrate 10, a plurality of semiconductor layers 30, 40, and 50, an electrode display unit 100, a light reflection layer R, a first electrode 80, and a second electrode 70. It includes.
기판(10)은 3족 질화물 반도체 발광소자를 예로 들면, 사파이어, SiC, Si, GaN 등이 이용되며, 기판(10)은 최종적으로 제거될 수도 있다.For example, sapphire, SiC, Si, GaN, and the like may be used as the substrate 10 as a group III nitride semiconductor light emitting device, and the substrate 10 may be finally removed.
복수의 반도체층(30, 40, 50)은 기판(10) 위에 형성된 버퍼층(도시되지 않음), 제1 도전성을 가지는 제1 반도체층(30; 예: Si 도핑된 GaN), 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층(50; 예: Mg 도핑된 GaN) 및 제1 반도체층(30)과 제2 반도체층(50) 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층(40; 예:InGaN/(In)GaN 다중양자우물구조)을 포함한다.The plurality of semiconductor layers 30, 40, and 50 may include a buffer layer (not shown) formed on the substrate 10, a first semiconductor layer 30 having a first conductivity (eg, Si-doped GaN), and different from the first conductivity. A second semiconductor layer 50 having a second conductivity (for example, Mg doped GaN) and interposed between the first semiconductor layer 30 and the second semiconductor layer 50 to generate light through recombination of electrons and holes An active layer 40 (eg, an InGaN / (In) GaN multi-quantum well structure).
복수의 반도체층(30, 40, 50) 각각은 다층으로 이루어질 수 있고, 버퍼층은 생략될 수 있다. 제1 반도체층(30)과 제2 반도체층(50)은 그 위치가 바뀔 수 있으며, 3족 질화물 반도체 발광소자에 있어서 주로 GaN으로 이루어진다.Each of the semiconductor layers 30, 40, and 50 may be formed in multiple layers, and the buffer layer may be omitted. The positions of the first semiconductor layer 30 and the second semiconductor layer 50 may be changed, and are mainly made of GaN in the group III nitride semiconductor light emitting device.
제1 전극(80)은 제1 반도체층(30)과 전기적으로 연통되어 전자를 공급한다. 본 예에서, 제1 전극(80)은 제1 도전성 즉, n형의 극성을 갖는다.The first electrode 80 is in electrical communication with the first semiconductor layer 30 to supply electrons. In this example, the first electrode 80 has a first conductivity, that is, an n-type polarity.
제2 전극(70)은 제2 반도체층(50)과 전기적으로 연통되어 정공을 공급한다. 본 예에서, 제2 전극(70)은 제2 도전성 즉, p형의 극성을 갖는다.The second electrode 70 is in electrical communication with the second semiconductor layer 50 to supply holes. In this example, the second electrode 70 has a second conductivity, that is, a p-type polarity.
제2 반도체층(50)과 제1 및 제2 전극(80, 70) 사이에는 광반사층(R)이 개재되며, 광반사층(R)은 SiO2와 같은 절연층, DBR(Distributed Bragg Reflector) 또는 ODR(Omni-Directional Reflector)을 포함하는 다층 구조를 가질 수 있다.A light reflection layer R is interposed between the second semiconductor layer 50 and the first and second electrodes 80 and 70, and the light reflection layer R is an insulating layer such as SiO 2, a distributed bragg reflector (DBR), or an ODR. It may have a multilayer structure including an omni-directional reflector.
전극 표시부(100)는 제1 전극(80) 및 제2 전극(70)이 형성되지 않는 제2 반도체층(50)과 광반사층(R) 사이에 개재되고, 제1 전극(80) 및 제2 전극(70) 사이에 위치한다. 즉, 전극 표시부(100)는 제1 전극(80) 및 제2 전극(70)과 중첩되어 위치하지 않는다.The electrode display unit 100 is interposed between the second semiconductor layer 50 and the light reflection layer R on which the first electrode 80 and the second electrode 70 are not formed, and the first electrode 80 and the second electrode. It is located between the electrodes 70. That is, the electrode display unit 100 does not overlap the first electrode 80 and the second electrode 70.
제1 전극(80) 및 제2 전극(70) 이 갖고 있는 극성을 표시한다. 본 예에서, 전극 표시부(100)는 다이오드 기호로 표시될 수 있고, 이에 한정되지 않고, 제1 전극(80) 및 제2 전극(70)에 대한 극성을 표시할 수 있는 기호로 표시될 수 있다.The polarity of the first electrode 80 and the second electrode 70 is displayed. In the present example, the electrode display unit 100 may be represented by a diode symbol, but is not limited thereto. The electrode display unit 100 may be represented by a symbol capable of displaying polarities of the first electrode 80 and the second electrode 70. .
본 예에서, 기판(10) 측면에서 관찰할 때, 제1 전극(80)이 n형의 극성을 갖고, 제2 전극(70)이 p형의 극성을 갖는 것을 전극 표시부(100)의 다이오드 기호를 통해 확인할 수 있다.In this example, when viewed from the side of the substrate 10, the diode symbol of the electrode display portion 100 indicates that the first electrode 80 has an n-type polarity and the second electrode 70 has a p-type polarity. You can check it through
도 9는 본 개시에 따른 반도체 발광소자의 또 다른 예를 보여주는 도면이다.9 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
도 9를 참조하면, 제2 반도체층(50) 위에 금속 반사막(R)이 구비되고, 제2 전극(70)이 금속 반사막(R) 위에 구비되며, 메사 식각으로 노출된 제1 반도체층(30)과 다른 제1 전극(80)이 될 수 있다.Referring to FIG. 9, a metal reflective film R is provided on the second semiconductor layer 50, a second electrode 70 is provided on the metal reflective film R, and the first semiconductor layer 30 exposed by mesa etching. ) May be different from the first electrode 80.
제2 반도체층(50)과 광반사층(R) 사이에는 투광성 도전막(미도시)이 개재될 수 있다.A transparent conductive film (not shown) may be interposed between the second semiconductor layer 50 and the light reflection layer R.
전극 표시부(100)는 제1 전극(80) 및 제2 전극(70)이 형성되지 않는 제2 반도체층(50)과 광반사층(R) 사이에 개재되고, 제1 전극(80) 및 제2 전극(70) 사이에 위치한다. 즉, 전극 표시부(100)는 제1 전극(80) 및 제2 전극(70)과 중첩되어 위치하지 않는다.The electrode display unit 100 is interposed between the second semiconductor layer 50 and the light reflection layer R on which the first electrode 80 and the second electrode 70 are not formed, and the first electrode 80 and the second electrode. It is located between the electrodes 70. That is, the electrode display unit 100 does not overlap the first electrode 80 and the second electrode 70.
제1 전극(80) 및 제2 전극(70) 이 갖고 있는 극성을 표시한다. 본 예에서, 전극 표시부(100)는 다이오드 기호로 표시될 수 있고, 이에 한정되지 않고, 제1 전극(80) 및 제2 전극(70)에 대한 극성을 표시할 수 있는 기호로 표시될 수 있다.The polarity of the first electrode 80 and the second electrode 70 is displayed. In the present example, the electrode display unit 100 may be represented by a diode symbol, but is not limited thereto. The electrode display unit 100 may be represented by a symbol capable of displaying polarities of the first electrode 80 and the second electrode 70. .
본 예에서, 기판(10) 측면에서 관찰할 때, 제1 전극(80)이 n형의 극성을 갖고, 제2 전극(70)이 p형의 극성을 갖는 것을 전극 표시부(100)의 다이오드 기호를 통해 확인할 수 있다.In this example, when viewed from the side of the substrate 10, the diode symbol of the electrode display portion 100 indicates that the first electrode 80 has an n-type polarity and the second electrode 70 has a p-type polarity. You can check it through
도 10는 본 개시에 따른 반도체 발광소자의 또 다른 예를 보여주는 도면이다.10 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
도 10에 도시된 반도체 발광소자는 전극 표시부(100)의 형성 위치를 제외하고는 도 9에서 설명된 반도체 발광소자와 실질적으로 동일하다. 따라서, 중복된 설명은 생략한다.The semiconductor light emitting device shown in FIG. 10 is substantially the same as the semiconductor light emitting device described in FIG. 9 except for the formation position of the electrode display unit 100. Therefore, duplicate description is omitted.
전극 표시부(100)는 제1 전극(80) 및 제2 전극(70)이 형성되지 않는 제2 반도체층(50)과 광반사층(R) 사이에 개재되고, 제1 전극(80) 및 제2 전극(70)과 중첩되어 위치하지 않는다.The electrode display unit 100 is interposed between the second semiconductor layer 50 and the light reflection layer R on which the first electrode 80 and the second electrode 70 are not formed, and the first electrode 80 and the second electrode. It does not overlap with the electrode 70.
예를 들어, 도 10(a)에 도시한 바와 같이, 제1 전극(80)의 제1 면, 즉, 상측면에 위치하거나, 도 10(b)에 도시한 바와 같이, 제1 전극(80)의 제1 면의 반대면인 제2 면, 즉, 하측면에 위치할 수 있다. 이에 한정되지 않고, 제1 전극(80) 및 제2 전극(70)과 중첩되지 않는 제2 반도체층(50)과 광반사층(R) 사이에 개재될 수 있다.For example, as shown in FIG. 10 (a), the first electrode 80 is positioned on the first surface, that is, the upper surface thereof, or as shown in FIG. 10 (b), the first electrode 80. It may be located on the second surface, that is, the lower surface opposite to the first surface of the). The present invention is not limited thereto and may be interposed between the second semiconductor layer 50 and the light reflection layer R which do not overlap the first electrode 80 and the second electrode 70.
도 11은 본 개시에 따른 반도체 발광소자의 일 예를 설명하기 위한 도면이고, 도 12는 도 11에서 A-A 선을 따라 절단한 단면의 일 예를 설명하기 위한 도면이다.FIG. 11 is a diagram illustrating an example of a semiconductor light emitting device according to the present disclosure, and FIG. 12 is a diagram illustrating an example of a cross section taken along line A-A in FIG. 11.
반도체 발광소자(1)는 도 11 및 도 12를 참조하면, 기판(10), 복수의 반도체층(30, 40, 50), 비도전성 반사막(91), 절연층(95), 제1 전극부(80), 제2 전극부(70) 및 전극 표시부(100)를 포함한다. 이하, 3족 질화물 반도체 발광소자를 예로 하여 설명한다.11 and 12, the semiconductor light emitting device 1 may include a substrate 10, a plurality of semiconductor layers 30, 40, and 50, a non-conductive reflective film 91, an insulating layer 95, and a first electrode part. 80, a second electrode portion 70, and an electrode display portion 100. Hereinafter, the group III nitride semiconductor light emitting element will be described as an example.
기판(10)으로 주로 사파이어, SiC, Si, GaN 등이 이용되며, 기판(10)은 최종적으로 제거될 수 있다.Sapphire, SiC, Si, GaN and the like are mainly used as the substrate 10, and the substrate 10 may be finally removed.
복수의 반도체층(30, 40, 50)은 순차적으로 적층된 제1 반도체층(30), 활성층(40) 및 제2 반도체층(50)을 포함한다.The plurality of semiconductor layers 30, 40, and 50 may include a first semiconductor layer 30, an active layer 40, and a second semiconductor layer 50 sequentially stacked.
제1 반도체층(30)과 제2 반도체층(50)은 그 위치가 바뀔 수 있으며, 3족 질화물 반도체 발광소자에 있어서 주로 GaN으로 이루어진다.The positions of the first semiconductor layer 30 and the second semiconductor layer 50 may be changed, and are mainly made of GaN in the group III nitride semiconductor light emitting device.
복수의 반도체층(30, 40, 50)은 기판(10) 위에 형성된 버퍼층(20), 제1 도전성을 가지는 제1 반도체층(30; 예: Si 도핑된 GaN), 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층(50; 예: Mg 도핑된 GaN) 및 제1 반도체층(30)과 제2 반도체층(50) 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층(40; 예: InGaN/(In)GaN 다중양자우물구조)을 포함한다. 복수의 반도체층(30, 40, 50) 각각은 다층으로 이루어질 수 있고, 버퍼층(20)은 생략될 수 있다.The plurality of semiconductor layers 30, 40, and 50 may include a buffer layer 20 formed on the substrate 10, a first semiconductor layer 30 having a first conductivity (eg, Si-doped GaN), and a second different from the first conductivity. A conductive second semiconductor layer 50 (eg, Mg-doped GaN) and an active layer interposed between the first semiconductor layer 30 and the second semiconductor layer 50 to generate light through recombination of electrons and holes ( 40; e.g., InGaN / (In) GaN multi-quantum well structure). Each of the plurality of semiconductor layers 30, 40, and 50 may be formed in multiple layers, and the buffer layer 20 may be omitted.
활성층(40)은 제1 반도체층(30)과 제2 반도체층(50) 사이에 형성되며, 빛이 발생한다.The active layer 40 is formed between the first semiconductor layer 30 and the second semiconductor layer 50 and generates light.
반도체 발광소자(1)는 복수의 반도체층(30, 40, 50)과 비도전성 반사막(91) 사이 예를 들어, 제2 반도체층(50)과 비도전성 반사막(91) 사이에 투광성 도전막(60)을 포함할 수 있다. 투광성 도전막(60)은 생략될 수 있다.The semiconductor light emitting device 1 includes a light-transmissive conductive film between the plurality of semiconductor layers 30, 40, 50 and the nonconductive reflecting film 91, for example, between the second semiconductor layer 50 and the nonconductive reflecting film 91. 60). The transparent conductive film 60 may be omitted.
투광성 도전막(60)은 투광성 도전성 물질(예: ITO), 오믹 금속층(Cr, Ti 등), 반사 금속층(Al, Ag, 등) 등으로 형성될 수 있으며, 이들의 조합으로 이루어질 수도 있다. 금속층에 의한 빛흡수를 감소하기 위해 투광성 도전막(60) 투광성 도전성 물질(예: ITO)로 이루어지는 것이 바람직하다.The transparent conductive layer 60 may be formed of a transparent conductive material (eg, ITO), an ohmic metal layer (Cr, Ti, etc.), a reflective metal layer (Al, Ag, etc.), or a combination thereof. In order to reduce light absorption by the metal layer, the light transmissive conductive film 60 is preferably made of a light transmissive conductive material (eg, ITO).
비도전성 반사막(91)은 활성층(40)에서 생성된 빛을 제1 반도체층(30) 측으로 반사하도록 복수의 반도체층(130, 140, 150) 위에 형성되며, 유전체로 형성될 수 있다. 본 개시에서 비도전성 반사막(91)은 투광성 도전막(60), 제1 및 제2 오믹 전극(81, 71), 복수의 반도체층(30, 40, 50)을 덮도록 형성된다.The non-conductive reflective film 91 may be formed on the plurality of semiconductor layers 130, 140, and 150 to reflect the light generated by the active layer 40 toward the first semiconductor layer 30, and may be formed of a dielectric material. In the present disclosure, the nonconductive reflective film 91 is formed to cover the transparent conductive film 60, the first and second ohmic electrodes 81 and 71, and the plurality of semiconductor layers 30, 40, and 50.
본 예에서, 비도전성 반사막(91)은 절연성을 가지며, 비도전성 반사막(91)을 관통하는 전기적 연결(an electrical connection)(82, 72)에 의해 복수의 반도체층(30, 40, 50)과 전기적으로 연통되는 플립칩(flip chip)이다.In this example, the non-conductive reflecting film 91 is insulative and is connected to the plurality of semiconductor layers 30, 40, 50 by an electrical connection 82, 72 passing through the non-conductive reflecting film 91. It is a flip chip in electrical communication.
예를 들어, 비도전성 반사막(91)은 금속 반사막에 의한 빛흡수 감소를 위해 적어도 비도전성 반사막(91)의 빛을 반사하는 측은 절연성 물질로 형성되며, 바람직하게는 DBR(Distributed Bragg Reflector) 또는 ODR(Omni-Directional Reflector)을 포함하는 다층 구조일 수 있다. 여기서 절연성이라는 의미는, 비도전성 반사막(91)이 전기적 도통의 수단으로 사용되지 않는다는 의미이며, 반드시 비도전성 반사막(91) 전체가 비도전성 물질로만 이루어져야 한다는 의미는 아니다.For example, the non-conductive reflecting film 91 is formed of an insulating material at least the side of the light reflecting of the non-conductive reflecting film 91 to reduce the light absorption by the metal reflecting film, preferably DBR (Distributed Bragg Reflector) or ODR It may be a multilayer structure including an omni-directional reflector. Insulating means that the non-conductive reflecting film 91 is not used as a means of electrical conduction, and does not necessarily mean that the entire non-conductive reflecting film 91 should be made of only a non-conductive material.
다층 구조의 일 예로, 유전체막(91b), 분포 브래그 리플렉터(91a) 및 클래드막(91c)을 포함한다. 유전체막(91b)은 높이차를 완화하여 분포 브래그 리플렉터(91a)를 안정적으로 제조할 수 있게 되며, 빛의 반사에도 도움을 줄 수 있다.An example of the multilayer structure includes a dielectric film 91b, a distributed Bragg reflector 91a, and a clad film 91c. The dielectric film 91b may reduce the height difference to stably manufacture the distributed Bragg reflector 91a and may also help to reflect light.
유전체막(91b)의 재질은 SiO2가 적당하다. 분포 브래그 리플렉터(91a)는 유전체막(91b) 위에 형성된다. 분포 브래그 리플렉터(91a)는 반사율이 다른 물질의 반복 적층, 예를 들어, SiO2/TiO2, SiO2/Ta2O2, 또는 SiO2/HfO의 반복 적층으로 이루어질 수 있으며, Blue 빛에 대해서는 SiO2/TiO2가 반사효율이 좋고, UV 빛에 대해서는 SiO2/Ta2O2, 또는 SiO2/HfO가 반사효율이 좋을 것이다.SiO 2 is a suitable material for the dielectric film 91b. The distributed Bragg reflector 91a is formed on the dielectric film 91b. The distribution Bragg reflector 91a may consist of repeated stacking of materials with different reflectances, for example, SiO 2 / TiO 2 , SiO 2 / Ta 2 O 2 , or SiO 2 / HfO, and for blue light SiO 2 / TiO 2 has a good reflection efficiency, and for UV light, SiO 2 / Ta 2 O 2 , or SiO 2 / HfO will have a good reflection efficiency.
클래드막(91c)은 Al2O3와 같은 금속 산화물, SiO2, SiON와 같은 유전체막(91b), MgF, CaF, 등의 물질로 이루어질 수 있다.The clad film 91c may be made of a metal oxide such as Al 2 O 3 , a dielectric film 91b such as SiO 2 , SiON, MgF, CaF, or the like.
분포 브래그 리플렉터(91a)는 수직 방향에 가까운 빛일수록 반사율이 높아서, 대략 99% 이상 반사한다. 비도전성 반사막(91)이 잘 기능 하기 위해서는 다층 구조의 각 물질층이 특별히 설계된 두께로 잘 형성되어야 한다. 비도전성 반사막(91)은 아래의 구조물들(예: 오믹 전극, 발광부들 사이 트렌치 등)로 인해 비도전성 반사막(91)에는 높이차가 발생하는 부분들이 있다. 이러한 높이차로 인해 비도전성 반사막(91)의 각 물질층이 설계된 두께로 형성되기 어려운 영역이 있고, 이 영역에서는 반사효율이 저하될 수 있다. 발광부들 사이에서 상대적으로 다른 부분보다 반사효율이 떨어질 수 있다. 따라서 가능한 한 발광부들 사이에 금속층이 적게 형성되는 것이 금속에 의한 광흡수 손실을 감소하는 데에 좋다.The distributed Bragg reflector 91a has a higher reflectance as light closer to the vertical direction reflects approximately 99% or more. In order for the non-conductive reflecting film 91 to function well, each material layer of a multilayer structure must be formed to a specially designed thickness. The non-conductive reflecting layer 91 has portions where height differences occur in the non-conductive reflecting layer 91 due to the following structures (for example, ohmic electrodes and trenches between the light emitting parts). Due to this height difference, there is an area in which each material layer of the nonconductive reflecting film 91 is hard to be formed to a designed thickness, and in this area, the reflection efficiency may decrease. The reflection efficiency may be lower than that of other parts between the light emitting parts. Therefore, forming as few metal layers between the light emitting portions as possible is preferable to reduce the light absorption loss by the metal.
절연층(95)은 비도전성 반사막(91) 위에 형성된다. 본 개시에서 절연층(95)은 제1 및 제2 연결 전극(83, 73) 및 비도전성 반사막(91)을 덮도록 형성된다.The insulating layer 95 is formed on the nonconductive reflecting film 91. In the present disclosure, the insulating layer 95 is formed to cover the first and second connection electrodes 83 and 73 and the nonconductive reflective film 91.
절연층(95)은 SiO2로 이루어질 수 있다. 절연층(95)은 이에 제한되지 않고 SiN, TiO2, Al2O3, Su-8 등이 사용될 수도 있다.The insulating layer 95 may be made of SiO 2 . The insulating layer 95 is not limited thereto, and SiN, TiO 2 , Al 2 O 3 , Su-8, or the like may be used.
비도전성 반사막(91) 위를 덮는 절연층(95)의 굴절률은 비도전성 반사막(91)의 굴절률과 비슷하여 반사되지 않고 투과가 잘된다. 그러므로, 비도전성 반사막(91)에서 반사되지 못한 일부의 빛은 절연층(95)으로 빠져나가 빛의 효율이 떨어지는 문제점이 있다. 따라서, 절연층(95)으로 빠져나가는 빛을 제1 및 제2 연결 전극(83, 73)이 비도전성 반사막(91) 위를 전체적으로 덮도록 하여, 절연층(95)으로 빠져나가는 빛을 반사하도록 한다.The refractive index of the insulating layer 95 covering the non-conductive reflective film 91 is similar to that of the non-conductive reflective film 91, so it is not reflected and transmits well. Therefore, some of the light that is not reflected by the non-conductive reflecting film 91 exits to the insulating layer 95 and has a problem in that light efficiency is inferior. Therefore, the first and second connection electrodes 83 and 73 cover the light exiting to the insulating layer 95 entirely on the non-conductive reflecting film 91 to reflect the light exiting to the insulating layer 95. do.
이로 인해, 비도전성 반사막(91)에서 반사되지 않은 일부의 빛도 제1 및 제2 연결 전극(83, 73)에 의해 반사되어 반도체 발광소자(1) 밖으로 나와 빛의 추출 효율이 높아진다.As a result, a part of light that is not reflected by the nonconductive reflecting film 91 is also reflected by the first and second connection electrodes 83 and 73 and exits the semiconductor light emitting device 1 to increase the light extraction efficiency.
제1 전극부(80) 및 제2 전극부(70)는 오믹 전극(81, 71), 연결 전극(83, 73), 전기적 연결(82, 84, 72, 74), 패드 전극(85, 75)을 각각 포함한다.The first electrode portion 80 and the second electrode portion 70 are the ohmic electrodes 81 and 71, the connection electrodes 83 and 73, the electrical connections 82, 84, 72 and 74, and the pad electrodes 85 and 75. Each).
제1 전극부(80) 및 제2 전극부(70)는 전류확산과 균등한 전류 공급을 위해 연결 전극(83, 73)을 중심으로 대칭적(symmetrically)으로 배열되어 있다. 따라서, 매우 대칭적 구조를 가지며, 균일성 향상에 좋은 구조가 된다.The first electrode portion 80 and the second electrode portion 70 are symmetrically arranged around the connecting electrodes 83 and 73 for current spreading and equal current supply. Therefore, it has a very symmetrical structure and is a good structure for improving uniformity.
제1 전극부(80)는 제1 반도체층(30)과 전기적으로 연통하도록 구비되며, 전자와 정공 중 하나를 공급하고, 제2 전극부(70)는 제2 반도체층(50)과 전기적으로 연통하도록 구비되며, 전자와 정공 중 나머지 하나를 공급한다.The first electrode part 80 is provided to be in electrical communication with the first semiconductor layer 30, and supplies one of electrons and holes, and the second electrode part 70 is electrically connected to the second semiconductor layer 50. It is provided to communicate, and supplies the other one of the electron and the hole.
제1 연결 전극(83) 및 제2 연결 전극(73)은 비도전성 반사막(191) 위에 형성된다. 구체적으로, 제1 연결 전극(83)은 비도전성 반사막(91)을 관통하며, 제1 전기적 연결(82)을 통해 제1 반도체층(30)과 전기적으로 연결되고, 제2 연결 전극(73)은 비도전성 반사막(91)을 관통하며, 제2 전기적 연결(72)을 통해 제2 반도체층(50)과 전기적으로 연결된다.The first connection electrode 83 and the second connection electrode 73 are formed on the nonconductive reflective film 191. In detail, the first connection electrode 83 penetrates the non-conductive reflecting film 91, is electrically connected to the first semiconductor layer 30 through the first electrical connection 82, and the second connection electrode 73. The light penetrates the non-conductive reflecting layer 91 and is electrically connected to the second semiconductor layer 50 through the second electrical connection 72.
제1 연결 전극(83) 및 제2 연결 전극(73)은 비도전성 반사막(91) 위를 대부분 넓게 형성되는 것이 바람직하다. 비도전성 반사막(91) 위에서 제1 연결 전극(83) 및 제2 연결 전극(73)이 충격을 흡수하여 비도전성 반사막(91)의 균열 또는 깨짐을 예방할 수 있기 때문이다.It is preferable that the first connection electrode 83 and the second connection electrode 73 are formed on the non-conductive reflecting film 91 in a wide manner. This is because the first connection electrode 83 and the second connection electrode 73 may absorb shocks on the nonconductive reflective film 91 to prevent cracking or breaking of the nonconductive reflective film 91.
일반적으로 제1 연결 전극(83) 및 제2 연결 전극(73)은 금속으로 형성되어, 제1 연결 전극(83) 및 제2 연결 전극(73)도 빛을 흡수할 수 있으므로, 좁게 형성하는 것이 휘도를 높이는 방법이라고 생각한다.In general, since the first connection electrode 83 and the second connection electrode 73 are made of metal, the first connection electrode 83 and the second connection electrode 73 may also absorb light, so that the first connection electrode 83 and the second connection electrode 73 may be formed to be narrow. I think that it is a method to raise brightness.
하지만 비도전성 반사막(91)에서 빛을 대부분 제1 반도체층(30) 측으로 반사하기 때문에 적은 양의 빛만 제1 연결 전극(83) 및 제2 연결 전극(73)측으로 들어오고, 그 중 일부가 흡수되므로 제1 연결 전극(83) 및 제2 연결 전극(73)이 넓은 것은 휘도에 많은 영향을 끼치지 않는다는 것을 발견하였다. 그러므로, 비도전성 반사막(91) 위에 제1 연결 전극(83) 및 제2 연결 전극(73)을 넓게 형성함으로써, 반도체 발광소자의 안정성, 신뢰성을 높일 수 있다.However, since most of the light is reflected by the non-conductive reflective film 91 toward the first semiconductor layer 30, only a small amount of light enters the first connection electrode 83 and the second connection electrode 73, and some of the light is absorbed. Therefore, it has been found that the wideness of the first connection electrode 83 and the second connection electrode 73 does not affect the brightness much. Therefore, by forming the first connection electrode 83 and the second connection electrode 73 wide on the nonconductive reflecting film 91, the stability and reliability of the semiconductor light emitting device can be improved.
제1 연결 전극(83) 및 제2 연결 전극(73)은 금속으로 형성될 수 있다. 예를 들면, Cr, Ti, Ni, Au, Ag, TiW, Pt, Al 등으로 형성되는 것이 바람직하다.The first connection electrode 83 and the second connection electrode 73 may be formed of metal. For example, it is preferable to form with Cr, Ti, Ni, Au, Ag, TiW, Pt, Al, etc.
제1 오믹 전극(81)은 제1 전기적 연결(82)과 제1 반도체층(30) 사이에 접촉저항 감소와 안정적 전기적 연결을 위해 형성되고, 제2 오믹 전극(71)은 제2 전기적 연결(72)과 제2 반도체층(50) 사이에 접촉저항 감소와 안정적 전기적 연결을 위해 형성된다.The first ohmic electrode 81 is formed between the first electrical connection 82 and the first semiconductor layer 30 to reduce contact resistance and provide stable electrical connection, and the second ohmic electrode 71 is formed of the second electrical connection ( It is formed between the 72 and the second semiconductor layer 50 for reducing contact resistance and stable electrical connection.
제1 오믹 전극(81) 및 제2 오믹 전극(71)은 오믹 금속(Cr, Ti 등)이 사용될 수 있다. 제1 오믹 전극(81) 및 제2 오믹 전극(71)은 원형, 다각형 등 점형으로 이루어진 섬형(island type) 전극으로 형성되며, 대체로 일 측으로 길게 연장(extending)되지 않는 형상을 의미한다.Ohmic metal (Cr, Ti, etc.) may be used for the first ohmic electrode 81 and the second ohmic electrode 71. The first ohmic electrode 81 and the second ohmic electrode 71 are formed of an island type electrode made of a dot, a circle, a polygon, and the like, and generally mean a shape that does not extend to one side.
제1 오믹 전극(81) 및 제2 오믹 전극(71)으로 인해 반도체 발광소자(1)의 동작 전압이 낮아진다. 본 개시에서는 비도전성 반사막(91)의 반사율이 증가할 수 있도록 제1 및 제2 오믹 전극(81, 71)의 높이를 최소화할 수 있다. 제1 오믹 전극(81) 및 제2 오믹 전극(71)의 높이가 감소함에 따라 비도전성 반사막(91)의 왜곡 현상이 감소하여 반사율의 저하가 감소할 수 있다.The operating voltage of the semiconductor light emitting device 1 is lowered due to the first ohmic electrode 81 and the second ohmic electrode 71. In the present disclosure, heights of the first and second ohmic electrodes 81 and 71 may be minimized to increase the reflectance of the non-conductive reflecting film 91. As the heights of the first ohmic electrode 81 and the second ohmic electrode 71 decrease, the distortion of the non-conductive reflecting film 91 may be reduced, thereby decreasing the reflectance.
제3 전기적 연결(84) 및 제4 전기적 연결(74)은 절연층(95)을 관통하며, 제1 패드 전극(85) 및 제2 패드 전극(75)과 제1 연결 전극(83) 및 제2 연결 전극(73)을 각각 전기적으로 연통한다. 본 개시에서는 제3 전기적 연결(84)은 제1 패드 전극(85)과 제1 연결 전극(83)을 전기적으로 연통하고, 제4 전기적 연결(74)은 제2 패드 전극(75)과 제2 연결 전극(73)을 전기적으로 연통한다. 제3 전기적 연결(84) 및 제4 전기적 연결(74)이 복수개로 형성될 수도 있다. 예를 들어, 제 제3 전기적 연결(84) 및 제4 전기적 연결(74)의 개수는 제1 전기적 연결(82) 및 제2 전기적 연결(72)의 개수보다 많게 형성될 수 있다.The third electrical connection 84 and the fourth electrical connection 74 penetrate through the insulating layer 95, and the first pad electrode 85 and the second pad electrode 75, the first connection electrode 83, and the first connection electrode 83 and the first connection electrode 83 and the first connection electrode 83 and the first connection electrode 83, respectively. The two connecting electrodes 73 are electrically connected to each other. In the present disclosure, the third electrical connection 84 is in electrical communication with the first pad electrode 85 and the first connection electrode 83, and the fourth electrical connection 74 is connected with the second pad electrode 75 and the second. The connection electrode 73 is in electrical communication. A plurality of third electrical connections 84 and fourth electrical connections 74 may be formed. For example, the number of the third electrical connection 84 and the fourth electrical connection 74 may be greater than the number of the first electrical connection 82 and the second electrical connection 72.
제1 패드 전극(85)은 제3 전기적 연결(84)을 통해 제1 연결 전극(83)과 전기적으로 연결되어 제1 반도체층(30)으로 전자를 공급한다.The first pad electrode 85 is electrically connected to the first connection electrode 83 through the third electrical connection 84 to supply electrons to the first semiconductor layer 30.
제2 패드 전극(75)은 제4 전기적 연결(74)을 통해 제2 연결 전극(73)과 전기적으로 연결되어 제2 반도체층(50)으로 정공을 공급한다.The second pad electrode 75 is electrically connected to the second connection electrode 73 through the fourth electrical connection 74 to supply holes to the second semiconductor layer 50.
제1 패드 전극(85) 및 제2 패드 전극(75)은 외부 전극과의 전기적 연결용 전극으로서, 외부 전극과 유테틱 본딩되거나, 솔더링되거나 또는 와이어 본딩도 가능하다. 외부 전극은 서브 마운트에 구비된 도통부, 패키지의 리드 프레임, PCB에 형성된 전기 패턴 등일 수 있으며, 반도체 발광소자와 독립적으로 구비된 도선이라면 그 형태에 특별한 제한이 있는 것은 아니다. 제1 패드 전극(85) 및 제2 패드 전극(75)은 어느 정도 면적을 가지도록 형성되어 있어서 방열 통로가 된다.The first pad electrode 85 and the second pad electrode 75 are electrodes for electrical connection with the external electrode, and may be eutectic bonded, soldered or wire bonded with the external electrode. The external electrode may be a conductive part provided in the sub-mount, a lead frame of the package, an electrical pattern formed on the PCB, and the like, and the external electrode may not be particularly limited in form. The first pad electrode 85 and the second pad electrode 75 are formed to have an area to some extent, so that they become heat dissipation passages.
또한, 일반적으로 반도체 발광소자에 제1 오믹 전극(81), 제2 오믹 전극(71), 제1 연결 전극(83) 및 제2 연결 전극(73) 등을 형성할 때, 복수의 금속 층으로 구성된다. 최하층은 접착면과 결합력이 높아야 하며, Cr, Ti와 같은 물질이 주로 사용되며, Ni, Ti, TiW 등도 사용될 수 있으며, 특별히 제한되는 것은 아니다. 최상층으로는 와이어 본딩 또는 외부 전극과 연결을 위해, Au이 사용된다. 그리고, Au의 양을 줄이고, 상대적으로 무른 Au의 특성을 보완하기 위해, 최하층과 최상층 사이에, 요구되는 사양에 따라, Ni, Ti, TiW, W 등이 사용되거나, 높은 반사율이 요구되는 경우에, Al, Ag 등이 사용된다.In general, when the first ohmic electrode 81, the second ohmic electrode 71, the first connection electrode 83, the second connection electrode 73, and the like are formed in the semiconductor light emitting device, a plurality of metal layers may be used. It is composed. The lowermost layer should have high bonding strength and bonding strength, and materials such as Cr and Ti may be mainly used, and Ni, Ti, TiW, and the like may also be used. As the top layer, Au is used for wire bonding or for connection with external electrodes. In order to reduce the amount of Au and compensate for the relatively soft Au properties, Ni, Ti, TiW, W, or the like is used between the lowermost layer and the uppermost layer depending on the required specification, or when a high reflectance is required. , Al, Ag and the like are used.
전극 표시부(100)는 비도전성 반사막(91)과 절연층(95) 사이에 개재되면, 제1 패드 전극(85) 및 제2 패드 전극(75)이 갖고 있는 극성을 표시한다.When the electrode display unit 100 is interposed between the non-conductive reflecting film 91 and the insulating layer 95, the electrode display unit 100 displays the polarity of the first pad electrode 85 and the second pad electrode 75.
전극 표시부(100)는 제1 패드 전극(85) 및 제2 패드 전극(75) 중 적어도 하나의 패드 전극 아래에 위치하며, 선택된 제1 패드 전극(85) 및 제2 패드 전극(75)에 대응하는 제1 연결 전극(83) 또는 제2 연결 전극(73)과 동일한 층에 위치한다. 이때, 전극 표시부(100)는 제1 연결 전극(83) 또는 제2 연결 전극(73)과 중첩되어 위치하지 않는다.The electrode display unit 100 is positioned below at least one pad electrode of the first pad electrode 85 and the second pad electrode 75, and corresponds to the selected first pad electrode 85 and the second pad electrode 75. It is positioned on the same layer as the first connection electrode 83 or the second connection electrode 73. In this case, the electrode display unit 100 does not overlap the first connection electrode 83 or the second connection electrode 73.
본 개시에서는 제2 패드 전극(75)에 대응하여 전극 표시부(100)가 제2 패드 전극(75) 아래에 제2 연결 전극(73)과 중첩되지 않으면서 제2 연결 전극(73)과 동일한 층에 위치할 수 있다. 이와 반대로, 전극 표시부(100)는 제1 패드 전극(85)에 대응하여 제1 패드 전극(85) 아래에 제1 연결 전극(83)과 중첩되지 않으며, 제1 연결 전극(83)과 동일한 층에 위치할 수 있다.In the present disclosure, the electrode display unit 100 corresponds to the second pad electrode 75, and the same layer as the second connection electrode 73 without overlapping the second connection electrode 73 under the second pad electrode 75. It can be located at On the contrary, the electrode display unit 100 does not overlap the first connection electrode 83 under the first pad electrode 85 in correspondence with the first pad electrode 85, and is the same layer as the first connection electrode 83. It can be located at
전극 표시부(100)는 적어도 1개이상의 홀을 포함하며, 원형, 사각형, 다각형 등 점형으로 이루어진 섬형(island type)의 형상으로 형성될 수 있다. 본 개시에서 전극 표시부(100)가 3개의 홀을 가지면 원형으로 형상되도록 도시하였지만, 이에 한정되지 않는다.The electrode display unit 100 may include at least one hole, and may be formed in an island type shape including a dot, a circle, a rectangle, and a polygon. In the present disclosure, the electrode display unit 100 is illustrated to have a circular shape when it has three holes, but is not limited thereto.
전극 표시부(100)는 반도체 발광소자(1)에 영향을 주지 않는 두께 및 크기로 형성되는 것이 바람직하다. 여기서, 전극 표시부(100)의 크기는 제2 전기적 연결(84) 및 제4 전기적 연결(74)의 개구 크기보다 크게 형성되며, 전극 표시부(100)의 두께는 제1 연결 전극(83) 및 제2 연결 전극(73)의 두께와 동일한 두께를 갖는 것이 바람직하다.The electrode display unit 100 may be formed to have a thickness and a size that do not affect the semiconductor light emitting device 1. Here, the size of the electrode display unit 100 is greater than the opening size of the second electrical connection 84 and the fourth electrical connection 74, the thickness of the electrode display unit 100 is the first connection electrode 83 and the first electrode. It is preferable to have the same thickness as the thickness of the two connection electrode 73.
전극 표시부(100)는 제1 연결 전극(83) 및 제2 연결 전극(73)과 동일한 물질로 이루어진다.The electrode display unit 100 is made of the same material as the first connection electrode 83 and the second connection electrode 73.
본 예에서, 제1 패드 전극(85)은 제1 도전성 즉, n형의 극성을 갖는 제1 반도체층(30; 예: Si 도핑된 GaN)과 연결되고, 제2 패드 전극(75)은 제2 도전성 즉, p형의 극성을 갖는 제2 반도체층(50; 예: Mg 도핑된 GaN)과 연결된다.In this example, the first pad electrode 85 is connected to the first semiconductor layer 30 having a first conductivity, that is, an n-type polarity (eg, Si-doped GaN), and the second pad electrode 75 is formed of a first pad electrode 75. It is connected to the second semiconductor layer 50 (eg, Mg-doped GaN) having a second conductivity, that is, a p-type polarity.
제1 패드 전극(85) 및 제2 패드 전극(75)이 비도전성 반사막(91)을 기준으로 복수의 반도체층(30, 40, 50)의 반대측에 구비되는 플립칩(flip chip)에 있어서, 기판(10) 방향에서 관찰할 때 전극 표시부(100)가 제2 패드 전극(75) 아래의 제2 연결 전극(73)과 동일한 층에 위치하므로, 제1 패드 전극(85)은 n형의 극성을 갖고, 제2 패드 전극(75)이 p형의 극성을 갖는 것을 전극 표시부(100)를 통해 확인할 수 있다. 이와 달리, 제1 패드 전극(85) 및 제2 전극(75)의 극성은 반대로 바뀔 수 있다.In a flip chip in which the first pad electrode 85 and the second pad electrode 75 are provided on opposite sides of the plurality of semiconductor layers 30, 40, and 50 with respect to the non-conductive reflective film 91, Since the electrode display part 100 is positioned on the same layer as the second connection electrode 73 under the second pad electrode 75 when viewed in the direction of the substrate 10, the first pad electrode 85 has an n-type polarity. It can be confirmed that the second pad electrode 75 has a p-type polarity through the electrode display unit 100. In contrast, the polarities of the first pad electrode 85 and the second electrode 75 may be reversed.
종래에는 전극의 극성을 식별하기 위해 마주보는 제1 패드 전극 및 제2 패드 전극의 에지에 홈 또는 노치를 형성하였다. 따라서, 기판 측면에서 관찰하는 경우, 전극의 극성의 구별이 어렵고, 홈 또는 노치의 유무의 식별이 어려웠다.Conventionally, grooves or notches have been formed in the edges of opposing first and second pad electrodes to identify the polarity of the electrodes. Therefore, when observing from the substrate side, it is difficult to distinguish the polarity of the electrode, and it is difficult to identify the presence or absence of grooves or notches.
하지만, 비도전성 반사막(91) 위에 전극 표시부(100)를 형성함으로써, 기판(10) 측면에서 관찰하는 경우, 제1 패드 전극(85) 및 제2 전극(75)이 갖고 있는 극성을 전극 표시부(100)를 통해 손쉽게 확인 할 수 있다.However, when the electrode display unit 100 is formed on the non-conductive reflecting film 91, when viewed from the side of the substrate 10, the polarity of the first pad electrode 85 and the second electrode 75 has the electrode display unit ( 100) can be easily checked.
본 개시에 따른 반도체 발광소자(1)의 제조방법을 살펴보면, 먼저, 기판(10) 상에 제1 반도체층(30), 활성층(40), 제2 반도체층(50), 전류 확산 전극(60; 예: ITO)을 형성하고, 메사 식각하여 제1 전기적 연결(73)에 대응하는 제1 반도체층(30)의 일부를 노출한다. 메사 식각은 전류 확산 전극(60) 형성 전 또는 이후에 수행될 수도 있다. 전류 확산 전극(60)은 생략될 수 있다.Looking at the manufacturing method of the semiconductor light emitting device 1 according to the present disclosure, first, the first semiconductor layer 30, the active layer 40, the second semiconductor layer 50, the current diffusion electrode 60 on the substrate 10 Eg, ITO is formed and mesa-etched to expose a portion of the first semiconductor layer 30 corresponding to the first electrical connection 73. Mesa etching may be performed before or after the current diffusion electrode 60 is formed. The current spreading electrode 60 can be omitted.
다음으로, 전류 확산 전극(60) 및 노출된 제1 반도체층(30)에 각각 오믹 전극(71, 81)을 형성한다. 오믹 전극(71, 81)은 생략될 수 있지만 동작전압 상승을 억제하고 안정적인 전기적 접촉을 위해 구비되는 것이 바람직하다.Next, ohmic electrodes 71 and 81 are formed on the current diffusion electrode 60 and the exposed first semiconductor layer 30, respectively. Although the ohmic electrodes 71 and 81 may be omitted, the ohmic electrodes 71 and 81 may be provided to suppress an increase in operating voltage and to provide stable electrical contact.
또한, 전류 확산 전극(60) 형성 전에 제2 반도체층(50) 위에 오믹 전극(81)에 대응하여 광흡수 방지막을 형성하는 것을 고려할 수 있다.In addition, before the current diffusion electrode 60 is formed, it may be considered to form a light absorption prevention film on the second semiconductor layer 50 corresponding to the ohmic electrode 81.
다음으로, 전류 확산 전극(60) 위에 비도전성 반사막(91)을 형성한다. 예를 들어, 도전막(60)을 덮는 유전체 막(91b), 분포 브래그 리플렉터(91a) 및 클래드 막(91c)이 형성된다. 유전체 막(91b) 또는 클래드 막(91c)은 생략될 수 있다.Next, a non-conductive reflecting film 91 is formed on the current spreading electrode 60. For example, the dielectric film 91b, the distributed Bragg reflector 91a, and the clad film 91c covering the conductive film 60 are formed. The dielectric film 91b or the clad film 91c may be omitted.
다음으로, 건식 식각 또는 습식 식각, 또는 이들의 조합에 의해 비도전성 반사막(91)에 개구로 이루어진 제1 전기적 연결(82) 및 제2 전기적 연결(72)을 형성한다. 제1 전기적 연결(82) 및 제2 전기적 연결(72)은 각각 제1 오믹 전극(81) 및 제2 오믹 전극(71)에 접촉하게 형성된다.Next, a first electrical connection 82 and a second electrical connection 72 formed of openings in the non-conductive reflective film 91 are formed by dry etching or wet etching, or a combination thereof. The first electrical connection 82 and the second electrical connection 72 are formed to contact the first ohmic electrode 81 and the second ohmic electrode 71, respectively.
제1 전기적 연결(82)은 비도전성 반사막(91), 제2 반도체층(50), 활성층(40) 및 제1 반도체층(30) 일부까지 형성된다. 제2 전기적 연결(72)은 비도전성 반사막(91)을 관통하여 전류 확산 전극(60)의 일부를 노출하도록 형성된다.The first electrical connection 82 is formed up to the non-conductive reflective film 91, the second semiconductor layer 50, the active layer 40, and a portion of the first semiconductor layer 30. The second electrical connection 72 is formed to penetrate the non-conductive reflecting film 91 to expose a portion of the current spreading electrode 60.
제1 전기적 연결(82) 및 제2 전기적 연결(72)은 비도전성 반사막(91) 형성 후에 형성될 수도 있지만, 이와 다르게, 비도전성 반사막(91) 형성 전에 또는 비도전성 반사막(91) 형성 후에 복수의 반도체층(30, 40, 50)에 제1 전기적 연결(82)가 일부 형성되고, 비도전성 반사막(91)이 제1 전기적 연결(82)를 덮도록 형성된 후에, 비도전성 반사막(91)을 관통하는 추가의 공정을 통해 제1 전기적 연결(82)가 형성되고, 추가의 공정과 동시에 또는 다른 공정으로 제2 전기적 연결(72)가 형성될 수 있다.The first electrical connection 82 and the second electrical connection 72 may be formed after the formation of the nonconductive reflecting film 91, but alternatively, a plurality of the first and second electrical connections 82 and 72 may be formed before or after the formation of the nonconductive reflecting film 91. After the first electrical connection 82 is partially formed in the semiconductor layers 30, 40, and 50 of the semiconductor layer 30, the non-conductive reflective film 91 is formed to cover the first electrical connection 82, and then the non-conductive reflective film 91 is formed. The first electrical connection 82 may be formed through additional processing therethrough, and the second electrical connection 72 may be formed concurrently or with another process.
다음으로, 비도전성 반사막(91) 위에 제1 연결 전극(83) 및 제2 연결 전극(73)을 형성한다. 예를 들어, 제1 연결 전극(83) 및 제2 연결 전극(73)은 스퍼터링 장비, E-빔 장비 등을 이용하여 증착 될 수 있다. 제1 연결 전극(83) 및 제2 연결 전극(73)은 안정적 전기적 접촉을 위해 Cr, Ti, Ni 또는 이들의 합금을 사용하여 형성될 수 있으며, Al 또는 Ag와 같은 반사 금속층을 포함할 수도 있다.Next, the first connection electrode 83 and the second connection electrode 73 are formed on the nonconductive reflecting film 91. For example, the first connection electrode 83 and the second connection electrode 73 may be deposited using sputtering equipment, E-beam equipment, or the like. The first connection electrode 83 and the second connection electrode 73 may be formed using Cr, Ti, Ni, or an alloy thereof for stable electrical contact, and may include a reflective metal layer such as Al or Ag. .
제1 연결 전극(83)은 복수의 제1 전기적 연결(82)을 통해 제1 반도체층(30)과 접촉하도록 형성될 수 있고, 제2 연결 전극(73)은 제2 전기적 연결(72)을 통해 전류 확산 전극(60)에 접하도록 형성될 수 있다.The first connection electrode 83 may be formed to contact the first semiconductor layer 30 through the plurality of first electrical connections 82, and the second connection electrode 73 may connect the second electrical connection 72. It may be formed to contact the current diffusion electrode 60 through.
다음으로, 패드 전극(85, 75)에 대응하여 비도전성 반사막(91) 위에 전극 표시부(100)를 형성한다. 전극 표시부(100)는 패드 전극(85, 75)에 대응하여 제1 연결 전극(83) 및 제2 연결 전극(73)이 형성되지 않은 비도전성 반사막(91) 위에 형성된다. 즉, 전극 표시부(100)는 제1 연결 전극(83) 및 제2 연결 전극(73)과 중첩되어 위치하지 않는다. 예를 들어, 도 13(a)에 도시된 바와 같이 제2 연결 전극(73)의 내측에 형성되거나, 도 13(b)에 도시된 바와 같이 제1 연결 전극(83)의 외측에 형성될 수 있다. 하지만, 이에 한정되지 않고, 전극 표시부(100)는 제1 연결 전극(83) 또는 제2 연결 전극(73)과 중첩되지 않는 비도전성 반사막(91) 위에 어디든 위치할 수 있다.Next, the electrode display unit 100 is formed on the nonconductive reflecting film 91 corresponding to the pad electrodes 85 and 75. The electrode display unit 100 is formed on the non-conductive reflective film 91 in which the first connection electrode 83 and the second connection electrode 73 are not formed corresponding to the pad electrodes 85 and 75. That is, the electrode display unit 100 does not overlap with the first connection electrode 83 and the second connection electrode 73. For example, it may be formed inside the second connection electrode 73 as shown in FIG. 13 (a) or may be formed outside the first connection electrode 83 as shown in FIG. 13 (b). have. However, the present invention is not limited thereto, and the electrode display unit 100 may be positioned anywhere on the non-conductive reflective film 91 that does not overlap the first connection electrode 83 or the second connection electrode 73.
이와 다르게, 전극 표시부(100)는 제1 연결 전극(83) 및 제2 연결 전극(73) 형성 전에 형성될 수도 있다. 예를 들어, 도 14(a)에 도시된 바와 같이 제2 연결 전극(73)의 내측에 형성되거나, 도 14(b)에 도시된 바와 같이 제1 연결 전극(83)의 외측에 형성될 수 있다. 하지만, 이에 한정되지 않고, 전극 표시부(100)는 제1 연결 전극(83) 또는 제2 연결 전극(73)과 중첩되지 않는 비도전성 반사막(91) 위에 어디든 위치할 수 있다.Alternatively, the electrode display unit 100 may be formed before forming the first connection electrode 83 and the second connection electrode 73. For example, it may be formed inside the second connection electrode 73 as shown in FIG. 14 (a) or may be formed outside the first connection electrode 83 as shown in FIG. 14 (b). have. However, the present invention is not limited thereto, and the electrode display unit 100 may be positioned anywhere on the non-conductive reflective film 91 that does not overlap the first connection electrode 83 or the second connection electrode 73.
다음으로, 전극 표시부(100), 제1 연결 전극(83) 및 제2 연결 전극(73)을 덮는 절연층(95)을 형성한다. 절연층(95)의 대표적인 물질은 SiO2이며, 이에 제한되지 않고 SiN, TiO2, Al2O3, Su-8 등이 사용될 수도 있다.Next, an insulating layer 95 is formed to cover the electrode display unit 100, the first connection electrode 83, and the second connection electrode 73. Representative material of the insulating layer 95 is SiO 2 , without being limited thereto, SiN, TiO 2 , Al 2 O 3 , Su-8 and the like may be used.
다음으로, 건식 식각 또는 습식 식각, 또는 이들의 조합에 의해 절연층(95)에 개구로 이루어진 제3 전기적 연결(84) 및 제4 전기적 연결(74)을 형성한다. 제3 전기적 연결(84) 및 제4 전기적 연결(74)은 각각 제1 연결 전극(83) 및 제2 연결 전극(73)에 접촉하게 형성된다.Next, a third electrical connection 84 and a fourth electrical connection 74 formed of openings in the insulating layer 95 are formed by dry etching or wet etching, or a combination thereof. The third electrical connection 84 and the fourth electrical connection 74 are formed to contact the first connection electrode 83 and the second connection electrode 73, respectively.
제3 전기적 연결(84) 및 제4 전기적 연결(74)은 절연층(95) 형성 후에 형성될 수도 있지만, 이와 다르게, 절연층(95) 형성 전에 형성될 수도 있다.The third electrical connection 84 and the fourth electrical connection 74 may be formed after the insulating layer 95 is formed, or alternatively, may be formed before the insulating layer 95 is formed.
다음으로, 제1 패드 전극(85) 및 제2 패드 전극(75)은 스터드 범프, 도전성 페이스트, 유테틱 본딩 등의 방법으로 외부(패키지, COB, 서브마운트 등)에 마련된 전극과 전기적으로 연결될 수 있다. 유테틱 본딩의 경우에, 제1 패드 전극(85) 및 제2 패드 전극(75)의 높이 차가 크게 나지 않는 것이 중요하다. 본 예에 따른 반도체 발광소자에 의하면 제1 패드 전극(85) 및 제2 패드 전극(75)이 절연층(95) 위에 동일한 공정에 의해 형성될 수 있으므로 양 전극의 높이 차가 거의 없다. 따라서 유테틱 본딩의 경우에 이점을 가진다. 반도체 발광소자가 유테틱 본딩을 통해 외부와 전기적으로 연결되는 경우에, 제1 패드 전극(85) 및 제2 패드 전극(75)의 최상부는 Au/Sn 합금, Au/Sn/Cu 합금과 같은 유테틱 본딩 물질로 형성될 수 있다.Next, the first pad electrode 85 and the second pad electrode 75 may be electrically connected to an external electrode (package, COB, submount, etc.) by a method such as stud bump, conductive paste, and eutectic bonding. have. In the case of eutectic bonding, it is important that the height difference between the first pad electrode 85 and the second pad electrode 75 is not large. According to the semiconductor light emitting device according to the present example, since the first pad electrode 85 and the second pad electrode 75 can be formed on the insulating layer 95 by the same process, there is almost no height difference between the two electrodes. Thus there is an advantage in the case of eutectic bonding. When the semiconductor light emitting device is electrically connected to the outside through utero bonding, the uppermost portions of the first pad electrode 85 and the second pad electrode 75 are Ute such as Au / Sn alloy and Au / Sn / Cu alloy. It may be formed of a tick bonding material.
도 17은 본 개시에 따른 반도체 발광소자의 일 예를 보여주는 도면이다.17 is a diagram illustrating an example of a semiconductor light emitting device according to the present disclosure.
반도체 발광소자(100)는 기판(110), 복수의 반도체층(130, 140, 150), 투광성 도전막(160), 제1 패드 전극(180) 및 제2 패드 전극(170)을 포함한다.The semiconductor light emitting device 100 may include a substrate 110, a plurality of semiconductor layers 130, 140, and 150, a transparent conductive film 160, a first pad electrode 180, and a second pad electrode 170.
기판(110) 위에 버퍼층(120), 제1 반도체층(130), 활성층(140) 및 제2 반도체층(150)이 순차적으로 형성된다. 예를 들어, 기판(110) 위에 에피성장 되는 반도체층들은 주로 유기금속기상성장법(MOCVD)에 의해 성장되며, 필요에 따라서 각 층들은 다시 세부층들을 포함할 수 있다.The buffer layer 120, the first semiconductor layer 130, the active layer 140, and the second semiconductor layer 150 are sequentially formed on the substrate 110. For example, semiconductor layers epitaxially grown on the substrate 110 are mainly grown by organometallic vapor phase growth (MOCVD), and each layer may further include sublayers as needed.
기판(110)은 주로 사파이어, SiC, Si, GaN 등이 이용되지만, 3족 질화물 반도체층이 성장될 수 있는 기판이라면 어떠한 형태이어도 좋다. 기판(110)은 최종적으로 제거될 수 있다.The substrate 110 is mainly sapphire, SiC, Si, GaN, etc., but may be in any form as long as the group III nitride semiconductor layer can be grown. The substrate 110 may be finally removed.
복수의 반도체층(130, 140, 150)은 기판(10) 위에 형성된 버퍼층(120), 제1 도전성을 가지는 제1 반도체층(130; 예: Si 도핑된 GaN), 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층(150; 예: Mg 도핑된 GaN) 및 제1 반도체층(130)과 제2 반도체층(150) 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층(140; 예: InGaN/(In)GaN 다중양자우물구조)을 포함한다. 복수의 반도체층(130,140,150) 각각은 다층으로 이루어질 수 있고, 버퍼층(20)은 생략될 수 있다.The plurality of semiconductor layers 130, 140, and 150 may include a buffer layer 120 formed on the substrate 10, a first semiconductor layer 130 having a first conductivity (eg, Si-doped GaN), and a second different from the first conductivity. A conductive second semiconductor layer 150 (eg, Mg-doped GaN) and an active layer interposed between the first semiconductor layer 130 and the second semiconductor layer 150 to generate light through recombination of electrons and holes ( 140; for example, InGaN / (In) GaN multi-quantum well structure). Each of the semiconductor layers 130, 140, and 150 may be formed in multiple layers, and the buffer layer 20 may be omitted.
제1 반도체층(130)과 제2 반도체층(150)은 서로 다른 도전성을 갖도록 구비되며, 그 위치가 바뀔 수 있다. 본 개시에서는 제1 반도체층(130)은 n형 질화물 반도체층(130; 예를 들어, n형 GaN층)으로, 제2 반도체층(150)은 p형 질화물 반도체층(150; 예를 들어, p형 GaN층)으로 예를 들어 설명한다.The first semiconductor layer 130 and the second semiconductor layer 150 are provided to have different conductivity, and their positions may be changed. In the present disclosure, the first semiconductor layer 130 is an n-type nitride semiconductor layer 130 (eg, an n-type GaN layer), and the second semiconductor layer 150 is a p-type nitride semiconductor layer 150 (eg, p-type GaN layer), for example.
제2 반도체층(150) 및 활성층(140)은 메사 식각되어 제1 반도체층(130)의 일부가 노출된다. 여기서, 메사 식각의 순서는 변경될 수 있다.The second semiconductor layer 150 and the active layer 140 are mesa-etched to expose a portion of the first semiconductor layer 130. Here, the order of mesa etching may be changed.
투광성 도전막(160)은 제2 패드 전극(170)으로 전류를 확산하는 기능을 수행하여 빛의 균일성을 향상한다. 투광성 도전막(160)은 메사 식각 공정을 통해 형성되는 제1 패드 전극(180)을 제외한 제2 반도체층(150) 위의 거의 대부분을 덮도록 형성된다. 특히, 제2 반도체층(150)이 p형 GaN으로 이루어지는 경우 전류 확산 능력이 떨어지므로, 투광성 도전막(160)이 형성되는 것이 바람직하다.The transparent conductive film 160 performs a function of diffusing current to the second pad electrode 170 to improve uniformity of light. The transmissive conductive layer 160 is formed to cover most of the second semiconductor layer 150 except for the first pad electrode 180 formed through the mesa etching process. In particular, when the second semiconductor layer 150 is made of p-type GaN, the current spreading ability is inferior, and therefore, the transparent conductive film 160 is preferably formed.
일반적으로, 투광성 도전막은 제2 반도체층 위에 동일한 두께를 갖는 하나의 층으로 형성된다. 투광성 도전막이 너무 얇게 형성되는 경우 전류 확산에 불리하여 구동 전압이 높아지고, 너무 두껍게 형성되는 경우 낮은 면저항을 갖지만 낮은 투과율에 의해 광추출 효율이 감소될 수 있다.Generally, the transparent conductive film is formed of one layer having the same thickness on the second semiconductor layer. When the light-transmissive conductive film is formed too thin, the driving voltage increases due to the current diffusion, and when the light-transmissive conductive film is formed too thick, the light extraction efficiency can be reduced by low transmittance, though it has a low sheet resistance.
본 개시에서는 구동 전압에 상관없이 전류 확산이 용이하고 높은 투과율을 가져 광추출 효율일 향상될 수 있도록 투광성 도저막(160)의 두께를 상이하게 형성할 수 있다. 즉, 제2 패드 전극(170)에 대응하여 위치하는 투광성 도전막(160)의 두께를 제2 반도체층(150) 위에 위치하는 투광성 도전막(160)의 두께보다 두껍게 형성할 수 있다. 본 개시에서는, 제2 패드 전극(170)이 위치하는 영역을 제1 영역(A)으로, 제2 패드 전극(170)이 위치하지 않는 나머지 영역을 제2 영역(B)으로 설명한다.In the present disclosure, the thickness of the light-transmitting doser film 160 may be differently formed so that current diffusion is easy and the light transmittance is improved regardless of the driving voltage. That is, the thickness of the transparent conductive film 160 positioned corresponding to the second pad electrode 170 may be greater than the thickness of the transparent conductive film 160 positioned on the second semiconductor layer 150. In the present disclosure, an area where the second pad electrode 170 is located is described as a first area A, and a remaining area where the second pad electrode 170 is not located is described as a second area B. FIG.
구체적으로, 제2 패드 전극(170)에 대응하는 제1 영역(A)에 위치하는 투광성 도전막(160)의 두께(T2)는 제1 영역(A)을 제외한 제2 패드 전극(170)에 대응하지 않는 제2 영역(B)에 위치하는 투광성 도전막(160)의 두께(T1)보다 두껍게 형성되는 것이 바람직하다. 예를 들어, 제1 영역(A)의 두께(T2)는 제2 영역(B)의 두께(T1)보다 최소 2배 이상의 두께를 가질 수 있으므로, 제2 영역(B)의 두께(T1)는 약 600Å이고, 제1 영역(A)의 두께(T2)는 약 1200 ~ 1800Å 인 것이 바람직하다.Specifically, the thickness T2 of the transparent conductive film 160 positioned in the first region A corresponding to the second pad electrode 170 may be formed on the second pad electrode 170 except for the first region A. FIG. It is preferable to be formed thicker than the thickness T1 of the transmissive conductive film 160 positioned in the second region B which does not correspond. For example, since the thickness T2 of the first region A may have a thickness that is at least two times greater than the thickness T1 of the second region B, the thickness T1 of the second region B may be It is preferably about 600 GPa, and the thickness T2 of the first region A is preferably about 1200 to 1800 GPa.
투광성 도전막(160)은 제2 반도체층(150) 위에 위치하는 제1 도전막(161)과 제1 도전막(161) 위에 위치하는 제2 도전막(162)을 포함한다.The transparent conductive layer 160 includes a first conductive layer 161 positioned on the second semiconductor layer 150 and a second conductive layer 162 positioned on the first conductive layer 161.
제1 도전막(161)은 제1 영역(A) 및 제2 영역(B)에 전체적으로 위치하며, 하나의 층으로 형성된다.The first conductive layer 161 is entirely located in the first region A and the second region B and is formed of one layer.
제2 도전막(162)은 제1 영역(A)에만 부분적으로 위치하며, 제1 도전막(161)과 제2 패드 전극(170) 사이에 형성된다.The second conductive layer 162 is partially positioned only in the first region A, and is formed between the first conductive layer 161 and the second pad electrode 170.
제1 도전막(161) 및 제2 도전막(162)은 동일한 물질로 이루어지는 것이 바람직하다. 예를 들어, 제1 도전막(161) 및 제2 도전막(162)은 ITO, Ni/Au와 같은 동일한 물질로 형성될 수 있다.It is preferable that the first conductive film 161 and the second conductive film 162 be made of the same material. For example, the first conductive layer 161 and the second conductive layer 162 may be formed of the same material as ITO and Ni / Au.
제1 도전막(161)의 두께(T1)는 제2 도전막(162)의 두께(T2)와 동일한 두께를 갖는 것이 바람직하지만, 이에 한정하지 않고 제2 도전막(162)의 두께(T2)보다 크거나 작은 두께를 가질 수 있다. 예를 들어, 제1 도전막(161) 및 제2 도전막(162)의 두께(T1, T2)는 각각 약 600Å~ 1200Å 로 형성되는 것이 바람직하다.Although the thickness T1 of the first conductive film 161 preferably has the same thickness as the thickness T2 of the second conductive film 162, the thickness T2 of the second conductive film 162 is not limited thereto. It may have a larger or smaller thickness. For example, the thicknesses T1 and T2 of the first conductive film 161 and the second conductive film 162 are preferably about 600 kPa to 1200 kPa, respectively.
제2 도전막(162)의 폭(W2)은 제1 도전막(161)의 폭(W1) 보다 작게 형성되고, 제2 패드 전극(170)의 폭과 동일하거나 넓게 형성될 수 있다.The width W2 of the second conductive layer 162 may be smaller than the width W1 of the first conductive layer 161 and may be the same as or wider than the width of the second pad electrode 170.
제1 패드 전극(180)은 메사 식각되어 노출된 제1 반도체층(130) 위에 형성되고, 제2 패드 전극(170)는 투광성 도전막(160) 위에 형성된다. 본 개시에서 제1 패드 전극(180)은 제1 반도체층(130)과 전기적으로 연결되는 n측 패드 전극(180)으로, 제2 패드 전극(170)은 제2 반도체층(150)과 연결되는 n측 패드 전극(170)으로 예를 들어 설명한다. 제1 패드 전극(180)은 상기 설명에서 제1 전극에 대응하고, 제2 패드 전극(170)은 상기 설명에서 제2 전극에 대응할 수 있다. 반대로 제1 패드 전극(180)은 상기 설명에서 제1 전극에 대응하고, 제2 패드 전극(170)은 상기 설명에서 제1 전극에 대응할 수 있다.The first pad electrode 180 is formed on the first semiconductor layer 130 exposed by mesa etching, and the second pad electrode 170 is formed on the transparent conductive layer 160. In the present disclosure, the first pad electrode 180 is an n-side pad electrode 180 electrically connected to the first semiconductor layer 130, and the second pad electrode 170 is connected to the second semiconductor layer 150. For example, the n-side pad electrode 170 will be described. The first pad electrode 180 may correspond to the first electrode in the above description, and the second pad electrode 170 may correspond to the second electrode in the above description. In contrast, the first pad electrode 180 may correspond to the first electrode in the above description, and the second pad electrode 170 may correspond to the first electrode in the above description.
제1 패드 전극(180) 및 제2 패드 전극(170)은 니켈, 크롬 및 금을 적층하여 형성될 수 있다.The first pad electrode 180 and the second pad electrode 170 may be formed by stacking nickel, chromium, and gold.
이하, 반도체 발광소자(100)의 제조 방법을 살펴보면 다음과 같다.Hereinafter, a method of manufacturing the semiconductor light emitting device 100 will be described.
반도체 발광소자(100)의 제조 방법에 있어서, 우선 기판(110) 위에 제1 버퍼층(120), 제1 반도체층(130), 활성층(140) 및 제2 반도체층(150)을 형성한 후, 메사(mesa) 형태로 제2 반도체층(150) 및 활성층(140)을 식각하여 제1 반도체층(130)을 노출한다. 여러 개의 반도체층을 제거하는 방법으로 건식식각 방법, 예를 들어 ICP(Inductively Coupled Plasma)이 사용될 수 있다.In the method of manufacturing the semiconductor light emitting device 100, first, the first buffer layer 120, the first semiconductor layer 130, the active layer 140, and the second semiconductor layer 150 are formed on the substrate 110. The second semiconductor layer 150 and the active layer 140 are etched in a mesa form to expose the first semiconductor layer 130. As a method of removing a plurality of semiconductor layers, a dry etching method, for example, an inductively coupled plasma (ICP) may be used.
다음으로, 스퍼터링(Sputtering)법, 전자빔 증작법(E-beam Evaporation), 열증착법 등을 이용하여 제2 반도체층(150)의 전면 위에 전체적으로 제1 도전막(161)을 형성한다.Next, the first conductive layer 161 is formed on the entire surface of the second semiconductor layer 150 by using a sputtering method, an E-beam evaporation method, a thermal evaporation method, or the like.
다음으로, 스퍼터링(Sputtering)법, 전자빔 증작법(E-beam Evaporation), 열증착법 등을 이용하여 제2 패드 전극(170)이 형성될 부분에 대응되는 제1 도전막(161) 위의 일부에 제2 도전막(162)을 부분적으로 형성한다. 여기서, 제2 도전막(162)은 제1 도전막(161)과 동일한 물질 및 동일한 두께로 형성될 수 있지만, 이에 한정하지 않는다.Next, a part of the first conductive layer 161 corresponding to the portion where the second pad electrode 170 is to be formed is formed by using a sputtering method, an E-beam evaporation method, a thermal evaporation method, or the like. The second conductive film 162 is partially formed. Here, the second conductive layer 162 may be formed of the same material and the same thickness as the first conductive layer 161, but is not limited thereto.
다음으로, 스퍼터링(Sputtering)법, 전자빔 증작법(Ebeam Evaporation), 열증착법 등의 방법을 이용하며, 제1 패드 전극(180) 및 제2 패드 전극(170)을 형성한다.Next, the first pad electrode 180 and the second pad electrode 170 are formed by using a method such as a sputtering method, an electron beam evaporation method, a thermal evaporation method, or the like.
한편, 제2 도전막(162)은 제1 도전막(161)의 위 전체면에 형성된 후, 별도의 식각 공정을 통해 제2 패드 전극(170)이 형성될 부분에 대응되는 제1 영역(A)만 위치할 수 있다.Meanwhile, after the second conductive layer 162 is formed on the entire surface of the first conductive layer 161, the first region A corresponding to a portion where the second pad electrode 170 is to be formed through a separate etching process. ) Can only be located.
이와 달리, 투광성 도전막(160)을 제1 도전막(161) 및 제2 도전막(162)을 합한 두께와 동일한 두께로 제2 반도체층(150)의 전면 위에 전체적으로 형성한 후, 별도의 식각 공정을 통해 제2 패드 전극(170)에 대응하는 부분을 제외한 투광성 도전막(160)의 일부를 노출시킬 수 있다. 이에 따라 식각에 의해 노출된 투광성 도전막(160)의 두께는 제2 패드 전극(170)에 대응되는 투광성 도전막(160)의 두께보다 작게 형성될 수 있다.On the contrary, the light-transmissive conductive layer 160 is formed on the entire surface of the second semiconductor layer 150 to have the same thickness as the sum of the first conductive layer 161 and the second conductive layer 162. Through the process, a portion of the transparent conductive film 160 except for the portion corresponding to the second pad electrode 170 may be exposed. Accordingly, the thickness of the transparent conductive layer 160 exposed by etching may be smaller than the thickness of the transparent conductive layer 160 corresponding to the second pad electrode 170.
본 개시에 따른 반도체 발광소자의 제조방법의 순서는 당업자가 용이하게 변경할 수 있는 범위에서는 본 개시의 범위에 포함될 수 있다. The order of the manufacturing method of the semiconductor light emitting device according to the present disclosure may be included in the scope of the present disclosure in a range that can be easily changed by those skilled in the art.
도 18은 본 개시에 따른 반도체 발광소자의 다른 예를 보여주는 도면이다.18 illustrates another example of the semiconductor light emitting device according to the present disclosure.
반도체 발광소자(200)는 보호막(201)을 포함한다.The semiconductor light emitting device 200 includes a protective film 201.
보호막(201)은 반도체 발광소자(200)를 보호하기 위해 복수의 반도체층(230, 240, 250)의 측면 및 상면, 그리고 투광성 도전막(260), 제1 및 제2 패드 전극(280, 270)의 상면 일부분을 덮도록 형성된다. 보호막(201)이 제1 반도체층(230) 및 제2 반도체층(250) 위의 모든 영역을 반드시 덮을 필요는 없다. 여기서, 투광성 도전막(260)은 제2 반도체층(250) 위에 위치하는 제1 도전막(261)과 제1 도전막(261) 위에 위치하는 제2 도전막(262)을 포함한다.The passivation layer 201 may include side and top surfaces of the semiconductor layers 230, 240, and 250, and the transparent conductive layer 260 and the first and second pad electrodes 280 and 270 to protect the semiconductor light emitting device 200. It is formed to cover a portion of the top surface. The protective film 201 does not necessarily cover all regions on the first semiconductor layer 230 and the second semiconductor layer 250. The light-transmissive conductive film 260 includes a first conductive film 261 positioned on the second semiconductor layer 250 and a second conductive film 262 positioned on the first conductive film 261.
보호막(201)은 SiO2, TiO2, SiNx, DBR 등과 같은 물질로 형성될 수 있으며, 생략될 수도 있다.The protective film 201 may be formed of a material such as SiO 2 , TiO 2 , SiNx, DBR, or the like, and may be omitted.
보호막(201)은 투광성 도전막(260)의 제2 도전막(262)과 동시에 형성될 수도 있다.The protective film 201 may be formed simultaneously with the second conductive film 262 of the transparent conductive film 260.
본 개시에 따른 반도체 발광소자의 제조방법의 순서는 당업자가 용이하게 변경할 수 있는 범위에서는 본 개시의 범위에 포함될 수 있다.The order of the manufacturing method of the semiconductor light emitting device according to the present disclosure may be included in the scope of the present disclosure in a range that can be easily changed by those skilled in the art.
도 18에 기재된 보호막(201)을 제외하고는 도 17에 기재된 반도체 발광소자(100)와 동일한 특성을 갖는다.Except for the protective film 201 of FIG. 18, the semiconductor light emitting device 100 has the same characteristics as the semiconductor light emitting device 100 of FIG. 17.
도 19는 본 개시에 따른 반도체 발광소자의 또 다른 예를 보여주는 도면이다.19 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
반도체 발광소자(300)는 빛흡수 방지막(390)을 포함한다.The semiconductor light emitting device 300 includes a light absorption prevention film 390.
투광성 도전막(360)은 빛흡수 방지막(390)을 덮으며, 제2 패드 전극(370)으로 전류를 확산하는 기능을 수행하여 빛의 균일성을 향상한다. 여기서, 투광성 도전막(360)은 제2 반도체층(350) 및 빛흡수 방지막(390) 위에 위치하는 제1 도전막(361)과 제1 도전막(361) 위에 위치하는 제2 도전막(362)을 포함한다.The transparent conductive film 360 covers the light absorption prevention film 390 and performs a function of diffusing current to the second pad electrode 370 to improve uniformity of light. The translucent conductive film 360 may include the first conductive film 361 disposed on the second semiconductor layer 350 and the light absorption prevention film 390, and the second conductive film 362 disposed on the first conductive film 361. ).
이에, 빛흡수 방지막(390)은 투광성 도전막(360)의 제1 도전막(361)과 제2 반도체층(350) 사이에 개재된다. 빛흡수 방지막(390)은 제2 패드 전극(370)에 대응되는 위치 즉, 제1 영역(A)의 제2 반도체층(350) 위에 형성된다.Accordingly, the light absorption prevention layer 390 is interposed between the first conductive layer 361 and the second semiconductor layer 350 of the transparent conductive layer 360. The light absorption prevention layer 390 is formed on a position corresponding to the second pad electrode 370, that is, on the second semiconductor layer 350 in the first region A. FIG.
빛흡수 방지막(390)은 활성층(340)에서 발생된 빛의 일부 또는 전부를 반사하여 투광성 도전막(360)에서의 빛 흡수를 방지한다. 또한 빛흡수 방지막(390)은 제2 패드 전극(370)의 바로 아래로 전류가 흐르지 못하도록 하는 기능(current blocking)을 가질 수 있다. 빛흡수 방지막(390)은 생략될 수 있다.The light absorption prevention layer 390 reflects some or all of the light generated from the active layer 340 to prevent light absorption from the transparent conductive layer 360. In addition, the light absorption prevention layer 390 may have a function of preventing current from flowing directly under the second pad electrode 370. The light absorption prevention layer 390 may be omitted.
빛흡수 방지막(390)은 제2 반도체층(350)보다 굴절률이 낮은 투광성 물질로 된 단일층(예: SiO2), 다층막(예: Si02/TiO2/SiO2), 분포 브래그 리플렉터, 단일층과 분포 브래그 리플렉터의 결합 등으로 이루어질 수 있다. 또한 빛흡수 방지막(390)은 비도전성 물질(예: SiOx, TiOx와 같은 유전체 막)로 이루어질 수 있다.The light absorption prevention layer 390 is a single layer (eg, SiO 2 ), a multilayer (eg, Si0 2 / TiO 2 / SiO 2 ), a distributed Bragg reflector, or a single layer made of a light transmissive material having a lower refractive index than the second semiconductor layer 350. Or a combination of a layer and a distributed Bragg reflector. In addition, the light absorption prevention layer 390 may be made of a non-conductive material (eg, a dielectric film such as SiOx or TiOx).
도 19에 기재된 빛흡수 방지막(390)을 제외하고는 도 17에 기재된 반도체 발광소자(100)와 동일한 특성을 갖는다.Except for the light absorption prevention film 390 illustrated in FIG. 19, the semiconductor light emitting diode 100 has the same characteristics as the semiconductor light emitting device 100 illustrated in FIG. 17.
도 20은 본 개시에 따른 반도체 발광소자의 또 다른 예를 보여주는 도면이다.20 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
반도체 발광소자(400)는 빛흡수 방지막(490) 및 빛흡수 차단막(492)을 포함한다.The semiconductor light emitting device 400 may include a light absorption prevention layer 490 and a light absorption blocking layer 492.
투광성 도전막(460)은 빛흡수 방지막(490) 및 빛흡수 차단막(492)을 덮으며, 제2 패드 전극(470)으로 전류를 확산하는 기능을 수행하여 빛의 균일성을 향상한다. 여기서, 투광성 도전막(460)은 제2 반도체층(450), 빛흡수 방지막(490) 및 빛흡수 차단막(492) 위에 위치하는 제1 도전막(461)과 제1 도전막(461) 위에 위치하는 제2 도전막(462)을 포함한다.The transparent conductive film 460 covers the light absorption prevention film 490 and the light absorption blocking film 492, and performs a function of diffusing current to the second pad electrode 470 to improve uniformity of light. Here, the transparent conductive film 460 is positioned on the first conductive film 461 and the first conductive film 461 positioned on the second semiconductor layer 450, the light absorption prevention film 490, and the light absorption blocking film 492. The second conductive film 462 is included.
이에 따라, 제1 도전막(461)과 제2 반도체층(450) 사이에 빛흡수 방지막(490) 및 빛흡수 차단막(492)이 개재된다.Accordingly, the light absorption prevention film 490 and the light absorption blocking film 492 are interposed between the first conductive film 461 and the second semiconductor layer 450.
빛흡수 방지막(490)은 제1 도전막(461)과 제2 반도체층(450) 사이에 개재된다. 빛흡수 방지막(490)은 제2 패드 전극(470)에 대응되는 위치 즉, 제1 영역(A)의 제2 반도체층(450) 위에 형성된다.The light absorption prevention film 490 is interposed between the first conductive film 461 and the second semiconductor layer 450. The light absorption prevention layer 490 is formed on the position corresponding to the second pad electrode 470, that is, on the second semiconductor layer 450 in the first region A. FIG.
빛흡수 차단막(492)은 제1 도전막(461)과 빛흡수 방지막(490) 사이에 개재된다. 빛흡수 차단막(492)은 제2 패드 전극(470)에 대응되는 위치 즉, 제1 영역(A)의 빛흡수 방지막(490) 위에 형성된다.The light absorption blocking film 492 is interposed between the first conductive film 461 and the light absorption prevention film 490. The light absorption blocking layer 492 is formed on a position corresponding to the second pad electrode 470, that is, on the light absorption prevention layer 490 in the first region A. FIG.
빛흡수 차단막(492)은 빛흡수 방지막(490)에 의해 반사되지 못하고 빛흡수 방지막(490)을 통과한 빛을 차단한다. 한편, 빛흡수 차단막(492)은 가지 전극으로도 기능할 수 있다.The light absorption blocking layer 492 blocks light that is not reflected by the light absorption prevention layer 490 and passes through the light absorption prevention layer 490. On the other hand, the light absorption blocking film 492 may also function as a branch electrode.
이에 본개시에서는 빛흡수 차단막(492)을 제1 도전막(461)과 빛흡수 방지막(490) 사이에 배치함으로써, 투광성 도전막(460)에서 발생하는 빛흡수를 차단하여 반도체 발광소자의 광 추출 효율(extraction efficiency)을 향상시킬 수 있다.Accordingly, in the present disclosure, the light absorption blocking film 492 is disposed between the first conductive film 461 and the light absorption preventing film 490 to block light absorption generated from the transparent conductive film 460 to extract light from the semiconductor light emitting device. It is possible to improve the extraction efficiency.
빛흡수 차단막(492)은 빛흡수 방지막(490)과 서로 다른 물질로 이루어지는 것이 바람직하다.The light absorption barrier layer 492 may be formed of a material different from that of the light absorption barrier layer 490.
빛흡수 차단막(492)은 빛을 반사하는 효율이 높아 반사성이 우수하고 전기적인 접촉이 우수한 금속성 물질, 예를 들어, 금속성 물질에는 은(Ag), 알루미늄(Al), 분포 브래그 리플렉터(DBR: Distributed Bragg Reflector), 고반사 백색 반사물질 등으로 될 수 있다. 하지만, 비용 및 효율을 고려했을 때 알루미늄(Al)이 바람직하다.The light absorption barrier layer 492 has a high reflectivity and a high reflectivity and a good electrical contact. For example, the metallic material may be silver (Ag), aluminum (Al), or distributed Bragg reflector (DBR). Bragg Reflector), highly reflective white reflector, and the like. However, aluminum (Al) is preferred in view of cost and efficiency.
빛흡수 방지막(490)이 SiOx로 이루어지고, 빛흡수 차단막(492)이 알루미늄(Al)으로 이루어지는 경우 접합력을 증가시키면서 제조 비용을 절감할 수 있다.When the light absorption prevention film 490 is made of SiOx and the light absorption blocking film 492 is made of aluminum (Al), the manufacturing cost can be reduced while increasing the bonding force.
빛흡수 방지막(490)의 두께(T3)와 빛흡수 차단막(492)의 두께(T4)는 서로 동일하게 형성되는 것이 바람직하다. 하지만, 이에 한정되지 않고 빛흡수 방지막(490)의 두께(T3)는 빛흡수 차단막(492)의 두께(T4) 보다 크게 또는 작게 형성될 수 있다.The thickness T3 of the light absorption prevention film 490 and the thickness T4 of the light absorption blocking film 492 are preferably formed to be the same. However, the present invention is not limited thereto, and the thickness T3 of the light absorption prevention layer 490 may be larger or smaller than the thickness T4 of the light absorption blocking layer 492.
본 예에서, 빛흡수 방지막(490)의 두께(T3)와 빛흡수 차단막(492)의 두께(T4)는 약 1000Å 이상, 약 6000Å 이하인 것이 바람직하다.In this example, the thickness T3 of the light absorption prevention film 490 and the thickness T4 of the light absorption blocking film 492 are preferably about 1000 GPa or more and about 6000 GPa or less.
빛흡수 방지막(490) 및 빛흡수 차단막(492)의 두께(T3, T4)가 1000Å 이하인 경우, 두께가 너무 얇아 빛 흡수에 대한 방지 및 차단 기능을 원활히 수행할 수 없고, 빛흡수 방지막(490) 및 빛흡수 차단막(492)의 두께(T3, T4)가 6000Å 이상인 경우 빛흡수 차단막(492) 위에 증착되는 투광성 도전막(460)의 증착이 어려워질 수 있다.When the thicknesses T3 and T4 of the light absorption prevention film 490 and the light absorption blocking film 492 are 1000 Å or less, the thickness is too thin to prevent the light absorption and blocking function smoothly, and the light absorption prevention film 490 And when the thickness (T3, T4) of the light absorption blocking film 492 is 6000 Å or more, it may be difficult to deposit the transparent conductive film 460 deposited on the light absorption blocking film 492.
빛흡수 방지막(490) 및 빛흡수 차단막(492)은 제2 패드 전극(470)에 대응하여 형성된다. 빛흡수 방지막(490) 및 빛흡수 차단막(492)은 제2 패드 전극(470) 아래에 섬 형태로 형성될 수 있다지만, 이에 한정되지 않는다.The light absorption prevention film 490 and the light absorption blocking film 492 are formed to correspond to the second pad electrode 470. The light absorption prevention layer 490 and the light absorption blocking layer 492 may be formed in an island shape under the second pad electrode 470, but are not limited thereto.
빛흡수 방지막(490)은 폭(W3)은 제2 패드 전극(470)의 폭과 동일하거나 넓게 형성될 수 있다.The light absorption prevention layer 490 may have a width W3 equal to or wider than that of the second pad electrode 470.
빛흡수 차단막(492)의 폭(W4)은 빛흡수 방지막(490)의 폭(W3)과 동일하거나 작게 형성될 수 있다. 또한 빛흡수 차단막(492)의 폭(W4)은 제2 패드 전극(470)의 폭과 동일하거나 넓게 형성될 수 있다.The width W4 of the light absorption blocking film 492 may be the same as or smaller than the width W3 of the light absorption blocking film 490. In addition, the width W4 of the light absorption blocking layer 492 may be the same as or wider than the width of the second pad electrode 470.
빛흡수 방지막(490) 및 빛흡수 차단막(492)의 폭(W3, W4)이 제2 패드 전극(470)의 폭보다 넓게 형성되는 경우 전류가 차단되는 영역이 너무 커져서 소자의 효율이 떨어질 수 있으며, 또한 활성층(440)에서 생성되어 빛흡수 방지막(490) 및 빛흡수 차단막(492)으로 입사된 빛이 필요 이상으로 복수의 반도체층 쪽으로 재반사 될수 있다. 이에 반해, 빛흡수 방지막(490) 및 빛흡수 차단막(492)의 폭(W3, W4)이 제2 패드 전극(470)의 폭보다 작게 형성되는 경우 제2 패드 전극(470)으로 입사하는 빛을 효과적으로 반사하지 못한다. 이에 따라, 빛흡수 방지막(490) 및 빛흡수 차단막(492)의 폭(W3, W4)은 제2 패드 전극(470)의 폭과 동일하거나 넓게 형성되는 것이 바람직하다.When the widths W3 and W4 of the light absorption prevention film 490 and the light absorption blocking film 492 are formed to be wider than the width of the second pad electrode 470, a region in which current is blocked may become too large to reduce the efficiency of the device. In addition, light generated by the active layer 440 and incident on the light absorption prevention layer 490 and the light absorption blocking layer 492 may be reflected back toward the plurality of semiconductor layers more than necessary. On the contrary, when the widths W3 and W4 of the light absorption prevention film 490 and the light absorption blocking film 492 are smaller than the width of the second pad electrode 470, the light incident to the second pad electrode 470 is emitted. It does not reflect effectively. Accordingly, the widths W3 and W4 of the light absorption prevention film 490 and the light absorption blocking film 492 may be the same as or wider than the width of the second pad electrode 470.
도 20에 기재된 빛흡수 방지막(490) 및 빛흡수 차단막(492)을 제외하고는 도 17에 기재된 반도체 발광소자(100)와 동일한 특성을 갖는다.Except for the light absorption prevention film 490 and the light absorption blocking film 492 illustrated in FIG. 20, the semiconductor light emitting device 100 has the same characteristics as the semiconductor light emitting device 100 illustrated in FIG. 17.
도 21은 본 개시에 따른 반도체 발광소자의 또 다른 예를 보여주는 도면이다.21 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
반도체 발광소자(500)는 빛흡수 방지막(590) 및 금속층(5920)과 부도체층(5921)을 포함하는 빛흡수 차단막(592)을 포함한다.The semiconductor light emitting device 500 includes a light absorption blocking layer 590 and a light absorption blocking layer 592 including a metal layer 5920 and a non-conductive layer 5921.
빛흡수 방지막(590)은 제2 반도체층(550) 위에 위치하고, 빛흡수 차단막(592)은 빛흡수 방지막(590)과 투광서 도전막(560) 사이에 위치합니다. 여기서, 투광성 도전막(560)은 제2 반도체층(550), 빛흡수 방지막(590) 및 빛흡수 차단막(592) 위에 위치하는 제1 도전막(561)과 제1 도전막(561) 위에 위치하는 제2 도전막(562)을 포함한다.The light absorption prevention layer 590 is positioned on the second semiconductor layer 550, and the light absorption blocking layer 592 is positioned between the light absorption prevention layer 590 and the light transmission conductive layer 560. Here, the transparent conductive film 560 is positioned on the first conductive film 561 and the first conductive film 561 on the second semiconductor layer 550, the light absorption prevention film 590, and the light absorption blocking film 592. A second conductive film 562 is included.
금속층(5920)은 빛흡수 방지막(590)의 상면에 위치하며, 빛흡수 방지막(590)과의 접합력을 높이면서 빛흡수를 차단하기 위해 반사율이 높으며 전기적인 접촉이 우수한 금속성 물질로 이루어질 수 있다. 예를 들어, 금속층(5920)은 은(Ag), 알루미늄(Al), 분포 브래그 리플렉터(DBR: Distributed Bragg Reflector), 고반사 백색 반사물질 등으로 될 수 있다. 하지만, 비용 및 효율을 고려했을 때 알루미늄(Al)이 바람직하다.The metal layer 5920 is positioned on an upper surface of the light absorption prevention layer 590, and may be formed of a metallic material having high reflectance and excellent electrical contact to block light absorption while increasing bonding force with the light absorption prevention layer 590. For example, the metal layer 5920 may be made of silver (Ag), aluminum (Al), a distributed Bragg reflector (DBR), a highly reflective white reflector, or the like. However, aluminum (Al) is preferred in view of cost and efficiency.
금속층(5920)은 PECVD(Plasma Enhanced Chemical Vapor Deposition), LPCVD(Low Pressure Chemical Vapor Deposition), sputtering, E-beam evaporation, thermal evaportation 등을 이용하여 빛흡수 방지막(590) 위에 형성될 수 있다.The metal layer 5920 may be formed on the light absorption prevention layer 590 by using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, e-beam evaporation, thermal evaportation, or the like.
부도체층(5921)은 금속층(5920) 위에 위치하며 즉, 금속층(5920)과 투광성 도전막(560)의 제1 도전막(561) 사이에 개재된다.The non-conductor layer 5921 is positioned on the metal layer 5920, that is, interposed between the metal layer 5920 and the first conductive film 561 of the transparent conductive film 560.
부도체층(5921)은 금속층(5920)의 표면을 아노다이징하는 방식으로 형성되거나, 금속층(5920)의 표면에 절연물질을 증착하는 방식으로 형성될 수 있다.The nonconductive layer 5921 may be formed by anodizing the surface of the metal layer 5920 or by depositing an insulating material on the surface of the metal layer 5920.
예를 들어, 금속층(5920)의 재질이 Al로 이루어지고 아노다이징을 통해 금속층(5920)을 표면 처리할 경우, 부도체층(5921)은 산화알루미늄막(Al2O3)으로 이루어질 수 있다. 또한, 부도체층(5921)은 증착을 통해 형성되는 SiO2, TiO2, SiN, SiON, Al2O3 및 Ta2O5 막 중 어느 하나일 수도 있다.For example, when the material of the metal layer 5920 is made of Al and the metal layer 5920 is surface-treated through anodizing, the nonconductive layer 5921 may be made of an aluminum oxide film (Al 2 O 3 ). In addition, the insulator layer 5921 may be any one of SiO 2 , TiO 2 , SiN, SiON, Al 2 O 3, and Ta 2 O 5 films formed through deposition.
금속층(5920)과 투광성 도전막(560)의 제1 도전막(561) 사이에 부도체층(5921)이 위치함으로써, 투광성 도전막(560)과 전기적으로 절연시켜 안정적인 절연 상태를 유지할 수 있다. 더욱이, 부도체층(5921)으로 인해 금속층(5920)과 투광성 도전막(560) 사이의 절연 상태를 안정적을 유지하면서 전류 확산을 향상할 수 있다.The nonconductive layer 5921 is positioned between the metal layer 5920 and the first conductive film 561 of the transparent conductive film 560 to electrically insulate the transparent conductive film 560 to maintain a stable insulating state. In addition, the insulator layer 5921 may improve current spreading while maintaining a stable state of insulation between the metal layer 5920 and the transparent conductive film 560.
도 21에 기재된 빛흡수 방지막(590) 및 금속층(5920)과 부도체층(5921)을 포함하는 빛흡수 차단막(592)을 제외하고는 도 17에 기재된 반도체 발광소자(100)와 동일한 특성을 갖는다.It has the same characteristics as the semiconductor light emitting device 100 of FIG. 17 except for the light absorption blocking film 590 and the light absorption blocking film 592 including the metal layer 5920 and the insulator layer 5921 shown in FIG. 21.
도 22은 본 개시에 따른 반도체 발광소자의 또 다른 예를 보여주는 도면이다.22 illustrates another example of the semiconductor light emitting device according to the present disclosure.
반도체 발광소자(600)는 비도전성 반사막(602)을 포함한다.The semiconductor light emitting device 600 includes a nonconductive reflecting film 602.
비도전성 반사막(602)은 식각되어 노출된 복수의 반도체층(630, 640, 650)의 측면 및 상면, 그리고 투광성 도전막(660)의 제1 도전막(661) 및 제2 도전막(662), 제1 및 제2 패드 전극(680, 670)의 상면 일부분을 덮도록 형성된다. 비도전성 반사막(602)이 제1 반도체층(630) 및 제2 반도체층(650) 위의 모든 영역을 반드시 덮을 필요는 없다. 비도전성 반사막(602)은 반사막으로 기능하되, 빛의 흡수를 방지하도록 투광성 물질로 형성되는 것이 바람직하다.The non-conductive reflecting film 602 is a side surface and an upper surface of the etched and exposed semiconductor layers 630, 640, 650, and the first conductive film 661 and the second conductive film 662 of the transparent conductive film 660. The first and second pad electrodes 680 and 670 may be formed to cover portions of the top surface of the first and second pad electrodes 680 and 670. The non-conductive reflecting film 602 does not necessarily cover all regions on the first semiconductor layer 630 and the second semiconductor layer 650. The non-conductive reflecting film 602 functions as a reflecting film but is preferably formed of a light transmitting material to prevent absorption of light.
비도전성 반사막(602)은 단일의 유전체층(예: SiOx, TiOx, Ta2O5, MgF2와 같은 투광성 유전체 물질)으로 이루어질 수도 있고, 다층 구조를 가질 수도 있다. 다층 구조의 일 예로, 비도전성 반사막(602)은 순차로 적층된 유전체막, 분포 브래그 리플렉터(Distributed Bragg Reflector; 예: SiO2와 TiO2의 조합으로 된 DBR) 및 클래드막을 포함할 수 있다.The nonconductive reflecting film 602 may be made of a single dielectric layer (eg, a transparent dielectric material such as SiOx, TiOx, Ta 2 O 5 , MgF 2 ), or may have a multilayer structure. As an example of the multilayer structure, the non-conductive reflective film 602 may include a dielectric film sequentially stacked, a distributed Bragg reflector (eg, a DBR made of a combination of SiO 2 and TiO 2 ) and a clad film.
비도전성 반사막(602)이 SiOx로 이루어지는 경우에, 제2 반도체층(650; 예: GaN)에 비해 낮은 굴절률을 가지므로, 임계각 이상의 입사각을 가진 빛을 복수의 반도체층(630, 640, 650) 측으로 일부 반사할 수 있게 된다.When the non-conductive reflecting film 602 is made of SiOx, since the non-conductive reflecting film 602 has a lower refractive index than the second semiconductor layer 650 (for example, GaN), light having an incident angle greater than or equal to a critical angle is provided in the plurality of semiconductor layers 630, 640, and 650. Some reflections can be made to the side.
한편, 비도전성 반사막(91)이 분포 브래그 리플렉터(DBR: Distributed Bragg Reflector; 예: SiO2와 TiO2의 조합으로 된 DBR)로 이루어지면 더 많은 양의 빛을 복수의 반도체층(630, 640, 650) 측으로 반사할 수 있다.On the other hand, when the non-conductive reflecting film 91 is made of a distributed Bragg reflector (DBR: DBR made of a combination of SiO 2 and TiO 2 ), a greater amount of light may be applied to the plurality of semiconductor layers 630, 640, and the like. 650) to the side.
도 22에 기재된 비도전성 반사막(602)을 제외하고는 도 17에 기재된 반도체 발광소자(100)와 동일한 특성을 갖는다.Except for the non-conductive reflecting film 602 shown in FIG. 22, it has the same characteristics as the semiconductor light emitting device 100 shown in FIG.
도 24 및 도 25는 본 개시에 따른 반도체 발광소자의 일 예를 보여주는 도면이다.24 and 25 illustrate an example of a semiconductor light emitting device according to the present disclosure.
도 24는 평면도이며, 도 25(a)는 AA'에 따른 단면도이고, 도 25(b)는 A의 상세 단면도이다.FIG. 24 is a plan view, FIG. 25A is a sectional view taken along AA ′, and FIG. 25B is a detailed sectional view of A. FIG.
반도체 발광소자(100)는 기판(110), 복수의 반도체층(130, 140, 150), 빛흡수 방지막(190), 빛흡수 차단막(192), 투광성 도전막(160), 제1 패드 전극(180) 및 제2 패드 전극(170)을 포함한다. 이하, 3족 질화물 반도체 발광소자를 예로 하여 설명한다.The semiconductor light emitting device 100 may include a substrate 110, a plurality of semiconductor layers 130, 140, and 150, a light absorption prevention film 190, a light absorption blocking film 192, a transparent conductive film 160, and a first pad electrode ( 180 and a second pad electrode 170. Hereinafter, the group III nitride semiconductor light emitting element will be described as an example.
여기서, 3족 질화물 반도체 발광소자는 Al(x)Ga(y)In(1-x-y)N (0≤x≤1, 0≤y≤1, 0≤x+y=1)로 된 3족 질화물 반도체층을 포함하는 발광다이오드와 같은 발광소자를 의미하며, 추가적으로 SiC, SiN, SiCN, CN와 같은 다른 족(group)의 원소들로 이루어진 물질이나 이들 물질로 된 반도체층을 포함하는 것을 배제하는 것은 아니다.Here, the group III nitride semiconductor light emitting device is a group III nitride of Al (x) Ga (y) In (1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y = 1). Means a light emitting device such as a light emitting diode including a semiconductor layer, and additionally excludes the inclusion of a material consisting of elements of other groups such as SiC, SiN, SiCN, CN or a semiconductor layer made of these materials. no.
기판(110) 위에 버퍼층(120), 제1 반도체층(130), 활성층(140) 및 제2 반도체층(150)이 순차적으로 형성된다. 예를 들어, 기판(110) 위에 에피성장 되는 반도체층들은 주로 유기금속기상성장법(MOCVD)에 의해 성장되며, 필요에 따라서 각 층들은 다시 세부층들을 포함할 수 있다.The buffer layer 120, the first semiconductor layer 130, the active layer 140, and the second semiconductor layer 150 are sequentially formed on the substrate 110. For example, semiconductor layers epitaxially grown on the substrate 110 are mainly grown by organometallic vapor phase growth (MOCVD), and each layer may further include sublayers as needed.
기판(110)은 주로 사파이어, SiC, Si, GaN 등이 이용되지만, 3족 질화물 반도체층이 성장될 수 있는 기판이라면 어떠한 형태이어도 좋다. 기판(110)은 최종적으로 제거될 수 있다.The substrate 110 is mainly sapphire, SiC, Si, GaN, etc., but may be in any form as long as the group III nitride semiconductor layer can be grown. The substrate 110 may be finally removed.
복수의 반도체층(130, 140, 150)은 기판(10) 위에 형성된 버퍼층(120), 제1 도전성을 가지는 제1 반도체층(130; 예: Si 도핑된 GaN), 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층(150; 예: Mg 도핑된 GaN) 및 제1 반도체층(130)과 제2 반도체층(150) 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층(140; 예: InGaN/(In)GaN 다중양자우물구조)을 포함한다. 복수의 반도체층(130,140,150) 각각은 다층으로 이루어질 수 있고, 버퍼층(20)은 생략될 수 있다.The plurality of semiconductor layers 130, 140, and 150 may include a buffer layer 120 formed on the substrate 10, a first semiconductor layer 130 having a first conductivity (eg, Si-doped GaN), and a second different from the first conductivity. A conductive second semiconductor layer 150 (eg, Mg-doped GaN) and an active layer interposed between the first semiconductor layer 130 and the second semiconductor layer 150 to generate light through recombination of electrons and holes ( 140; for example, InGaN / (In) GaN multi-quantum well structure). Each of the semiconductor layers 130, 140, and 150 may be formed in multiple layers, and the buffer layer 20 may be omitted.
제1 반도체층(130)과 제2 반도체층(150)은 서로 다른 도전성을 갖도록 구비되며, 그 위치가 바뀔 수 있다. 본 개시에서는 제1 반도체층(130)은 n형 질화물 반도체층(130; 예를 들어, n형 GaN층)으로, 제2 반도체층(150)은 p형 질화물 반도체층(150; 예를 들어, p형 GaN층)으로 예를 들어 설명한다.The first semiconductor layer 130 and the second semiconductor layer 150 are provided to have different conductivity, and their positions may be changed. In the present disclosure, the first semiconductor layer 130 is an n-type nitride semiconductor layer 130 (eg, an n-type GaN layer), and the second semiconductor layer 150 is a p-type nitride semiconductor layer 150 (eg, p-type GaN layer), for example.
제2 반도체층(150) 및 활성층(140)은 메사 식각되어 제1 반도체층(130)의 일부가 노출된다. 메사 식각의 순서는 변경될 수 있다.The second semiconductor layer 150 and the active layer 140 are mesa-etched to expose a portion of the first semiconductor layer 130. The order of mesa etching can be changed.
투광성 도전막(160)은 빛흡수 방지막(190) 및 빛흡수 차단막(192)을 덮으며, 제2 패드 전극(170)으로 전류를 확산하는 기능을 수행하여 빛의 균일성을 향상한다. 투광성 도전막(160)은 메사 식각 공정을 통해 형성되는 제1 패드 전극(180)을 제외한 제2 반도체층(150) 위의 거의 대부분을 덮도록 형성된다. 따라서, 투광성 도전막(160)과 제2 반도체층(150) 사이에 빛흡수 방지막(190) 및 빛흡수 차단막(192)이 개재된다. 특히, 제2 반도체층(150)이 p형 GaN으로 이루어지는 경우 전류 확산 능력이 떨어지므로, 투광성 도전막(160)이 형성되는 것이 바람직하다. 예를 들어, 투광성 도전막(160)은 ITO, Ni/Au와 같은 물질로 형성될 수 있다.The transparent conductive layer 160 covers the light absorption barrier layer 190 and the light absorption barrier layer 192 and improves the uniformity of light by performing a function of diffusing current to the second pad electrode 170. The transmissive conductive layer 160 is formed to cover most of the second semiconductor layer 150 except for the first pad electrode 180 formed through the mesa etching process. Therefore, the light absorption prevention film 190 and the light absorption blocking film 192 are interposed between the transparent conductive film 160 and the second semiconductor layer 150. In particular, when the second semiconductor layer 150 is made of p-type GaN, the current spreading ability is inferior, and therefore, the transparent conductive film 160 is preferably formed. For example, the transparent conductive layer 160 may be formed of a material such as ITO or Ni / Au.
투광성 도전막(160)이 너무 얇게 형성되는 경우 전류 확산에 불리하여 구동 전압이 높아지고, 너무 두껍게 형성되는 경우 빛흡수로 인해 광추출 효율이 감소될 수 있다.When the light-transmissive conductive layer 160 is formed too thin, the driving voltage is increased due to the current diffusion, and when the light-transmissive conductive layer 160 is formed too thick, light extraction efficiency may be reduced due to light absorption.
제1 패드 전극(180)은 메사 식각되어 노출된 제1 반도체층(130) 위에 형성되고, 제2 패드 전극(170)는 투광성 도전막(160) 위에 형성된다. 본 개시에서는 제1 패드 전극(180)은 제1 반도체층(130)과 전기적으로 연결되는 n측 패드 전극(180)으로, 제2 패드 전극(170)은 제2 반도체층(150)과 연결되는 n측 패드 전극(170)으로 예를 들어 설명한다.The first pad electrode 180 is formed on the first semiconductor layer 130 exposed by mesa etching, and the second pad electrode 170 is formed on the transparent conductive layer 160. In the present disclosure, the first pad electrode 180 is an n-side pad electrode 180 electrically connected to the first semiconductor layer 130, and the second pad electrode 170 is connected to the second semiconductor layer 150. For example, the n-side pad electrode 170 will be described.
제1 패드 전극(180) 및 제2 패드 전극(170)은 니켈, 크롬 및 금을 적층하여 형성될 수 있다.The first pad electrode 180 and the second pad electrode 170 may be formed by stacking nickel, chromium, and gold.
빛흡수 방지막(190)은 제2 패드 전극(170)에 대응하여 제2 반도체층(150) 위에 형성된다.The light absorption prevention layer 190 is formed on the second semiconductor layer 150 corresponding to the second pad electrode 170.
빛흡수 방지막(190)은 활성층(140)에서 발생된 빛의 일부 또는 전부를 반사하여 투광성 도전막(160)에서의 빛 흡수를 방지한다. 또한 빛흡수 방지막(190)은 제2 패드 전극(170)의 바로 아래로 전류가 흐르지 못하도록 하는 기능(current blocking)을 가질 수 있다. 빛흡수 방지막(190)은 생략될 수 있다.The light absorption prevention layer 190 reflects some or all of the light generated from the active layer 140 to prevent light absorption from the transmissive conductive layer 160. In addition, the light absorption prevention layer 190 may have a function of preventing current from flowing directly under the second pad electrode 170. The light absorption prevention layer 190 may be omitted.
빛흡수 방지막(190)은 제2 반도체층(150)보다 굴절률이 낮은 투광성 물질로 된 단일층(예: SiO2), 다층막(예: Si02/TiO2 /SiO2), 분포 브래그 리플렉터, 단일층과 분포 브래그 리플렉터의 결합 등으로 이루어질 수 있다. 또한 빛흡수 방지막(190)은 비도전성 물질(예: SiOx, TiOx와 같은 유전체 막)로 이루어질 수 있다.The light absorption prevention layer 190 may be formed of a single layer (eg, SiO 2 ), a multilayer (eg, Si0 2 / TiO 2 / SiO 2 ), a distributed Bragg reflector, or a single layer of a light transmissive material having a lower refractive index than the second semiconductor layer 150. Or a combination of a layer and a distributed Bragg reflector. In addition, the light absorption prevention layer 190 may be made of a non-conductive material (eg, a dielectric film such as SiOx or TiOx).
빛흡수 차단막(192)은 제2 패드 전극(170)에 대응하여 빛흡수 방지막(190) 위에 형성된다. 즉, 투광성 도전막(160)과 빛흡수 방지막(190) 사이에 위치한다.The light absorption blocking layer 192 is formed on the light absorption prevention layer 190 in correspondence with the second pad electrode 170. That is, it is positioned between the transparent conductive film 160 and the light absorption prevention film 190.
빛흡수 차단막(192)은 빛흡수 방지막(190)에 의해 반사되지 못하고 빛흡수 방지막(190)을 통과한 빛을 차단한다. 한편, 빛흡수 차단막(192)은 가지 전극으로도 기능할 수 있다.The light absorption blocking layer 192 blocks light that is not reflected by the light absorption prevention layer 190 and passes through the light absorption prevention layer 190. Meanwhile, the light absorption blocking layer 192 may also function as a branch electrode.
종래에는 투광성 도전막과 복수의 반도체층 사이에 빛흡수 방지막만 위치하였다. 활성층에서 발생된 빛의 일부는 빛흡수 방지막에 의해 반사되고, 반사되지 않는 나머지 빛은 빛흡수 방지막을 관통하여 투광성 도전막에서 1차 흡수되고, 1차 흡수된 나머지 빛은 패드 전극에 의해 재반사되어 투광성 도전막에서 2차 흡수된 후 빛흡수 방지막을 관통하여 복수의 반도체층으로 재입사된다. 이에 따라, 광효율 추출이 감소될 수 있었다.Conventionally, only the light absorption prevention film is positioned between the transparent conductive film and the plurality of semiconductor layers. Some of the light generated from the active layer is reflected by the anti-reflective film, and the remaining non-reflected light is first absorbed by the transmissive conductive film through the anti-reflective film, and the remaining light is primarily reflected back by the pad electrode. After the second absorption in the light-transmissive conductive film is passed through the light absorption prevention film and re-incident into a plurality of semiconductor layers. Accordingly, light efficiency extraction could be reduced.
이에 본 개시에서는 빛흡수 차단막(192)을 투광성 도전막(160)과 빛흡수 방지막(190) 사이에 배치함으로써, 투광성 도전막(160)에서 발생하는 빛흡수를 차단하여 반도체 발광소자의 광 추출 효율(extraction efficiency)을 향상시킬 수 있다.Accordingly, in the present disclosure, the light absorption blocking layer 192 is disposed between the light transmissive conductive layer 160 and the light absorption prevention layer 190, thereby blocking light absorption generated from the light transmissive conductive layer 160 to thereby extract light efficiency of the semiconductor light emitting device. (extraction efficiency) can be improved.
빛흡수 차단막(192)은 빛흡수 방지막(190)과 서로 다른 물질로 이루어지는 것이 바람직하다.The light absorption blocking layer 192 may be formed of a material different from that of the light absorption blocking layer 190.
빛흡수 차단막(192)은 빛을 반사하는 효율이 높아 반사성이 우수하고 전기적인 접촉이 우수한 금속성 물질, 예를 들어, 금속성 물질에는 은(Ag), 알루미늄(Al), 분포 브래그 리플렉터(DBR: Distributed Bragg Reflector), 고반사 백색 반사물질 등으로 될 수 있다. 하지만, 비용 및 효율을 고려했을 때 알루미늄(Al)이 바람직하다.The light absorption blocking layer 192 has a high reflectivity and is highly reflective and has excellent electrical contact. For example, the metallic material may be silver (Ag), aluminum (Al), or distributed Bragg reflector (DBR). Bragg Reflector), highly reflective white reflector, and the like. However, aluminum (Al) is preferred in view of cost and efficiency.
빛흡수 방지막(190)이 SiOx로 이루어지고, 빛흡수 차단막(192)이 알루미늄(Al)으로 이루어지는 경우 접합력을 증가시키면서 제조 비용을 절감할 수 있다.When the light absorption prevention layer 190 is made of SiOx and the light absorption blocking layer 192 is made of aluminum (Al), the manufacturing cost may be reduced while increasing the bonding force.
도 25(b)를 참조하면, 빛흡수 방지막(190)은 제1 두께(T1)로 형성되고, 빛흡수 차단막(192)는 제2 두께(T2)로 형성된다.Referring to FIG. 25B, the light absorption prevention layer 190 is formed to have a first thickness T1, and the light absorption blocking layer 192 is formed to have a second thickness T2.
빛흡수 방지막(190)의 제1 두께(T1)와 빛흡수 차단막(192)의 제2 두께(T2)는 서로 동일하게 형성되는 것이 바람직하다. 하지만, 이에 한정되지 않고 빛흡수 방지막(190)의 제1 두께(T1)는 빛흡수 차단막(192)의 제2 두께(T2) 보다 크게 또는 작게 형성될 수 있다.The first thickness T1 of the light absorption prevention film 190 and the second thickness T2 of the light absorption blocking film 192 are preferably formed to be the same. However, the present invention is not limited thereto, and the first thickness T1 of the light absorption prevention layer 190 may be larger or smaller than the second thickness T2 of the light absorption blocking layer 192.
본 예에서, 빛흡수 방지막(190)의 제1 두께(T1)와 빛흡수 차단막(192)의 제2 두께(T2)는 약 1000Å 이상, 약 6000Å 이하인 것이 바람직하다.In this example, the first thickness T1 of the light absorption prevention film 190 and the second thickness T2 of the light absorption blocking film 192 are preferably about 1000 kPa or more and about 6000 kPa or less.
제1 및 제2 두께(T1, T2)가 1000Å 이하인 경우, 두께가 너무 얇아 빛흡수에 대한 방지 및 차단 기능을 원활히 수행할 수 없고, 제1 및 제2 두께(T1, T2)가 6000Å 이상인 경우 빛흡수 차단막(192) 위에 증착되는 투광성 도전막(160)의 증착이 어려워질 수 있다.When the first and second thicknesses T1 and T2 are 1000 μs or less, the thickness is too thin to prevent the function of preventing and blocking light absorption, and when the first and second thicknesses T1 and T2 are 6000 μs or more. Deposition of the transparent conductive film 160 deposited on the light absorption blocking layer 192 may be difficult.
빛흡수 방지막(190) 및 빛흡수 차단막(192)은 제2 패드 전극(170)에 대응하여 형성된다. 빛흡수 방지막(190) 및 빛흡수 차단막(192)은 제2 패드 전극(170) 아래에 섬 형태로 형성될 수 있다지만, 이에 한정되지 않는다.The light absorption prevention layer 190 and the light absorption blocking layer 192 are formed to correspond to the second pad electrode 170. The light absorption prevention layer 190 and the light absorption blocking layer 192 may be formed in an island shape under the second pad electrode 170, but are not limited thereto.
빛흡수 방지막(190)은 제1 폭(W1)으로 형성되며, 제2 패드 전극(170)의 폭과 동일하거나 넓게 형성될 수 있다.The light absorption prevention layer 190 may be formed to have a first width W1 and may be formed to be the same as or wider than the width of the second pad electrode 170.
빛흡수 차단막(192)은 제2 폭(W1)으로 형성되며, 빛흡수 방지막(190)의 제1 폭(W1)과 동일하거나 작게 형성될 수 있다. 또한 빛흡수 차단막(192)은 제2 패드 전극(170)의 폭과 동일하거나 넓게 형성될 수 있다.The light absorption blocking layer 192 may be formed to have a second width W1, and may be formed to be the same as or smaller than the first width W1 of the light absorption prevention layer 190. In addition, the light absorption blocking layer 192 may be formed to be the same as or wider than the width of the second pad electrode 170.
빛흡수 방지막(190) 및 빛흡수 차단막(192)의 제1 및 제2 폭(W1, W2)이 제2 패드 전극(170)의 폭보다 넓게 형성되는 경우 전류가 차단되는 영역이 너무 커져서 소자의 효율이 떨어질 수 있으며, 또한 활성층(140)에서 생성되어 빛흡수 방지막(190) 및 빛흡수 차단막(192)으로 입사된 빛이 필요 이상으로 복수의 반도체층 쪽으로 재반사 될수 있다. 이에 반해, 빛흡수 방지막(190) 및 빛흡수 차단막(192)의 제1 및 제2 폭(W1, W2)이 제2 패드 전극(170)의 폭보다 작게 형성되는 경우 제2 패드 전극(170)으로 입사하는 빛을 효과적으로 반사하지 못한다. 이에 따라, 빛흡수 방지막(190) 및 빛흡수 차단막(192)의 제1 및 제2 폭(W1, W2)은 제2 패드 전극(170)의 폭과 동일하거나 넓게 형성되는 것이 바람직하다.When the first and second widths W1 and W2 of the light absorption prevention film 190 and the light absorption blocking film 192 are formed to be wider than the width of the second pad electrode 170, the area where the current is cut off becomes too large. Efficiency may be reduced, and light generated in the active layer 140 and incident on the light absorption prevention layer 190 and the light absorption blocking layer 192 may be reflected back toward the plurality of semiconductor layers more than necessary. On the contrary, when the first and second widths W1 and W2 of the light absorption prevention layer 190 and the light absorption blocking layer 192 are smaller than the width of the second pad electrode 170, the second pad electrode 170 may be formed. It does not reflect light incident to it effectively. Accordingly, the first and second widths W1 and W2 of the light absorption blocking layer 190 and the light absorption blocking layer 192 may be the same as or wider than the width of the second pad electrode 170.
이하, 반도체 발광소자(100)의 제조 방법을 살펴보면 다음과 같다.Hereinafter, a method of manufacturing the semiconductor light emitting device 100 will be described.
반도체 발광소자(100)의 제조 방법에 있어서, 우선 기판(110) 위에 제1 버퍼층(120), 제1 반도체층(130), 활성층(140) 및 제2 반도체층(150)을 형성한 후, 메사(mesa) 형태로 제2 반도체층(150) 및 활성층(140)을 식각하여 제1 반도체층(130)을 노출한다. 여러 개의 반도체층을 제거하는 방법으로 건식식각 방법, 예를 들어 ICP(Inductively Coupled Plasma)이 사용될 수 있다.In the method of manufacturing the semiconductor light emitting device 100, first, the first buffer layer 120, the first semiconductor layer 130, the active layer 140, and the second semiconductor layer 150 are formed on the substrate 110. The second semiconductor layer 150 and the active layer 140 are etched in a mesa form to expose the first semiconductor layer 130. As a method of removing a plurality of semiconductor layers, a dry etching method, for example, an inductively coupled plasma (ICP) may be used.
다음으로, PECVD(Plasma Enhanced Chemical Vapor Deposition), LPCVD(Low Pressure Chemical Vapor Deposition), sputtering, E-beam evaporation, thermal evaportation 등을 이용하여 제2 패드 전극(170)이 형성될 부분에 대응되는 제2 반도체층(150) 위의 일부에 빛흡수 방지막(190)를 형성한다.Next, a second pad electrode 170 corresponding to a portion where the second pad electrode 170 is to be formed by using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, e-beam evaporation, thermal evaportation, or the like. The light absorption prevention layer 190 is formed on a portion of the semiconductor layer 150.
다음으로, PECVD(Plasma Enhanced Chemical Vapor Deposition), LPCVD(Low Pressure Chemical Vapor Deposition), sputtering, E-beam evaporation, thermal evaportation 등을 이용하여 빛흡수 방지막(190) 위에 빛흡수 차단막(192)을 형성한다.Next, a light absorption blocking layer 192 is formed on the light absorption prevention layer 190 by using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, e-beam evaporation, and thermal evaportation. .
이때, 빛흡수 방지막(190)과 빛흡수 차단막(192)은 동시에 형성될 수도 있다.In this case, the light absorption prevention layer 190 and the light absorption blocking layer 192 may be formed at the same time.
다음으로, 스퍼터링(Sputtering)법, 전자빔 증작법(E-beam Evaporation), 열증착법 등을 사용하여, 도 24 및 도 25(a)에 도시된 것과 같이, 제2 반도체층(150)의 거의 전면 및 빛흡수 방지막(190)과 빛흡수 차단막(192) 위에 투광성 전도막(160)을 형성한다.Next, using the sputtering method, the E-beam evaporation method, the thermal evaporation method, and the like, as shown in FIGS. 24 and 25 (a), almost the entire surface of the second semiconductor layer 150 is used. And a light transmissive conductive layer 160 on the light absorption preventing layer 190 and the light absorption blocking layer 192.
다음으로, 스퍼터링(Sputtering)법, 전자빔 증작법(Ebeam Evaporation), 열증착법 등의 방법을 이용하며, 제1 패드 전극(180) 및 제2 패드 전극(170)을 형성한다.Next, the first pad electrode 180 and the second pad electrode 170 are formed by using a method such as a sputtering method, an electron beam evaporation method, a thermal evaporation method, or the like.
도 26은 본 개시에 따른 반도체 발광소자의 다른 예를 보여주는 도면이다.26 illustrates another example of the semiconductor light emitting device according to the present disclosure.
반도체 발광소자(200)는 보호막(201)을 포함한다.The semiconductor light emitting device 200 includes a protective film 201.
보호막(201)은 반도체 발광소자(200)를 보호하기 위해 복수의 반도체층(230, 240, 250)의 측면 및 상면, 그리고 투광성 도전막(260), 제1 및 제2 패드 전극(280, 270)의 상면 일부분을 덮도록 형성된다. 보호막(201)이 제1 반도체층(230) 및 제2 반도체층(250) 위의 모든 영역을 반드시 덮을 필요는 없다.The passivation layer 201 may include side and top surfaces of the semiconductor layers 230, 240, and 250, and the transparent conductive layer 260 and the first and second pad electrodes 280 and 270 to protect the semiconductor light emitting device 200. It is formed to cover a portion of the top surface. The protective film 201 does not necessarily cover all regions on the first semiconductor layer 230 and the second semiconductor layer 250.
보호막(201)은 SiO2, TiO2, SiNx, DBR 등과 같은 물질로 형성될 수 있으며, 생략될 수도 있다.The protective film 201 may be formed of a material such as SiO 2 , TiO 2 , SiNx, DBR, or the like, and may be omitted.
보호막(201)은 투광성 도전막(260)과 동시에 형성될 수도 있다.The protective film 201 may be formed simultaneously with the transparent conductive film 260.
본 개시에 따른 반도체 발광소자의 제조방법의 순서는 당업자가 용이하게 변경할 수 있는 범위에서는 본 개시의 범위에 포함될 수 있다.The order of the manufacturing method of the semiconductor light emitting device according to the present disclosure may be included in the scope of the present disclosure in a range that can be easily changed by those skilled in the art.
도 26에 기재된 보호막(201)을 제외하고는 도 24 및 도 25에 기재된 반도체 발광소자(100)와 동일한 특성을 갖는다.Except for the protective film 201 shown in FIG. 26, it has the same characteristics as the semiconductor light emitting device 100 shown in FIGS.
도 27은 본 개시에 따른 반도체 발광소자의 또 다른 예를 보여주는 도면이다.27 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
반도체 발광소자(300)는 금속층(3920) 및 부도체층(3921)을 포함하는 빛흡수 차단막(392)을 포함한다.The semiconductor light emitting device 300 includes a light absorption blocking layer 392 including a metal layer 3920 and a non-conductive layer 3921.
금속층(3920)은 빛흡수 방지막(390)의 상면에 위치하며, 빛흡수 방지막(390)과의 접합력을 높이면서 빛흡수를 차단하기 위해 반사율이 높으며 전기적인 접촉이 우수한 금속성 물질로 이루어질 수 있다. 예를 들어, 금속층(392)은 은(Ag), 알루미늄(Al), 분포 브래그 리플렉터(DBR: Distributed Bragg Reflector), 고반사 백색 반사물질 등으로 될 수 있다. 하지만, 비용 및 효율을 고려했을 때 알루미늄(Al)이 바람직하다.The metal layer 3920 is positioned on an upper surface of the light absorption prevention layer 390, and may be formed of a metallic material having high reflectance and excellent electrical contact to block light absorption while increasing bonding strength with the light absorption prevention layer 390. For example, the metal layer 392 may be made of silver (Ag), aluminum (Al), a distributed Bragg reflector (DBR), a highly reflective white reflector, or the like. However, aluminum (Al) is preferred in view of cost and efficiency.
금속층(3920)은 PECVD(Plasma Enhanced Chemical Vapor Deposition), LPCVD(Low Pressure Chemical Vapor Deposition), sputtering, E-beam evaporation, thermal evaportation 등을 이용하여 빛흡수 방지막(390) 위에 형성될 수 있다.The metal layer 3920 may be formed on the light absorption prevention layer 390 using Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), sputtering, E-beam evaporation, thermal evaportation, or the like.
부도체층(3921)은 금속층(3920) 위에 위치하며 즉, 금속층(3920)과 투광성 도전막(360) 사이에 개재된다.The insulator layer 3921 is positioned on the metal layer 3920, that is, interposed between the metal layer 3920 and the transparent conductive film 360.
부도체층(3921)은 금속층(3920)의 표면을 아노다이징하는 방식으로 형성되거나, 금속층(3920)의 표면에 절연물질을 증착하는 방식으로 형성될 수 있다.The nonconductive layer 3921 may be formed by anodizing the surface of the metal layer 3920 or by depositing an insulating material on the surface of the metal layer 3920.
예를 들어, 금속층(3920)의 재질이 Al로 이루어지고 아노다이징을 통해 금속층(3920)을 표면처리할 경우, 부도체층(3921)은 산화알루미늄막(Al2O3)으로 이루어질 수 있다. 또한, 부도체층(3921)은 증착을 통해 형성되는 SiO2, TiO2, SiN, SiON, Al2O3 및 Ta2O5 막 중 어느 하나일 수도 있다.For example, when the material of the metal layer 3920 is made of Al and the metal layer 3920 is surface-treated through anodizing, the nonconductive layer 3921 may be made of aluminum oxide film (Al 2 O 3). In addition, the insulator layer 3921 may be any one of SiO 2 , TiO 2 , SiN, SiON, Al 2 O 3, and Ta 2 O 5 films formed through deposition.
금속층(3920)과 투광성 도전막(360) 사이에 부도체층(3921)이 위치함으로써, 투광성 도전막(360)과 전기적으로 절연시켜 안정적인 절연 상태를 유지할 수 있다. 더욱이, 부도체층(3921)으로 인해 금속층(3920)과 투광성 도전막(360) 사이의 절연 상태를 안정적을 유지하면서 전류 확산을 향상할 수 있다.The nonconductive layer 3921 is positioned between the metal layer 3920 and the transparent conductive film 360 to electrically insulate the transparent conductive film 360 to maintain a stable insulating state. In addition, the insulator layer 3921 may improve current spreading while maintaining a stable state of insulation between the metal layer 3920 and the transparent conductive film 360.
도 27에 기재된 금속층(3920) 및 부도체층(3921)을 포함하는 빛흡수 차단막(392)을 제외하고는 도 24 및 도 25에 기재된 반도체 발광소자(100)와 동일한 특성을 갖는다.Except for the light absorption barrier layer 392 including the metal layer 3920 and the nonconductive layer 3921 illustrated in FIG. 27, the semiconductor light emitting device 100 has the same characteristics as the semiconductor light emitting device 100 illustrated in FIGS. 24 and 25.
도 28은 본 개시에 따른 반도체 발광소자의 또 다른 예를 보여주는 도면이다.28 illustrates another example of the semiconductor light emitting device according to the present disclosure.
반도체 발광소자(400)는 비도전성 반사막(402)을 포함한다.The semiconductor light emitting device 400 includes a nonconductive reflecting film 402.
비도전성 반사막(402)은 식각되어 노출된 복수의 반도체층(430, 440, 450)의 측면 및 상면, 그리고 투광성 도전막(460), 제1 및 제2 패드 전극(480, 470)의 상면 일부분을 덮도록 형성된다. 비도전성 반사막(402)이 제1 반도체층(430) 및 제2 반도체층(450) 위의 모든 영역을 반드시 덮을 필요는 없다. 비도전성 반사막(402)은 반사막으로 기능하되, 빛의 흡수를 방지하도록 투광성 물질로 형성되는 것이 바람직하다.The non-conductive reflecting layer 402 is formed on side surfaces and top surfaces of the plurality of etched and exposed semiconductor layers 430, 440, and 450, and a portion of the upper surface of the transparent conductive layer 460 and the first and second pad electrodes 480 and 470. It is formed to cover. The non-conductive reflective film 402 does not necessarily cover all regions on the first semiconductor layer 430 and the second semiconductor layer 450. The non-conductive reflecting film 402 functions as a reflecting film but is preferably formed of a light transmitting material to prevent absorption of light.
비도전성 반사막(402)은 단일의 유전체층(예: SiOx, TiOx, Ta2O5, MgF2와 같은 투광성 유전체 물질)으로 이루어질 수도 있고, 다층 구조를 가질 수도 있다. 다층 구조의 일 예로, 비도전성 반사막(402)은 순차로 적층된 유전체막, 분포 브래그 리플렉터(Distributed Bragg Reflector; 예: SiO2와 TiO2의 조합으로 된 DBR) 및 클래드막을 포함할 수 있다.The nonconductive reflective film 402 may be made of a single dielectric layer (eg, a transparent dielectric material such as SiOx, TiOx, Ta 2 O 5 , MgF 2 ), or may have a multilayer structure. As an example of the multilayer structure, the non-conductive reflective film 402 may include a dielectric film sequentially stacked, a distributed Bragg reflector (eg, a DBR made of a combination of SiO 2 and TiO 2 ) and a clad film.
비도전성 반사막(402)이 SiOx로 이루어지는 경우에, 제2 반도체층(450; 예: GaN)에 비해 낮은 굴절률을 가지므로, 임계각 이상의 입사각을 가진 빛을 복수의 반도체층(430, 440, 450) 측으로 일부 반사할 수 있게 된다.When the non-conductive reflective film 402 is made of SiOx, since the non-conductive reflective film 402 has a lower refractive index than the second semiconductor layer 450 (for example, GaN), light having an incident angle greater than or equal to a critical angle is provided in the plurality of semiconductor layers 430, 440, and 450. Some reflections can be made to the side.
한편, 비도전성 반사막(91)이 분포 브래그 리플렉터(DBR: Distributed Bragg Reflector; 예: SiO2와 TiO2의 조합으로 된 DBR)로 이루어지면 더 많은 양의 빛을 복수의 반도체층(430, 440, 450) 측으로 반사할 수 있다.On the other hand, when the non-conductive reflecting film 91 is made of a distributed Bragg reflector (DBR: DBR of a combination of SiO 2 and TiO 2 ), a greater amount of light may be applied to the plurality of semiconductor layers 430, 440, and the like. 450) can be reflected to the side.
도 28에 기재된 비도전성 반사막(402)을 제외하고는 도 24 및 도 25에 기재된 반도체 발광소자(100)와 동일한 특성을 갖는다.Except for the non-conductive reflecting film 402 shown in FIG. 28, it has the same characteristics as the semiconductor light emitting device 100 shown in FIGS.
도 33은 본 개시에 따른 반도체 발광소자의 일 예를 설명하기 위한 도면이고, 도 34는 도 33의 A-A 선을 따라 취한 절단면의 일 예를 설명하는 도면이다.33 is a view for explaining an example of a semiconductor light emitting device according to the present disclosure, and FIG. 34 is a view for explaining an example of a cut plane taken along line A-A of FIG. 33.
반도체 발광소자는 기판(10) 위에 서로 마주보도록 형성된 제1 발광부(101)와 제2 발광부(102), 연결 전극(92), 반사층(91), 제1 전극(80), 제2 전극(70), 제1 전기적 연결(71) 및 제2 전기적 연결(81)을 포함한다.The semiconductor light emitting device may include a first light emitting part 101 and a second light emitting part 102, a connection electrode 92, a reflective layer 91, a first electrode 80, and a second electrode formed to face each other on a substrate 10. 70, a first electrical connection 71, and a second electrical connection 81.
제1 발광부(101) 및 제2 발광부(102)는 각각 제1 반도체층(30), 활성층(40) 및 제2 반도체층(50)이 순차로 적층된 복수의 반도체층을 포함한다.The first light emitting unit 101 and the second light emitting unit 102 each include a plurality of semiconductor layers in which the first semiconductor layer 30, the active layer 40, and the second semiconductor layer 50 are sequentially stacked.
반사층(91)은 제1 발광부(101), 제2 발광부(102), 및 제1 발광부(101)와 제2 발광부(102)의 사이를 덮도록 형성되며, 활성층(40)에서 생성된 빛을 반사한다.The reflective layer 91 is formed to cover the first light emitting part 101, the second light emitting part 102, and the first light emitting part 101 and the second light emitting part 102. Reflect the generated light.
제1 전극(80)은 제1 발광부(101)의 제1 반도체층(30)과 전기적으로 연통하도록 구비되며, 전자와 정공 중 하나를 공급한다.The first electrode 80 is provided to be in electrical communication with the first semiconductor layer 30 of the first light emitting part 101, and supplies one of electrons and holes.
제2 전극(70)은 제2 발광부(102)의 제2 반도체층(50)과 전기적으로 연통하도록 구비되며, 전자와 정공 중 나머지 하나를 공급한다.The second electrode 70 is provided to be in electrical communication with the second semiconductor layer 50 of the second light emitting part 102, and supplies the other one of electrons and holes.
제1 전기적 연결(71) 및 제2 전기적 연결(81)은 반사층(91)을 관통하며, 복수의 반도체층과 전기적으로 연통한다. 본 예는 제1 전기적 연결(81)은 제1 반도체층(30)과 전기적으로 연통하고, 제2 전기적 연결(71)은 제2 반도체층(50)과 전기적으로 연통한다.The first electrical connection 71 and the second electrical connection 81 pass through the reflective layer 91 and are in electrical communication with the plurality of semiconductor layers. In this example, the first electrical connection 81 is in electrical communication with the first semiconductor layer 30, and the second electrical connection 71 is in electrical communication with the second semiconductor layer 50.
연결 전극(92)은 반사층(91) 위에서 뻗으며, 제1 발광부(101)와 제2 발광부(102)를 전기적으로 연통한다. 이하, 3족 질화물 반도체 발광소자를 예로 하여 설명한다.The connection electrode 92 extends over the reflective layer 91 and electrically connects the first light emitting part 101 and the second light emitting part 102. Hereinafter, the group III nitride semiconductor light emitting element will be described as an example.
기판(10)으로 주로 사파이어, SiC, Si, GaN 등이 이용되며, 기판(10)은 최종적으로 제거될 수 있다.Sapphire, SiC, Si, GaN and the like are mainly used as the substrate 10, and the substrate 10 may be finally removed.
제1 반도체층(30)과 제2 반도체층(50)은 그 위치가 바뀔 수 있으며, 3족 질화물 반도체 발광소자에 있어서 주로 GaN으로 이루어진다.The positions of the first semiconductor layer 30 and the second semiconductor layer 50 may be changed, and are mainly made of GaN in the group III nitride semiconductor light emitting device.
복수의 반도체층(30, 40, 50)은 기판(10) 위에 형성된 버퍼층(20), 제1 도전성을 가지는 제1 반도체층(30; 예: Si 도핑된 GaN), 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층(50; 예: Mg 도핑된 GaN) 및 제1 반도체층(30)과 제2 반도체층(50) 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층(40; 예: InGaN/(In)GaN 다중양자우물구조)을 포함한다. 복수의 반도체층(30, 40, 50) 각각은 다층으로 이루어질 수 있고, 버퍼층(20)은 생략될 수 있다.The plurality of semiconductor layers 30, 40, and 50 may include a buffer layer 20 formed on the substrate 10, a first semiconductor layer 30 having a first conductivity (eg, Si-doped GaN), and a second different from the first conductivity. A conductive second semiconductor layer 50 (eg, Mg-doped GaN) and an active layer interposed between the first semiconductor layer 30 and the second semiconductor layer 50 to generate light through recombination of electrons and holes ( 40; e.g., InGaN / (In) GaN multi-quantum well structure). Each of the plurality of semiconductor layers 30, 40, and 50 may be formed in multiple layers, and the buffer layer 20 may be omitted.
반도체 발광소자는 복수의 발광부를 포함할 수 있다. 본 예에서, 반도체 발광소자는 제1 발광부(101) 및 제2 발광부(102)를 포함한다. 위에서 바라볼 때 각각의 제1 발광부(101) 및 제2 발광부(102)는 장방향(x 방향)으로 형성된 장변과 단방향(y 방향)으로 형성된 단변을 갖는 사각 형상 예를 들어 직사각 형상을 갖는다. 각각의 제1 발광부(101) 및 제2 발광부(102)의 장변 측이 서로 마주보도록 단방향(y 방향)으로 배열되어 있다. 따라서, 반도체 발광소자는 전체적으로 가로와 세로가 거의 비슷한 형상을 갖는다.The semiconductor light emitting device may include a plurality of light emitting parts. In this example, the semiconductor light emitting element includes a first light emitting portion 101 and a second light emitting portion 102. As viewed from above, each of the first light emitting part 101 and the second light emitting part 102 has a rectangular shape having a long side formed in the long direction (x direction) and a short side formed in the short direction (y direction), for example, a rectangular shape. Have The long sides of each of the first light emitting units 101 and the second light emitting units 102 are arranged in one direction (y direction) to face each other. Therefore, the semiconductor light emitting device has a shape substantially similar in width and length as a whole.
반사층(91)은 복수의 반도체층(30, 40, 50), 제1 발광부(101), 제2 발광부(102) 및 연결 전극(92)을 덮도록 형성된다.The reflective layer 91 is formed to cover the plurality of semiconductor layers 30, 40, and 50, the first light emitting part 101, the second light emitting part 102, and the connection electrode 92.
본 예에서, 반사층(91)은 절연성을 가지며, 제1 전극(80) 및 제2 전극(70) 중 적어도 하나는 반사층(91)을 기준으로 복수의 반도체층(30, 40, 50)의 반대 측에 구비되며, 반사층(91)을 관통하는 전기적 연결(an electrical connection)에 의해 복수의 반도체층과 전기적으로 연통되는 플립칩(flip chip)이다.In this example, the reflective layer 91 is insulative, and at least one of the first electrode 80 and the second electrode 70 is opposite to the plurality of semiconductor layers 30, 40, and 50 based on the reflective layer 91. A flip chip provided at the side and electrically connected to the plurality of semiconductor layers by an electrical connection passing through the reflective layer 91.
예를 들어, 반사층(91)은 금속 반사막에 의한 광흡수 감소를 위해 절연성 물질로 형성되며, 바람직하게는 DBR(Distributed Bragg Reflector) 또는 ODR(Omni-Directional Reflector)을 포함하는 다층 구조일 수 있다. 다층 구조의 일 예로, 유전체막(91b), 분포 브래그 리플렉터(91a) 및 클래드막(91c)을 포함한다. 유전체막(91b)은 높이차를 완화하여 분포 브래그 리플렉터(91a)를 안정적으로 제조할 수 있게 되며, 빛의 반사에도 도움을 줄 수 있다. 유전체막(91b)의 재질은 SiO2가 적당하다. 분포 브래그 리플렉터(91a)는 유전체막(91b) 위에 형성된다. 분포 브래그 리플렉터(91a)는 반사율이 다른 물질의 반복 적층, 예를 들어, SiO2/TiO2, SiO2/Ta2O2, 또는 SiO2/HfO의 반복 적층으로 이루어질 수 있으며, Blue 빛에 대해서는 SiO2/TiO2가 반사효율이 좋고, UV 빛에 대해서는 SiO2/Ta2O2, 또는 SiO2/HfO가 반사효율이 좋을 것이다. 클래드막(91c)은 Al2O3와 같은 금속 산화물, SiO2, SiON와 같은 유전체막(91b), MgF, CaF, 등의 물질로 이루어질 수 있다. 분포 브래그 리플렉터(91a)는 수직 방향에 가까운 빛일수록 반사율이 높아서, 대략 99% 이상 반사한다.For example, the reflective layer 91 may be formed of an insulating material to reduce light absorption by the metal reflective film, and may preferably have a multilayer structure including a distributed bragg reflector (DBR) or an omni-directional reflector (ODR). An example of the multilayer structure includes a dielectric film 91b, a distributed Bragg reflector 91a, and a clad film 91c. The dielectric film 91b may reduce the height difference to stably manufacture the distributed Bragg reflector 91a and may also help to reflect light. SiO 2 is a suitable material for the dielectric film 91b. The distributed Bragg reflector 91a is formed on the dielectric film 91b. The distribution Bragg reflector 91a may be composed of repeated stacking of materials having different reflectances, for example, SiO 2 / TiO 2 , SiO 2 / Ta 2 O 2 , or SiO 2 / HfO. SiO 2 / TiO 2 has good reflection efficiency, and for UV light, SiO 2 / Ta 2 O 2 , or SiO 2 / HfO will have good reflection efficiency. The clad film 91c may be made of a metal oxide such as Al 2 O 3 , a dielectric film 91b such as SiO 2 , SiON, MgF, CaF, or the like. The distributed Bragg reflector 91a has a higher reflectance as light closer to the vertical direction reflects approximately 99% or more.
반사층(91)이 잘 기능 하기 위해서는 다층 구조의 각 물질층이 특별히 설계된 두께로 잘 형성되어야 한다. 반사층(91)은 아래의 구조물들(예: 오믹 전극, 발광부들 사이 트렌치 등)로 인해 반사층(91)에는 높이 차가 발생하는 부분들이 있다. 이러한 높이 차로 인해 반사층(91)의 각 물질층이 설계된 두께로 형성되기 어려운 영역이 있고, 이 영역에서는 반사효율이 저하될 수 있다. 발광부들 사이에서 상대적으로 다른 부분보다 반사효율이 떨어질 수 있다. 따라서 가능한 한 발광부들 사이에 금속층이 적게 형성되는 것이 금속에 의한 광흡수 손실을 감소하는데 좋다.In order for the reflective layer 91 to function well, each material layer having a multilayer structure must be formed to a specially designed thickness. The reflective layer 91 has portions where height differences occur in the reflective layer 91 due to the following structures (eg, ohmic electrodes, trenches between the light emitting parts, etc.). Due to the height difference, there is an area in which each material layer of the reflective layer 91 is hard to be formed in the designed thickness, and the reflection efficiency may be reduced in this area. The reflection efficiency may be lower than that of other parts between the light emitting parts. Therefore, forming as few metal layers between the light emitting portions as possible is preferable to reduce the light absorption loss by the metal.
연결 전극(92)은 서로 마주하여 위치하는 제1 발광부(101) 및 제2 발광부(102)를 장방향(x 방향)으로 전기적으로 연결한다. 연결 전극(92)은 제1 발광부(101)와 제2 발광부(102) 사이에서 각각 일부가 중첩되어 위치한다. 즉, 제1 발광부(101)와 제2 발광부(102)는 연결 전극(92)에 의해 서로 전기적으로 연결된다.The connection electrode 92 electrically connects the first light emitting part 101 and the second light emitting part 102 that face each other in the long direction (x direction). Part of the connection electrode 92 overlaps with each other between the first light emitting part 101 and the second light emitting part 102. That is, the first light emitting part 101 and the second light emitting part 102 are electrically connected to each other by the connection electrode 92.
연결 전극(92)의 일 측 끝은 제2 반도체층(50)과 반사층(91) 사이에서 제2 반도체층(50)과 전기적으로 연통되며, 연결 전극(92)의 타 측 끝은 제2 반도체층(50) 및 활성층(40)이 식각되어 노출된 제1 반도체층(30)과 전기적으로 연통된다.One end of the connection electrode 92 is in electrical communication with the second semiconductor layer 50 between the second semiconductor layer 50 and the reflective layer 91, and the other end of the connection electrode 92 is the second semiconductor. The layer 50 and the active layer 40 are etched and in electrical communication with the exposed first semiconductor layer 30.
연결 전극(92)은 반사층(91)을 기준으로 복수의 반도체층(30, 40, 50)의 반대 측에 구비되므로, 활성층(40)에서 생성된 빛이 연결 전극(92)에 충돌하기 전에 반사층(91)에서 거의 대부분 반사될 수 있다.Since the connection electrode 92 is provided on the opposite side of the plurality of semiconductor layers 30, 40, and 50 with respect to the reflective layer 91, the reflective layer before the light generated in the active layer 40 impinges on the connection electrode 92. In (91) it can almost be reflected.
연결 전극(92)의 폭은 제1 발광부(101) 및 제2 발광부(102)의 폭보다 작게 형성될 수 있지만, 이에 한정되는 것은 아니다. 본 예에서, 연결 전극(92)의 폭은 제1 발광부(101) 및 제2 발광부(102)의 폭보다 작게 형성되고, 제1 발광부(101)과 제2 발광부(102) 사이의 간격보다 크게 형성되는 것이 바람직하다. 따라서, 제1 발광부(101)과 제2 발광부(102) 사이의 간격을 최소화할 수 있으므로, 반도체 발광소자의 크기를 작게 형성할 수 있다.The width of the connection electrode 92 may be smaller than the width of the first light emitting part 101 and the second light emitting part 102, but is not limited thereto. In this example, the width of the connection electrode 92 is smaller than the width of the first light emitting part 101 and the second light emitting part 102, and between the first light emitting part 101 and the second light emitting part 102. It is preferable to form larger than the interval of. Therefore, since the distance between the first light emitting part 101 and the second light emitting part 102 can be minimized, the size of the semiconductor light emitting device can be reduced.
이와 같이, 제1 발광부(101) 및 제2 발광부(102) 각각의 장변 측이 서로 마주하며 서로 이격된 거리를 최소화 함으로써, 전류 확산의 균일성이 더욱 향상될 수 있다.As such, the long side of each of the first light emitting part 101 and the second light emitting part 102 may face each other and minimize the distance from each other, thereby improving the uniformity of current spreading.
연결 전극(92)은 제1 발광부(101) 및 제2 발광부(102)의 길이와 동일한 길이를 가질 수 있지만, 이에 한정하지 않는다. 본 예에서, 연결 전극(92)은 제1 발광부(101) 및 제2 발광부(102)의 길이보다 짧은 길이를 갖도록 도시하였다.The connection electrode 92 may have the same length as that of the first light emitting part 101 and the second light emitting part 102, but is not limited thereto. In this example, the connection electrode 92 is illustrated to have a length shorter than the length of the first light emitting part 101 and the second light emitting part 102.
이와 같이, 연결 전극(92)이 제1 발광부(101) 및 제2 발광부(102) 각각의 장변 측에 대응하여 장방향(x 방향)으로 길게 형성됨으로써, 제1 발광부(101) 및 제2 발광부(102) 사이의 연결 안정성이 더욱 향상될 수 있다.As such, the connection electrode 92 is formed to be elongated in the longitudinal direction (x direction) corresponding to the long sides of each of the first light emitting part 101 and the second light emitting part 102, thereby forming the first light emitting part 101 and The connection stability between the second light emitting units 102 may be further improved.
따라서, 제1 발광부(101) 및 제2 발광부(102)는 연결전극(92)에 의해 장방향(x 방향)으로 병렬 연결되며, 하나의 발광부보다 고전압(high-voltage)으로 구동된다.Therefore, the first light emitting part 101 and the second light emitting part 102 are connected in parallel in the long direction (x direction) by the connecting electrode 92 and are driven at a higher voltage than one light emitting part. .
제1 전극(80) 및 제2 전극(70) 각각은 제1 발광부(101) 및 제2 발광부(102)에 대응하여 반사층(91) 위에 형성된다. 제1 전극(80)은 제1 발광부(101)의 제1 전기적 연결(81)과 연결되고, 제2 전극(70)은 제2 발광부(102)의 제2 전기적 연결(71)과 연결된다.Each of the first electrode 80 and the second electrode 70 is formed on the reflective layer 91 in correspondence with the first light emitting part 101 and the second light emitting part 102. The first electrode 80 is connected to the first electrical connection 81 of the first light emitting part 101, and the second electrode 70 is connected to the second electrical connection 71 of the second light emitting part 102. do.
제1 전기적 연결(81)은 반사층(91)을 관통하여 제1 전극(80)과 제1 반도체층(30)을 전기적으로 연결한다. 제1 전기적 연결(81)과 제1 반도체층(30) 사이에는 접촉저항 감소와 안정적 전기적 연결을 위해 제1 오믹 전극(82)이 개재될 수 있다. 바람직하게는 전류 확산 전극(60; 예: ITO,Ni/Au)이 제2 반도체층(50)과 반사층(91) 사이에 형성된다. 전류 확산 전극(60)은 생략될 수 있다.The first electrical connection 81 penetrates the reflective layer 91 to electrically connect the first electrode 80 and the first semiconductor layer 30. The first ohmic electrode 82 may be interposed between the first electrical connection 81 and the first semiconductor layer 30 to reduce contact resistance and provide stable electrical connection. Preferably, a current diffusion electrode 60 (eg, ITO, Ni / Au) is formed between the second semiconductor layer 50 and the reflective layer 91. The current spreading electrode 60 can be omitted.
제2 전기적 연결(71)은 반사층(91)을 관통하여 제2 전극(70)과 제2 반도체층(50)을 전기적으로 연결한다. 제2 전기적 연결(71)과 제2 반도체층(50) 사이의 접촉저항 감소와 안정적 전기적 연결을 위해 제2 오믹 전극(72)이 개재될 수 있다.The second electrical connection 71 penetrates the reflective layer 91 to electrically connect the second electrode 70 and the second semiconductor layer 50. The second ohmic electrode 72 may be interposed to reduce contact resistance and to provide stable electrical connection between the second electrical connection 71 and the second semiconductor layer 50.
제1 전극(80) 및 제2 전극(70)은 외부 전극과의 전기적 연결용 전극으로서, 외부 전극과 유테틱 본딩되거나, 솔더링되거나 또는 와이어 본딩도 가능하다. 외부 전극은 서브마운트에 구비된 도통부, 패키지의 리드 프레임, PCB에 형성된 전기 패턴 등일 수 있으며, 반도체 발광소자와 독립적으로 구비된 도선이라면 그 형태에 특별한 제한이 있는 것은 아니다. 제1 전극(80) 및 제2 전극(70)은 어느 정도 면적을 가지도록 형성되어 있어서 방열 통로가 된다.The first electrode 80 and the second electrode 70 are electrodes for electrical connection with the external electrode, and may also be eutectic bonded, soldered, or wire bonded with the external electrode. The external electrode may be a conductive part provided in the submount, a lead frame of the package, an electrical pattern formed on the PCB, and the like, and the external electrode may be any type of conductive wire independently of the semiconductor light emitting device. The first electrode 80 and the second electrode 70 are formed to have a certain area to be a heat dissipation passage.
본 개시에 따른 반도체 발광소자의 제조 방법을 살펴보면, 먼저, 기판(10) 상에 제1 반도체층(30), 활성층(40), 제2 반도체층(50), 전류 확산 전극(60; 예: ITO)을 형성하고, 메사 식각하여 제1 전기적 연결(81)에 대응하는 제1 반도체층(30)의 일부를 노출한다. 메사 식각은 전류 확산 전극(60) 형성 전 또는 이후에 수행될 수도 있다. 전류 확산 전극(60)은 생략될 수 있다. 메사 식각 공정과 함께 또는 별개로 복수의 발광부를 서로 전기적으로 절연시키는 공정이 수행되어 각 발광부는 성장 기판(10)을 노출하는 트렌치에 의해 서로 전기적으로 절연될 수 있다.Looking at the manufacturing method of the semiconductor light emitting device according to the present disclosure, first, the first semiconductor layer 30, the active layer 40, the second semiconductor layer 50, the current diffusion electrode 60 on the substrate 10; ITO) and mesa etching to expose a portion of the first semiconductor layer 30 corresponding to the first electrical connection 81. Mesa etching may be performed before or after the current diffusion electrode 60 is formed. The current spreading electrode 60 can be omitted. A process of electrically insulating the plurality of light emitting parts together with or separately from the mesa etching process may be performed so that each light emitting part may be electrically insulated from each other by a trench exposing the growth substrate 10.
다음으로, 전류 확산 전극(60) 및 노출된 제1 반도체층(30)에 각각 오믹 전극(72, 82)을 형성한다. 오믹 전극(72, 82)은 생략될 수 있지만 동작전압 상승을 억제하고 안정적인 전기적 접촉을 위해 구비되는 것이 바람직하다. 한편, 오믹 전극(72, 82) 형성과 함께 또는 별개로 연결 전극(92)이 형성된다.Next, ohmic electrodes 72 and 82 are formed on the current diffusion electrode 60 and the exposed first semiconductor layer 30, respectively. The ohmic electrodes 72 and 82 may be omitted, but are preferably provided for suppressing an increase in operating voltage and for stable electrical contact. On the other hand, the connection electrode 92 is formed together with or separately from the formation of the ohmic electrodes 72 and 82.
또한, 전류 확산 전극(60) 형성 전에 제2 반도체층(50) 위에 오믹 전극(72)에 대응하여 광흡수 방지막을 형성하는 것을 고려할 수 있다.In addition, before the current diffusion electrode 60 is formed, it may be considered to form a light absorption prevention film on the second semiconductor layer 50 corresponding to the ohmic electrode 72.
다음으로, 전류 확산 전극(60) 위에 반사층(91)을 형성한다. 이후, 반사층(91)에 개구를 형성하고, 제1 전기적 연결(81) 및 제2 전기적 연결(71)이 개구를 관통하여 각각 제1 오믹 전극(82) 및 제2 오믹 전극(72)에 접촉하게 형성된다.Next, the reflective layer 91 is formed on the current spreading electrode 60. Thereafter, an opening is formed in the reflective layer 91, and the first electrical connection 81 and the second electrical connection 71 penetrate through the opening to contact the first ohmic electrode 82 and the second ohmic electrode 72, respectively. Is formed.
다음으로 제1 전극(80) 및 제2 전극(70)이 각각 제1 전기적 연결(81) 및 제2 전기적 연결(71)과 연결되도록 형성된다. 제1 및 제2 전기적 연결(81, 70)과 제1 및 제2 전극(80, 70)은 별개로 형성될 수도 있지만, 하나의 과정에서 일체로 형성될 수도 있다.Next, the first electrode 80 and the second electrode 70 are formed to be connected to the first electrical connection 81 and the second electrical connection 71, respectively. The first and second electrical connections 81 and 70 and the first and second electrodes 80 and 70 may be formed separately, but may be integrally formed in one process.
이와 같이, 웨이퍼 상에서 복수의 발광부를 포함하는 개별 반도체 발광소자별로 절단함으로써, 복수의 발광부를 포함하는 반도체 발광소자가 제조된다. 절단에 있어서, 스크라이빙 및/또는 브레이킹 공정이 진행될 수 있으며, 화학적 식각공정이 추가될 수도 있다.In this way, the semiconductor light emitting device including the plurality of light emitting parts is manufactured by cutting the individual semiconductor light emitting devices including the plurality of light emitting parts on the wafer. In cutting, the scribing and / or breaking process may proceed, and a chemical etching process may be added.
도 35는 연결 전극의 일 예를 설명하기 위한 도면이다.35 is a diagram for explaining an example of a connection electrode.
연결 전극(92)은 복수개로 형성되며, 장방향(x 방향)으로 이격되어 위치하는 제1 연결 전극(92a), 제2 연결 전극(92b) 및 제3 연결 전극(92c)을 포함한다. 본 예에서, 연결 전극(92)이 3개로 이격되어 위치하도록 한정하였지만, 이에 한정하지 않는다.The connection electrode 92 is formed in plural and includes a first connection electrode 92a, a second connection electrode 92b, and a third connection electrode 92c which are spaced apart in the longitudinal direction (x direction). In this example, the connection electrodes 92 are limited to three spaced apart locations, but the embodiment is not limited thereto.
제1 연결 전극(92a), 제2 연결 전극(92b) 및 제3 연결 전극(92c)은 서로 마주하는 제1 발광부(101) 및 제2 발광부(102)를 장방향(x 방향)으로 전기적으로 연결한다. 이와 같이, 제1 발광부(101) 및 제2 발광부(102)는 연결전극(92)에 의해 장방향(x 방향)으로 병렬 연결되며, 하나의 발광부보다 고전압(high-voltage)으로 구동된다.The first connection electrode 92a, the second connection electrode 92b, and the third connection electrode 92c each have a first light emitting portion 101 and a second light emitting portion 102 facing each other in the long direction (x direction). Connect electrically. As such, the first light emitting part 101 and the second light emitting part 102 are connected in parallel in the long direction (x direction) by the connecting electrode 92 and are driven at a higher voltage than one light emitting part. do.
도 36은 본 개시에 따른 반도체 발광소자의 다른 예를 설명하기 위한 도면이다. 본 예에서, 반도체 발광소자는 광흡수 방지막(41)을 포함한다.36 is a view for explaining another example of the semiconductor light emitting device according to the present disclosure. In this example, the semiconductor light emitting element includes a light absorption prevention film 41.
광흡수 방지막(41)은 제2 반도체층(50)과 전류 확산 전극(60) 사이에 대응하게 구비될 수 있다. 광흡수 방지막(41)은 SiO2, TiO2 등으로 형성될 수 있으며, 활성층(40)에서 발생된 빛의 일부 또는 전부를 반사하는 기능만을 가져도 좋고, 제2 오믹 전극(72)으로부터 바로 아래로 전류가 흐르지 못하도록 하는 기능만을 가져도 좋고, 양자의 기능을 모두 가져도 좋다.The light absorption prevention layer 41 may be provided between the second semiconductor layer 50 and the current diffusion electrode 60. The light absorption prevention layer 41 may be formed of SiO 2, TiO 2, or the like, and may have only a function of reflecting some or all of the light generated in the active layer 40, and may be configured to directly flow down from the second ohmic electrode 72. It may have only a function to prevent the flow of or may have both functions.
도 36에 기재된 광흡수 방지막(41)을 제외하고는 도 34에 기재된 반도체 발광소자와 동일한 특성을 갖는다.Except for the light absorption prevention film 41 shown in FIG. 36, it has the same characteristics as the semiconductor light emitting element shown in FIG.
도 37은 본 개시에 따른 반도체 발광소자의 또 다른 예를 설명하기 위한 도면이다. 본 예에서, 반도체 발광소자는 절연층(35)을 포함한다.37 is a view for explaining another example of the semiconductor light emitting device according to the present disclosure. In this example, the semiconductor light emitting element includes an insulating layer 35.
절연층(35)은 제2 발광부(102)의 제1 반도체층(30)의 측면, 노출된 기판(10), 및 제1 발광부(101)의 복수의 반도체층(30, 40, 50)의 측면에 형성된다.The insulating layer 35 may include the side surfaces of the first semiconductor layer 30 of the second light emitting unit 102, the exposed substrate 10, and the plurality of semiconductor layers 30, 40, and 50 of the first light emitting unit 101. Is formed on the side.
절연층(35)은 투광성을 가지는 패시베이션(passivation)층으로서, SiO2, TiO2, Al2O3와 같은 물질로 식각부(21, 25)에 증착된다. 증착의 두께는 일 예로, 수천 Å일수 있지만, 물론 이 두께는 변경될 수 있다. 본 예에서, 식각부(21, 25)가 제1 발광부(101)와 제2 발광부(102) 사이 전체에 제1 발광부(101) 및 제2 발광부(102)의 서로 마주하는 에지들을 따라 형성되어 있어서 전기적 절연을 더욱 확실히 할 수 있고, 특히, 전술한 바와 같이, 제1 발광부(101)와 제2 발광부(102) 사이가 좁기 때문에, 복수의 발광부를 고전압(high-voltage)으로 동작하는 반도체 발광소자에서는 본 예와 같이 절연층(35)을 형성하는 것이 전기적 절연 측면에서 유리한 점이 많다. 또한, 바람직하게는, 절연층(35)은 제1 발광부(101) 및 제2 발광부(102)의 테두리의 식각부(25)까지 형성되어 전기적 절연의 신뢰성을 더 향상할 수 있다.The insulating layer 35 is a passivation layer having transparency, and is deposited on the etching portions 21 and 25 by using materials such as SiO 2 , TiO 2 , and Al 2 O 3 . The thickness of the deposition can be, for example, thousands of millimeters, but of course the thickness can be varied. In this example, the edges 21 and 25 of the first light emitting part 101 and the second light emitting part 102 face each other between the first light emitting part 101 and the second light emitting part 102. And a plurality of light emitting portions are formed at high-voltage because the distance between the first light emitting portion 101 and the second light emitting portion 102 is narrow, as described above. In the semiconductor light emitting device operating as a), it is advantageous in terms of electrical insulation to form the insulating layer 35 as in this example. In addition, the insulating layer 35 may be formed to the etching portion 25 of the edge of the first light emitting portion 101 and the second light emitting portion 102 to further improve the reliability of electrical insulation.
한편, 도시하지 않았지만, 절연층(35)은 제2 오믹 전극(72)에 대응하여 제2 발광부(102)의 제2 반도체층(50) 위에 형성되며, 연결 전극(92) 에 대응하여 제1 발광부(101)의 제2 반도체층(50) 위에 형성될 수 있다. 이에 따라 절연층(35)은 광흡수 방지막으로도 기능한다. 물론, 절연층(35)과 별개의 공정으로 광흡수 방지막을 형성하는 것도 고려할 수 있으며, 이 경우 절연층(35)를 더 두껍게 형성하는 것도 가능하다.Although not illustrated, the insulating layer 35 is formed on the second semiconductor layer 50 of the second light emitting part 102 in correspondence with the second ohmic electrode 72, and corresponds to the connection electrode 92. 1 may be formed on the second semiconductor layer 50 of the light emitting unit 101. Accordingly, the insulating layer 35 also functions as a light absorption prevention film. Of course, it may be considered to form a light absorption prevention film in a separate process from the insulating layer 35, in which case it is also possible to form a thicker insulating layer 35.
연결 전극(92)은 제1 발광부(101)와 제2 발광부(102) 사이의 절연층(35) 위를 가로지르며, 제1 발광부(101)와 제2 발광부(102)를 전기적으로 연결한다.The connection electrode 92 intersects the insulating layer 35 between the first light emitting part 101 and the second light emitting part 102, and electrically connects the first light emitting part 101 and the second light emitting part 102. Connect with
제1 발광부(101) 및 제2 발광부(102)는 주변의 복수의 반도체층(30, 40, 50)이 제거(예: 메사 식각)되어 트렌치(trench) 또는, 식각부(21, 25)가 형성된다.The first light emitting part 101 and the second light emitting part 102 are trenched or removed as the plurality of semiconductor layers 30, 40, and 50 are removed (eg, mesa etching). ) Is formed.
식각부(21, 25)에서 복수의 반도체층(30, 40, 50)이 제거되어 기판(10)이 노출될 수도 있지만, 복수의 반도체층(30, 40, 50)과 기판(10) 사이에 추가의 층이 노출될 수도 있다. 웨이퍼에 형성된 복수의 반도체 발광소자가 제1 발광부(101) 및 제2 발광부(102)의 외곽(테두리)의 식각부(25)에서 분리되어 개별 반도체 발광소자로 제조된다. 본 예에서, 위에서 볼 때, 제1 발광부(101) 및 제2 발광부(102)는 대략 사각 형상을 가지며, 에지가 서로 마주하도록 구비된다. 제1 발광부(101) 및 제2 발광부(102)의 사이와 제1 발광부(101) 및 제2 발광부(102)의 테두리는 복수의 반도체층(30, 40, 50)이 제거되어 식각부(21, 25)가 되며, 기판(10)이 노출될 수 있다. 이러한 식각부(21, 25)에 의해 제1 발광부(101) 및 제2 발광부(102)는 자체로는 전기적으로 분리(isolation) 또는 절연되어 있다. 복수의 반도체층(30, 40, 50)은 발광영역이 되므로 식각부(21, 25)로 인한 복수의 반도체층(30, 40, 50)의 감소를 줄이는 것이 바람직한데, 개별 반도체 발광소자로 분리를 위해 상기 테두리의 식각부(25)는 어느 정도 폭이 필요하다. 본 예에서, 제1 발광부(101) 및 제2 발광부(102) 사이의 식각부(21)의 폭은 제1 발광부(101) 및 제2 발광부(102) 테두리의 식각부(25)의 폭보다 좁게 형성되어, 테두리의 마진을 확보하면서 복수의 반도체층(30, 40, 50)의 감소를 억제한다. 여기서 테두리의 식각부의 폭은 웨이퍼 상에서 복수의 반도체 발광소자 사이의 식각부의 폭을 의미하거나, 개별 소자로 분리된 반도체 발광소자의 테두리의 식각부(25)를 의미할 수도 있다.Although the plurality of semiconductor layers 30, 40, and 50 may be removed from the etching portions 21 and 25 to expose the substrate 10, the semiconductor layers 30, 40, and 50 may be exposed between the plurality of semiconductor layers 30, 40, and 50. Additional layers may be exposed. A plurality of semiconductor light emitting devices formed on the wafer are separated from the etching part 25 of the outer edges of the first light emitting part 101 and the second light emitting part 102 to be manufactured as individual semiconductor light emitting devices. In this example, when viewed from above, the first light emitting portion 101 and the second light emitting portion 102 have a substantially rectangular shape and are provided so that the edges face each other. A plurality of semiconductor layers 30, 40, and 50 are removed between the first light emitting part 101 and the second light emitting part 102 and the edges of the first light emitting part 101 and the second light emitting part 102. Etch portions 21 and 25 may be exposed and the substrate 10 may be exposed. By the etching parts 21 and 25, the first light emitting part 101 and the second light emitting part 102 are electrically isolated or insulated by themselves. Since the plurality of semiconductor layers 30, 40, and 50 become light emitting regions, it is desirable to reduce the reduction of the plurality of semiconductor layers 30, 40, and 50 due to the etching portions 21 and 25. For the etch portion 25 of the rim needs a certain width. In this example, the width of the etching portion 21 between the first light emitting portion 101 and the second light emitting portion 102 is the etching portion 25 of the edge of the first light emitting portion 101 and the second light emitting portion 102. It is formed to be narrower than the width of), and the reduction of the plurality of semiconductor layers 30, 40, 50 is suppressed while securing margins of the edges. The width of the edge portion of the edge may mean the width of the edge portion of the plurality of semiconductor light emitting elements on the wafer, or may mean the edge portion 25 of the edge of the semiconductor light emitting element separated into individual elements.
도 37에 기재된 식각부(21, 25) 및 절연층(35)을 제외하고는 도 34에 기재된 반도체 발광소자와 동일한 특성을 갖는다.Except for the etching portions 21 and 25 and the insulating layer 35 shown in FIG. 37, the semiconductor light emitting device has the same characteristics as the semiconductor light emitting device shown in FIG.
도 38은 본 개시에 따른 반도체 발광소자의 또 다른 예를 설명하기 위한 도면이다. 본 예에서 반도체 발광소자는 기판(110) 위에 서로 마주보도록 형성된 제1 발광부(103) 및 제2 발광부(104), 연결 전극(192), 반사층(191), 절연층(195), 제1 내지 제4 전기적 연결(181, 183, 171, 173), 제1 및 제2 중간 연결층(180, 170), 제1 패드 전극(184), 제2 패드 전극(174)을 포함한다. 여기서, 반사층(191) 위에 위치하는 절연층(195), 제1 중간 연결층(180), 제2 전기적 연결(183), 제1 패드 전극(184), 제2 중간 연결층(170), 제4 전기적 연결(173), 제2 패드 전극(174)을 제외하고는 도 34에 도시된 반도체 발광소자와 동일한 특성을 갖는다.38 is a view for explaining another example of the semiconductor light emitting device according to the present disclosure. In this example, the semiconductor light emitting device includes the first light emitting part 103 and the second light emitting part 104, the connection electrode 192, the reflective layer 191, the insulating layer 195, and the first light emitting part 103 formed to face each other on the substrate 110. 1 to 4 electrical connections 181, 183, 171, and 173, first and second intermediate connection layers 180 and 170, first pad electrodes 184, and second pad electrodes 174. Here, the insulating layer 195, the first intermediate connection layer 180, the second electrical connection 183, the first pad electrode 184, the second intermediate connection layer 170, and the first intermediate connection layer 180 disposed on the reflective layer 191 are formed. Except for the electrical connection 173 and the second pad electrode 174, the semiconductor light emitting device has the same characteristics as the semiconductor light emitting device illustrated in FIG. 34.
본 예에서, 제1 발광부(103) 및 제2 발광부(104)는 반사층(191) 위에 위치하며, 제1 전기적 연결(181), 제3 전기적 연결(171) 및 연결 전극(192)을 덮는 절연층(195)을 포함한다. 절연층(195)은 SiO2로 이루어질 수 있다.In this example, the first light emitting unit 103 and the second light emitting unit 104 are positioned on the reflective layer 191, and the first electrical connection 181, the third electrical connection 171, and the connection electrode 192 are disposed. Covering insulating layer 195. The insulating layer 195 may be made of SiO 2 .
제1 전기적 연결(181)은 반사층(191)을 관통하며, 식각되어 노출된 제1 반도체층(130)과 전기적으로 연통된다. 제3 전기적 연결(171)은 반사층(191)을 관통하며, 제2 반도체층(150)과 전기적으로 연통된다. 제1 전기적 연결(181)과 제1 반도체층(130) 사이에는 접촉저항 감소와 안정적 전기적 연결을 위해 제1 오믹 전극(182)이 개재될 수 있고, 제3 전기적 연결(171)과 제2 반도체층(150) 사이에는 접촉저항 감소와 안정적 전기적 연결을 위해 제2 오믹 전극(172)이 개재될 수 있다.The first electrical connection 181 passes through the reflective layer 191 and is in electrical communication with the exposed first semiconductor layer 130. The third electrical connection 171 passes through the reflective layer 191 and is in electrical communication with the second semiconductor layer 150. The first ohmic electrode 182 may be interposed between the first electrical connection 181 and the first semiconductor layer 130 to reduce contact resistance and provide stable electrical connection, and the third electrical connection 171 and the second semiconductor may be interposed therebetween. The second ohmic electrode 172 may be interposed between the layers 150 to reduce contact resistance and provide stable electrical connection.
연결 전극(192)의 일 측 끝은 제2 반도체층(150)과 반사층(191) 사이에서 제2 반도체층(150)과 전기적으로 연통되며, 연결 전극(192)의 타 측 끝은 제2 반도체층(150) 및 활성층(140)이 식각되어 노출된 제1 반도체층(130)과 전기적으로 연통된다.One end of the connection electrode 192 is in electrical communication with the second semiconductor layer 150 between the second semiconductor layer 150 and the reflective layer 191, and the other end of the connection electrode 192 is the second semiconductor. The layer 150 and the active layer 140 are etched in electrical communication with the exposed first semiconductor layer 130.
제1 패드 전극(184) 및 제2 패드 전극(174) 각각은 제1 발광부(103) 및 제2 발광부(104)에 대응하여 절연층(195) 위에 형성된다.Each of the first pad electrode 184 and the second pad electrode 174 is formed on the insulating layer 195 corresponding to the first light emitting part 103 and the second light emitting part 104.
제1 패드 전극(184)은 절연층(195)를 관통하여 제2 전기적 연결(183)을 통해 제1 전기적 연결(181)과 전기적으로 연결되어 제1 반도체층(130)에 전자를 공급한다.The first pad electrode 184 penetrates through the insulating layer 195 and is electrically connected to the first electrical connection 181 through the second electrical connection 183 to supply electrons to the first semiconductor layer 130.
제2 전기적 연결(183)과 제1 전기적 연결(181) 사이에는 접촉저항 감소와 안정적 전기적 연결을 위해 제1 중간 연결층(180)이 개재될 수 있다.The first intermediate connection layer 180 may be interposed between the second electrical connection 183 and the first electrical connection 181 to reduce contact resistance and provide stable electrical connection.
제2 패드 전극(174)은 절연층(195)을 관통하여 제4 전기적 연결(173)을 통해 제3 전기적 연결(171)과 전기적으로 연결되어 제2 반도체층(150)에 정공을 공급한다. The second pad electrode 174 penetrates through the insulating layer 195 and is electrically connected to the third electrical connection 171 through the fourth electrical connection 173 to supply holes to the second semiconductor layer 150.
제4 전기적 연결(173)과 제2 전기적 연결(171) 사이에는 접촉저항 감소와 안정적 전기적 연결을 위해 제2 중간 연결층(170)이 개재될 수 있다.The second intermediate connection layer 170 may be interposed between the fourth electrical connection 173 and the second electrical connection 171 to reduce contact resistance and provide stable electrical connection.
이하 본 개시의 다양한 실시 형태에 대하여 설명한다.Hereinafter, various embodiments of the present disclosure will be described.
(1) 반도체 발광소자에 있어서, 제1 도전성을 가지는 제1 반도체층, 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층 및 제1 반도체층과 제2 반도체층 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 가지는 복수의 반도체층; 활성층에서 생성된 빛을 제1 반도체층 측으로 반사하도록 복수의 반도체층 위에 형성된 반사막; 제1 반도체층과 전기적으로 연결되며 전자와 정공 중 하나를 공급하는 제1 전극부; 제2 반도체층과 전기적으로 연결되며 전자와 정공 중 나머지 하나를 공급하는 제2 전극부; 그리고 복수의 반도체층과 반사막 사이에 개재되는 전극 표시부를 포함하는 반도체 발광소자.(1) A semiconductor light emitting device comprising: a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and interposed between the first semiconductor layer and the second semiconductor layer and having electrons and holes A plurality of semiconductor layers having an active layer that generates light through recombination of the semiconductors; A reflection film formed on the plurality of semiconductor layers to reflect light generated in the active layer toward the first semiconductor layer; A first electrode part electrically connected to the first semiconductor layer and supplying one of electrons and holes; A second electrode part electrically connected to the second semiconductor layer and supplying the other one of electrons and holes; And an electrode display unit interposed between the plurality of semiconductor layers and the reflective film.
(2) 전극 표시부는 제1 전극부 및 제2 전극부와 중첩되어 위치하지 않는 반도체 발광소자.(2) A semiconductor light emitting element in which the electrode display portion does not overlap with the first electrode portion and the second electrode portion.
(3) 전극 표시부는 제1 전극부와 제2 전극부 사이에 위치하는 반도체 발광소자.(3) The electrode display unit is a semiconductor light emitting element located between the first electrode portion and the second electrode portion.
(4) 전극 표시부는 제1 전극부 또는 제2 전극부 중 적어도 하나의 물질과 동일한 물질로 이루어지는 반도체 발광소자.(4) The semiconductor light emitting device comprising the same material as at least one of the first electrode portion and the second electrode portion.
(5) 전극 표시부의 크기는 100㎛ 이하인 반도체 발광소자.(5) The semiconductor light emitting element having a size of the electrode display portion of 100 µm or less.
(6) 전극 표시부의 두께는 5㎛ 이하인 반도체 발광소자.(6) The semiconductor light emitting element having a thickness of 5 μm or less of the electrode display portion.
(7) 제1 전극부 및 제2 전극부 각각은 반사막과 절연층 사이에 위치하는 연결전극; 을 포함하는 반도체 발광소자.(7) each of the first electrode portion and the second electrode portion includes a connecting electrode positioned between the reflective film and the insulating layer; Semiconductor light emitting device comprising a.
(8) 절연층 위에 형성된 제1 전극부 및 제2 전극부는 각각 상부 전극; 을 포함하는 반도체 발광소자.(8) a first electrode portion and a second electrode portion formed on the insulating layer, respectively, an upper electrode; Semiconductor light emitting device comprising a.
(9) 반사막은 비도전성 반사막으로서, 분포 브래그 리플렉터(DBR: Distributed Bragg Reflector)을 포함하는 반도체 발광소자.(9) A semiconductor light emitting element comprising a distributed Bragg reflector (DBR) as a non-conductive reflecting film.
(10) 반사막의 위에 형성된 절연층; 을 포함하는 반도체 발광소자.(10) an insulating layer formed on the reflective film; Semiconductor light emitting device comprising a.
(11) 반도체 발광소자에 있어서, 제1 도전성을 가지는 제1 반도체층, 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층 및 제1 반도체층과 제2 반도체층 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 가지는 복수의 반도체층; 활성층에서 생성된 빛을 제1 반도체층 측으로 반사하도록 복수의 반도체층 위에 형성된 비도전성 반사막; 비도전성 반사막의 위에 형성된 절연층; 제1 반도체층과 전기적으로 연결되며 전자와 정공 중 하나를 공급하는 제1 전극부; 제2 반도체층과 전기적으로 연결되며 전자와 정공 중 나머지 하나를 공급하는 제2 전극부; 그리고 비도전성 반사막과 절연층 사이에 개재되는 전극 표시부를 포함하는 반도체 발광소자.(11) A semiconductor light emitting device comprising: a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and interposed between the first semiconductor layer and the second semiconductor layer and having electrons and holes A plurality of semiconductor layers having an active layer that generates light through recombination of the semiconductors; A non-conductive reflecting film formed over the plurality of semiconductor layers to reflect light generated in the active layer toward the first semiconductor layer; An insulating layer formed on the nonconductive reflecting film; A first electrode part electrically connected to the first semiconductor layer and supplying one of electrons and holes; A second electrode part electrically connected to the second semiconductor layer and supplying the other one of electrons and holes; And an electrode display disposed between the nonconductive reflecting film and the insulating layer.
(12) 제1 전극부와 제2 전극부 중 적어도 하나는: 비도전성 반사막 위에 형성된 연결 전극; 비도전성 반사막을 관통하여 연결 전극과 복수의 반도체층을 전기적으로 연결하는 제1 전기적 연결; 절연성 반사층 위에 형성된 패드 전극; 그리고 절연성 반사층을 관통하여 패드 전극과 연결 전극을 전기적으로 연결하는 제2 전기전 연결을 포함하는 반도체 발광소자.(12) At least one of the first electrode portion and the second electrode portion includes: a connection electrode formed on the nonconductive reflecting film; A first electrical connection penetrating the non-conductive reflective film to electrically connect the connection electrode and the plurality of semiconductor layers; A pad electrode formed on the insulating reflective layer; And a second electrical connection connecting the pad electrode and the connection electrode to penetrate through the insulating reflective layer.
(13) 전극 표시부는 제1 전극부의 패드 전극과 제2 전극부의 패드 전극 중 적어도 하나의 패드 전극 아래에 위치하는 반도체 발광소자.(13) A semiconductor light emitting element, wherein the electrode display portion is positioned under at least one pad electrode of a pad electrode of the first electrode portion and a pad electrode of the second electrode portion.
(14) 전극 표시부는 연결 전극과 동일한 층에 위치하는 반도체 발광소자.(14) A semiconductor light emitting element in which the electrode display portion is located on the same layer as the connection electrode.
(15) 전극 표시부는 연결 전극과 중첩되어 위치하지 않는 반도체 발광소자.15. A semiconductor light emitting element in which the electrode display portion does not overlap with the connection electrode.
(16) 전극 표시부는 제2 전기적 연결의 개구보다 크게 형성되는 반도체 발광소자.(16) A semiconductor light emitting element in which the electrode display portion is formed larger than the opening of the second electrical connection.
(17) 전극 표시부는 복수개의 홀을 포함하는 반도체 발광소자.(17) A semiconductor light emitting device comprising electrode holes in a plurality of holes.
(18) 전극 표시부는 원형, 삼각형, 사각형 등의 섬형으로 이루어진 반도체 발광소자.(18) A semiconductor light emitting element in which the electrode display portion is made of islands such as circles, triangles, squares, and the like.
(19) 제1 전극부 및 제2 전극부는 서로 대칭적으로 배치되어 형성되는 반도체 발광소자. 특히, 제1 전극부 및 제2 전극부는 연결 전극을 중심으로 대칭적으로 배열되어 있다.(19) A semiconductor light emitting element, wherein the first electrode portion and the second electrode portion are formed symmetrically with each other. In particular, the first electrode portion and the second electrode portion are symmetrically arranged around the connection electrode.
(20) 비도전성 반사막은 분포 브래그 리플렉터(DBR: Distributed Bragg Reflector)을 포함하는 반도체 발광소자.(20) A semiconductor light emitting device in which the nonconductive reflecting film includes a distributed Bragg reflector (DBR).
(21) 반도체 발광소자에 있어서, 제1 도전성을 가지는 제1 반도체층, 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층, 제1 반도체층과 제2 반도체층 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 구비하며, 성장 기판을 이용하여 성장되는 복수의 반도체층; 전자와 정공을 공급하는 제1 전극 및 제2 전극;으로서, 제1 반도체층과 전기적으로 연결된 제1 전극 및 제2 반도체층과 전기적으로 연결된 제2 전극; 그리고 제2 반도체층 위에 위치하는 투광성 도전막;을 포함하고, 제2 전극에 대응하는 제1 영역에 위치하는 투광성 도전막의 제1 두께는 제1 영역을 제외한 나머지 제2 영역에 위치하는 투광성 도전막의 제2 두께보다 두꺼운 반도체 발광소자.(21) A semiconductor light emitting device comprising: a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and interposed between the first semiconductor layer and the second semiconductor layer and having electrons and holes A plurality of semiconductor layers having an active layer for generating light through recombination of and grown using a growth substrate; A first electrode and a second electrode supplying electrons and holes, comprising: a first electrode electrically connected to the first semiconductor layer and a second electrode electrically connected to the second semiconductor layer; And a light-transmissive conductive film positioned on the second semiconductor layer, wherein the first thickness of the light-transmissive conductive film located in the first region corresponding to the second electrode is equal to that of the light-transmissive conductive film positioned in the second region except the first region. A semiconductor light emitting element thicker than the second thickness.
(22) 제1 영역의 제1 두께는 제2 영역의 제2 두께보다 최소 2배 이상의 두께를 갖는 반도체 발광소자.(22) A semiconductor light emitting device, wherein the first thickness of the first region has a thickness of at least two times or more than the second thickness of the second region.
(23) 투광성 도전막은: 제1 영역 및 제2 영역에 전체적으로 위치하며 하나의 층으로 형성되는 제1 도전막; 그리고 제2 영역에 부분적으로 위치하며 제2 전극과 제1 도전막 사이에 형성되는 제2 도전막;을 포함하는 반도체 발광소자.(23) The light-transmissive conductive film includes: a first conductive film which is entirely formed in the first region and the second region and formed of one layer; And a second conductive film partially positioned in the second region and formed between the second electrode and the first conductive film.
(24) 제1 도전막 및 제2 도전막은 동일한 물질 및 동일한 두께로 형성되는 반도체 발광소자.(24) A semiconductor light emitting element, wherein the first conductive film and the second conductive film are formed of the same material and the same thickness.
(25) 제2 도전막의 폭은 제1 도전막의 폭보다 작게 형성되는 반도체 발광소자.The width of the second conductive film is smaller than the width of the first conductive film.
(26) 제2 도전막의 폭은 제2 전극의 폭과 동일하거나 넓게 형성되는 반도체 발광소자.(26) A semiconductor light emitting element, wherein the width of the second conductive film is equal to or wider than that of the second electrode.
(27) 제2 반도체층과 투광성 도전막 사이에 개재되는 빛흡수 방지막;을 포함하고, 빛흡수 방지막은 제1 영역에 위치하는 반도체 발광소자.(27) a light absorption prevention film interposed between the second semiconductor layer and the transparent conductive film; wherein the light absorption prevention film is located in the first region.
(28) 빛흡수 방지막과 투광성 도전막 사이에 개재되는 빛흡수 차단막;을 더 포함하고, 빛흡수 차단막은 제1 영역에 위치하는 반도체 발광소자.(28) a light absorption blocking film interposed between the light absorption prevention film and the transparent conductive film; wherein the light absorption blocking film is positioned in the first region.
(29) 빛흡수 방지막 및 빛흡수 차단막은 서로 다른 물질로 이루어지는 반도체 발광소자.(29) The light absorption prevention film and the light absorption blocking film are semiconductor light emitting devices made of different materials.
(30) 반도체 발광소자에 있어서, 제1 도전성을 가지는 제1 반도체층, 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층, 제1 반도체층과 제2 반도체층 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 구비하며, 성장 기판을 이용하여 성장되는 복수의 반도체층; 전자와 정공을 공급하는 제1 전극 및 제2 전극;으로서, 제1 반도체층과 전기적으로 연결된 제1 전극 및 제2 반도체층과 전기적으로 연결된 제2 전극; 제2 반도체층 위에 위치하는 투광성 도전막; 제2 반도체층과 투광성 도전막 사이에 개재되는 빛흡수 방지막; 빛흡수 방지막과 투광성 도전막 사이에 개재되는 빛흡수 차단막;을 포함하고, 빛흡수 방지막과 빛흡수 차단막은 서로 다른 물질로 이루어지는 반도체 발광소자.(30) A semiconductor light emitting device comprising: a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and interposed between the first semiconductor layer and the second semiconductor layer and having electrons and holes A plurality of semiconductor layers having an active layer for generating light through recombination of and grown using a growth substrate; A first electrode and a second electrode supplying electrons and holes, comprising: a first electrode electrically connected to the first semiconductor layer and a second electrode electrically connected to the second semiconductor layer; A translucent conductive film on the second semiconductor layer; A light absorption prevention film interposed between the second semiconductor layer and the transparent conductive film; And a light absorption blocking layer interposed between the light absorption prevention film and the light-transmitting conductive film, wherein the light absorption prevention film and the light absorption blocking film are made of different materials.
제1 전극은 상기 설명에서 제1 패드 전극에 대응하고, 제2 전극은 상기 설명에서 제2 패드 전극에 대응할 수 있다. 반대로 제1 패드 전극은 상기 설명에서 제1 전극에 대응하고, 제2 패드 전극은 상기 설명에서 제1 전극에 대응할 수 있다.The first electrode may correspond to the first pad electrode in the above description, and the second electrode may correspond to the second pad electrode in the above description. In contrast, the first pad electrode may correspond to the first electrode in the above description, and the second pad electrode may correspond to the first electrode in the above description.
빛흡수 차단막은 가지 전극으로도 기능할 수 있다.The light absorption barrier may also function as a branch electrode.
(31) 빛흡수 방지막은 SiO2, SiN, AlOx, SiON 및 TiO2중 적어도 하나로 이루어지는 반도체 발광소자.The light absorption prevention film is a semiconductor light emitting element comprising at least one of SiO 2 , SiN, AlO x , SiON, and TiO 2 .
(32) 빛흡수 차단막은 알루미늄(Al), 은(Ag), 분포 브래그 리플렉터(DBR: Distributed Bragg Reflector) 및 고반사 백색 반사물질 중 적어도 하나로 이루어지는 반도체 발광소자.(32) The light absorption blocking film is a semiconductor light emitting device comprising at least one of aluminum (Al), silver (Ag), a distributed Bragg reflector (DBR) and a highly reflective white reflecting material.
(33) 흡수 방지막의 두께는 빛흡수 차단막의 두께와 동일한 반도체 발광소자.(33) A semiconductor light emitting element in which the thickness of the absorption prevention film is the same as that of the light absorption blocking film.
(34) 빛흡수 방지막 및 빛흡수 차단막의 두께는 약 1000Å 이상인 반도체 발광소자.(34) The semiconductor light emitting device having a thickness of light absorption preventing film and light absorption blocking film of about 1000 GPa or more.
(35) 빛흡수 방지막 및 빛흡수 차단막은 제2 전극에 대응하여 위치하는 반도체 발광소자.35. A semiconductor light emitting device, wherein the light absorption prevention film and the light absorption blocking film are positioned corresponding to the second electrode.
(36) 빛흡수 차단막은 제2 전극의 폭과 동일하거나 넓게 형성되는 반도체 발광소자.(36) The light absorption blocking film is a semiconductor light emitting device which is formed to be equal to or wider than the width of the second electrode.
(37) 빛흡수 방지막은 빛흡수 차단막의 폭과 동일하거나 넓게 형성되는 반도체 발광소자.(37) The light absorption prevention film is a semiconductor light emitting element formed with the same or wider width of the light absorption blocking film.
(38) 빛흡수 방지막 및 빛흡수 차단막은 섬 형태로 형성되는 반도체 발광소자.The light absorption prevention film and the light absorption blocking film are formed in an island shape.
(39) 빛흡수 차단막은 제2 전극과 접촉하는 면에 부도체층;을 더 구비하는 반도체 발광소자.(39) The light absorption blocking film further comprises a non-conductive layer on the surface in contact with the second electrode.
(40) 반도체 발광소자에 있어서, 장방향으로 형성된 제1 발광부 및 제2 발광부로서, 제1 도전성을 가지는 제1 반도체층, 전자와 정공의 재결합을 통해 빛을 생성하는 활성층 및 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층이 순차로 적층된 복수의 반도체층;을 포함하는 제1 발광부 및 제2 발광부; 장방향으로 형성되며, 제1 발광부 및 제2 발광부를 전기적으로 연결하는 연결 전극; 제1 발광부, 제2 발광부 및 연결 전극을 덮도록 형성되며, 활성층에서 생성된 빛을 반사하는 반사층; 제1 발광부의 제1 반도체층과 전기적으로 연통하도록 구비되며, 전자와 정공 중 하나를 공급하는 제1 전극부; 그리고, 제2 발광부의 제2 반도체층과 전기적으로 연통하도록 구비되며, 전자와 정공 중 나머지 하나를 공급하는 제2 전극부;를 포함하고, 연결 전극은 제1 발광부 및 제2 발광부와 일부 중첩되어 위치하는 반도체 발광소자.(40) A semiconductor light emitting device comprising: a first light emitting portion and a second light emitting portion formed in a longitudinal direction, a first semiconductor layer having a first conductivity, an active layer for generating light through recombination of electrons and holes, and a first conductivity A plurality of semiconductor layers in which a second semiconductor layer having a second conductivity different from the first semiconductor layer is sequentially stacked; A connection electrode formed in a long direction and electrically connecting the first light emitting part and the second light emitting part; A reflective layer formed to cover the first light emitting part, the second light emitting part, and the connection electrode, and reflecting light generated by the active layer; A first electrode part provided to be in electrical communication with the first semiconductor layer of the first light emitting part and supplying one of electrons and holes; And a second electrode part provided to be in electrical communication with the second semiconductor layer of the second light emitting part and supplying the other one of electrons and holes, wherein the connection electrode is partially connected to the first light emitting part and the second light emitting part. A semiconductor light emitting device which is positioned overlapping.
(41) 연결 전극은 제1 발광부 및 제2 발광부 중 적어도 하나의 발광부 길이와 동일하거나 짧은 길이를 갖는 반도체 발광소자.The connection electrode has a length equal to or shorter than a length of at least one of the first light emitting part and the second light emitting part.
(42) 연결 전극은 복수개로 이루어지며, 복수의 연결 전극은 제1 발광부 및 제2 발광부 중 적어도 하나의 발광부 보다 짧은 길이를 가지며, 장방향으로 서로 이격되어 위치하는 반도체 발광소자.42. A semiconductor light emitting device comprising a plurality of connection electrodes, wherein the plurality of connection electrodes have a length shorter than at least one of the first and second light emitting parts, and are spaced apart from each other in the longitudinal direction.
(43) 연결 전극은 서로 마주하여 위치하는 제1 발광부 및 제2 발광부의 제1 반도체층과 제2 반도체층을 전기적으로 연결하는 반도체 발광소자.The connecting electrode electrically connects the first semiconductor layer and the second semiconductor layer of the first light emitting part and the second light emitting part to face each other.
(44) 반도체 발광소자는 플립칩(flip chip)으로서, 제1 전극부는: 제1 발광부의 반사층 위에 형성된 제1 전극; 그리고 반사층을 관통하여 제1 발광부의 제1 반도체층과 제1 전극을 전기적으로 연통하는 제1 전기적 연결;을 포함하고, 제2 전극부는: 제2 발광부의 반사층 위에 형성된 제2 전극; 그리고 반사층을 관통하여 제2 발광부의 제2 반도체층과 제2 전극을 전기적으로 연통하는 제2 전기적 연결;을 포함하는 반도체 발광소자.(44) The semiconductor light emitting element is a flip chip, wherein the first electrode portion comprises: a first electrode formed on the reflective layer of the first light emitting portion; And a first electrical connection penetrating the reflective layer to electrically connect the first semiconductor layer and the first electrode of the first light emitting part, wherein the second electrode part comprises: a second electrode formed on the reflective layer of the second light emitting part; And a second electrical connection penetrating the reflective layer to electrically connect the second semiconductor layer and the second electrode of the second light emitting unit.
(45) 반사층 위에 형성된 절연층;을 포함하고, 제1 전극부는: 제1 발광부의 반사층 위에 형성된 제1 중간 연결층; 반사층을 관통하여 제1 발광부의 제1 반도체층과 제1 중간 연결층을 전기적으로 연통하는 제1 전기적 연결; 제1 발광부의 절연층 위에 형성된 제1 패드 전극; 그리고 절연층을 관통하여 제1 중간 연결층과 제1 패드 전극을 전기적으로 연통하는 제2 전기적 연결;을 포함하고, 제2 전극부는:An insulating layer formed on the reflective layer, wherein the first electrode part comprises: a first intermediate connection layer formed on the reflective layer of the first light emitting part; A first electrical connection penetrating the reflective layer to electrically communicate the first semiconductor layer and the first intermediate connection layer of the first light emitting part; A first pad electrode formed on the insulating layer of the first light emitting part; And a second electrical connection penetrating the insulating layer to electrically connect the first intermediate connection layer and the first pad electrode.
제2 발광부의 반사층 위에 형성된 제2 중간 연결층; 반사층을 관통하여 제2 발광부의 제2 반도체층과 제2 중간 연결층을 전기적으로 연통하는 제3 전기적 연결; 제2 발광부의 절연층 위에 형성된 제2 패드 전극; 그리고 절연층을 관통하여 제2 중간 연결층과 제2 패드 전극을 전기적으로 연통하는 제4 전기적 연결;을 포함하는 반도체 발광소자.A second intermediate connecting layer formed on the reflective layer of the second light emitting part; A third electrical connection penetrating the reflective layer to electrically connect the second semiconductor layer and the second intermediate connection layer of the second light emitting part; A second pad electrode formed on the insulating layer of the second light emitting part; And a fourth electrical connection penetrating through the insulating layer to electrically connect the second intermediate connection layer and the second pad electrode.
(46) 절연층은 SiO2를 포함하며, 반사층은 절연성을 가지며, 분포 브래그 리플렉터(Distributed Bragg Reflector) 및 ODR(Omni-Directional Reflector) 중 하나를 포함하는 반도체 발광소자.(46) A semiconductor light emitting device, wherein the insulating layer comprises SiO 2 , and the reflective layer is insulating and includes one of a distributed Bragg reflector and an Omni-Directional Reflector (ODR).
본 개시에 따른 하나의 반도체 발광소자에 의하면, 전극의 극성을 표시하기 위해 홈 또는 노치를 형성하지 않고, 별도의 전극 표시부를 이용하여 각각의 전극의 극성을 용이하게 표시할 수 있다.According to one semiconductor light emitting device according to the present disclosure, the polarity of each electrode may be easily displayed using a separate electrode display unit without forming a groove or notch to display the polarity of the electrode.
본 개시에 따른 반도체 발광소자에 의하면, 별도의 전극 표시부를 구비하지 않고, 연결 전극의 형상에 섬형 전극 표시부로 이루어짐으로써, 공정의 간소화할 수 있다.According to the semiconductor light emitting device according to the present disclosure, the process can be simplified by forming an island type electrode display unit in the shape of the connection electrode without providing a separate electrode display unit.
본 개시에 따르면, 전극에 대응하여 위치하는 투광성 도전막의 두께를 다른 부분의 두께보다 두껍게 형성함으로써, 광 추출 효율(extraction efficiency)의 감소 없이 전류 확산을 원활하게 할 수 있다.According to the present disclosure, the thickness of the transparent conductive film positioned in correspondence with the electrode is made thicker than the thickness of other portions, so that the current spreading can be smoothly performed without reducing the extraction efficiency.
따라서, 전류 확산이 원활하게 이루어짐으로써, 빛의 균일성이 향상되고 빛의 투과율이 증가하여 반도체 발광소자의 광 추출 효율을 향상시킬 수 있다.Therefore, since the current is smoothly spread, the light uniformity is improved and the light transmittance is increased to improve the light extraction efficiency of the semiconductor light emitting device.
본 개시에 따르면 서로 물질이 상이한 빛흡수 방지막을 이중막으로 형성함으로써, 패드 전극 측으로 빛이 흡수되는 것을 방지하여 빛 흡수량을 감소시킬 수 있다.According to the present disclosure, by forming a light absorption prevention film having different materials from each other into a double layer, it is possible to prevent light from being absorbed to the pad electrode side, thereby reducing the light absorption amount.
또한 패드 전극 아래에 반사율이 높은 빛흡수 방지막을 추가로 형성하여 빛의 흡수가 감소하므로, 반도체 발광소자의 광 추출 효율(extraction efficiency)을 향상시킬 수 있다.In addition, since a light absorption prevention film having a high reflectance is further formed under the pad electrode, light absorption is reduced, thereby improving light extraction efficiency of the semiconductor light emitting device.
또한 패드 전극과 빛흡수 방지막 사이에 부도체층이 위치함으로써, 절연 상태를 안정적으로 유지하여 전류 확산을 향상할 수 있다.In addition, since the non-conductive layer is positioned between the pad electrode and the light absorption prevention film, it is possible to maintain the insulating state stably and improve current spreading.
본 개시에 의하면, 장방향으로 서로 마주보도록 형성된 복수의 발광부를 동일한 장방향으로 연결함으로써, 연결의 안정성이 향상될 수 있다.According to the present disclosure, by connecting a plurality of light emitting parts formed to face each other in the longitudinal direction in the same longitudinal direction, the stability of the connection can be improved.
본 개시에 의하면, 장방향으로 복수의 발광부를 연결함으로써, 전류확산의 균일성이 더욱 향상될 수 있다.According to the present disclosure, by connecting a plurality of light emitting units in the long direction, the uniformity of current spreading can be further improved.

Claims (10)

  1. 반도체 발광소자에 있어서,In a semiconductor light emitting device,
    제1 도전성을 가지는 제1 반도체층, 제1 도전성과 다른 제2 도전성을 가지는 제2 반도체층 및 제1 반도체층과 제2 반도체층 사이에 개재되며 전자와 정공의 재결합을 통해 빛을 생성하는 활성층을 가지는 복수의 반도체층;A first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer and generating light through recombination of electrons and holes A plurality of semiconductor layers having;
    활성층에서 생성된 빛을 제1 반도체층 측으로 반사하도록 복수의 반도체층 위에 형성된 반사막;A reflection film formed on the plurality of semiconductor layers to reflect light generated in the active layer toward the first semiconductor layer;
    제1 반도체층과 전기적으로 연결되며 전자와 정공 중 하나를 공급하는 제1 전극부;A first electrode part electrically connected to the first semiconductor layer and supplying one of electrons and holes;
    제2 반도체층과 전기적으로 연결되며 전자와 정공 중 나머지 하나를 공급하는 제2 전극부; 그리고A second electrode part electrically connected to the second semiconductor layer and supplying the other one of electrons and holes; And
    복수의 반도체층과 반사막 사이에 개재되는 전극 표시부를 포함하는 반도체 발광소자.A semiconductor light emitting device comprising an electrode display unit interposed between a plurality of semiconductor layers and a reflective film.
  2. 제1항에 있어서,The method of claim 1,
    전극 표시부는 제1 전극부 및 제2 전극부와 중첩되어 위치하지 않는 반도체 발광소자.The electrode display unit does not overlap the first electrode unit and the second electrode unit.
  3. 제1항에 있어서,The method of claim 1,
    전극 표시부는 제1 전극부와 제2 전극부 사이에 위치하는 반도체 발광소자.The electrode display unit is a semiconductor light emitting element positioned between the first electrode portion and the second electrode portion.
  4. 제1항에 있어서,The method of claim 1,
    전극 표시부는 제1 전극부 또는 제2 전극부 중 적어도 하나의 물질과 동일한 물질로 이루어지는 반도체 발광소자.The electrode display unit is a semiconductor light emitting device made of the same material as at least one of the first electrode portion or the second electrode portion.
  5. 제1항에 있어서,The method of claim 1,
    전극 표시부의 크기는 100㎛ 이하인 반도체 발광소자.A semiconductor light emitting element having a size of an electrode display portion of 100 μm or less.
  6. 제1항에 있어서,The method of claim 1,
    전극 표시부의 두께는 5㎛ 이하인 반도체 발광소자.The thickness of the electrode display unit is a semiconductor light emitting element of 5㎛ or less.
  7. 제1항에 있어서,The method of claim 1,
    제1 전극부 및 제2 전극부 각각은 반사막과 절연층 사이에 위치하는 연결전극; 을 포함하는 반도체 발광소자.Each of the first electrode part and the second electrode part may include a connection electrode positioned between the reflective film and the insulating layer; Semiconductor light emitting device comprising a.
  8. 제1항에 있어서,The method of claim 1,
    절연층 위에 형성된 제1 전극부 및 제2 전극부는 각각 상부 전극; 을 포함하는 반도체 발광소자.A first electrode portion and a second electrode portion formed on the insulating layer, respectively; Semiconductor light emitting device comprising a.
  9. 제1항에 있어서,The method of claim 1,
    반사막은 비도전성 반사막으로서, 분포 브래그 리플렉터(DBR: Distributed Bragg Reflector)을 포함하는 반도체 발광소자.The reflective film is a non-conductive reflecting film, and includes a distributed Bragg reflector (DBR).
  10. 제1항에 있어서,The method of claim 1,
    반사막의 위에 형성된 절연층; 을 포함하는 반도체 발광소자.An insulating layer formed on the reflective film; Semiconductor light emitting device comprising a.
PCT/KR2017/010728 2016-09-27 2017-09-27 Semiconductor light emitting element WO2018062852A1 (en)

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KR1020160124002A KR101766329B1 (en) 2016-09-27 2016-09-27 Semiconductor light emitting device
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KR10-2016-0172794 2016-12-16
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KR1020160176550A KR101895227B1 (en) 2016-12-22 2016-12-22 Semiconductor light emitting device
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