WO2018059572A1 - 一种非易失性内存的持久化方法和计算设备 - Google Patents

一种非易失性内存的持久化方法和计算设备 Download PDF

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Publication number
WO2018059572A1
WO2018059572A1 PCT/CN2017/104743 CN2017104743W WO2018059572A1 WO 2018059572 A1 WO2018059572 A1 WO 2018059572A1 CN 2017104743 W CN2017104743 W CN 2017104743W WO 2018059572 A1 WO2018059572 A1 WO 2018059572A1
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Prior art keywords
write instruction
target
memory
instruction set
media
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PCT/CN2017/104743
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English (en)
French (fr)
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卢天越
陈明宇
阮元
杨伟
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华为技术有限公司
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Priority to CN201780059962.6A priority Critical patent/CN110088740B/zh
Priority to JP2019517220A priority patent/JP6878577B2/ja
Priority to KR1020197010570A priority patent/KR102364332B1/ko
Priority to EP17855022.4A priority patent/EP3514690B1/en
Publication of WO2018059572A1 publication Critical patent/WO2018059572A1/zh
Priority to US16/366,325 priority patent/US10976956B2/en

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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
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Definitions

  • the present invention relates to the field of computers, and in particular, to a non-volatile memory (Non-Volatile Memory, NVM for short) method and a computing device.
  • NVM Non-Volatile Memory
  • Data persistence means that data is successfully written to persistent NVM non-volatile memory, and data is not lost in the event of a system crash or power loss. For example, when the application's data has persistent attributes, the application can resume normal operation from the data stored on the NVM after a system crash or power failure. In current applications, NVM is usually used as memory, so that the application can resume from memory directly after a system crash or power failure. However, when NVM is used as memory, the existing DDR (Double Data Rate) memory protocol cannot support data persistence confirmation because the write command in the existing DDR memory protocol writes data to the CPU ( The Central Processing Unit (CPU) will be committed after the cache is completed, and the CPU and application cannot continue to track and know if the data in the write command is actually written to the memory.
  • DDR Double Data Rate
  • the PCOMMIT instruction and the CLFLUSH instruction are used to implement the acknowledgment of the persistence, and the CLFLUSH instruction can write back the specified data in the CPU cache and A write write command is sent to the memory controller.
  • the PCOMMIT instruction forces all write instructions in the memory controller to be written to memory.
  • the memory controller blocks new write instructions from entering the memory controller until all write instructions in the memory controller are sent to the memory chip.
  • the PCOMMIT instruction is used to instruct all write instructions in the memory controller to complete the persistence operation.
  • all write instructions are blocked from entering the memory controller, thus reducing the new write. Instructions are sent to the memory controller to avoid affecting the execution of the PCOMMIT instruction. While achieving the above effects, it will also cause all application write instructions to be temporarily unable to be sent to the memory controller, making the application that calls the PCOMMIT instruction have a large performance impact on other applications, resulting in the operation of the entire system. low efficiency.
  • the technical problem to be solved by the embodiments of the present invention is to provide an NVM persistence method and a computing device.
  • the local write blocking with the minimum set of memory write instruction sets can be realized, and the memory controller is improved. Parallel processing efficiency.
  • the present application provides a method for persisting a non-volatile memory NVM.
  • the memory controller is associated with at least two sets of memory write instructions, and at least two sets of memory write instructions can be set inside the memory controller, for example, at least two sets of memory write instructions are located in the memory space of the memory controller, at least two memory
  • Each memory write instruction set in the set of write instructions is configured with a credit value indicating a number of write instructions allowed to enter the memory write instruction set.
  • the credit value of a memory write instruction is equal to 0, the memory write instruction set The write command is not allowed, and the credit value of each memory write command set has a maximum value.
  • NVM is a memory that can save data after power off.
  • NVM includes but is not limited to Read-Only Memory (ROM), Programmable Read-Only Memory (PROM), and electrically rewritable read-only. Electrically Alterable Read Only Memory (EAROM) erasable programmable read-only memory (Erasable) Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM) and Flash Memory;
  • NVM media controller associated with at least two sets of media write instructions The at least two media write instruction sets may be disposed inside the media controller, for example, the at least two media write instruction sets are located in a buffer space of the media controller, and each media write instruction set configuration in the at least two media write instruction sets There is a credit value, the credit value indicates the number of write instructions allowed to enter the media write instruction set.
  • the credit value of a medium write instruction set When the credit value of a medium write instruction set is equal to 0, the medium write instruction set is not allowed to enter the write instruction, and each medium is written.
  • the credit value of the instruction set has a maximum value.
  • the data structure of the memory write instruction set and the media write instruction set may be a queue, an array, a linked list, a stack, etc., which is not limited in this application.
  • the number of memory write instruction sets in the at least two memory write instruction sets is equal to the number of media write instruction sets in the at least two media write instruction sets, and at least two memory write instruction sets are in a one-to-one mapping relationship with at least two media write instructions.
  • the maximum value of the credit value of each pair of associated memory write instruction sets and media write instruction sets is equal.
  • the persistence method of the present application is applied to a process of writing data to be written to the NVM in the memory, including: the memory controller first receives a write instruction, the write instruction includes a write address of the data to be written, and the write instruction can be sent by the processor, and the memory The controller determines a target memory write instruction set from the at least two memory write instruction sets according to the write address, stores the write instruction into the selected target memory write instruction set, and the target memory write instruction set is at least two memory write instruction sets. In one case, the memory controller reduces the credit value of the target memory write command set by a specified value, and the specified value is a preset value, and the specific value is not limited.
  • the memory controller may select a target memory write instruction set from the at least two memory instruction sets according to a preset selection rule, take a write instruction from the target memory write instruction set, and send the fetched write instruction to the media controller;
  • the media controller receives the write instruction, and determines a target media write instruction set from the at least two media write instruction sets according to the write instruction, the target media write instruction set has a binding relationship with the target memory write instruction set, and the target media write instruction set is at least two.
  • the media controller stores the write instruction in the target media write instruction set, and reduces the credit value of the target media write instruction set by a specified value.
  • the media controller may select a target media write instruction set from the combination of the at least two media write instructions according to a preset selection rule, and extract the write instruction from the target write instruction set;
  • the media controller obtains the write address carried in the write command, and searches the physical block address of the NVM associated with the write address according to the preset address mapping table, and writes the data to be written corresponding to the write command to the physical block corresponding to the physical block address. If the physical block address is not queried in the address mapping table, that is, the physical block address is not allocated, the media controller selects a physical block from the free physical block list for allocation, and establishes the selected physical block in the address mapping table. Mapping of physical block addresses to write addresses;
  • the credit value of the target media write instruction set is increased by a specified value, and the media controller sends the credit value of the target media write instruction set to the memory controller to make the target memory write instruction set.
  • the credit value is synchronized with the credit value of the target media write instruction set.
  • the credit value corresponding to each set of the plurality of memory write instruction sets is synchronized with the credit value corresponding to each of the plurality of media write instruction sets set in the media controller, because the media controller can write the instruction set according to each medium.
  • the credit value determines the execution state of the write command, so after the memory controller and the media controller's credit value are kept in sync, the write command can be accurately checked according to the credit value to complete the persistence.
  • the local blocking of the memory write instruction set can be realized in the persistent query to improve the parallel processing efficiency of the memory controller.
  • the total address interval of the NVM is pre-divided into a plurality of regions that do not coincide with each other.
  • each memory write instruction set in the at least two memory write instruction sets is configured with an address interval of the NVM, and each memory write instruction set in the at least two memory write instruction sets has a different address interval.
  • the memory controller determines a target memory write instruction set from the at least two memory write instruction sets according to the write address, stores the write instruction in the target memory write instruction set, and reduces the credit value of the target memory write instruction set by a specified value, including: memory control
  • the device determines a target address range in which the write address carried in the write command is located, and the target address interval is one of the address ranges in which at least two memory write command sets are respectively configured in advance, and the memory write instruction set associated with the target address interval is written as the target memory.
  • the set of instructions, the specified value is 1, the memory controller stores the write instruction into the target memory write instruction set, and decrements the credit value of the target memory write instruction set by one.
  • the target memory write instruction set is determined according to the address range in which the write address is located, and the write instruction can be quickly and accurately stored, thereby improving processing efficiency.
  • the total address interval of the NVM is pre-divided into a plurality of address intervals that are not coincident with each other, and the number of the address intervals is equal to the number of the medium write instruction sets in the at least two medium write instruction sets, at least Each set of media write instructions in the set of two media write instructions is configured with a different address range.
  • the media controller determines a target media write instruction set from the at least two media write instruction sets according to the write address, stores the write instruction in the target media write instruction set, and reduces the credit value of the target media write instruction set by a specified value, including: the media controller acquires Write a write address carried in the instruction, determine a target address range in which the write address is located, the target address interval is one of address ranges configured by at least two media write instruction sets, and the media controller stores the write instruction in the target medium write instruction set .
  • the data structure of the target medium write instruction set is a queue, and the media controller stores the write instruction in the queue tail of the queue; for example, the data structure of the target medium write instruction set is a stack, and the media controller stores the write instruction on the stack of the stack.
  • Top the default specified value is 1, after the write command is written, the media controller decrements the credit value of the target media write command set by one.
  • the target medium write instruction set is determined by the target address interval in which the write address falls, and the write instruction can be quickly and accurately stored, thereby improving the processing efficiency.
  • the memory controller determines the current credit value of the target memory write instruction set after determining the target memory write instruction set, and determines the current credit degree. If the value is greater than 0, if the judgment result is yes, the write instruction is stored in the target memory write instruction set; if the judgment result is no, the write instruction is cached, and the credit value of the target memory write instruction set is queried according to the preset period. When the credit value of the target memory write instruction set is greater than 0, the cached write instruction is stored in the target memory write instruction set.
  • the number of write commands entering the memory controller is controlled by the credit value, so as to prevent the memory controller from being unable to process the write command in time to cause overload.
  • the target medium write instruction set after determining, by the medium controller, the target medium write instruction set, obtaining a current credit value of the target medium write instruction set, determining whether the current credit value is greater than 0, and if the judgment result is yes, The write instruction is stored in the target medium write instruction set; if the judgment result is no, the write instruction is cached, and the credit value of the target medium write instruction set is queried according to the preset period, and the credit value of the target medium write instruction set is greater than 0 when queried. The cached write command is then stored in the target media write instruction set.
  • the number of write commands entering the media controller is controlled by the credit value, and the medium controller is prevented from being unable to process the write command in time to cause an overload.
  • the method before the memory controller receives the write command that carries the write address, the method further includes: the total address interval of the NVM is pre-divided into a plurality of address intervals that do not coincide with each other, and the number of the address intervals is equal to the memory.
  • the number of controllers, the number of memory controllers is equal to the number of media controllers.
  • the memory controller configures an address range of each memory write instruction set in the at least two memory write instruction sets by calling a library function, each memory write instruction set has a different address interval; the memory controller configures at least two medium write instruction sets Each medium writes an address range of the instruction set, and each medium write instruction set does not have a different address range; wherein the two memory write instruction sets and the media write instruction set having the binding relationship have the same address interval.
  • at least two memory write instructions are configured by a library function call. The address interval of the set and the at least two media write instruction sets facilitates confirming the target memory write instruction set and the target media write instruction set according to the write address of the write instruction.
  • the media controller sends the credit value of the target media write instruction set to the memory controller, where the media controller receives the query request sent by the memory controller, and the query request is used to query the target medium.
  • Writing a credit value of the instruction set the media controller may store the credit value of the target media write instruction set in a register, and the media controller immediately updates the target media write stored in the register when the credit value of the target media write instruction set is updated.
  • the credit value of the instruction set, the memory controller can directly query in the register, and the media controller receives the query request to send a query response carrying the credit value of the target media write instruction set to the memory controller.
  • the media controller sends the credit value of the target media write instruction set to the memory controller, where the media controller periodically sends the target media write instruction set to the memory controller. Credit value.
  • the method further includes: the memory controller receiving a persistent query instruction for the target memory write instruction set, and acquiring a receiving moment of the persistent query instruction; the memory The controller blocks a write instruction that enters the target memory write instruction set after the receiving time; the memory controller reads a credit value of the target memory write instruction set; if the read credit value is equal to a preset The maximum value, the memory controller determines that the write instruction in the set of target memory write instructions completes persistence.
  • the memory controller receives the persistent query instruction, and only needs to block the memory write instruction set to be queried, and does not need to block other memory write instruction sets, thereby realizing the local blocking with the granularity of the memory write instruction set. Parallel processing efficiency of the memory controller.
  • the memory controller blocking a write instruction that enters the target memory write instruction set after the receiving moment includes: the memory controller will enter after the receiving moment The write instruction of the target memory write instruction set performs a cache process; or at the receiving moment, the memory controller adds the target memory write instruction set to a software mutex lock.
  • the method further includes: the media controller receiving a persistent query instruction for a target media write instruction set; the media controller reading a credit value of the target media write instruction set And if the read credit value is equal to a preset maximum value, the media controller determines that the write instruction in the target media write instruction set completes the persistence operation.
  • the media controller receives the persistent query instruction, and only needs to block the media write instruction set to be queried, and does not need to block other media write instruction sets, thereby realizing the local blocking with the granularity of the memory write instruction set. Parallel processing efficiency of the media controller.
  • the present application further provides a computing device, including a memory controller, a media controller, and a non-volatile memory NVM, including but not limited to a data center server, a network server, a video server, and a workstation Or a personal computer, etc.
  • the memory controller includes a cache space, and the cache space is used to store at least two sets of memory write instructions. Each memory write instruction set in the at least two memory write instruction sets is configured with a credit value; the media controller includes a cache space, and the cache space is used.
  • the media controller is associated with at least two media write instruction sets, and each media write instruction set in the at least two media write instruction sets is configured with a credit value.
  • the data structure of the memory write instruction set and the media write instruction set may be a queue, an array, a stack, a linked list, etc., which is not limited in this application.
  • the number of memory write instruction sets in the at least two memory write instruction sets may be equal to the number of media write instruction sets in the at least two media write instruction sets, and the at least two memory write instruction sets are mapped one-to-one with the at least two media write instruction sets. Relationship, the maximum value of the credit value of the set of two memory write instructions and the set of media write instructions having an association relationship are equal.
  • Memory controller for:
  • the write instruction including a write address of the data to be written
  • the target memory write instruction set is selected from the at least two memory write instruction sets stored in the memory controller's cache space, the write instruction is stored in the target memory write instruction set, and the credit value of the target memory write instruction set is reduced. Specify a value;
  • the write instruction is stored in the target medium write instruction set, and the credit value of the target medium write instruction set is reduced by a specified value;
  • the credit value corresponding to each set of the plurality of memory write instruction sets is synchronized with the credit value corresponding to each of the plurality of media write instruction sets, and the media controller is capable of determining the write instruction according to the credit value of each medium write instruction set. Execution status, so the memory controller and the media controller's credit value are kept in sync, and the write command can be accurately checked according to the credit value to complete the persistence.
  • the local blocking of the memory write instruction set can be realized in the persistent query to improve the parallel processing efficiency of the memory controller.
  • the memory controller further includes: a receiver, a cache controller, a plurality of counters, and a transmitter, wherein each memory write instruction set is configured with a counter;
  • the media controller further includes: a receiver, a cache controller, a plurality of counters, and a transmitter, wherein each media write instruction set is configured with a counter;
  • a receiver of the memory controller configured to receive a write instruction carrying a write address
  • a cache controller of the memory controller configured to select a target memory write instruction set from the set of at least two memory write instructions stored in a cache space of the memory controller according to the write address, and store the write instruction in the target memory write instruction set, And decreasing the specified value of the credit value of the counter target memory write instruction set indicating the target write instruction set;
  • a transmitter of the memory controller configured to send a write instruction in the target memory write instruction set to the receiver of the media controller
  • the receiver of the memory controller is further configured to receive a credit value of the target media write instruction set sent by the transmitter of the media controller;
  • the cache controller of the memory controller is further configured to instruct the counter of the memory controller to update the credit value of the target memory write instruction set according to the credit value of the target media write instruction set;
  • the receiver of the media controller is configured to receive a write command sent by a transmitter of the memory controller
  • a cache controller of the media controller configured to determine, according to the write address, a target media write instruction set from the at least two media write instruction sets stored in the media controller's cache space; and store the write instruction in the target media write instruction set, Instructing a counter corresponding to the target medium write instruction set to decrease a credit value of the target medium write instruction set by a specified value;
  • a transmitter of the media controller configured to send a write instruction in the target media write instruction set to the NVM
  • the cache controller of the media controller is further configured to: after the NVM successfully executes the write instruction, instruct the counter corresponding to the target media write instruction set to increase the credit value of the target media write instruction set by a specified value;
  • the transmitter of the media controller is also used to send the credit value of the target media write instruction set to the receiver of the memory controller.
  • each memory write instruction set in the at least two memory write instruction sets is configured with an address interval of the NVM
  • the memory controller's cache controller is used to:
  • the write instruction is stored in the target memory write instruction set, indicating that the counter corresponding to the target medium write instruction set decrements the credit value of the target memory write instruction set by one.
  • each media write instruction set in the at least two media write instruction sets is configured with an address interval of the NVM
  • the media controller's cache controller is used to:
  • the write instruction is stored in the target media write instruction set, and the counter corresponding to the target media write instruction set is decremented by 1 for the credit value of the target media write instruction set.
  • the cache controller of the memory controller is further configured to:
  • the transmitter of the media controller is used to:
  • a query response carrying a credit value of the target media write instruction set is returned to the receiver of the memory controller according to the credit value query request sent by the transmitter of the memory controller.
  • the transmitter of the media controller is used to:
  • the periodic initiative actively sends the credit value of the target media write instruction set to the receiver of the memory controller.
  • the cache controller of the memory controller is further configured to:
  • controller of the media controller is further configured to:
  • Reading according to the received persistent query instruction for the target medium write instruction set, a credit value of the target medium write instruction set in a counter corresponding to the target medium write instruction set; if the read credit value is equal to a preset maximum value, Determining the write instruction in the target media write instruction set completes the persistence operation.
  • FIG. 1 is a schematic structural diagram of a computing device according to an embodiment of the present invention.
  • FIG. 2a is a schematic flowchart of a method for persisting an NVM according to an embodiment of the present invention
  • 2b to 2e are schematic diagrams showing the principle of adjusting the credit degree in the memory controller and the media controller according to the embodiment of the present invention
  • FIG. 3 is another schematic structural diagram of a computing device according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a computing device according to an embodiment of the present invention.
  • the computing device includes a memory controller 10, a media controller 11 and an NVM 12, and the computing device includes but is not limited to a data center server, a network server, a video server, a gateway server, a personal computer or a mobile terminal.
  • NVM represents a memory that can still store data after power off.
  • NVM includes but is not limited to ROM, PROM, EAROM, EPROM, EEPROM, and Flash Memory.
  • the memory controller 10 is associated with at least two sets of memory write instructions, and at least two sets of memory write instructions may be disposed inside the memory controller. For example, at least two sets of memory write instructions are set in the cache space 100 of the memory controller. Each set of write instructions in at least two sets of memory write instructions is configured with a credit value indicating the number of write instructions that are allowed to enter the set of memory write instructions.
  • the media controller 12 is associated with at least two media write instruction sets, and at least two media write instruction sets may be disposed inside the media controller, for example, at least two media controllers are located in the cache space 110, and at least two media write instructions are provided.
  • Each set of media write instructions in the set is configured with a credit value representing the number of write instructions allowed to enter the set of media write instructions, wherein the set of memory write instructions and the set of media write instructions can be queued.
  • the number of memory write instruction sets in the at least two memory write instruction sets is equal to the number of media write instruction sets in the at least two media write instruction sets, the number of memory write instruction sets is n, and the data write instruction set data is n, n
  • the n memory write instruction sets are in a one-to-one mapping relationship with the n media write instruction sets, and one memory write instruction set has a binding relationship with one media write instruction set; in the initial state, n
  • the credit value of each memory write instruction set in the memory write instruction set is a maximum value, and the credit value of each medium write instruction set in the n medium write instruction sets is a maximum value; the two memory write instruction sets having a binding relationship
  • the set of media write instructions has the same maximum value of the credit value.
  • the working process of the computing device includes:
  • the memory controller receives the write instruction, and the write instruction includes a write address of the data to be written;
  • the memory controller determines a target memory write instruction set from the at least two memory write instruction sets according to the write address, stores the write instruction in the target memory write instruction set, and reduces a credit value of the target memory write instruction set by a specified value;
  • the memory controller sends a write instruction in the target memory write instruction set to the media controller
  • the media controller receives a write command sent by the memory controller
  • the media controller determines a target media write instruction set from the at least two media write instruction sets according to the write address, stores the write instruction in the target media write instruction set, and reduces the credit value of the target media write instruction set by a specified value;
  • the media controller queries the physical block address of the NVM associated with the write address according to the preset address mapping table, and writes the data to be written corresponding to the write instruction into the physical block corresponding to the physical block address, if there is no query in the address mapping table.
  • the media controller selects a physical block from the list of free physical blocks for allocation, and establishes a mapping of the physical block address and the write address of the selected physical block in the address mapping table.
  • the media controller After the NVM successfully executes the write instruction and writes the data to be written to the corresponding physical block, the media controller will target the medium.
  • the credit value of the set of write instructions is increased by a specified value, that is, the media controller restores the credit of the target medium write instruction set to a maximum value after confirming that the NVM completes the persistence of the write instruction; the media controller writes the credit of the target medium to the set of instructions.
  • the value is sent to the memory controller; the memory controller receives the credit value of the target media write instruction set sent by the media controller; the memory controller updates the credit value of the target memory write instruction set according to the credit value of the target media write instruction set, and the target memory writes
  • the credit value of the set of instructions is synchronized with the credit value of the associated set of target media write instructions.
  • the total address interval of the NVM is pre-divided into a plurality of address intervals that are not coincident with each other, and the number of at least two memory write instruction sets associated with the memory controller is equal to the number of the plurality of address intervals, and each The memory write instruction set allocates an address interval; likewise, the number of at least two media write instruction sets associated with the media controller is equal to the number of the plurality of address intervals, and each media write instruction set is assigned an address interval.
  • the memory controller and the media controller can determine the target memory write instruction set and the medium write instruction set according to the address interval in which the write instruction falls.
  • memory write instruction queues in the memory controller's cache space, which are memory write command queue 1, memory write command queue 2 and memory write command queue 3.
  • media write instruction queues in the buffer space of the media controller, namely the memory write command queue 1, the memory write command queue 2 and the memory write command queue 3, the address allocated by the memory write command queue 1 and the medium write command queue 1.
  • the interval is 0x90000000 ⁇ 0x90fffff, 0x90000000 is the starting address of the address range, 0x90ffffff is the ending address of the address range;
  • the address range allocated by the memory write command queue 2 is 0x856000000 ⁇ 0x857ffff, 0x856000000 is the starting address, 0x857ffff is the ending address;
  • the address range allocated by the instruction queue 3 is 0x65600000 to 0x657fffff, 0x65600000 is the start address, and 0x657fffff is the termination address.
  • the credit value corresponding to each set of the plurality of memory write instruction sets is synchronized with the credit value corresponding to each of the plurality of media write instruction sets, and the media controller is capable of determining the write instruction according to the credit value of each medium write instruction set.
  • the execution state so the memory controller and the media controller's credit value are kept in sync, and the write command can be accurately checked according to the credit value to complete the persistence.
  • the local blocking of the memory write instruction set can be realized in the persistent query to improve the parallel processing efficiency of the memory controller.
  • FIG. 2 is a schematic flowchart of a method for persisting a non-volatile memory according to an embodiment of the present invention.
  • the method includes:
  • the memory controller receives the write instruction.
  • the write command includes a write address of the data to be written
  • the write command may be sent by the processor
  • the memory controller may receive the write address sent by the processor through the address bus, and receive the data to be written sent by the processor through the data bus.
  • the memory controller determines a target memory write instruction set from the at least two memory write instruction sets according to the write address.
  • the memory controller is associated with at least two sets of memory write instructions, the set of memory write instructions is for storing write instructions, and the data structure of the set of memory write instructions may be a queue, an array, a stack or a linked list; at least two memory write instructions
  • the set may be set inside the memory controller, for example, at least two sets of memory write instructions are set in the cache space of the memory controller, and the memory controller determines the target memory write instruction set from the set of at least two memory write instructions according to the write address. .
  • the memory controller determines, according to the write address, the target memory write instruction set from the at least two memory write instruction sets, where the total address interval of the NVM is pre-divided into at least two address intervals, and the divided address intervals.
  • the number is equal to the number of memory write instruction sets, each of the at least two address intervals is associated with a memory write instruction set, and the memory controller determines the address range in which the write address falls, and the memory associated with the address range in which the write address falls.
  • the set of write instructions is used as a set of target memory write instructions.
  • the specified value is equal to 1
  • the memory controller is provided with four memory write instruction sets, namely: memory write instruction set 1, memory write instruction set 2, memory write instruction set 3, and memory write.
  • the instruction set 4 has corresponding maximum credit value values of 5, 4, 4, and 3, and the medium controller is also provided with four medium write instruction sets, a medium write instruction set 1, a medium write instruction set 2, and a medium write instruction.
  • the set 3 and the medium write instruction set 4, the four memory write instruction sets and the four media write instruction sets are in a one-to-one mapping relationship, and the mapping relationship is: a memory write instruction set 1 associated medium write instruction set 1 and a memory write instruction set 2 association
  • the medium write instruction set 2, the memory write instruction set 3 associated medium write instruction set 3, the memory write instruction set 4 are associated with the medium write instruction set 4, and the maximum value of the credit value of each pair of associated memory instruction sets and media write queue sets is equal.
  • the address range and credit value of the four memory write instruction sets and the four media write instruction sets are as shown in Table 1:
  • Memory write instruction set Media write instruction set Credit value Address range Memory write instruction set 1 Media write instruction set 1 5 0x90000000 ⁇ 0x90fffff Memory write instruction set 2 Media write instruction set 2 4 0x85600000 ⁇ 0x857ffff Memory write instruction set 3 Media write instruction set 3 4 0x65600000 ⁇ 0x657ffff Memory write instruction set 4 Media write instruction set 4 3 0x50000000 ⁇ 0x70ffffffffff
  • the memory controller receives the write command, and the write command includes the write address 0x656033fe of the data to be written.
  • the memory controller determines that the write address falls into the address range 0x65600000 ⁇ 0x657fffff according to the four address intervals, and the address range corresponds to the memory write instruction set 3, and the memory write
  • the instruction set 3 is a set of target memory write instructions, and the memory controller stores the write instructions into the memory write instruction set 3.
  • the memory controller stores the write command into the target memory write instruction set, and reduces the credit value of the target memory write instruction set by a specified value.
  • the credit value indicates the number of write instructions allowed to enter the target memory write instruction set. If the credit value of the target memory write instruction set is less than the preset value, the target memory write instruction set is not allowed to enter the write instruction, and the target is not allowed.
  • the credit value set of the memory write instruction set has a maximum value, and the maximum value indicates the maximum number of write instructions allowed to enter the target memory write instruction set.
  • the memory controller stores the write instruction in the target memory write instruction set.
  • the data structure of the target memory write instruction set is a queue, and the memory controller stores the write instruction in the queue end of the target memory write instruction set; the target memory write instruction set
  • the data structure is a stack, and the memory controller stores the write instructions on top of the stack of the target memory write instruction set. After the memory controller stores the write command into the target memory write command set, the credit value of the target memory write command set is reduced by a specified value, and the specific value of the specified value is not limited, and can be set as needed.
  • the memory controller decrements the credit value 4 of the memory write command set by one, and the updated memory write command set 3 has a credit value of three.
  • the memory controller extracts the write instruction from the target memory write instruction set.
  • the memory controller may select a memory write instruction set from the at least two memory write instruction sets according to a preset selection rule, where the selected memory write instruction set is the target memory write instruction set of S203, and in S203 When the write command reaches the fetch time, the memory controller fetches the write command from the target memory write command set.
  • the selection rule may be: random selection, number polling according to a set of memory write instructions, priority polling according to a set of memory write instructions, and the like.
  • the memory controller sends a write instruction to the media controller.
  • the write command carries the write address of the data to be written.
  • the media controller determines the target medium from the set of at least two media write instructions according to the write address carried by the write command. A set of written instructions.
  • the set of media write instructions is used to store write instructions
  • the data structure of the set of media write instructions includes but is not limited to a queue, a linked list, an array, or a stack
  • at least two sets of media write instructions may be disposed inside the media controller, for example:
  • the at least two media write instruction sets are disposed in a buffer space of the media controller, and the media controller determines the target media write instruction set from the at least two media write instruction sets according to the write address carried by the write instruction.
  • the method for determining, by the media controller, the target medium write instruction set may be: the total address interval of the NVM is divided into two address intervals that are at least consecutive and not coincident, and each of the at least two address intervals The interval is associated with a set of media write instructions, the number of media write instruction sets in the at least two media write instruction sets being equal to the number of memory write instruction sets in the at least two memory write instruction sets, the associated two memory write instruction sets and the media write The address set configured by the instruction set is the same.
  • the media controller determines an address range in which the write address falls, and sets a medium write instruction set corresponding to the interval in which the write address falls as the target medium write instruction set.
  • the memory controller fetches the write command from the memory write command set 3, and sends the write command to the media controller.
  • the media controller determines that the write address falls into the address interval according to the write address 0x656033fe of the write command. 0x65600000 ⁇ 0x657ffff, the address range corresponds to the medium write instruction set 3, the medium write instruction set 3 is the target medium write instruction set, and the media controller stores the write instruction into the medium write instruction set 3.
  • the media controller stores the write command in the target media write instruction set, and reduces the credit value of the target media write command set by a specified value.
  • the credit value indicates the number of write instructions allowed to enter the target medium write instruction set. If the credit value of the target medium write instruction set is less than the preset value, the target medium write instruction set is not allowed to enter the write instruction, and the target is not allowed.
  • the credit value of the set of media write instructions has a maximum value, the maximum value indicating the maximum number of write instructions allowed to enter the target media write instruction set. Since the two sets of memory write instructions and media write instruction sets having an association have equal maximum values of credit values, the target memory write instruction set and the target medium write instruction set have the maximum value of equal credit values.
  • the data structures of the target media write instruction set include, but are not limited to, arrays, linked lists, queues, and stacks.
  • the media controller stores the write command into the medium write command set 3, and the media controller decrements the credit value 4 of the medium write command set 3 by one, and the medium write command set 3 is updated.
  • the credit value is 3.
  • the media controller extracts the write instruction from the target media write instruction set.
  • the media controller may select a media write instruction set from the at least two media write instruction sets according to a preset selection rule, where the selected media write instruction set is the target media write instruction set in S207, and When the write command of S207 in the target medium write command set reaches the fetch time, the media controller fetches the write command from the target media write command set.
  • the selection rule for selecting a set of media write instructions from the at least two sets of media write instructions may be: random selection, number polling according to a set of media write instructions, priority polling according to a set of media write instructions.
  • the media controller sends a write command to the NVM.
  • the media controller acquires a write address carried in the write command, converts the write address into a physical block address according to a preset address mapping table, and the media controller sends a write instruction carrying the physical block address to the NVM.
  • S210 and NVM execute a write instruction to complete the persistence operation.
  • the NVM writes the data to be written to the address block pointed to by the physical block address, and completes the persistence operation after the input to be written is written.
  • the NVM returns a response message to the media controller.
  • the response message is used to notify the media controller that the write command is completed in NVM. Become a persistent operation.
  • the media controller increases a credit value of the target media write instruction set by a specified value.
  • the media controller determines that the write instruction completes the persistence operation on the NVM, and increases the credit value of the target medium write instruction set by a specified value, so that the credit value decreases by a specified value after entering the target medium write instruction set by the write instruction of S207, and After the write instruction completes the persistence operation, the credit value of the target medium write instruction set is increased by a specified value, and the credit value of the media write instruction set is restored to the maximum value.
  • the media controller fetches the write command from the media write instruction set 3 and sends it to the NVM.
  • the NVM maps the write address to the physical block address according to the preset address mapping table, and the NVM will write the data to be written.
  • the NVM successfully writes the data to be written, and after completing the persistence operation, can notify the media controller of the response message, and the media controller writes the medium after confirming that the write command completes the persistence operation.
  • the credit value of the instruction set 3 is incremented by 1, and the credit value of the medium write command set 3 becomes 4.
  • the credit value of the target memory write instruction set is synchronized with the credit value of the target medium write instruction set.
  • the method for synchronizing the credit value may be: the memory controller actively queries the media controller for the credit value of the target medium write instruction set according to the preset period, and the credit value of the target medium write instruction set may be stored in the register of the media controller.
  • the memory controller updates the credit value of the target memory write instruction set according to the queried credit value; or the media controller actively notifies the memory controller when the credit value of the target medium write instruction set is updated, and the memory controller according to the notification
  • the credit value updates the credit value of the target memory write instruction set; or the credit value of the target medium write instruction set carries the response message of the write instruction.
  • the media controller sends the updated credit value 4 of the media write command set 3 to the memory controller, and the memory controller sets the memory write command set according to the credit value 4 of the medium write command set 3.
  • the credit value is updated to 4.
  • the memory controller determines the current credit value of the target memory write instruction set after determining the target memory write instruction set, and determines whether the current credit value is greater than 0, and if the result is determined If yes, the write instruction is stored in the target memory write instruction set; if the judgment result is no, the write instruction is cached, and the credit value of the target memory write instruction set is queried according to the preset period, and the target memory write instruction set is queried in the query.
  • the cached write command is stored in the target memory write instruction set.
  • the number of write commands entering the memory controller is controlled by the credit value, so as to prevent the memory controller from being unable to process the write command in time to cause overload.
  • the media controller After determining the target medium write instruction set, the media controller obtains a current credit value of the target media write instruction set, and determines whether the current credit value is greater than 0. If the judgment result is yes, the write instruction is stored in the target medium write instruction. If the judgment result is no, the write instruction is cached, and the credit value of the target medium write instruction set is queried according to the preset period, and when the credit value of the target medium write instruction set is greater than 0, the cached write instruction is further executed. Stored in the target media write instruction set.
  • the number of write commands entering the media controller is controlled by the credit value, and the medium controller is prevented from being unable to process the write command in time to cause an overload.
  • a non-volatile memory persistence method of the present application further includes:
  • the memory controller receives a persistent query instruction for the target memory write instruction set, and acquires a receiving moment of the persistent query instruction;
  • the memory controller blocks a write instruction that enters the target memory write instruction set
  • the memory controller reads a credit value of the target memory write instruction set
  • the memory controller determines that the write instruction in the target memory write instruction set is persistent.
  • the memory controller receives the persistent query instruction of the target memory write instruction set, and the persistent query instruction may be sent by the processor, and the persistent query instruction may be a CPU instruction or a calling function, and the CPU instruction or the calling function carries the target memory write instruction.
  • the identifier of the collection the memory controller receives the receiving moment of receiving the persistent query instruction, and after the receiving moment, the memory controller blocks the write instruction entering the target memory write instruction set, wherein at least two out of the memory write instruction set The other memory write instruction set of the memory write instruction set, the memory controller does not perform the blocking operation.
  • the memory controller reads the credit value of the target memory write instruction set. If the read credit value is equal to the preset maximum value, it indicates that there is no write command occupying the credit value in the target memory write instruction set, and the write in the target memory write instruction set The instruction completes the persistence operation.
  • the memory controller when the memory controller receives the persistent query instruction for the memory write instruction set 3, the memory controller obtains the persistent query instruction receiving time as t0, and the memory controller blocks the t0 time and enters.
  • the blocking method may be: buffering the write instruction that enters the memory write instruction set 3 after the time t0 or adding a software mutex lock to the memory write instruction set, wherein the memory write instruction Sets 1, 2, and 4 can still normally enter the write command; the memory controller obtains the credit value of the memory write command set 3, and finds that the credit value of the memory write command set 3 is equal to the maximum value of 4, and then determines that the memory write command set 3 is not written.
  • the instruction takes up the credit value, and the memory write instruction set 3 completes the persistence operation.
  • the media controller receives the persistent query instruction for the media write instruction set 3, the media controller obtains the credit value of the media write instruction set 3, and finds that the credit value of the media write command set 3 is equal to the maximum value of 4, then the media write command In the set 3, there is no write command occupying the credit value, and the write command in the medium write command set 3 completes the persistence operation.
  • the memory controller blocking a write instruction that enters the target memory write instruction set includes:
  • the memory controller caches a write instruction that enters the target memory write instruction set
  • the memory controller adds the target memory write instruction set to a software mutex lock.
  • the method for the memory controller to block the write instruction entering the target write instruction set includes: after the receiving time, the memory controller caches the write instruction that enters the target memory write instruction set, and the memory controller is When the credit value of the target memory write instruction set is equal to the preset maximum value, the cached write instruction is sent to the target memory write instruction set; or the memory controller adds a software mutex lock to the target memory write instruction set, thereby blocking the entry.
  • a non-volatile memory persistence method of the present application further includes:
  • the media controller receives a persistent query instruction for a target media write instruction set
  • the media controller reads a credit value of the target media write instruction set
  • the media controller determines that the write instruction in the target media write instruction set completes the persistence operation.
  • the media controller receives the persistent query instruction of the target media write instruction set, and the persistent query instruction may be sent by the processor, and the persistent query instruction may be a CPU instruction or a call function, and the CPU instruction or the call function carries the target medium write instruction.
  • the media controller reads the credit value of the target medium write instruction set, and if the read credit value is equal to the preset maximum value, indicating that the target medium write instruction set has no write command occupation credit value, the target medium write instruction The write instruction in the collection completes the persistence operation.
  • the credit value corresponding to each set of the plurality of memory write instruction sets is synchronized with the credit value corresponding to each of the plurality of media write instruction sets, because the media controller can determine the credit value according to each media write instruction set.
  • Write the execution status of the instruction so after the memory controller and the media controller's credit value are kept in sync, it can accurately query whether the write command is completed according to the credit value.
  • the local blocking of the memory write instruction set can be realized in the persistent query to improve the parallel processing efficiency of the memory controller.
  • FIG. 3 is another schematic structural diagram of a computing device according to an embodiment of the present disclosure.
  • the computing device includes a memory controller 10, a media controller 11, and an NVM 12.
  • the memory controller 10 includes: a cache space 100, a receiver 101, a cache controller 102, n counters, and a transmitter 103.
  • the cache space 100 is provided with n memory write instruction sets, and each memory write instruction set Configured with a counter, n is an integer greater than one.
  • the media controller 11 includes: a cache space 110, a receiver 111, a cache controller 112, n counters, and a transmitter 113.
  • the cache space 110 is provided with n sets of medium write instructions, and each medium write instruction set is configured with a counter.
  • the total address interval of the NVM 12 is divided into n address intervals, n sets of memory write instructions are mapped one by one with n address intervals, and n sets of medium write instructions are mapped one by one with n address intervals.
  • the components included in the memory controller 10 and the media controller 11 can be implemented by an application-specific integrated circuit (ASIC: ASIC) or a programmable logic device (English: Programmable Logic Device, Abbreviation: PLD) implementation.
  • the PLD may be a Complex Programmable Logic Device (CPLD), an FPGA, a Generic Array Logic (GAL), or any combination thereof.
  • the working process of the computing device includes:
  • a receiver 101 of the memory controller 10 configured to receive a write command that carries a write address
  • the cache controller 102 of the memory controller 10 is configured to select a target memory write instruction set from the at least two memory write instruction sets stored in the memory controller's cache space according to the write address, and store the write instruction in the target memory write instruction. Aggregating, and decreasing a credit value of a counter target memory write instruction set indicating a target write instruction set by a specified value;
  • the transmitter 103 of the memory controller 10 is configured to send a write instruction in the target memory write instruction set to the receiver of the media controller;
  • the receiver 101 of the memory controller 10 is further configured to receive a credit value of a target media write instruction set sent by a transmitter of the media controller;
  • the cache controller 102 of the memory controller 10 is further configured to instruct the counter of the memory controller to update the credit value of the target memory write instruction set according to the credit value of the target medium write instruction set;
  • the receiver 111 of the media controller 11 is configured to receive a write command sent by a transmitter of the memory controller
  • the cache controller 112 of the media controller 11 is configured to determine, according to the write address, a target media write instruction set from at least two media write instruction sets stored in a cache space of the media controller; and store the write instruction in the target media write instruction a set, indicating that the counter corresponding to the target medium write instruction set reduces the credit value of the target medium write instruction set by a specified value;
  • the transmitter 113 of the media controller 11 is configured to send a write instruction in the target media write instruction set to the NVM 12;
  • the cache controller 112 of the media controller 11 is further configured to: after the NVM successfully executes the write instruction, instruct the counter corresponding to the target media write instruction set to increase the credit value of the target media write instruction set by a specified value;
  • the transmitter 113 of the media controller 11 is further configured to send the credit value of the target media write instruction set to the receiver of the memory controller.
  • each memory write instruction set in the at least two memory write instruction sets is configured with an address interval of the NVM
  • the cache controller 102 of the memory controller 10 is used to:
  • the write instruction is stored in the target memory write instruction set, indicating that the counter corresponding to the target medium write instruction set decrements the credit value of the target memory write instruction set by one.
  • each medium write instruction set in the at least two media write instruction sets is configured with an address interval of the NVM
  • the cache controller 112 of the media controller 11 is used to:
  • the write instruction is stored in the target media write instruction set, and the counter corresponding to the target media write instruction set is decremented by 1 for the credit value of the target media write instruction set.
  • the cache controller 102 of the memory controller 10 is further configured to:
  • the transmitter 113 of the media controller 11 is used to:
  • a query response carrying a credit value of the target media write instruction set is returned to the receiver of the memory controller according to the credit value query request sent by the transmitter of the memory controller.
  • the transmitter 113 of the media controller 11 is used to:
  • the periodic initiative actively sends the credit value of the target media write instruction set to the receiver of the memory controller.
  • the cache controller 102 of the memory controller 10 is further configured to:
  • the cache controller 112 of the media controller 11 is further configured to:
  • Reading according to the received persistent query instruction for the target medium write instruction set, a credit value of the target medium write instruction set in a counter corresponding to the target medium write instruction set; if the read credit value is equal to a preset maximum value, Determining the write instruction in the target media write instruction set completes the persistence operation.
  • the credit value corresponding to each set of the plurality of memory write instruction sets is synchronized with the credit value corresponding to each of the plurality of media write instruction sets, and the media controller is capable of determining the write instruction according to the credit value of each medium write instruction set. Execution status, so the memory controller and the media controller's credit value are kept in sync, and the write command can be accurately checked according to the credit value to complete the persistence.
  • the local blocking of the memory write instruction set can be realized in the persistent query to improve the parallel processing efficiency of the memory controller.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

Abstract

本申请公开了一种非易失性内存NVM的持久化方法和计算设备，内存控制器关联的至少两个内存写指令集合中每个内存写指令集合配置有信用度值，介质控制器关联的至少两个介质写指令集合中每个介质写指令集合配置为信用度值，通过写指令的收发状态和执行状态变更信用度值，多个内存写指令集合各自对应的信用度值与介质控制器中设置的多个介质写指令集合各自对应的信用度值保持同步，内存控制器与介质控制器的信用度值保持同步后，能准确根据信用度值查询写指令是否完成持久化。同时，通过设置多个内存写指令集合，在持久化查询时能实现以内存写指令集合为粒度的局部阻塞，以提高内存控制器的并行处理效率。

Description

一种非易失性内存的持久化方法和计算设备 技术领域
本发明涉及计算机领域，尤其涉及一种非易失性内存(Non-Volatile Memory，简称NVM)的持久化方法和计算设备。
背景技术
数据持久性表示数据成功写入持久性的NVM非易失性内存，在系统崩溃或掉电的情况下数据也不会丢失。例如，应用程序的数据具有持久性的属性时，应用程序可以在系统崩溃或掉电之后从NVM上存储的数据中恢复正常运行状态。在目前的应用中，通常将NVM作为内存使用，这样应用程序就可以在系统崩溃或掉电后直接从内存中恢复运行。但是NVM作为内存使用时，现有的DDR(Double Data Rate，双倍数据率)内存协议无法支持数据的持久性确认，这是因为现有的DDR内存协议中的写指令在数据写入CPU(Central Processing Unit，中央处理器)缓存中之后就会提交完成，CPU和应用程序无法继续跟踪和获知写指令中数据是否真正写入内存。
为了确认写指令的数据是否写入内存，目前提出了一种持久化确认的方案是：使用PCOMMIT指令和CLFLUSH指令来实现持久化的确认，CLFLUSH指令可以将CPU缓存中的指定的数据写回并生成写指令发送至内存控制器。PCOMMIT指令会将内存控制器中所有写指令都强制写入内存。在PCOMMIT指令的执行过程中，内存控制器会阻塞新的写指令进入内存控制器，直到内存控制器中所有的写指令被发送到内存芯片。通过上述方法可以在确认数据成功写入内存并完成持久化。
目前的持久化确认方案中，PCOMMIT指令用于指示内存控制器中所有写指令完成持久化操作，PCOMMIT指令在执行过程中，会阻塞所有的写指令进入内存控制器，这样就会减少新的写指令发送给内存控制器，避免影响到PCOMMIT指令的执行。在达到上述效果的同时，也会导致所有应用程序的写指令都暂时无法发送到内存控制器中，使得调用PCOMMIT指令的应用程序对其他应用程序造成了比较大的性能影响，导致整个系统的运行效率低下。
发明内容
本发明实施例所要解决的技术问题在于，提供一种NVM的持久化方法和计算设备，通过设置多个内存写指令集合，能实现以内存写指令集合为最小粒度的局部阻塞，提高内存控制器的并行处理效率。
第一方面，本申请提供了一种非易失性内存NVM的持久化方法。
内存控制器关联有至少两个内存写指令集合，至少两个内存写指令集合可设置在内存控制器的内部，例如至少两个内存写指令集合位于内存控制器的缓存空间中，至少两个内存写指令集合中每个内存写指令集合配置有一个信用度值，信用度值表示允许进入内存写指令集合中的写指令的数量，某个内存写指令的信用度值等于0时，则该内存写指令集合不允许进入写指令，每个内存写指令集合的信用度值具有一个最大值。
NVM是在断电后仍能保存数据的存储器，NVM包括但不限于只读存储器(Read-Only Memory，ROM)、可编程只读内存(Programmable Read-Only Memory，PROM)、电可改写只读内存(Electrically Alterable Read Only Memory，EAROM)可擦除可编程只读内存(Erasable  Programmable Read-Only Memory，EPROM)、电可擦除可编程只读内存(Electrically Erasable Programmable Read-Only Memory，EEPROM)和闪存(Flash Memory)；NVM的介质控制器关联有至少两个介质写指令集合，至少两个介质写指令集合可设置在介质控制器的内部，例如：至少两个介质写指令集合位于介质控制器的缓存空间中，至少两个介质写指令集合中每个介质写指令集合配置有一个信用度值，信用度值表示允许进入介质写指令集合的写指令的数量，当某个介质写指令集合的信用度值等于0时，则该介质写指令集合不允许进入写指令，每个介质写指令集合的信用度值具有一个最大值。内存写指令集合和介质写指令集合的数据结构可以是队列、数组、链表、堆栈等，本申请不作限制。
至少两个内存写指令集合中内存写指令集合的数量等于至少两个介质写指令集合中介质写指令集合的数量，至少两个内存写指令集合与至少两个介质写指令呈一一映射关系，每对关联的内存写指令集合和介质写指令集合的信用度值的最大值相等。
本申请的持久化方法应用于将内存中的待写数据写入到NVM的过程，包括：内存控制器首先接收写指令，写指令包括待写数据的写地址，写指令可由处理器发送，内存控制器根据写地址从至少两个内存写指令集合中确定目标内存写指令集合，将写指令存入到选择的目标内存写指令集合中，目标内存写指令集合为至少两个内存写指令集合中的一个，内存控制器将目标内存写指令集合的信用度值减少指定数值，指定数值为预先设定的值，具体值不作限制。
内存控制器可根据预设的选择规则从至少两个内存指令集合中选择出目标内存写指令集合，从目标内存写指令集合中取出写指令，将取出的写指令发送给介质控制器；
介质控制器接收写指令，根据写指令从至少两个介质写指令集合中确定目标介质写指令集合，目标介质写指令集合与目标内存写指令集合具有绑定关系，目标介质写指令集合为至少两个介质写指令集合中的一个，介质控制器将写指令存入目标介质写指令集合，将目标介质写指令集合的信用度值减少指定数值。
介质控制器可根据预设的选择规则从至少两个介质写指令结合中选择目标介质写指令集合，从目标写指令集合中取出写指令；
介质控制器获取写指令中携带的写地址，根据预设的地址映射表查询与写地址关联的NVM的物理块地址，将写指令对应的待写数据写入到该物理块地址对应的物理块中，如果地址映射表中没有查询到物理块地址，即物理块地址没有分配，介质控制器从空闲的物理块列表中选择一个物理块进行分配，并且在地址映射表中建立选择的物理块的物理块地址与写地址的的映射；
介质控制器确定待写数据成功写入NVM之后，将目标介质写指令集合的信用度值增加指定数值，介质控制器将目标介质写指令集合的信用度值发送给内存控制器，使目标内存写指令集合的信用度值与目标介质写指令集合的信用度值保持同步。
上述实施例，设置的多个内存写指令集合各自对应的信用度值与介质控制器中设置的多个介质写指令集合各自对应的信用度值保持同步，由于介质控制器能够根据各个介质写指令集合的信用度值确定写指令的执行状态，因此内存控制器与介质控制器的信用度值保持同步后，能准确根据信用度值查询写指令是否完成持久化。同时，通过设置多个内存写指令集合，在持久化查询时能实现以内存写指令集合为粒度的局部阻塞，以提高内存控制器的并行处理效率。
在本方面的一种可能的实施方式中，NVM的总地址区间预先划分为多个不相互重合的地 址区间，至少两个内存写指令集合中每个内存写指令集合配置有NVM的一个地址区间，至少两个内存写指令集合中每个内存写指令集合具有不同的地址区间。内存控制器根据写地址从至少两个内存写指令集合中确定目标内存写指令集合，将写指令存入目标内存写指令集合，并对目标内存写指令集合的信用度值减少指定数值包括：内存控制器确定写指令中携带的写地址所在的目标地址区间，目标地址区间为至少两个内存写指令集合预先各自配置的地址区间中的一个，将目标地址区间关联的内存写指令集合作为目标内存写指令集合，指定数值为1，内存控制器将写指令存入到目标内存写指令集合中，将目标内存写指令集合的信用度值减1。上述实施例，根据写地址所在的地址区间确定目标内存写指令集合，能快速和准确的存放写指令，提高处理效率。
在本方面的一种可能的实施方式中，NVM的总地址区间预先划分为多个不相互重合的地址区间，地址区间的数量等于至少两个介质写指令集合中介质写指令集合的数量，至少两个介质写指令集合中每个介质写指令集合配置有一个不同的地址区间。介质控制器根据写地址从至少两个介质写指令集合中确定目标介质写指令集合，将写指令存放目标介质写指令集合，将目标介质写指令集合的信用度值减少指定数值包括：介质控制器获取写指令中携带的写地址，确定写地址所在的目标地址区间，目标地址区间为至少两个介质写指令集合各自配置的地址区间中的一个，介质控制器将写指令存入目标介质写指令集合。例如：目标介质写指令集合的数据结构为队列，介质控制器将写指令存入队列的队列尾；又例如；目标介质写指令集合的数据结构为堆栈，介质控制器将写指令存放堆栈的栈顶；预设的指定数值为1，在存入写指令后介质控制器将目标介质写指令集合的信用度值减1。上述实施例，通过写地址落入的目标地址区间确定目标介质写指令集合，能快速和准确的存放写指令，提高处理效率。
在本方面的一种可能的实施方式中，在预设的指定数值为1的情况下，内存控制器确定目标内存写指令集合后，获取目标内存写指令集合当前的信用度值，判断当前的信用度值是否大于0，若判断结果为是，将写指令存入目标内存写指令集合；若判断结果为否，将写指令进行缓存处理，根据预设周期查询目标内存写指令集合的信用度值，在查询到目标内存写指令集合的信用度值大于0时，再将缓存的写指令存入目标内存写指令集合中。上述实施例，通过信用度值控制进入内存控制器的写指令的数量，避免内存控制器无法及时处理写指令导致过载。
在本方面的一种可能的实施方式中，介质控制器确定目标介质写指令集合后，获取目标介质写指令集合当前的信用度值，判断当前的信用度值是否大于0，若判断结果为是，将写指令存入目标介质写指令集合；若判断结果为否，将写指令进行缓存处理，根据预设周期查询目标介质写指令集合的信用度值，在查询到目标介质写指令集合的信用度值大于0时，再将缓存的写指令存入目标介质写指令集合中。上述实施例，通过信用度值控制进入介质控制器的写指令的数量，避免介质控制器无法及时处理写指令而导致过载。
在本方面的一种可能的实施方式中，内存控制器接收携带写地址的写指令之前，还包括：NVM的总地址区间预先划分为多个不相互重合的地址区间，地址区间的数量等于内存控制器的数量，内存控制器的数量等于介质控制器的数量。内存控制器通过调用库函数配置至少两个内存写指令集合中每个内存写指令集合的地址区间，每个内存写指令集合具有不同的地址区间；内存控制器配置至少两个介质写指令集合中每个介质写指令集合的地址区间，每个介质写指令集合不有不同的地址区间；其中，具有绑定关系的两个内存写指令集合和介质写指令集合具有相同的地址区间。上述实施例，通过库函数调用的方式配置至少两个内存写指令 集合和至少两个介质写指令集合的地址区间，便于根据写指令的写地址确认目标内存写指令集合和目标介质写指令集合。
在本方面的一种可能的实施方式中，介质控制器将目标介质写指令集合的信用度值发送给内存控制器包括：介质控制器接收内存控制器发送的查询请求，查询请求用于查询目标介质写指令集合的信用度值；介质控制器可以将目标介质写指令集合的信用度值存储在寄存器中，介质控制器发现目标介质写指令集合的信用度值发生更新时，立即更新寄存器中存储的目标介质写指令集合的信用度值，内存控制器可直接在寄存器中查询，介质控制器接收到查询请求向内存控制器发送携带目标介质写指令集合的信用度值的查询响应。
在本方面的一种可能的实施方式中，介质控制器将所述目标介质写指令集合的信用度值发送给内存控制器包括：介质控制器周期性的主动向内存控制器发送目标介质写指令集合的信用度值。
在本方面的一种可能的实施方式中，还包括：所述内存控制器接收针对所述目标内存写指令集合的持久化查询指令，以及获取所述持久化查询指令的接收时刻；所述内存控制器阻塞在所述接收时刻之后进入所述目标内存写指令集合的写指令；所述内存控制器读取所述目标内存写指令集合的信用度值；若读取到的信用度值等于预设的最大值，所述内存控制器确定所述目标内存写指令集合中的写指令完成持久化。上述实施例，内存控制器接收到持久化查询指令，只需要阻塞待查询的内存写指令集合，不需要阻塞其他的内存写指令集合，实现了以内存写指令集合为粒度的局部阻塞，提高了内存控制器的并行处理效率。
在本方面的一种可能的实施方式中，所述内存控制器阻塞在所述接收时刻之后进入所述目标内存写指令集合的写指令包括：所述内存控制器将在所述接收时刻之后进入所述目标内存写指令集合的写指令进行缓存处理；或在所述接收时刻，所述内存控制器将所述目标内存写指令集合加软件互斥锁。
在本方面的一种可能的实施方式中，还包括：所述介质控制器接收针对目标介质写指令集合的持久化查询指令；所述介质控制器读取所述目标介质写指令集合的信用度值；若读取到的信用度值等于预设的最大值，所述介质控制器确定所述目标介质写指令集合中的写指令完成持久化操作。上述实施例，介质控制器接收到持久化查询指令，只需要阻塞待查询的介质写指令集合，不需要阻塞其他的介质写指令集合，实现了以内存写指令集合为粒度的局部阻塞，提高了介质控制器的并行处理效率。
第二方面，本申请还提供了一种计算设备，该计算设备包括内存控制器、介质控制器和非易失性内存NVM，计算设备包括但不限于数据中心服务器、网络服务器、视频服务器、工作站或个人电脑等。内存控制器包括缓存空间，缓存空间用来存储至少两个内存写指令集合，至少两个内存写指令集合中每个内存写指令集合配置有一个信用度值；介质控制器包括缓存空间，缓存空间用来存储至少两个介质写指令集合，介质控制器关联有至少两个介质写指令集合，至少两个介质写指令集合中每个介质写指令集合配置有一个信用度值。内存写指令集合和介质写指令集合的数据结构可以是队列、数组、堆栈、链表等，本申请不作限制。至少两个内存写指令集合中内存写指令集合的数量可以等于至少两个介质写指令集合中介质写指令集合的数量，至少两个内存写指令集合与至少两个介质写指令集合呈一一映射关系，具有关联关系的两个内存写指令集合和介质写指令集合的信用度值的最大值相等。
内存控制器，用于：
接收写指令，写指令包括待写数据的写地址；
根据写地址，从内存控制器的缓存空间存储的至少两个内存写指令集合中选择目标内存写指令集合，将写指令存入目标内存写指令集合，并对目标内存写指令集合的信用度值减少指定数值；
将目标内存写指令集合中的写指令发送给介质控制器；
接收介质控制器发送的目标介质写指令集合的信用度值；
根据目标介质写指令集合的信用度值更新目标内存写指令集合的信用度值；
介质控制器，用于：
接收内存控制器发送的写指令；
根据写地址，从介质控制器的缓存空间存储的至少两个介质写指令集合中确定目标介质写指令集合；
将写指令存入目标介质写指令集合，将目标介质写指令集合的信用度值减少指定数值；
将目标介质写指令集合中的写指令发送给NVM，在NVM成功执行写指令后，将目标介质写指令集合的信用度值增加指定数值；
将目标介质写指令集合的信用度值发送给内存控制器。
上述实施例，设置的多个内存写指令集合各自对应的信用度值与多个介质写指令集合各自对应的信用度值保持同步，由于介质控制器能够根据各个介质写指令集合的信用度值确定写指令的执行状态，因此内存控制器与介质控制器的信用度值保持同步后，能准确根据信用度值查询写指令是否完成持久化。同时，通过设置多个内存写指令集合，在持久化查询时能实现以内存写指令集合为粒度的局部阻塞，以提高内存控制器的并行处理效率。
在本方面的一种可能的实施方式中，内存控制器还包括：接收器、缓存控制器、多个计数器、发送器，其中，每个内存写指令集合配置有一个计数器；
介质控制器还包括：接收器、缓存控制器、多个计数器和发送器，其中，每个介质写指令集合配置有一个计数器；
内存控制器的接收器，用于接收携带写地址的写指令；
内存控制器的缓存控制器，用于根据写地址，从内存控制器的缓存空间中存储的至少两个内存写指令集合中选择目标内存写指令集合，将写指令存入目标内存写指令集合，并对指示目标写指令集合的计数器目标内存写指令集合的信用度值减少指定数值；
内存控制器的发送器，用于将目标内存写指令集合中的写指令发送给介质控制器的接收器；
内存控制器的接收器还用于接收介质控制器的发送器发送的目标介质写指令集合的信用度值；
内存控制器的缓存控制器还用于指示内存控制器的计数器根据目标介质写指令集合的信用度值更新目标内存写指令集合的信用度值；
介质控制器的接收器用于接收内存控制器的发送器发送的写指令；
介质控制器的缓存控制器，用于根据写地址，从介质控制器的缓存空间中存储的至少两个介质写指令集合中确定目标介质写指令集合；将写指令存入目标介质写指令集合，指示目标介质写指令集合对应的计数器将目标介质写指令集合的信用度值减少指定数值；
介质控制器的发送器，用于将目标介质写指令集合中的写指令发送给NVM；
介质控制器的缓存控制器还用于在NVM成功执行写指令后，指示目标介质写指令集合对应的计数器将目标介质写指令集合的信用度值增加指定数值；
介质控制器的发送器还用于将目标介质写指令集合的信用度值发送给内存控制器的接收器。
在本方面的一种可能的实施方式中，至少两个内存写指令集合中每个内存写指令集合配置有NVM的一个地址区间；
内存控制器的缓存控制器用于：
确定写地址所在的目标地址区间，将目标地址区间关联的内存写指令集合作为目标内存写指令集合；
将写指令存入目标内存写指令集合，指示目标介质写指令集合对应的计数器将目标内存写指令集合的信用度值减1。
在本方面的一种可能的实施方式中，至少两个介质写指令集合中每个介质写指令集合配置有NVM的一个地址区间；
介质控制器的缓存控制器用于：
确定写地址所在的目标地址区间，将目标地址区间关联的介质写指令集合作为目标介质写指令集合；
将写指令存入目标介质写指令集合，以及指示目标介质写指令集合对应的计数器将目标介质写指令集合的信用度值减1。
在本方面的一种可能的实施方式中，内存控制器的缓存控制器还用于：
通过调用库函数配置至少两个内存写指令集合中每个内存写指令集合的地址区间，以及配置至少两个介质写指令集合中每个介质写指令集合的地址区间；其中，至少两个内存写指令集合与至少两个介质写指令集合呈一一映射关系，关联的内存写指令集合和介质写指令集合具有相同的地址区间。
在本方面的一种可能的实施方式中，介质控制器的发送器用于：
根据内存控制器的发送器发送的信用度值查询请求，向内存控制器的接收器返回携带目标介质写指令集合的信用度值的查询响应。
在本方面的一种可能的实施方式中，介质控制器的发送器用于：
周期性的主动向内存控制器的接收器发送目标介质写指令集合的信用度值。
在本方面的一种可能的实施方式中，内存控制器的缓存控制器还用于：
接收针对目标内存写指令集合的持久化查询指令，以及获取持久化查询指令的接收时刻；阻塞在接收时刻之后进入目标内存写指令集合的写指令；在目标介质写指令集合对应的计数器中读取目标内存写指令集合的信用度值；若读取到的信用度值等于预设的最大值，确定目标内存写指令集合中的写指令完成持久化。
在本方面的一种可能的实施方式中，介质控制器的控制器还用于：
根据接收的针对目标介质写指令集合的持久化查询指令，在目标介质写指令集合对应的计数器中读取目标介质写指令集合的信用度值；若读取到的信用度值等于预设的最大值，确定目标介质写指令集合中的写指令完成持久化操作。
附图说明
下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1是本发明实施例提供的一种计算设备的结构示意图；
图2a是本发明实施例提供的一种NVM的持久化方法的流程示意图；
图2b至图2e是本发明实施例提供的内存控制器和介质控制器中的信用度的调整的原理示意图；
图3是本发明实施例提供的一种计算设备的另一结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚地描述。
参见图1，为本发明实施例提供的一种计算设备的结构示意图。在本发明实施例中，计算设备包括内存控制器10、介质控制器11和NVM 12，计算设备包括但不限于数据中心服务器、网络服务器、视频服务器、网关服务器、个人电脑或移动终端。NVM表示断电后仍能保存数据的存储器，NVM包括但不限于ROM、PROM、EAROM、EPROM、EEPROM和Flash Memory。
内存控制器10关联有至少两个内存写指令集合，至少两个内存写指令集合可设置在内存控制器的内部，例如：至少两个内存写指令集合设置在内存控制器的缓存空间100中，至少两个内存写指令集合中每个写指令集合配置有一个信用度值，信用度值表示允许进入内存写指令集合的写指令的数量。
介质控制器12关联有至少两个介质写指令集合，至少两个介质写指令集合可设置在介质控制器的内部，例如：至少两个介质控制器位于缓存空间110中，至少两个介质写指令集合中每个介质写指令集合配置有一个信用度值，信用度值表示允许进入介质写指令集合中的写指令的数量，其中，内存写指令集合和介质写指令集合可以为队列。
至少两个内存写指令集合中内存写指令集合的数量等于至少两个介质写指令集合中介质写指令集合的数量，设内存写指令集合的数量为n，介质写指令集合的数据为n，n为大于1的整数，n个内存写指令集合与n个介质写指令集合呈一一映射关系，1个内存写指令集合与1个介质写指令集合具有绑定关系；在初始状态下，n个内存写指令集合中每个内存写指令集合的信用度值为最大值，且n个介质写指令集合中每个介质写指令集合的信用度值为最大值；具有绑定关系的两个内存写指令集合和介质写指令集合具有相同的信用度值的最大值。
计算设备的工作过程包括：
内存控制器接收写指令，写指令包括待写数据的写地址；
内存控制器根据写地址，从至少两个内存写指令集合中确定目标内存写指令集合，将写指令存入目标内存写指令集合，并对目标内存写指令集合的信用度值减少指定数值；
内存控制器将目标内存写指令集合中的写指令发送给介质控制器；
介质控制器接收内存控制器发送的写指令；
介质控制器根据写地址，从至少两个介质写指令集合中确定目标介质写指令集合，将写指令存入目标介质写指令集合，将目标介质写指令集合的信用度值减少指定数值；
介质控制器根据预设的地址映射表查询与写地址关联的NVM的物理块地址，将写指令对应的待写数据写入到该物理块地址对应的物理块中，如果地址映射表中没有查询到物理块地址，即物理块地址没有分配，介质控制器从空闲的物理块列表中选择一个物理块进行分配，并且在地址映射表中建立选择的物理块的物理块地址与写地址的的映射；
在NVM成功执行写指令，将待写数据写入到对应的物理块之后，介质控制器将目标介质 写指令集合的信用度值增加指定数值，即介质控制器在确认NVM完成对写指令的持久化之后，将目标介质写指令集合的信用度恢复为最大值；介质控制器将目标介质写指令集合的信用度值发送给内存控制器；内存控制器接收介质控制器发送的目标介质写指令集合的信用度值；内存控制器根据目标介质写指令集合的信用度值更新目标内存写指令集合的信用度值，目标内存写指令集合的信用度值与关联的目标介质写指令集合的信用度值保持同步。
在一种可能的实施方式中，NVM的总地址区间预先划分为多个不相互重合的地址区间，内存控制器关联的至少两个内存写指令集合的数量等于多个地址区间的数量，且每个内存写指令集合分配一个地址区间；同样的，介质控制器关联的至少两个介质写指令集合的数量等于多个地址区间的数量，且每个介质写指令集合分配一个地址区间。这样内存控制器和介质控制器在接收到写指令时，可根据写指令落入的地址区间确定目标内存写指令集合和介质写指令集合。
内存控制器的缓存空间内设置有3个内存写指令队列，分别为内存写指令队列1、内存写指令队列2和内存写指令队列3。介质控制器的缓存空间内设置有3个介质写指令队列，分别为内存写指令队列1、内存写指令队列2和内存写指令队列3，内存写指令队列1和介质写指令队列1分配的地址区间为0x90000000～0x90ffffff，0x90000000为地址区间的起始地址，0x90ffffff为地址区间的终止地址；内存写指令队列2分配的地址区间为0x856000000～0x857fffff，0x856000000为起始地址，0x857fffff为终止地址；内存写指令队列3分配的地址区间为0x65600000～0x657fffff，0x65600000为起始地址，0x657fffff为终止地址。
实施上述实施例，设置的多个内存写指令集合各自对应的信用度值与多个介质写指令集合各自对应的信用度值保持同步，由于介质控制器能够根据各个介质写指令集合的信用度值确定写指令的执行状态，因此内存控制器与介质控制器的信用度值保持同步后，能准确根据信用度值查询写指令是否完成持久化。同时，通过设置多个内存写指令集合，在持久化查询时能实现以内存写指令集合为粒度的局部阻塞，以提高内存控制器的并行处理效率。
参见图2，为本发明实施例提供的一种非易失性内存的持久化方法的流程示意图，在本发明实施例中，所述方法包括：
S201、内存控制器接收写指令。
具体的，写指令包括待写数据的写地址，写指令可以是处理器发出的，内存控制器可以通过地址总线接收处理器发送的写地址，以及通过数据总线接收处理器发送的待写数据。
S202、内存控制器根据写地址，从至少两个内存写指令集合中确定目标内存写指令集合。
具体的，内存控制器关联有至少两个内存写指令集合，内存写指令集合表示用于存放写指令，内存写指令集合的数据结构可以是队列、数组、堆栈或链表；至少两个内存写指令集合可设置在内存控制器的内部，例如至少两个内存写指令集合设置在内存控制器的缓存空间中，内存控制器根据写地址，从至少两个内存写指令集合中确定目标内存写指令集合。
在一种可能的实施方式中，内存控制器根据写地址从至少两个内存写指令集合中确定目标内存写指令集合包括：NVM的总地址区间预先划分为至少两个地址区间，划分的地址区间的数量等于内存写指令集合的数量，至少两个地址区间中每个地址区间关联一个内存写指令集合，内存控制器判断写地址落入的地址区间，将写地址落入的地址区间关联的内存写指令集合作为目标内存写指令集合。
举例说明，参见图2b所示，指定数值等于1，内存控制器中设置有4个内存写指令集合，分别为：内存写指令集合1、内存写指令集合2、内存写指令集合3和内存写指令集合4，分别对应的信用度值的最大值为5、4、4和3，介质控制器中同样设置有4个介质写指令集合，介质写指令集合1、介质写指令集合2、介质写指令集合3和介质写指令集合4，4个内存写指令集合和4个介质写指令集合呈一一映射关系，映射关系为：内存写指令集合1关联介质写指令集合1，内存写指令集合2关联介质写指令集合2、内存写指令集合3关联介质写指令集合3，内存写指令集合4关联介质写指令集合4，每对关联的内存指令集合和介质写队列集合的信用度值的最大值相等。4个内存写指令集合和4个介质写指令集合配置的地址区间和信用度值如表1所示：
内存写指令集合 介质写指令集合 信用度值 地址区间
内存写指令集合1 介质写指令集合1 5 0x90000000～0x90ffffff
内存写指令集合2 介质写指令集合2 4 0x85600000～0x857fffff
内存写指令集合3 介质写指令集合3 4 0x65600000～0x657fffff
内存写指令集合4 介质写指令集合4 3 0x50000000～0x70ffffff
表1
内存控制器接收写指令，假设写指令包括待写数据的写地址0x656033fe，内存控制器根据4个地址区间确定写地址落入地址区间0x65600000～0x657fffff，该地址区间对应内存写指令集合3，内存写指令集合3为目标内存写指令集合，内存控制器将写指令存入到内存写指令集合3中。
S203、内存控制器将写指令存入目标内存写指令集合，并对目标内存写指令集合的信用度值减少指定数值。
具体的，信用度值表示允许进入目标内存写指令集合中的写指令的数量，在目标内存写指令集合的信用度值小于预设数值的情况下，目标内存写指令集合中不允许进入写指令，目标内存写指令集合的信用度值有一个最大值，最大值表示允许进入目标内存写指令集合中的写指令的最大数量。内存控制器将写指令存入目标内存写指令集合，例如：目标内存写指令集合的数据结构为队列，内存控制器将写指令存入目标内存写指令集合的队列尾；目标内存写指令集合的数据结构为堆栈，内存控制器将写指令存入目标内存写指令集合的栈顶。内存控制器将写指令存入到目标内存写指令集合后，将目标内存写指令集合的信用度值减少指定数值，指定数值的具体值不做限制，可根据需要进行设置。
续上例，参见图2c所示，内存控制器将内存写指令集合的信用度值4进行减1，更新后的内存写指令集合3的信用度值为3。
S204、内存控制器从目标内存写指令集合中取出写指令。
具体的，内存控制器可根据预设的选择规则从至少两个内存写指令集合选择一个内存写指令集合，在选择的内存写指令集合为S203的目标内存写指令集合的情况下，且S203中的写指令到达取出时刻时，内存控制器从目标内存写指令集合中取出写指令。其中，选择规则可以是：随机选择、根据内存写指令集合的编号轮询、根据内存写指令集合的优先级轮询等。
S205、内存控制器向介质控制器发送写指令。
其中，写指令中携带待写数据的写地址。
S206、介质控制器根据写指令携带的写地址，从至少两个介质写指令集合中确定目标介 质写指令集合。
具体的，介质写指令集合用于存储写指令，介质写指令集合的数据结构包括但不限于队列、链表、数组或堆栈，至少两个介质写指令集合可设置在介质控制器的内部，例如：至少两个介质写指令集合设置在介质控制器的缓存空间中，介质控制器根据写指令携带的写地址从至少两个介质写指令集合中确定目标介质写指令集合。
在一种可能的实施方式中，介质控制器确定目标介质写指令集合的方法可以是：NVM的总地址区间划分为至少连续且不重合的两个地址区间，至少两个地址区间中每个地址区间关联一个介质写指令集合，至少两个介质写指令集合中介质写指令集合的数量等于至少两个内存写指令集合中内存写指令集合的数量，具有关联的两个内存写指令集合和介质写指令集合配置的地址区间相同。介质控制器确定写地址落入的地址区间，将写地址落入的区间对应的介质写指令集合作为目标介质写指令集合。
续上例，参见图2c所示，内存控制器从内存写指令集合3中取出写指令，将写指令发送给介质控制器，介质控制器根据写指令的写地址0x656033fe确定写地址落入地址区间0x65600000～0x657fffff，该地址区间对应介质写指令集合3，介质写指令集合3为目标介质写指令集合，介质控制器将写指令存入到介质写指令集合3中。
S207、介质控制器将写指令存入目标介质写指令集合，将目标介质写指令集合的信用度值减少指定数值。
具体的，信用度值表示允许进入目标介质写指令集合中的写指令的数量，在目标介质写指令集合的信用度值小于预设数值的情况下，目标介质写指令集合中不允许进入写指令，目标介质写指令集合的信用度值有一个最大值，最大值表示允许进入目标介质写指令集合中的写指令的最大数量。由于具有关联关系的两个内存写指令集合和介质写指令集合具有相等的信用度值的最大值，因此目标内存写指令集合和目标介质写指令集合具有相等的信用度值的最大值。目标介质写指令集合的数据结构包括但不限于数组、链表、队列和堆栈。介质控制器在写指令存入目标介质写指令集合后，将目标介质写指令集合的信用度值减少指定数值，指定数值的具体值不作限制，可根据需要进行设置。
续上例，参见图2c所示，介质控制器将写指令存入到介质写指令集合3中，介质控制器将介质写指令集合3的信用度值4进行减1，介质写指令集合3更新后的的信用度值为3。
S208、介质控制器从目标介质写指令集合中取出写指令。
具体的，介质控制器可根据预设的选择规则从至少两个介质写指令集合中选择一个介质写指令集合，在选择的介质写指令集合为S207中的目标介质写指令集合的情况下，且目标介质写指令集合中S207的写指令到达取出时刻时，介质控制器从目标介质写指令集合中取出写指令。其中，从至少两个介质写指令集合中选择介质写指令集合的选择规则可是：随机选择、根据介质写指令集合的编号轮询、根据介质写指令集合的优先级轮询。
S209、介质控制器向NVM发送写指令。
具体的，介质控制器获取写指令中携带的写地址，根据预设的地址映射表，将写地址转换为物理块地址，介质控制器向NVM发送携带物理块地址的写指令。
S210、NVM执行写指令，完成持久化操作。
具体的，NVM将待写数据写入到物理块地址指向的地址块，在待写输入写入完毕后，完成持久化操作。
S211、NVM向介质控制器返回响应消息。响应消息用于通知介质控制器写指令在NVM完 成持久化操作。
S212、介质控制器将目标介质写指令集合的信用度值增加指定数值。
其中，介质控制器确定写指令在NVM上完成持久化操作时，将目标介质写指令集合的信用度值增加指定数值，这样经过S207的写指令进入目标介质写指令集合后信用度值减少指定数值，以及写指令完成持久化操作后目标介质写指令集合的信用度值增加指定数值，此时介质写指令集合的信用度值恢复为最大值。
续上例子，参见图2d所示，介质控制器从介质写指令集合3中取出该写指令发给NVM，NVM根据预设的地址映射表将写地址映射成物理块地址，NVM将待写数据写到物理块地址对应的物理块中，NVM在成功写入待写数据，完成持久化操作后可向介质控制器通知响应消息，介质控制器在确认写指令完成持久化操作后，将介质写指令集合3的信用度值加1，此时介质写指令集合3的信用度值变为4。
S213、目标内存写指令集合的信用度值与目标介质写指令集合的信用度值进行同步。
具体的，信用度值的同步方法可以是：内存控制器根据预设周期主动向介质控制器查询目标介质写指令集合的信用度值，目标介质写指令集合的信用度值可存储在介质控制器的寄存器中，内存控制器根据查询到的信用度值更新目标内存写指令集合的信用度值；或者，介质控制器在目标介质写指令集合的信用度值发生更新时，主动通知内存控制器，内存控制器根据通知的信用度值更新目标内存写指令集合的信用度值；或者目标介质写指令集合的信用度值携带在写指令的响应消息。
续上例，参见图2e所示，介质控制器将介质写指令集合3更新后的信用度值4发送给内存控制器，内存控制器根据介质写指令集合3的信用度值4将内存写指令集合3的信用度值更新为4。
可选的，在预设的指定数值为1的情况下，内存控制器确定目标内存写指令集合后，获取目标内存写指令集合当前的信用度值，判断当前的信用度值是否大于0，若判断结果为是，将写指令存入目标内存写指令集合；若判断结果为否，将写指令进行缓存处理，根据预设周期查询目标内存写指令集合的信用度值，在查询到目标内存写指令集合的信用度值大于0时，再将缓存的写指令存入目标内存写指令集合中。上述实施例，通过信用度值控制进入内存控制器的写指令的数量，避免内存控制器无法及时处理写指令导致过载。
可选的，介质控制器确定目标介质写指令集合后，获取目标介质写指令集合当前的信用度值，判断当前的信用度值是否大于0，若判断结果为是，将写指令存入目标介质写指令集合；若判断结果为否，将写指令进行缓存处理，根据预设周期查询目标介质写指令集合的信用度值，在查询到目标介质写指令集合的信用度值大于0时，再将缓存的写指令存入目标介质写指令集合中。上述实施例，通过信用度值控制进入介质控制器的写指令的数量，避免介质控制器无法及时处理写指令而导致过载。
可选的，本申请的一种非易失性内存的持久化方法还包括：
所述内存控制器接收针对所述目标内存写指令集合的持久化查询指令，以及获取所述持久化查询指令的接收时刻；
在所述接收时刻之后，所述内存控制器阻塞进入所述目标内存写指令集合的写指令；
所述内存控制器读取所述目标内存写指令集合的信用度值；
若读取到的信用度值等于预设的最大值，所述内存控制器确定所述目标内存写指令集合中的写指令完成持久化。
具体的，内存控制器接收目标内存写指令集合的持久化查询指令，持久化查询指令可由处理器发送，持久化查询指令可以是CPU指令或者调用函数，CPU指令或调用函数中携带目标内存写指令集合的标识，内存控制器接收接收持久化查询指令的接收时刻，在接收时刻之后，内存控制器阻塞进入目标内存写指令集合中的写指令，其中，至少两个内存写指令集合中的出目标内存写指令集合的其他内存写指令集合，内存控制器不进行阻塞操作。内存控制器读取目标内存写指令集合的信用度值，若读取到的信用度值等于预设的最大值，表明目标内存写指令集合中没有写指令占用信用度值，目标内存写指令集合中的写指令完成持久化操作。
续上例，参见图2e所示，内存控制器接收到针对内存写指令集合3的持久化查询指令时，内存控制器获取持久化查询指令的接收时刻为t0，内存控制器阻塞t0时刻之后进入到内存写指令集合3的写指令，阻塞的方法可以是：将t0时刻之后进入到内存写指令集合3的写指令进行缓存或者，对内存写指令集合加软件互斥锁，其中，内存写指令集合1、2和4仍能正常进入写指令；内存控制器获取内存写指令集合3的信用度值，发现内存写指令集合3的信用度值等于最大值4，则确定内存写指令集合3中没有写指令占用信用度值，内存写指令集合3完成持久化操作。
又例如，介质控制器接收针对介质写指令集合3的持久化查询指令，介质控制器获取介质写指令集合3的信用度值，发现介质写指令集合3的信用度值等于最大值4，则介质写指令集合3中没有写指令占用信用度值，介质写指令集合3中的写指令完成持久化操作。
可选的，在所述接收时刻之后，所述内存控制器阻塞进入所述目标内存写指令集合的写指令包括：
在所述接收时刻之后，所述内存控制器将进入所述目标内存写指令集合的写指令进行缓存处理；或
在所述接收时刻，所述内存控制器将所述目标内存写指令集合加软件互斥锁。
具体的，在接收时刻之后，内存控制器阻塞进入目标写指令集合的写指令的方法包括：在接收时刻之后，内存控制器将进入目标内存写指令集合的写指令进行缓存处理，内存控制器在确定目标内存写指令集合的信用度值等于预设的最大值时，将缓存的写指令发送给目标内存写指令集合；或者，内存控制器对目标内存写指令集合加软件互斥锁，从而阻塞进入目标内存写指令集合的写指令。
可选的，本申请的一种非易失性内存的持久化方法，还包括：
所述介质控制器接收针对目标介质写指令集合的持久化查询指令；
所述介质控制器读取所述目标介质写指令集合的信用度值；
若读取到的信用度值等于预设的最大值，所述介质控制器确定所述目标介质写指令集合中的写指令完成持久化操作。
具体的，介质控制器接收目标介质写指令集合的持久化查询指令，持久化查询指令可由处理器发送，持久化查询指令可以是CPU指令或者调用函数，CPU指令或调用函数中携带目标介质写指令集合的标识，介质控制器读取目标介质写指令集合的信用度值，若读取到的信用度值等于预设的最大值，表明目标介质写指令集合中没有写指令占用信用度值，目标介质写指令集合中的写指令完成持久化操作。
上述实施例，设置的多个内存写指令集合各自对应的信用度值与多个介质写指令集合各自对应的信用度值保持同步，由于介质控制器能够根据各个介质写指令集合的信用度值确定 写指令的执行状态，因此内存控制器与介质控制器的信用度值保持同步后，能准确根据信用度值查询写指令是否完成持久化。同时，通过设置多个内存写指令集合，在持久化查询时能实现以内存写指令集合为粒度的局部阻塞，以提高内存控制器的并行处理效率。
参见图3，为本申请实施例提供的一种计算设备的另一结构示意图，在本实施例中，计算设备包括内存控制器10、介质控制器11和NVM 12。其中，内存控制器10包括：缓存空间100、接收器101、缓存控制器102、n个计数器、发送器103，其中，缓存空间100内设置有n个内存写指令集合，每个内存写指令集合配置有一个计数器，n为大于1的整数。
介质控制器11包括：缓存空间110、接收器111、缓存控制器112、n个计数器和发送器113，其中，缓存空间110内设置有n个介质写指令集合，每个介质写指令集合配置有一个计数器。
NVM 12的总地址区间划分为n个地址区间，n个内存写指令集合与n个地址区间一一映射，且n个介质写指令集合与n个地址区间一一映射。
需要说明的是，内存控制器10和介质控制器11包括的各个部件可以通过专用集成电路(英文：Application-Specific Integrated Circuit，缩写：ASIC)实现，或可编程逻辑器件(英文：Programmable Logic Device，缩写：PLD)实现。上述PLD可以是复杂可编程逻辑器件(英文：Complex Programmable Logic Device，缩写：CPLD)，FPGA，通用阵列逻辑(英文：Generic Array Logic,缩写：GAL)或其任意组合。
计算设备的工作过程包括：
内存控制器10的接收器101，用于接收携带写地址的写指令；
内存控制器10的缓存控制器102，用于根据写地址，从内存控制器的缓存空间中存储的至少两个内存写指令集合中选择目标内存写指令集合，将写指令存入目标内存写指令集合，并对指示目标写指令集合的计数器目标内存写指令集合的信用度值减少指定数值；
内存控制器10的发送器103，用于将目标内存写指令集合中的写指令发送给介质控制器的接收器；
内存控制器10的接收器101还用于接收介质控制器的发送器发送的目标介质写指令集合的信用度值；
内存控制器10的缓存控制器102还用于指示内存控制器的计数器根据目标介质写指令集合的信用度值更新目标内存写指令集合的信用度值；
介质控制器11的接收器111用于接收内存控制器的发送器发送的写指令；
介质控制器11的缓存控制器112，用于根据写地址，从介质控制器的缓存空间中存储的至少两个介质写指令集合中确定目标介质写指令集合；将写指令存入目标介质写指令集合，指示目标介质写指令集合对应的计数器将目标介质写指令集合的信用度值减少指定数值；
介质控制器11的发送器113，用于将目标介质写指令集合中的写指令发送给NVM12；
介质控制器11的缓存控制器112还用于在NVM成功执行写指令后，指示目标介质写指令集合对应的计数器将目标介质写指令集合的信用度值增加指定数值；
介质控制器11的发送器113还用于将目标介质写指令集合的信用度值发送给内存控制器的接收器。
在一种可能的实施方式中，至少两个内存写指令集合中每个内存写指令集合配置有NVM的一个地址区间；
内存控制器10的缓存控制器102用于：
确定写地址所在的目标地址区间，将目标地址区间关联的内存写指令集合作为目标内存写指令集合；
将写指令存入目标内存写指令集合，指示目标介质写指令集合对应的计数器将目标内存写指令集合的信用度值减1。
在一种可能的实施方式中，至少两个介质写指令集合中每个介质写指令集合配置有NVM的一个地址区间；
介质控制器11的缓存控制器112用于：
确定写地址所在的目标地址区间，将目标地址区间关联的介质写指令集合作为目标介质写指令集合；
将写指令存入目标介质写指令集合，以及指示目标介质写指令集合对应的计数器将目标介质写指令集合的信用度值减1。
在一种可能的实施方式中，内存控制器10的缓存控制器102还用于：
通过调用库函数配置至少两个内存写指令集合中每个内存写指令集合的地址区间，以及配置至少两个介质写指令集合中每个介质写指令集合的地址区间；其中，至少两个内存写指令集合与至少两个介质写指令集合呈一一映射关系，关联的内存写指令集合和介质写指令集合具有相同的地址区间。
在一种可能的实施方式中，介质控制器11的发送器113用于：
根据内存控制器的发送器发送的信用度值查询请求，向内存控制器的接收器返回携带目标介质写指令集合的信用度值的查询响应。
在一种可能的实施方式中，介质控制器11的发送器113用于：
周期性的主动向内存控制器的接收器发送目标介质写指令集合的信用度值。
在一种可能的实施方式中，内存控制器10的缓存控制器102还用于：
接收针对目标内存写指令集合的持久化查询指令，以及获取持久化查询指令的接收时刻；阻塞在接收时刻之后进入目标内存写指令集合的写指令；在目标内存写指令集合对应的计数器中读取目标内存写指令集合的信用度值；若读取到的信用度值等于预设的最大值，确定目标内存写指令集合中的写指令完成持久化。
在一种可能的实施方式中，介质控制器11的缓存控制器112还用于：
根据接收的针对目标介质写指令集合的持久化查询指令，在目标介质写指令集合对应的计数器中读取目标介质写指令集合的信用度值；若读取到的信用度值等于预设的最大值，确定目标介质写指令集合中的写指令完成持久化操作。
上述实施例，设置的多个内存写指令集合各自对应的信用度值与多个介质写指令集合各自对应的信用度值保持同步，由于介质控制器能够根据各个介质写指令集合的信用度值确定写指令的执行状态，因此内存控制器与介质控制器的信用度值保持同步后，能准确根据信用度值查询写指令是否完成持久化。同时，通过设置多个内存写指令集合，在持久化查询时能实现以内存写指令集合为粒度的局部阻塞，以提高内存控制器的并行处理效率。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (33)

  1. 一种非易失性内存NVM的持久化方法，其特征在于，应用于将内存中的待写数据写入到所述非易失性内存NVM的过程中，所述方法包括：
    内存控制器接收写指令，所述写指令包括所述待写数据的写地址；
    所述内存控制器根据所述写地址，从至少两个内存写指令集合中选择目标内存写指令集合，将所述写指令存入所述目标内存写指令集合，并对所述目标内存写指令集合关联的信用度值减少指定数值；
    所述内存控制器将所述目标内存写指令集合中的所述写指令发送给所述介质控制器；
    在接收到所述写指令之后，所述介质控制器根据所述写地址，从所述至少两个介质写指令集合中确定目标介质写指令集合，将所述写指令存入所述目标介质写指令集合，将所述目标介质写指令集合的信用度值减少所述指定数值；
    所述介质控制器将所述目标介质写指令集合中的所述写指令发送给所述NVM，在所述NVM成功执行所述写指令后，所述介质控制器将所述目标介质写指令集合的信用度值增加所述指定数值；
    所述介质控制器将所述目标介质写指令集合的信用度值发送给所述内存控制器；
    在接收到所述目标介质写指令集合的信用度值之后，所述内存控制器根据所述目标介质写指令集合的信用度值更新所述目标内存写指令集合的信用度值。
  2. 如权利要求1所述的方法，其特征在于，所述至少两个内存写指令集合中每个内存写指令集合关联有所述NVM的一个地址区间；
    所述内存控制器根据所述写地址，从所述至少两个内存写指令集合中选择目标内存写指令集合，将所述写指令存入所述目标内存写指令集合，并对所述目标内存写指令集合的信用度值减少指定数值包括：
    所述内存控制器确定所述写地址所在的目标地址区间，将所述目标地址区间关联的内存写指令集合作为所述目标内存写指令集合；
    所述内存控制器将所述写指令存入所述目标内存写指令集合，以及将所述目标内存写指令集合的信用度值减1。
  3. 如权利要求2所述的方法，其特征在于，所述至少两个介质写指令集合中每个介质写指令集合配置有所述NVM的一个地址区间；
    所述介质控制器根据所述写地址，从所述至少两个介质写指令集合中确定目标介质写指令集合，将所述写指令存入所述目标介质写指令集合，将所述目标介质写指令集合的信用度值减少所述指定数值包括：
    所述介质控制器确定所述写地址所在的目标地址区间，将所述目标地址区间关联的介质写指令集合作为所述目标介质写指令集合；
    所述介质控制器将所述写指令存入所述目标介质写指令集合，以及将所述目标介质写指令集合的信用度值减1。
  4. 如权利要求3所述的方法，其特征在于，所述内存控制器接收写指令之前，还包括：
    所述内存控制器通过调用库函数配置所述至少两个内存写指令集合中每个内存写指令集合的地址区间，以及配置所述至少两个介质写指令集合中每个介质写指令集合的地址区间；其中，所述至少两个内存写指令集合与所述至少两个介质写指令集合呈一一映射关系，关联的内存写指令集合和介质写指令集合具有相同的地址区间。
  5. 如权利要求1-4任意一项所述的方法，其特征在于，所述介质控制器将所述目标介质写指令集合的信用度值发送给所述内存控制器包括：
    所述介质控制器接收所述内存控制器发送的查询请求；所述查询请求用于查询所述目标介质写指令集合的信用度值；
    所述介质控制器向所述内存控制器发送携带所述目标介质写指令集合的信用度值的查询响应。
  6. 如权利要求1-4任意一项所述的方法，其特征在于，所述介质控制器将所述目标介质写指令集合的信用度值发送给所述内存控制器包括：
    所述介质控制器周期性的主动向所述内存控制器发送所述目标介质写指令集合的信用度值。
  7. 如权利要求1所述的方法，其特征在于，还包括：
    所述内存控制器接收针对所述目标内存写指令集合的持久化查询指令，以及获取所述持久化查询指令的接收时刻；
    在所述接收时刻之后，所述内存控制器阻塞进入所述目标内存写指令集合的写指令；
    所述内存控制器读取所述目标内存写指令集合的信用度值；
    若读取到的信用度值等于预设的最大值，所述内存控制器确定所述目标内存写指令集合中的写指令完成持久化。
  8. 如权利要求7所述的方法，其特征在于，在所述接收时刻之后，所述内存控制器阻塞进入所述目标内存写指令集合的写指令包括：
    在所述接收时刻之后，所述内存控制器将进入所述目标内存写指令集合的写指令进行缓存处理；或
    在所述接收时刻，所述内存控制器将所述目标内存写指令集合加软件互斥锁。
  9. 如权利要求1所述的方法，其特征在于，还包括：
    所述介质控制器接收针对目标介质写指令集合的持久化查询指令；
    所述介质控制器读取所述目标介质写指令集合的信用度值；
    若读取到的信用度值等于预设的最大值，所述介质控制器确定所述目标介质写指令集合中的写指令完成持久化操作。
  10. 一种计算设备，其特征在于，包括：内存控制器、介质控制器和非易失性内存NVM，所述内存控制器包括缓存空间，所述内存控制器的缓存空间用来存储至少两个内存写指令集合，所述至少两个内存写指令集合中每个内存写指令集合配置有一个信用度值；所述介质控 制器包括缓存空间，所述介质控制器的缓存空间用来存储至少两个介质写指令集合，所述至少两个内存写指令集合中每个介质写指令集合配置有一个信用度值；
    所述内存控制器，用于：
    接收写指令，所述写指令包括待写数据的写地址；
    根据所述写地址，从所述内存控制器的缓存空间存储的所述至少两个内存写指令集合中选择目标内存写指令集合，将所述写指令存入所述目标内存写指令集合，并对所述目标内存写指令集合的信用度值减少指定数值；
    将所述目标内存写指令集合中的所述写指令发送给所述介质控制器；
    接收所述介质控制器发送的所述目标介质写指令集合的信用度值；
    根据所述目标介质写指令集合的信用度值更新所述目标内存写指令集合的信用度值；
    所述介质控制器，用于：
    接收内存控制器发送的所述写指令；
    根据所述写地址，从所述介质控制器的缓存空间存储的所述至少两个介质写指令集合中确定目标介质写指令集合；
    将所述写指令存入所述目标介质写指令集合，将所述目标介质写指令集合的信用度值减少所述指定数值；
    将所述目标介质写指令集合中的所述写指令发送给所述NVM，在所述NVM成功执行所述写指令后，将所述目标介质写指令集合的信用度值增加所述指定数值；
    将所述目标介质写指令集合的信用度值发送给所述内存控制器。
  11. 如权利要求10所述的计算设备，其特征在于，所述内存控制器还包括：接收器、缓存控制器、多个计数器、发送器，其中，每个内存写指令集合配置有一个计数器；
    所述介质控制器还包括：接收器、缓存控制器、多个计数器和发送器，其中，每个介质写指令集合配置有一个计数器；
    所述内存控制器的接收器，用于接收携带写地址的写指令；
    所述内存控制器的缓存控制器，用于根据所述写地址，从所述内存控制器的缓存空间中存储的所述至少两个内存写指令集合中选择目标内存写指令集合，将所述写指令存入所述目标内存写指令集合，并对指示所述目标写指令集合的计数器所述目标内存写指令集合的信用度值减少指定数值；
    所述内存控制器的发送器，用于将所述目标内存写指令集合中的所述写指令发送给所述介质控制器的接收器；
    所述内存控制器的接收器还用于接收所述介质控制器的发送器发送的所述目标介质写指令集合的信用度值；
    所述内存控制器的缓存控制器还用于指示所述内存控制器的计数器根据所述目标介质写指令集合的信用度值更新所述目标内存写指令集合的信用度值；
    所述介质控制器的接收器用于接收所述内存控制器的发送器发送的所述写指令；
    所述介质控制器的缓存控制器，用于根据所述写地址，从所述介质控制器的缓存空间中存储的所述至少两个介质写指令集合中确定目标介质写指令集合；将所述写指令存入所述目标介质写指令集合，指示所述目标介质写指令集合对应的计数器将所述目标介质写指令集合 的信用度值减少所述指定数值；
    所述介质控制器的发送器，用于将所述目标介质写指令集合中的所述写指令发送给所述NVM；
    所述介质控制器的缓存控制器还用于在所述NVM成功执行所述写指令后，指示所述目标介质写指令集合对应的计数器将所述目标介质写指令集合的信用度值增加所述指定数值；
    所述介质控制器的发送器还用于将所述目标介质写指令集合的信用度值发送给所述内存控制器的接收器。
  12. 如权利要求11所述的计算设备，其特征在于，所述至少两个内存写指令集合中每个内存写指令集合配置有所述NVM的一个地址区间；
    所述内存控制器的缓存控制器用于：
    确定所述写地址所在的目标地址区间，将所述目标地址区间关联的内存写指令集合作为所述目标内存写指令集合；
    将所述写指令存入所述目标内存写指令集合，指示所述目标介质写指令集合对应的计数器将所述目标内存写指令集合的信用度值减1。
  13. 如权利要求12所述的计算设备，其特征在于，所述至少两个介质写指令集合中每个介质写指令集合配置有所述NVM的一个地址区间；
    所述介质控制器的缓存控制器用于：
    确定所述写地址所在的目标地址区间，将所述目标地址区间关联的介质写指令集合作为所述目标介质写指令集合；
    将所述写指令存入所述目标介质写指令集合，以及指示所述目标介质写指令集合对应的计数器将所述目标介质写指令集合的信用度值减1。
  14. 如权利要求13所述的计算设备，其特征在于，所述内存控制器的缓存控制器还用于：
    通过调用库函数配置所述至少两个内存写指令集合中每个内存写指令集合的地址区间，以及配置所述至少两个介质写指令集合中每个介质写指令集合的地址区间；其中，所述至少两个内存写指令集合与所述至少两个介质写指令集合呈一一映射关系，关联的内存写指令集合和介质写指令集合具有相同的地址区间。
  15. 如权利要求11-14任意一项所述的计算设备，其特征在于，所述介质控制器的发送器用于：
    根据所述内存控制器的发送器发送的所述信用度值查询请求，向所述内存控制器的接收器返回携带所述目标介质写指令集合的信用度值的查询响应。
  16. 如权利要求11-14任意一项所述的计算设备，其特征在于，所述介质控制器的发送器用于：
    周期性的主动向所述内存控制器的接收器发送所述目标介质写指令集合的信用度值。
  17. 如权利要求11所述的计算设备，其特征在于，所述内存控制器的缓存控制器还用于：
    接收针对所述目标内存写指令集合的持久化查询指令，以及获取所述持久化查询指令的接收时刻；阻塞在所述接收时刻之后进入所述目标内存写指令集合的写指令；在所述目标内存写指令集合对应的计数器中读取所述目标内存写指令集合的信用度值；若读取到的信用度值等于预设的最大值，确定所述目标内存写指令集合中的写指令完成持久化。
  18. 如权利要求11所述的计算设备，其特征在于，所述介质控制器的控制器还用于：
    根据接收的针对目标介质写指令集合的持久化查询指令，在所述目标介质写指令集合对应的计数器中读取所述目标介质写指令集合的信用度值；若读取到的信用度值等于预设的最大值，确定所述目标介质写指令集合中的写指令完成持久化操作。
  19. 一种确认数据持久化的方法，其特征在于，所述方法应用于计算机系统中，所述计算机系统包括内存控制器、介质控制器以及与所述介质控制器连接的非易失性内存NVM，所述方法包括：
    所述内存控制器接收所述介质控制器发送的目标介质写指令集合的信用度值,其中，所述介质控制器关联有多个介质写指令集合，所述内存控制器关联有多个内存写指令集合，所述目标介质写指令集合的写指令来自于所述内存控制器中的目标内存写指令集合，所述目标介质写指令集合为所述多个介质写指令集合中的一个，所述目标内存写指令集合为所述多个内存写指令集合中的一个，所述目标内存写指令集合和所述目标介质写指令集合具有相同的信用度值的最大值，所述目标介质写指令集合的信用度值用于表示允许进入所述目标介质写指令集合中的写指令的数量；
    所述内存控制器根据所述目标介质写指令集合的信用度值更新所述目标内存写指令集合的信用度值，所述目标内存写指令结合的信用度值用于表示允许进入内存写指令集合的写指令的数量；
    当更新后的所述目标内存写指令集合的信用度值等于所述最大值时，所述内存控制器确定所述目标内存写指令集合中的写指令中的待写数据已被持久化。
  20. 根据权利要求19所述的方法，其特征在于，在所述内存控制器接收所述介质控制器发送的目标介质写指令集合的信用度值之前，所述方法还包括：
    所述内存控制器接收写指令，所述写指令包括所述待写数据的写地址；
    所述内存控制器将所述写指令存入与所述写地址对应的所述目标内存写指令集合中，并对所述目标内存写指令集合的信用度值减少指定数值；
    所述内存控制器将所述目标内存写指令集合中的所述写指令发送给所述介质控制器；
    所述介质控制器将所述写指令存入与所述写地址对应的目标介质写指令集合，并将所述目标介质写指令集合的信用度值减少所述指定数值；
    在将所述目标介质写指令集合的写指令的所述待写入数据写入所述NVM后，所述介质控制器将所述目标介质写指令集合的信用度值增加所述指定数值。
  21. 根据权利要求20所述的方法，其特征在于，所述多个内存写指令集合中每个内存写指令集合关联有所述NVM的一个地址区间；所述多个介质写指令集合中每个介质写指令集合关联有所述NVM的一个地址区间；
    所述内存控制器将所述写指令存入与所述写地址对应的所述目标内存写指令集合中包括：
    所述内存控制器将所述写指令存入与所述写地址所属的目标地址区间关联的所述目标内存写指令集合中；
    所述介质控制器将所述写指令存入与所述写地址对应的目标介质写指令集合包括：
    所述介质控制器将所述写指令存入与所述写地址所属的目标地址区间关联的所述目标介质写指令集合中。
  22. 根据权利要求19-21任意一项所述的方法，其特征在于，还包括：
    所述内存控制器接收针对所述目标内存写指令集合的持久化查询指令；
    所述内存控制器阻塞在接收所述持久化查询指令之后待存入所述目标内存写指令集合的写指令；
    所述内存控制器向所述介质控制器发送所述持久化查询指令；
    所述内存控制器接收所述介质控制器发送的目标介质写指令集合的信用度值包括：
    所述内存控制器接收所述介质控制器响应所述持久化查询指令向所述内存控制器发送的所述目标介质写指令集合的信用度值。
  23. 根据权利要求19-21任意一项所述的方法，其特征在于，所述内存控制器接收所述介质控制器发送的目标介质写指令集合的信用度值包括：
    所述内存控制器接收所述介质控制器周期性的向所述内存控制器发送的所述目标介质写指令集合的信用度值。
  24. 根据权利要求22所述的方法，其特征在于，还包括：
    所述介质控制器接收所述内存控制器发送的所述持久化查询指令；
    所述介质控制器读取所述目标介质写指令集合的信用度值；
    当读取的所述目标介质写指令集合的信用度值等于所述最大值时，所述介质控制器确定所述目标介质写指令集合中的写指令中的数据已被持久化。
  25. 根据权利要求19-24任意一项所述的方法，其特征在于，还包括：
    所述内存控制器配置与所述多个内存写指令集合中每个内存写指令集合关联的地址区间；
    所述内存控制器配置与所述多个介质写指令集合中每个介质写指令集合关联的地址区间；
    其中，所述多个内存写指令集合与所述多个介质写指令集合呈一一映射关系，具有映射关系的内存写指令集合和介质写指令集合与同一个地址区间相关联。
  26. 一种计算机系统，其特征在于，包括内存控制器、介质控制器以及与所述介质控制器连接的非易失性内存NVM，
    所述内存控制器的缓存空间存储有多个内存写指令集合，所述至少两个内存写指令集合中的每个内存写指令集合配置有一个信用度值；
    所述介质控制器的缓存空间存储有多个介质写指令集合，所述至少两个介质写指令集合中的每个介质写指令集合配置有一个信用度值；
    所述内存控制器用于：
    接收所述介质控制器发送的目标介质写指令集合的信用度值,其中，所述介质控制器关联有多个介质写指令集合，所述内存控制器关联有多个内存写指令集合，所述目标介质写指令集合的写指令来自于所述内存控制器中的目标内存写指令集合，所述目标介质写指令集合为所述多个介质写指令集合中的一个，所述目标内存写指令集合为所述多个内存写指令集合中的一个，所述目标内存写指令集合和所述目标介质写指令集合具有相同的信用度值的最大值，所述目标介质写指令集合的信用度值用于表示允许进入所述目标介质写指令集合中的写指令的数量；
    根据所述目标介质写指令集合的信用度值更新所述目标内存写指令集合的信用度值，所述目标内存写指令结合的信用度值用于表示允许进入内存写指令集合的写指令的数量；
    当更新后的所述目标内存写指令集合的信用度值等于所述最大值时，确定所述目标内存写指令集合中的写指令中的待写数据已被持久化。
  27. 根据权利要求26所述的计算机系统，其特征在于，
    所述内存控制器还用于：
    接收写指令，所述写指令包括所述待写数据的写地址；
    将所述写指令存入与所述写地址对应的所述目标内存写指令集合中，并对所述目标内存写指令集合的信用度值减少指定数值；
    将所述目标内存写指令集合中的所述写指令发送给所述介质控制器；
    所述介质控制器还用于：
    将所述写指令存入与所述写地址对应的目标介质写指令集合，并将所述目标介质写指令集合的信用度值减少所述指定数值；
    在将所述目标介质写指令集合的写指令的所述待写入数据写入所述NVM后，将所述目标介质写指令集合的信用度值增加所述指定数值。
  28. 根据权利要求27所述的计算机系统，其特征在于，所述多个内存写指令集合中每个内存写指令集合关联有所述NVM的一个地址区间；所述多个介质写指令集合中每个介质写指令集合关联有所述NVM的一个地址区间；
    所述内存控制器用于将所述写指令存入与所述写地址所属的目标地址区间关联的所述目标内存写指令集合中；
    所述介质控制器用于将所述写指令存入与所述写地址所属的目标地址区间关联的所述目标介质写指令集合中。
  29. 根据权利要求26-28任意一项所述的计算机系统，其特征在于，所述内存控制器还用于：
    接收针对所述目标内存写指令集合的持久化查询指令；
    阻塞在接收所述持久化查询指令之后待存入所述目标内存写指令集合的写指令；
    向所述介质控制器发送所述持久化查询指令；
    接收所述介质控制器响应所述持久化查询指令向所述内存控制器发送的所述目标介质写指令集合的信用度值。
  30. 根据权利要求26-28任意一项所述的计算机系统，其特征在于，所述内存控制器用于：
    接收所述介质控制器周期性的向所述内存控制器发送的所述目标介质写指令集合的信用度值。
  31. 根据权利要求29所述的计算机系统，其特征在于，所述介质控制器用于：
    接收所述内存控制器发送的所述持久化查询指令；
    读取所述目标介质写指令集合的信用度值；
    当读取的所述目标介质写指令集合的信用度值等于所述最大值时，确定所述目标介质写指令集合中的写指令中的数据已被持久化。
  32. 根据权利要求26-31任意一项所述的计算机系统，其特征在于，所述内存控制器还用于：
    配置与所述多个内存写指令集合中每个内存写指令集合关联的地址区间；
    配置与所述多个介质写指令集合中每个介质写指令集合关联的地址区间；
    其中，所述多个内存写指令集合与所述多个介质写指令集合呈一一映射关系，具有映射关系的内存写指令集合和介质写指令集合与同一个地址区间相关联。
  33. 一种计算机可读存储介质，包括一个或多个计算机可执行指令，当所述一个或多个计算机可执行指令在计算机上运行时，使得计算机执行如权利要求19-25任意一项所述的方法。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3834069A4 (en) * 2018-08-08 2022-05-04 Micron Technology, Inc. OPTIMIZATION OF INFORMATION REQUESTS IN A MEMORY SYSTEM
EP3834068A4 (en) * 2018-08-08 2022-05-04 Micron Technology, Inc. PROACTIVE RECYCLING OF WRITING BALANCE IN A STORAGE SYSTEM

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107885671B (zh) * 2016-09-30 2021-09-14 华为技术有限公司 一种非易失性内存的持久化方法和计算设备
US11048645B2 (en) * 2018-02-01 2021-06-29 Samsung Electronics Co., Ltd. Memory module, operation method therof, and operation method of host
US10969994B2 (en) 2018-08-08 2021-04-06 Micron Technology, Inc. Throttle response signals from a memory system
US11409436B2 (en) 2018-08-08 2022-08-09 Micron Technology, Inc. Buffer management in memory systems for read and write requests
US11947995B2 (en) 2020-05-19 2024-04-02 Intel Corporation End-to-end data protection for far memory data transfer from host to media
US20220374168A1 (en) * 2021-05-21 2022-11-24 Micron Technology, Inc. Memory with memory-initiated command insertion, and associated systems, devices, and methods

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1790293A (zh) * 2004-12-17 2006-06-21 自动车电机工业株式会社 用于非易失性存储器的数据写装置
CN101082852A (zh) * 2006-05-29 2007-12-05 联阳半导体股份有限公司 用于存储器的控制装置及控制方法
CN104239252A (zh) * 2013-06-21 2014-12-24 华为技术有限公司 数据存储系统的数据传输方法、装置及系统

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6289386B1 (en) * 1998-05-11 2001-09-11 Lsi Logic Corporation Implementation of a divide algorithm for buffer credit calculation in a high speed serial channel
TW451132B (en) * 1998-12-15 2001-08-21 Nippon Electric Co System and method for cache processing
US7103672B1 (en) * 2000-05-01 2006-09-05 Hewlett-Packard Development Company, L.P. Method and apparatus for improving system performance through remote credit management
JP3525867B2 (ja) * 2000-07-07 2004-05-10 日本電気株式会社 通信装置および通信端末
JP4403677B2 (ja) * 2001-08-27 2010-01-27 ブラザー工業株式会社 通信装置及び通信システム
CN1292568C (zh) 2001-09-02 2006-12-27 中兴通讯股份有限公司 一种多队列数据分组连续转发的装置和方法
CN1249722C (zh) 2002-01-23 2006-04-05 华为技术有限公司 多计数器的构造方法、多计数器及使用其的多队列装置
JP2006309579A (ja) * 2005-04-28 2006-11-09 Hitachi Ltd 記憶制御装置及びストレージシステム
US8516211B2 (en) * 2005-06-17 2013-08-20 Flexera Software Llc Secure storage management system and method
US7702871B1 (en) * 2007-08-31 2010-04-20 Emc Corporation Write pacing
CN101801061B (zh) 2010-02-11 2013-06-05 华为技术有限公司 一种信用度消耗法则上报方法、准入控制方法及装置
JP2012252416A (ja) * 2011-05-31 2012-12-20 Toshiba Corp 記憶装置、データ制御方法、及びデータコントローラ
US10176184B2 (en) * 2012-01-17 2019-01-08 Oracle International Corporation System and method for supporting persistent store versioning and integrity in a distributed data grid
JP5978660B2 (ja) * 2012-03-06 2016-08-24 ソニー株式会社 情報処理装置及び情報処理方法
KR101380452B1 (ko) 2012-08-14 2014-04-14 한국과학기술원 버퍼리스 온칩 네트워크의 전력 소모 감소를 위한 목적지 기반 크레딧 흐름 제어 방법 및 장치
US10346095B2 (en) * 2012-08-31 2019-07-09 Sandisk Technologies, Llc Systems, methods, and interfaces for adaptive cache persistence
CN102890631B (zh) * 2012-09-13 2016-12-07 新浪网技术(中国)有限公司 基于持久化消息队列传输消息的方法及消息传输装置
KR101932920B1 (ko) 2012-09-14 2019-03-18 삼성전자 주식회사 비휘발성 메모리 카드를 제어하는 호스트, 이를 포함하는 시스템 및 이의 동작 방법
KR20160127168A (ko) * 2013-03-15 2016-11-02 인텔 코포레이션 메모리 시스템
JP2014230072A (ja) * 2013-05-22 2014-12-08 株式会社リコー データ通信デバイス、データ通信装置及びデータ通信方法
CN103268291B (zh) * 2013-05-23 2016-02-24 清华大学 在闪存存储系统中延迟持久化索引元数据的方法
US9423959B2 (en) * 2013-06-29 2016-08-23 Intel Corporation Method and apparatus for store durability and ordering in a persistent memory architecture
WO2015005903A1 (en) 2013-07-09 2015-01-15 Hewlett-Packard Development Company, L.P. Write flow control for memory modules that include or interface with non-compliant memory technologies
WO2015155824A1 (ja) * 2014-04-07 2015-10-15 株式会社日立製作所 ストレージシステム
CN104079502B (zh) 2014-06-27 2017-05-10 国家计算机网络与信息安全管理中心 一种多用户多队列调度方法
JP6331787B2 (ja) * 2014-07-08 2018-05-30 富士通株式会社 データ送受信システム、データ送信装置およびデータ送受信システムの制御方法
US10489158B2 (en) * 2014-09-26 2019-11-26 Intel Corporation Processors, methods, systems, and instructions to selectively fence only persistent storage of given data relative to subsequent stores
US9626297B2 (en) * 2014-10-08 2017-04-18 Wisconsin Alumni Research Foundation Memory fault patching using pre-existing memory structures
US20160188414A1 (en) * 2014-12-24 2016-06-30 Intel Corporation Fault tolerant automatic dual in-line memory module refresh
US10318340B2 (en) * 2014-12-31 2019-06-11 Ati Technologies Ulc NVRAM-aware data processing system
US11086521B2 (en) * 2015-01-20 2021-08-10 Ultrata, Llc Object memory data flow instruction execution
CN104881371B (zh) * 2015-05-29 2018-02-09 清华大学 持久性内存事务处理缓存管理方法与装置
US10579560B2 (en) * 2016-08-31 2020-03-03 Futurewei Technologies, Inc. Transaction-based hybrid memory
CN107885671B (zh) * 2016-09-30 2021-09-14 华为技术有限公司 一种非易失性内存的持久化方法和计算设备

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1790293A (zh) * 2004-12-17 2006-06-21 自动车电机工业株式会社 用于非易失性存储器的数据写装置
CN101082852A (zh) * 2006-05-29 2007-12-05 联阳半导体股份有限公司 用于存储器的控制装置及控制方法
CN104239252A (zh) * 2013-06-21 2014-12-24 华为技术有限公司 数据存储系统的数据传输方法、装置及系统

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3514690A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3834069A4 (en) * 2018-08-08 2022-05-04 Micron Technology, Inc. OPTIMIZATION OF INFORMATION REQUESTS IN A MEMORY SYSTEM
EP3834068A4 (en) * 2018-08-08 2022-05-04 Micron Technology, Inc. PROACTIVE RECYCLING OF WRITING BALANCE IN A STORAGE SYSTEM

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