WO2018059108A1 - Dispositif semi-conducteur, procédé de fabrication de celui-ci et appareil électronique le comprenant - Google Patents

Dispositif semi-conducteur, procédé de fabrication de celui-ci et appareil électronique le comprenant Download PDF

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Publication number
WO2018059108A1
WO2018059108A1 PCT/CN2017/095130 CN2017095130W WO2018059108A1 WO 2018059108 A1 WO2018059108 A1 WO 2018059108A1 CN 2017095130 W CN2017095130 W CN 2017095130W WO 2018059108 A1 WO2018059108 A1 WO 2018059108A1
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layer
source
drain
semiconductor
channel layer
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PCT/CN2017/095130
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English (en)
Chinese (zh)
Inventor
朱慧珑
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中国科学院微电子研究所
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Priority claimed from CN201610872541.2A external-priority patent/CN106298778A/zh
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US16/338,169 priority Critical patent/US11195765B2/en
Publication of WO2018059108A1 publication Critical patent/WO2018059108A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Definitions

  • an electronic device including an integrated circuit formed of the above semiconductor device is provided.
  • a gate stack is formed around the outer circumference of the channel layer and a channel is formed in the channel layer, so that the gate length is determined by the thickness of the channel layer.
  • the channel layer can be formed, for example, by epitaxial growth, so that its thickness can be well controlled. Therefore, the gate length can be well controlled.
  • Vertical devices formed in different regions on the substrate can have different gate lengths.
  • the outer circumference of the channel layer may be recessed inwardly with respect to the outer circumferences of the first and second source/drain layers, so that the gate stack may be embedded in the recess, reducing or even avoiding overlap with the source/drain regions, contributing to Reduce the parasitic capacitance between the gate and the source/drain.
  • the channel layer may be a single crystal semiconductor material, which may have high carrier mobility and low leakage current, thereby improving device performance.
  • 29 to 32 are schematic views showing a part of stages in a process of fabricating a semiconductor device in accordance with another embodiment of the present disclosure.
  • a vertical type semiconductor device may include a first source/drain layer, a channel layer, and a second source/drain layer which are sequentially stacked on a substrate.
  • the layers may be adjacent to each other, although other semiconductor layers may be present in the middle, such as a leakage suppression layer and/or an on-state current enhancement layer (a semiconductor layer having a band gap larger or smaller than an adjacent layer).
  • Source/drain regions of the device may be formed in the first source/drain layer and the second source/drain layer, and a channel region of the device may be formed in the channel layer.
  • a conductive path may be formed through the channel region between the source/drain regions at both ends of the channel region.
  • the gate stack particularly the gate conductor layer therein, may need to be first
  • the device and the second device are formed differently (for example, gate conductor materials of different work functions are used to form gate conductor layers of the n-type device and the p-type device, respectively).
  • the first device and the second device can each comprise a respective gate conductor material having a suitable work function and embedded within the respective recess.
  • a gate conductor layer of a device may extend outward from a respective recess to act as a gate contact pad, and another portion of its gate conductor layer may extend to another device (eg, The gate conductor layer of the second device) acts as a gate contact pad.
  • different stress engineering may be performed separately for the first device and the second device to introduce different stresses in the respective second source/drain layers of the first device and the second device.
  • Stress engineering can include strain source/drain, stress liners, stress memory, and the like.
  • at least one of the second source/drain layers of each of the first device and the second device may comprise a stressed semiconductor material (which may be referred to as a "first semiconductor material") to be in the channel layer Stress is generated in the middle.
  • the stressed semiconductor material may be adjacent to the channel layer, or an intermediate layer may be present between the stressed semiconductor layer and the channel layer (for example, as a seed layer for growing a stress-bearing semiconductor layer, which may be referred to as a "second semiconductor" material").
  • the lattice constant of the first semiconductor material when there is no strain may be greater than the lattice constant of the second semiconductor material when there is no strain, thereby generating compressive stress in the channel layer (especially for p-type devices); or,
  • the lattice constant of a semiconductor material when unstrained can be less than the lattice constant of the second semiconductor material when there is no strain, thereby generating tensile stress in the channel layer (especially for n-type devices).
  • the first semiconductor material is a first SiGe
  • the second semiconductor material is a second SiGe
  • the Ge concentration in the first SiGe is greater than the Ge concentration in the second SiGe.
  • the first semiconductor material is a first SiGe
  • the second semiconductor material is a second SiGe
  • the Ge concentration in the first SiGe is less than the Ge concentration in the second SiGe.
  • the channel layer single crystal semiconductor material may have the same crystal structure as the first and second source/drain layers (particularly, a portion in which the channel layer is adjacent, such as the above intermediate layer).
  • the lattice constants of the first and second source/drain layers may be larger than the channel layer single crystal semiconductor without strain. The lattice constant of the material without strain.
  • the hole mobility of the channel layer single crystal semiconductor material may be greater than the hole mobility thereof without strain, or the effective mass of the light hole of the channel layer single crystal semiconductor material may be smaller than that without strain
  • the effective mass of the light holes in the case, or the concentration of the light holes of the channel layer single crystal semiconductor material may be greater than the concentration of the light holes in the absence of strain.
  • the lattice constants of the first and second source/drain layers may be smaller than the channel layer single crystal semiconductor material without strain The lattice constant without strain.
  • the electron mobility of the channel layer single crystal semiconductor material is greater than the electron mobility in the absence of strain, or the electron of the channel layer single crystal semiconductor material.
  • the effective mass is less than the effective mass of the electrons in the absence of strain.
  • the layers in the active region can be formed by epitaxial growth so that the thickness can be precisely controlled.
  • the first source/drain layer may be a semiconductor layer epitaxially grown on a substrate
  • the channel layer may be a semiconductor layer epitaxially grown on the first source/drain layer
  • the second source/drain layer may be in the channel A semiconductor layer epitaxially grown on the layer.
  • a liner may also be disposed on the surfaces of the first source/drain layer and the second source/drain layer of each of the first device and/or the second device.
  • the liner can even be stressed.
  • the stress liner can be compressively stressed to create tensile stress in the channel layer; for p-type devices, the stress liner can be tensile stressed to create compressive stress in the channel layer. Therefore, the device performance can be further improved.
  • Such a semiconductor device can be manufactured, for example, as follows. Specifically, a stack of the first source/drain layer, the channel layer, and the second source/drain layer may be disposed on the substrate. The first source/drain layer may be provided by the substrate itself or by epitaxial growth on the substrate. Next, a channel layer may be epitaxially grown on the first source/drain layer, and a second source/drain layer may be epitaxially grown on the channel layer. At the time of epitaxial growth, the thickness of the grown channel layer can be controlled. Due to epitaxial growth, respectively, at least one pair of adjacent layers may have a clear crystal interface. In addition, the layers may be separately doped differently, such that at least one pair of adjacent layers may have a doping concentration interface.
  • a certain process can be performed such that it can have different thicknesses in the first device region and the second device region. For example, it can be in a certain device region after growing the channel layer A portion of the domain is thinned (eg, etched), or a channel layer is further grown (ie, thickened) in a device region; or, may be in a device region after the first source/drain layer is grown The portion is subjected to a thinning process (for example, etching), and then the long channel layer is regenerated.
  • a thinning process for example, etching
  • the active regions of the first device and the second device may be defined in the first device region and the second device region, respectively. For example, they can be selectively etched sequentially into a desired shape.
  • the respective active regions of the first device and the second device may be derived from the same first source/drain layer, channel layer, and second source/drain layer.
  • the active region may be columnar (eg, cylindrical).
  • the outer circumference of the channel layer may be recessed inwardly with respect to the outer circumferences of the first and second source/drain layers to define a space for accommodating the gate stack. For example, this can be achieved by selective etching. In this case, the gate stack can be embedded in the recess.
  • Source/drain regions may be formed in the first and second source/drain layers. For example, this can be achieved by doping the first and second source/drain layers. For example, ion implantation, plasma doping, or the like can be performed.
  • a sacrificial gate may be formed in the recess formed on the outer circumference of the channel layer with respect to the outer circumferences of the first and second source/drain layers, and then on the surfaces of the first and second source/drain layers A dopant source layer is formed and dopants in the dopant source layer enter the active region through the first and second source/drain layers by, for example, annealing.
  • the sacrificial gate can prevent dopants in the dopant source layer from directly entering the channel layer. However, a portion of the dopant may enter the end of the channel layer adjacent to the first source/drain layer and the second source/drain layer via the first and second source/drain layers. If the first device and the second device have different conductivity types, doping can be performed separately.
  • stress engineering can also be applied to introduce different stresses in the respective second source/drain layers of the first device and the second device.
  • strain source/drain techniques can be applied.
  • a strained or stressed material may be introduced into the second source/drain layer of at least one of the first device and the second device to facilitate the trench Stress is generated in the layer.
  • the second source/drain layer can be patterned to at least partially remove the second source/drain layer and then with the remaining portion of the second source/drain layer (in the case where the second source/drain layer is not completely removed)
  • the underlying layer or the channel layer is a seed to grow the stressed semiconductor material.
  • 1 to 26 are schematic views showing a flow of manufacturing a semiconductor device in accordance with an embodiment of the present disclosure.
  • description will be made by taking an n-type device and a p-type device, respectively, as an example to more fully show the case of forming devices of different conductivity types. It should be understood that it is of course also possible to form devices of the same conductivity type.
  • a substrate 1001 is provided.
  • the substrate 1001 may be various forms of substrates including, but not limited to, bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrate will be described as an example for convenience of explanation.
  • a p-type silicon wafer is provided as the substrate 1001.
  • an n-type well region 1001w can be formed, for example, by ion implantation.
  • a p-type device may be formed on the n-type well region 1001w (thus referred to as a p-type device region); and an n-type device may be formed on other regions of the p-type Si substrate 1001 (hence it is referred to as an n-type device) region).
  • the first source/drain layer 1031, the channel layer 1003, and the second source/drain layer 1005 may be sequentially formed by, for example, epitaxial growth.
  • the first source/drain layer 1031 may include SiGe (the atomic percentage of Ge may be about 10-40%) and the thickness is about 20-50 nm;
  • the channel layer 1003 may include Si and have a thickness of about 10-100 nm;
  • the source/drain layer 1005 may include SiGe (the atomic percentage of Ge may be about 10-40%) and the thickness is about 20-50 nm.
  • the lattice constant of SiGe without strain is greater than the lattice constant of Si without strain.
  • the material selection of the first source/drain layer 1031, the channel layer 1003, and the second source/drain layer 1005 is not limited thereto, and may include other semiconductor materials capable of providing appropriate etching selectivity.
  • the channel layer 1003 may comprise a Si:C, Ge or III-V compound semiconductor material.
  • the channel layer 1003 may include the same constituent components as the first source/drain layer 1031, the second source/drain layer 1005, but a semiconductor material having a different composition content (for example, all of SiGe, but an atom of Ge) The percentages are different) as long as the channel layer 1031 has an etch selectivity with respect to the first source/drain layer 1031 and the second source/drain layer 1005 thereon.
  • first source/drain layer 1031 and the second source/drain layer 1005 may include Si:C (the atomic percentage of C may be about 0.1 to 5%), and the channel layer 1003 may include Si.
  • Si:C is not strained
  • the lattice constant in the case is smaller than the lattice constant of Si in the absence of strain.
  • the dielectric layer 1501 can be formed by, for example, deposition.
  • the dielectric layer 1501 can function as a mask, a protective layer, or the like.
  • dielectric layer 1501 can include a nitride having a thickness of between about 10 and 100 nm.
  • the active area of the device can be defined. For example, this can be done as follows. Specifically, as shown in FIGS. 2(a) and 2(b) (Fig. 2(a) is a cross-sectional view, and Fig. 2(b) is a plan view, in which the line AA' shows the intercepted position of the cross section), A photoresist (not shown) is formed on the dielectric layer 1501 shown in FIG. 1, and the photoresist is patterned into a desired shape (in this example, substantially circular) by photolithography (exposure and development), and patterned.
  • a desired shape in this example, substantially circular
  • the active regions for the p-type device and the n-type device are patterned in the p-type device region and the n-type device region, respectively.
  • the first source/drain layer, the channel layer, and the second source/drain layer for the p-type device are denoted as 1031p, 1003p, and 1005p, respectively, and will be the first source for the n-type device/
  • the drain layer, the channel layer, and the second source/drain layer are labeled as 1031n, 1003n, and 1005n, respectively.
  • the reference numerals of 1031, 1003, and 1005 are used; and when the p-type device region and the n-type device region are separately described, , the reference numerals of 1031p, 1003p, and 1005p and 1031n, 1003n, and 1005n are used, respectively.
  • the lattice constant of Si:C in the absence of strain is smaller than the lattice constant of Si without strain.
  • Producing strain in Si which causes the electron mobility of Si to be greater than the electron mobility in the absence of strain, or the effective mass of Si electrons is less than the effective mass of electrons in the absence of strain This in turn increases the on-state current of the n-type device and thereby enhances the performance of the n-type device.
  • this option can increase the on-state current of the p-type device and reduce the off-state current of the p-type device, thereby enhancing the p-type.
  • the performance of the device The reason is that the forbidden band width of Si is larger than the forbidden band width of SiGe, and the hole mobility in SiGe is larger than the hole mobility of Si.
  • the outer circumference of the channel layer 1003 may be recessed with respect to the outer circumferences of the first source/drain layer 1031 and the second source/drain layer 1005 (in this example, along substantially parallel to the substrate surface)
  • the lateral direction is concave).
  • the recessed upper and lower sidewalls are respectively defined by an interface between the channel layer 1003 and the second source/drain layer 1005 and the channel layer and the first source/drain layer 1031.
  • this can be further selectively etched (eg, isotropic etching, eg, wet etching using a TMAH solution) with respect to the first source/drain layer 1031 and the second source/drain layer 1005.
  • Layer 1003 is implemented.
  • atomic layer etching ALE or digital etching can be used for selective etching.
  • the surfaces of the first source/drain layer 1031, the channel layer 1003, and the second source/drain layer 1005 are oxidized by, for example, heat treatment, and then their respective surface oxide layers are removed.
  • the oxidation rate of SiGe is higher than that of Si, and the oxide on SiGe is more easily removed.
  • the step of oxidative-oxidation removal can be repeated to achieve the desired recess. This approach allows for better control of the degree of recession than conventional selective etching.
  • the shape of the active region is not limited thereto, but other shapes may be formed according to the design layout.
  • the active area may be elliptical, square, rectangular, or the like.
  • a gate stack will be subsequently formed.
  • a recess may be filled in the recess to occupy the space of the gate stack (thus, This layer of material can be referred to as a "sacrificial gate"). For example, this can be performed by depositing a nitride on the structure shown in FIG. 3 and then etching back the deposited nitride such as RIE.
  • the RIE can be performed in a direction substantially perpendicular to the surface of the substrate, and the nitride can remain only in the recess to form the sacrificial gate 1007, as shown in FIG.
  • the sacrificial gate 1007 can substantially fill the recesses described above.
  • shallow trench isolation can be fabricated.
  • the STI 1051 can be formed by etching a trench where isolation is required and then filling the trench with an oxide, as shown in FIG.
  • a variety of STI processes are known to those skilled in the art and will not be described herein.
  • the STI 1051 can be disposed around the active region of the p-type device and around the active region of the n-type device, respectively.
  • source/drain regions may be formed in the first source/drain layer 1031 and the second source/drain layer 1005. This can be formed by doping the first source/drain layer 1031 and the second source/drain layer 1005. For example, this can be done as follows.
  • a p-type dopant source layer 1009p may be formed on the structure shown in FIG.
  • the p-type dopant source layer 1009p may include an oxide such as silicon oxide containing a p-type dopant such as B.
  • the dopant source layer 1009 may be a thin film, for example, having a thickness of about 2-10 nm, so as to be substantially conformally deposited by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). 5 on the surface of the structure shown.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • a diffusion barrier layer 1053 may be formed on the p-type dopant source layer 1009p.
  • the diffusion barrier layer 1053 may include a nitride, an oxynitride, an oxide, or the like, having a thickness of about 0.5 to 5 nm.
  • the p-type dopant source layer 1009p (and the diffusion barrier layer 1053) can be patterned (eg, by photolithography) to be left in the region where p-doping is required.
  • the p-type dopant source layer 1009p can remain in the p-type device region (because its source/drain layers require p-type doping) and the regions in the n-type device region where body contact will be formed (if any) Because a p-type body contact region can be formed for an n-type device).
  • an n-type dopant source layer 1009n can be formed on the structure shown in FIG.
  • the n-type dopant source layer 1009n may include an oxide containing an n-type dopant such as As or P having a thickness of about 2-10 nm.
  • the n-type dopant source layer 1009n can be formed in the same manner as the p-type dopant source layer 1009p.
  • the n-type dopant source layer 1009n may cover regions requiring n-type doping, such as an n-type device region (because its source/drain layers require n-type doping) and regions in the p-type device region where body contact will be formed (if If so, an n-type body contact region can be formed for the p-type device.
  • another diffusion barrier layer may be formed on the n-type dopant source layer 1009n to inhibit outdiffusion or cross-contamination.
  • the dopant contained in the dopant source layers 1009p and 1009n may be introduced into the active region by annealing at about 800-1100 ° C, for example, thereby forming a doped region therein.
  • the shaded part of the figure More specifically, in the p-type device region, one of the source/drain regions 1011p-1 of the p-type device may be formed in the first source/drain layer 1031p, and a p-type device is formed in the second source/drain layer 1005p. Another source/drain region 1011p-2.
  • one of the source/drain regions 1011n-1 of the n-type device may be formed in the first source/drain layer 1031n, and an n-type device is formed in the second source/drain layer 1005n. Another source/drain region 1011n-2. Thereafter, the dopant source layers 1009p and 1009n and the diffusion barrier layer 1053 can be removed.
  • the dopant may enter the channel layer 1003 via the first source/drain layer 1031 and the second source/drain layer 1005, thereby being at the upper and lower ends of the channel layer 1003.
  • a certain doping profile is formed (eg, forming an extension) as shown by the elliptical dashed line in the figure. This doping profile can reduce the resistance between the source and drain regions when the device is turned on, thereby improving device performance.
  • the source/drain regions are formed by driving the dopant from the dopant source layer into the active region, but the disclosure is not limited thereto.
  • the source/drain regions can be formed by ion implantation, plasma doping (eg, conformal doping along the surface of the structure in FIG. 5), and the like.
  • plasma doping eg, conformal doping along the surface of the structure in FIG. 5
  • another area can be blocked by, for example, photoresist. This sub-regional processing is common in CMOS processes.
  • in-situ doping can also be performed while growing the source/drain layers.
  • the p-type dopant source layer 1009p is formed first, and then the n-type dopant source layer 1009n is formed.
  • the present disclosure is not limited thereto, and their order may be exchanged.
  • the source/drain layer can also be thinned and partially replaced with a low-k dielectric.
  • the source/drain layer may be selectively etched to make it thinner (even finer than the channel) in the structure shown in FIG. 9 (removing the dopant source layer and the diffusion barrier layer). Floor).
  • the low-k dielectric spacer 1007' may be formed by a spacer forming process using a low-k dielectric.
  • the source/drain layers may be silicided.
  • a layer may be deposited on the structure shown in FIG. 9 (removing the dopant source layer and the diffusion barrier layer or after the above-described source/drain refinement treatment and before forming the low-k dielectric spacer 1007')
  • NiPt for example, a Pt content of about 2 to 10% and a thickness of about 2 to 10 nm
  • annealed at a temperature of about 200 to 400 ° C to cause NiPt to react with Si to form SiNiPt. Thereafter, unreacted remaining NiPt can be removed.
  • a gate stack can be formed.
  • a dielectric layer may be formed around the active region to block the underlying source/drain layer 1031.
  • an oxide may be deposited on the structure shown in FIG. 9 (or, in the case of performing source/drain layer refinement processing, on the structure shown in FIG. 28), and The etch back is performed to form the dielectric layer 1013.
  • the deposited oxide may be subjected to a planarization treatment such as chemical mechanical polishing (CMP) or sputtering before etch back.
  • CMP chemical mechanical polishing
  • the top surface of dielectric layer 1013 can be located between the top and bottom surfaces of channel layer 1003, which helps to form a self-aligned gate stack, as will be described in further detail below.
  • the sacrificial gate 1007 may be left to prevent the material of the dielectric layer from entering the recesses that are to accommodate the gate stack. Thereafter, the sacrificial gate 1007 can be removed to release the space in the recess.
  • the sacrificial gate 1007 nitride
  • the dielectric layer 1013 oxide
  • the second source/drain layer 1005 SiGe
  • the channel layer 1003 Si.
  • a gate dielectric layer 1015 and a gate conductor layer 1017p for a p-type device may be sequentially deposited on the structure shown in FIG. 10 (removing the sacrificial gate 1007), and the deposited gate conductor layer 1017p (and optionally The ground dielectric layer 1015) is etched back such that the top surface of the portion other than the recess is not higher than and preferably lower than the top surface of the channel layer 1003.
  • the gate dielectric layer 1015 may include a high K gate dielectric such as HfO 2 ; the gate conductor layer 1017p may include a metal gate conductor.
  • a function adjustment layer can also be formed between the gate dielectric layer 1015 and the gate conductor layer 1017p.
  • An interface layer such as an oxide may also be formed before the gate dielectric layer 1015 is formed.
  • the gate stack overlaps only the side in the vertical direction of the channel layer 1003, and does not overlap the sides of the first and second source/drain layers in the vertical direction. That is, the gate stack is self-aligned to the channel layer 1003. In this way, the gate stack can be embedded in the recess to overlap the entire height of the channel layer 1003.
  • the gate conductor layer 1017p may be selectively etched such as RIE.
  • the etching may use a second source/drain layer of the active region, particularly the top end, as a mask.
  • the RIE can be performed in a direction substantially perpendicular to the surface of the substrate, so that the gate conductor layer 1019p can remain only in the recess.
  • the etch may stop at the gate dielectric layer 1015.
  • the gate conductor layer 1017p (currently in the recess) in the p-type device region may be shielded with, for example, a photoresist 1055, and the gate conductor layer 1017p in the n-type device region is exposed.
  • the gate conductor layer 1017p in the n-type device region can be removed by selective etching such as wet etching.
  • a gate stack (1015/1017p) for the p-type device is formed, which is embedded in the recess of the channel layer 1003p of the p-type device.
  • a gate stack for the n-type device can be formed.
  • the gate stack of the n-type device can also be formed similarly.
  • a gate conductor layer 1017n for an n-type device can be formed.
  • the gate conductor layer 1017n may be deposited on the structure shown in FIG. 13 (removing photoresist 1055), and the deposited gate conductor layer 1017n may be etched back to the top of the portion other than the recess.
  • the face is not higher than and preferably lower than the top surface of the channel layer 1003.
  • the gate conductor layer 1017n may include a metal gate conductor.
  • a function adjustment layer can also be formed between the gate dielectric layer 1015 and the gate conductor layer 1017n.
  • the n-type device and the p-type device may share the same gate dielectric layer 1015; of course, the present disclosure is not limited thereto, for example, the gate dielectric layer 1015 may also be removed, and a gate dielectric layer may be additionally formed for the n-type device.
  • the gate conductor layer 1017n is formed not only in the n-type device region but also in the p-type device region and in contact with the gate conductor layer 1017p. After that, it can be fabricated by using the gate conductor layer 1017n. The gate contacts the pad to subsequently make a contact to the gate.
  • the manner of forming the gate stack is not limited thereto.
  • the p-type device region may be masked with a photoresist, and a portion of the gate conductor layer 1017p at the n-type device region may be removed by selective etching such as RIE.
  • a gate stack for the n-type device can then be formed in the n-type device region (eg, with the photoresist masked p-type device region remaining).
  • the gate conductor layer 1017n can be patterned to form a gate contact pad for subsequent interconnect fabrication.
  • FIG. 15(a) is a cross-sectional view
  • Fig. 15(b) is a plan view, in which the line AA' shows the intercepted position of the cross section
  • a photoresist 1019 is formed on the structure shown in FIG.
  • the photoresist 1019 is patterned, for example, by photolithography to cover a portion of the gate conductor layer 1017n exposed outside the recess, and expose the gate conductor layer 1017n to other portions than the recess.
  • FIG. 15(a) is a cross-sectional view
  • Fig. 15(b) is a plan view, in which the line AA' shows the intercepted position of the cross section
  • the gate conductor layer 1017n may be selectively etched such as RIE by using the photoresist 1019 as a mask.
  • the portion of the gate conductor layer 1017n that is hidden by the photoresist 1019 is retained except for the portion remaining in the recess, and functions as a gate contact pad. Electrical connections to the gate stack can then be achieved by such gate contact pads.
  • the semiconductor device may include a p-type device and an n-type device both in the form of vertical devices.
  • the p-type device and the n-type device each include a first source/drain layer 1031, a channel layer 1003, and a second source/drain layer 1005 stacked in the vertical direction. Source/drain regions are formed in the first source/drain layer 1031 and the second source/drain layer 1005.
  • the channel layer 1003 is laterally recessed, and a gate stack is formed around the outer circumference of the channel layer 1003 and embedded in the recess.
  • Each device also includes a gate contact pad that extends outwardly from the gate conductor.
  • a strain source/drain technique can be applied.
  • a stressed semiconductor material can be bonded in the second source/drain layer 1005 at the upper end.
  • the gate dielectric layer 1015 and the isolation layer 1013 may be further selectively etched such as RIE.
  • the RIE can be performed in a direction substantially perpendicular to the surface of the substrate.
  • the photoresist 1019 can be removed.
  • a liner layer can be formed on the structure shown in FIG.
  • the liner may be stressed for the purpose of further improving the performance, and different stress liners may be formed for the p-type device and the n-type device.
  • a liner 1101 (which may be stressed) for a p-type device may be formed on the structure shown in FIG.
  • the liner 1101 can be formed by depositing a layer of nitride substantially conformally.
  • the liner 1101 may have a thickness of about 10 to 50 nm and may be tensilely stressed to generate compressive stress in the channel layer.
  • an etch stop layer 1103, such as an oxide, may be formed on the liner 1101, for example.
  • a photoresist 1057 covering the p-type device region may be formed, and the etch stop layer 1103 and the liner layer 1101 are selectively etched, such as RIE, with the photoresist 1057 as a mask to be left in the p-type device. In the area. Thereafter, the photoresist 1057 can be removed.
  • the liner 1105 can be formed on the n-type device region in a similar manner.
  • a liner 1105 (which may be stressed) for an n-type device may be formed on the structure shown in FIG.
  • the liner 1105 can be formed by depositing a layer of nitride substantially conformally.
  • the liner 1105 may have a thickness of about 10 to 50 nm and may be subjected to compressive stress to generate tensile stress in the channel layer.
  • corresponding (stressed) liners are formed in the p-type device region and the n-type device region, respectively, and their formation order can be exchanged.
  • the liner can cover the upper surface of the source/drain layer, thus protecting the active region and acting as an etch stop layer during subsequent contact hole etching.
  • a liner may be uniformly formed for the p-type device region and the n-type device region, and the liner may be unstressed or stressed.
  • the liners 1101 and 1105 can cover the upper surfaces of the first source/drain layer 1031 and the second source/drain layer 1005, thus protecting the active region and subsequently acting as an etch stop layer.
  • an interlayer dielectric layer 1021 can be formed on the structure shown in FIG.
  • an oxide can be deposited and planarized, such as CMP, to form interlayer dielectric layer 1021.
  • the CMP can stop at the liner 1101.
  • an oxide etch stop layer 1103 and an interlayer dielectric layer 1021 are integrally shown.
  • strain source/drain processing can be performed.
  • strain source/drain processing can be performed separately for the p-type device and the n-type device. It should be understood that only one of the devices may be processed, or the order of processing may vary.
  • the liner 1101 of the p-type device region can be patterned to at least partially expose the top surface of the second source/drain layer 1005p.
  • the liner 1101 can be selectively etched such as RIE.
  • the RIE can be performed, for example, in a direction substantially perpendicular to the surface of the substrate.
  • the portion of the lining layer 1101 on the top surface of the second source/drain layer 1005p can be removed, and the top end of the vertical portion can also be removed.
  • an opening is left in the interlayer dielectric layer 1021 (and the liner layer 1101) through which the second source/drain layer 1005p is exposed.
  • a spacer 1203 may be formed on the sidewall of the opening formed as described above in the interlayer dielectric layer 1021.
  • the spacer 1203 may include a nitride whose width (dimension in the horizontal direction in the drawing) may be large to cover the sidewall portion of the semiconductor layer 1005 (but not completely cover the top surface of the second source/drain layer 1005p).
  • a layer of nitride can be deposited in a substantially conformal manner on the structure shown in FIG.
  • RIE reactive ion etching
  • silicide 1005s is formed on the surfaces of the first source/drain layer 1031p and the second source/drain layer 1005p as described above (only For the sake of convenience, the silicide formed on the surface of the first source/drain layer 1031p is not shown, and after the opening in the interlayer dielectric layer 1021 (and the liner layer 1101) as described above, it is also possible to selectively etch as RIE.
  • the second source/drain layer 1005p is recessed to a certain extent.
  • the sidewall forming process can be performed as described above.
  • the sidewalls can be formed on the sidewalls of the openings in the interlayer dielectric layer 1021, but also the sidewalls 1203' can be formed on the sidewalls of the silicide 1005s.
  • the formed sidewall spacers 1203 may be used as a mask to selectively etch the second source. / drain layer 1005p.
  • RIE can be used, or atomic layer etching (ALE) can be used for precise control of etching depth and reduction of loading effects.
  • ALE atomic layer etching
  • the etching does not proceed to the bottom surface of the second source/drain layer 1005p, but leaves a portion of the second source/drain layer 1005p at the bottom.
  • the sidewall portion of the second source/drain layer 1005p is also retained due to the presence of the sidewall spacer 1203.
  • the second source/drain layer 1005p has a "U" shape.
  • the stressed semiconductor material 1205 may be epitaxially grown by using the remaining portion of the second source/drain layer 1005p as a seed. Since the second source/drain layer 1005p is in a "U" shape, epitaxial growth can be performed on the bottom and sidewall portions of the second source/drain layer 1005p, facilitating formation of a high quality epitaxial layer.
  • the lining layer 1101 (bonding the interlayer dielectric layer 1021) functions as a stress retention or reinforcement and may be referred to as a stress enhancement layer.
  • the stress enhancement layer limits the free movement of the residual portion or seed of the second source/drain layer 1005p, thereby increasing the stress applied to the channel.
  • the stress enhancement layer can have a stress that is opposite to the stress carried by the grown stressed semiconductor material.
  • the semiconductor material 1205 can generate compressive stress in the channel layer for the p-type device.
  • the semiconductor material 1205 may include SiGe (the atomic percentage of Ge is greater than the percentage of Ge atoms in the second source/drain layer) .
  • the semiconductor material 1205 is not limited thereto, and may include other semiconductor materials such as GeSn or III-V compound semiconductor materials having a different lattice constant from the second source/drain layer 1005p.
  • the semiconductor material 1205 when the semiconductor material 1205 is epitaxially grown, it may be doped in situ, for example, p-type doping for a p-type device (doping concentration is, for example, about 1E18-2E20 cm -3 ).
  • the liner 1101 is opened.
  • the liner 1101 may be complemented for the purpose of providing active area protection and an etch stop layer.
  • a lining complement all of 1101' can be formed in the opening.
  • a nitride may be deposited on the structure shown in FIG. 23, and a nitride may be planarized, such as CMP, and CMP may be stopped at the interlayer dielectric layer 1021.
  • CMP chemical nitride
  • the nitride is filled in the opening to form a liner complement all 1101'.
  • the semiconductor material 1207 can generate tensile stress in the channel layer for the n-type device.
  • the semiconductor material 1207 may include SiGe (the atomic percentage of Ge is smaller than the percentage of Ge atoms in the second source/drain layer) .
  • the semiconductor material 1207 is not limited thereto, and may include other semiconductor materials having a different lattice constant than the second source/drain layer 1005n, such as Si:C, GeSn or III-V compound semiconductor materials.
  • the semiconductor material 1207 when the semiconductor material 1207 is epitaxially grown, it may be doped in situ, for example, n-type doping for an n-type device (doping concentration is, for example, about 1E18-1E21 cm -3 ).
  • the sidewalls 1203 or 1203' are utilized as a mask when etching the second source/drain layer 1005.
  • the side walls 1203 or 1203' may not be formed.
  • the exposed semiconductor layer 1005 can be selectively etched directly.
  • the etching may not proceed to the bottom surface of the semiconductor layer 1005, but leave a portion of the semiconductor layer 1005 at the bottom.
  • the remaining portion of the semiconductor layer 1005 does not have a vertically extending portion, but is substantially planar.
  • the semiconductor layer 1005 can also be completely etched away.
  • the etching of the semiconductor layer 1005 can be stopped at the channel layer 1003.
  • the channel layer 1003 may be a seed layer to grow a stress-bearing semiconductor layer.
  • the interlayer dielectric layer 1021 can be thickened.
  • an oxide may be further deposited on the interlayer dielectric layer 1021, and a planarization treatment such as CMP may be performed on the deposited oxide to thicken the interlayer dielectric layer.
  • CMP planarization treatment
  • the contact portion 1023p-1 to the source/drain region 1011p-1, the contact portion 1023p-2 to the source/drain region 1011p-2, and the gate conductor layer can be formed.
  • the contact portion 1023p-3 of 1017 may be formed to the contact portion 1023n-w of the well region 1001w.
  • the contact portion 1023n-1 to the source/drain region 1011n-1, the contact portion 1023n-2 to the source/drain region 1011n-2, and the contact portion 1023n to the gate conductor layer 1017 may be formed.
  • -3 and can be formed to the contact portion 1023p-w of the p-type substrate 1001.
  • These contacts may be etched in the interlayer dielectric layer 1021 and the liner, and filled with a conductive material therein.
  • the material is formed such as a metal (for example, tungsten).
  • a barrier layer such as TiN may be formed on the inner wall of the contact hole before the metal is filled.
  • the etching of the interlayer dielectric layer 1021 can be stopped at the liner, and then the liner of substantially uniform thickness can be etched. Since the contacts to the source/drain regions and the contacts to the gate conductor layers have different heights, etching of the contact holes is difficult. In this embodiment, however, the stop of the contact hole etching can be controlled relatively easily due to the presence of the liner.
  • the contacts to the gate can be easily formed.
  • the doped region in the first source/drain layer extends beyond the active region and there is no gate contact pad at least over a portion thereof, its contact portion can be easily formed.
  • connection mode there is no junction leakage between the first source/drain layer and the well region (or p-type substrate) in the p-type device region and the n device region. However, there may be junction leakage between the wells (between the n-type well region and the p-type substrate).
  • the connections of the first source/drain layer and the second source/drain layer shown in FIG. 20 may be interchanged.
  • this connection mode although there may be junction leakage between the first source/drain layer and the well region (or p-type substrate), in some cases, area can be saved because the n-type device and the p-type device Contacts can be shared. This will be further described below.
  • 29 to 32 are schematic views showing a part of stages in a process of fabricating a semiconductor device in accordance with another embodiment of the present disclosure.
  • a conductive bridge 1107 may be formed between the p-type device and the n-type device region.
  • a layer of a conductive material such as a metal may be deposited on the structure shown in Figure 9 (with the dopant source layer removed and the diffusion barrier layer removed).
  • a photoresist 1061 is then formed which is patterned to cover a portion of the conductive material extending between the p-type device and the n-type device region. After that, the photoresist 1061 can be The conductive material is selectively etched, such as RIE, to form a conductive bridge 1107.
  • the conductive bridge 1107 electrically connects the first source/drain layer 1031p of the p-type device and the first source/drain layer 1031n of the n-type device across the STI.
  • a layer of Si may be formed in a manner to form the conductive bridge 1107. Then, in the case where silicidation is performed, the Si layer can be converted into a conductive silicide and constitute a conductive bridge 1107.
  • a p-type device can be formed. And a respective gate stack of the n-type device, and then a photoresist 1019' is formed to pattern the gate conductor layer to form a gate contact pad.
  • the photoresist 1019' extends continuously between the p-type device region and the n-type device region.
  • 31(b) is a plan view, in which the line AA' shows the intercepted position of the cross section), the gate conductor layer The 1017n extends from the n-type device to the p-type device.
  • the conductive bridge 1017 is schematically illustrated by a broken line frame.
  • Fig. 32 shows the device structure after the formation of the contact portion.
  • the p-type device and the n-type device may share the gate contact portion 1023-3 and the source/drain contact portion 1023-1.
  • Other connections may be the same as in the previous embodiment. It can be seen that the number of contacts is reduced from 8 to 6, so that the contact area can be reduced.
  • FIG. 33 illustrates a cross-sectional view of a semiconductor device in accordance with another embodiment of the present disclosure.
  • the p-type device and the n-type device can share the gate contact 1023-3 and can receive an input signal. However, in this example, a conductive bridge is not formed.
  • the source/drain contacts 1023p-2, 1023n-2 of the p-type device and the n-type device may be interconnected together in the second metal layer M2 and constitute an output. In the connection mode shown in Fig. 33, as described above, there may be no junction leakage between the source/drain layer and the well region, so that power consumption can be reduced.
  • the channel layer 1003 may be subjected to a thinning process.
  • the first source/drain layer 1031 and the channel layer 1003 may grow substantially uniformly (thus having a substantially uniform thickness due to Their respective upper and lower surfaces may extend substantially parallel to the surface of the substrate).
  • the thickness of the channel layer 1003 can be reduced by selective etching, at which point the second device region can be masked (eg, by photoresist).
  • etching may use atomic layer etching (ALE).
  • the second source/drain layer 1005 may be further grown on the channel layer 1003.
  • the difference in thickness between the device regions can be gradually reduced or even eventually disappeared (indicating that the top surface of the second source/drain layer 1005 is substantially flat and substantially parallel to the lining The bottom surface; however, if the second source/drain layer 1005 is thin, there may still be thickness fluctuations, which does not affect the progress of the subsequent process).
  • the first source/drain layer 1031 may be subjected to a thinning process.
  • the first source/drain layer 1031 can be grown substantially uniformly (so having a substantially uniform thickness such that its upper and lower surfaces can extend substantially parallel to the substrate surface).
  • the thickness of the first source/drain layer 1031 can be reduced by selective etching, at which point the second device region can be masked (eg, by photoresist).
  • the channel layer 1003 may be further grown on the first source/drain layer 1031.
  • the difference in thickness between the device regions can be gradually reduced or even eventually disappeared (indicating that the top surface of the channel layer 1003 is substantially flat and substantially parallel to the lining The bottom surface; however, if the channel layer 1003 is thin, there may still be thickness fluctuations, which does not affect the progress of the subsequent process).
  • the second source/drain layer 1005 may be further grown on the channel layer 1003.
  • a semiconductor device can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (eg, other forms of transistors, etc.), an integrated circuit (IC) can be formed, and thereby an electronic device can be constructed. Accordingly, the present disclosure also provides an electronic device including the above semiconductor device.
  • the electronic device can also include a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit.
  • Such electronic devices are, for example, smart phones, computers, tablets (PCs), artificial intelligence, wearable devices, mobile power supplies, and the like.
  • a method of fabricating a chip system is also provided.
  • the method can include the above method of fabricating a semiconductor device.
  • a plurality of devices can be integrated on the chip. At least some of them are made in accordance with the methods of the present disclosure.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un dispositif semi-conducteur, son procédé de fabrication, et un appareil électronique le comprenant. Le dispositif semi-conducteur comprend : un substrat (1001); un premier dispositif et un second dispositif formés sur le substrat (1001), le premier dispositif et le second dispositif comprenant respectivement une première couche de source/drain (1031), une couche de tranchée (1003), et une seconde couche de source/drain (1005) empilées séquentiellement sur le substrat (1001); et un empilement de grille formé autour d'une périphérie de la couche de tranchée (1003), la couche de tranchée (1003p) du premier dispositif et la couche de tranchée (1003n) du second dispositif sont sensiblement coplanaires, et la seconde couche de source/drain (1005) du premier dispositif a une contrainte différente de celle de la seconde couche de source/drain du second dispositif.
PCT/CN2017/095130 2016-09-30 2017-07-31 Dispositif semi-conducteur, procédé de fabrication de celui-ci et appareil électronique le comprenant WO2018059108A1 (fr)

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CN201610872541.2A CN106298778A (zh) 2016-09-30 2016-09-30 半导体器件及其制造方法及包括该器件的电子设备
CN201710530297.6 2017-06-30
CN201710530297.6A CN107887387B (zh) 2016-09-30 2017-06-30 半导体器件及其制造方法及包括该器件的电子设备

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