WO2018056100A1 - High-speed serial signal equalizer and high-speed serial interface - Google Patents
High-speed serial signal equalizer and high-speed serial interface Download PDFInfo
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- WO2018056100A1 WO2018056100A1 PCT/JP2017/032736 JP2017032736W WO2018056100A1 WO 2018056100 A1 WO2018056100 A1 WO 2018056100A1 JP 2017032736 W JP2017032736 W JP 2017032736W WO 2018056100 A1 WO2018056100 A1 WO 2018056100A1
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- speed serial
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- digital control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
Definitions
- the present invention relates to a high-speed serial signal equalizer that performs signal improvement on the receiving side in high-speed serial transmission.
- an equalizer for signal improvement is provided on the receiving side.
- a line that transmits a high-speed differential signal has a low-pass filter characteristic, and greatly attenuates a high-frequency component of a signal propagating therethrough.
- the amount of attenuation increases as the transmission distance increases and the frequency increases. Therefore, when high-speed differential signals are transmitted over long distances, inter-symbol interference (ISI: Inter-Symbol Interference) increases, and the code error rate increases. Therefore, an equalizer (receiver equalizer) for improving the frequency characteristics of the received signal is provided on the reception (receiver / deserializer) side of the transmission signal.
- ISI Inter-Symbol Interference
- the basic structure of the receiver equalizer is a bandpass filter.
- the high-frequency region attenuated by the transmission line is enhanced, and the increase of noise components due to the high-pass filter is suppressed in the low-pass property region.
- CTLE Continuous Opera Time Linear Equalizer
- Discrete Time Linear Equalizer Discrete Time Linear Equalizer
- FIG. 12 is a diagram showing the relationship between various protocols of the high-speed serial interface and the data transfer rate in one lane.
- many protocols already exist, and the data transfer rate is also wide, for example, from several Gbps to several tens of Gbps.
- an equalizer having the same circuit configuration that is, one equalizer can be adapted to many high-speed serial interfaces having different protocols.
- variable capacitance element when used to make the frequency response of the equalizer variable, it is difficult to provide it integrally with a semiconductor element including a switch or the like.
- the high-speed serial signal equalizer of the present invention is Provided in the high-speed serial signal receiver, equipped with a filter to improve the frequency characteristics of the received signal,
- the filter includes a variable filter circuit capable of switching frequency characteristics, and a control signal input unit that inputs a control signal for switching the frequency characteristics,
- the variable filter circuit includes a plurality of passive elements, and a switch element that switches a connection state of the plurality of passive elements,
- the plurality of passive elements are provided in a passive circuit chip on which a passive circuit is formed, and the switch element is provided in a digital control circuit chip.
- variable filter circuit is provided in a passive circuit chip different from the semiconductor chip for configuring the digital control circuit, for example, a high-capacity variable capacitance element can be configured, and the frequency response variation width of the equalizer is increased. It can be secured.
- the passive circuit chip and the digital control circuit chip are stacked on the circuit board. As a result, the current path length between the plurality of passive elements and the switch elements is shortened, and desired filter characteristics can be obtained. Further, the area occupied by the passive circuit chip and the digital control circuit chip with respect to the circuit board is reduced.
- the passive element is, for example, a capacitive element. With this configuration, the frequency characteristics of the variable filter can be effectively switched by switching the plurality of capacitive elements.
- the capacitive element is a thin film capacitor including a ferroelectric thin film and a pair of electrode films facing each other with the ferroelectric thin film interposed therebetween.
- a high-capacity variable capacitance element can be configured, and a large frequency response variation width of the equalizer can be secured.
- the digital control circuit chip provides a demultiplexer that determines the state of the switch element by an output signal, and provides a plurality of bits of data to the input of the demultiplexer, inputs control data from a control data input unit, and performs the control And a register for setting data.
- the variable filter circuit is connected to an amplifier circuit, a high-pass filter circuit including a variable capacitance element and a resistance element, connected to the input section of the amplifier circuit, and connected to an output section of the amplifier circuit, and includes a resistance element and a capacitor And a low-pass filter circuit including the element.
- a digital feedback equalizer connected to a subsequent stage of the variable filter circuit may be further provided. With this configuration, the equalizing intensity according to the data pattern can be changed and effective compensation can be performed.
- a high-speed serial interface of the present invention includes the high-speed serial signal equalizer described in any one of (1) to (7) above and a differential line to which the high-speed serial signal equalizer is connected.
- the frequency response of the equalizer that improves the frequency characteristics of the received signal can be made variable and integrated with a switch or the like so that the frequency response can be changed adaptively according to the required protocol.
- a high-speed serial signal equalizer can be obtained.
- FIG. 1 is a diagram illustrating a configuration of a high-speed serial signal equalizer 10 and a high-speed serial interface according to the first embodiment.
- FIG. 2 is a diagram illustrating an example of a change in the frequency response of CTLE 11.
- FIG. 3A shows an example of an eye pattern of a received signal before applying CTLE 11
- FIG. 3B shows an example of an eye pattern of a received signal after applying CTLE 11.
- FIG. 4 is a circuit diagram of a passive circuit chip and a digital control circuit chip.
- FIG. 5 is a waveform diagram showing an example of the state transition of each terminal of the digital control circuit chip 120 and the value set in the shift register.
- FIG. 6A is a perspective view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120.
- the passive circuit chip 110 is connected to the digital control circuit chip 120 via a plurality of solder balls SB. It is a perspective view in the state before doing.
- FIG. 6B is a front view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120.
- FIG. 7A is a plan view showing the arrangement of the plurality of terminals T11 of the passive circuit chip 110
- FIG. 7B is a plan view showing the arrangement of the plurality of terminals T12 of the digital control circuit chip 120.
- FIG. 8A is a perspective view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120 used in the high-speed serial signal equalizer according to the second embodiment.
- FIG. 8B is a front view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120.
- FIG. 9A is a plan view showing the arrangement of the plurality of terminals T11 of the passive circuit chip 110 according to the second embodiment, and FIG. 9B shows the arrangement of the plurality of terminals T12 of the digital control circuit chip 120.
- FIG. FIG. 10 is a circuit diagram of CTLE 11 of the high-speed serial signal equalizer according to the third embodiment.
- FIG. 11 shows a connection relationship between the passive circuit chip 110 constituting the variable capacitance element VC1 and the variable resistance element VR11 according to the third embodiment and the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 connected thereto.
- FIG. FIG. 12 is a diagram showing the relationship between various protocols of the high-speed serial interface and the data transfer rate in one lane.
- FIG. 1 is a circuit diagram of a high-speed serial signal equalizer 10 and a high-speed serial interface including the same according to the first embodiment.
- the high-speed serial signal equalizer 10 includes a CTLE (Continuous-Time Linear Equalizer) 11 and a DTLE (Discrete Time Linear Equalizer) 12 for receiving a high-speed serial (data) signal.
- CTLE Continuous-Time Linear Equalizer
- DTLE Discrete Time Linear Equalizer
- the high-speed serial signal equalizer 10 improves the frequency spectrum so as to reduce the code error rate of the received signal input from the input terminals RXin + and RXin ⁇ , and outputs it from the output terminal RXo.
- FIG. 1 is a circuit diagram of a high-speed serial signal equalizer 10 and a high-speed serial interface including the same according to the first embodiment.
- the high-speed serial signal equalizer 10 includes a CTLE (Continuous-Time Linear Equalizer) 11 and a DTLE (Discrete Time Linear Equalizer) 12 for
- a termination resistor Rin is connected between the input terminals RXin + and RXin ⁇ .
- the high-speed serial signal equalizer 10 is connected to the differential line.
- a high-speed serial interface is configured including this high-speed serial signal equalizer 10 and a differential line to which it is connected.
- the CTLE 11 includes an amplifier circuit A1, resistance elements R11, R12, R21, R22, and R30, variable capacitance elements VC1 and VC2, and a capacitance element Co.
- the variable capacitance elements VC1 and VC2 and the resistance elements R11, R12, R21, and R22 constitute a high pass filter. Further, a low-pass filter is configured by the resistor element R30 and the capacitive element Co.
- the amplifier circuit A1 differentially amplifies the differential signal input to the input terminals RXin + and RXin ⁇ , and outputs an unbalanced signal.
- the cut-off frequency of the high-pass filter is determined by the resistance values of the resistance elements R11, R12, R21, and R22 and the capacitances of the variable capacitance elements VC1 and VC2.
- the cut-off frequency of the low-pass filter is determined by the resistance value of the resistance element R30 and the capacitance of the capacitive element Co.
- the DTLE 12 includes an adder 1, a sampler 2, a CDR (Clock Data Recovery) 3, and a DFE (Decision Feedback Feedback Equalizer) 4.
- the DFE 4 feeds back by adding a plurality of delay circuits and outputs of the plurality of taps by the adder 1, and changes the equalizer strength in accordance with the data pattern.
- CDR shapes the waveform disturbance in the time axis direction and reduces the influence of jitter.
- FIG. 2 is a diagram showing an example of changes in the frequency response of the CTLE 11 described above.
- the characteristic FR1 having a center frequency (peak frequency) of the passband of 2.5 GHz is a characteristic applied to, for example, a PCIe gen2 signal having a data transfer rate of 5 Gbps.
- a characteristic FR2 having a passband center frequency (peak frequency) of 4 GHz is a characteristic applied to, for example, a PCIe gen3 signal having a data transfer rate of 8 Gbps.
- the characteristic FR3 having a passband center frequency (peak frequency) of 8 GHz is a characteristic applied to, for example, a PCIe gen4 signal having a data transfer rate of 16 Gbps.
- FIG. 3A shows an example of an eye pattern (eye diagram) of a received signal before applying the CTLE 11
- FIG. 3B shows an eye pattern (eye pattern) of the received signal after applying the CTLE 11. It is an example of an eye diagram.
- FIG. 4 is a circuit diagram of a passive circuit chip and a digital control circuit chip.
- the passive circuit chip 110 is formed with a plurality of capacitive elements C1 to C7.
- Other circuits are formed in the digital control circuit chip 120.
- the digital control circuit chip 120 includes switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR, AND gates AG1, AG2, AG3, D-type flip-flops D1, D2, D3, D4, and a demultiplexer DMPX. Is provided.
- switches SW1, SW2, SW3, SW4, SW5, SW6, and SW7 are connected to the capacitive elements C1, C2, C3, C4, C5, C6, and C7, respectively.
- a common connection portion of the capacitive elements C1, C2, C3, C4, C5, C6, and C7 is connected to the terminal C ⁇ .
- a switch SWS is inserted between the common connection of the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 and the terminal C +.
- the circuit between the terminals C + and C ⁇ of the digital control circuit chip 120 corresponds to the variable capacitance element VC1 or the variable capacitance element VC2 shown in FIG.
- the passive circuit chip 110 corresponds to a single variable capacitance element
- two sets of the passive circuit chip and the digital control circuit chip shown in FIG. 4 are used to configure the variable capacitance elements VC1 and VC2.
- it can also be composed of one passive circuit chip and one digital control circuit chip.
- the D-type flip-flops D1, D2, D3, and D4 are connected in four stages to form a 4-bit shift register.
- the input signal of the terminal DATA is given to the first stage of this shift register.
- the outputs of the D-type flip-flops D1, D2, and D3 are input to the Q1, Q2, and Q3 inputs of the demultiplexer DMPX.
- Output signals S1, S2, S3, S4, S5, S6 and S7 of the demultiplexer DMPX are given as control signals for the switches SW1, SW2, SW3, SW4, SW5, SW6 and SW7.
- the input signal of the terminal SET of the digital control circuit chip 120 and the output signal Q4 of the D flip-flop D4 (end stage of the shift register) are input to the AND gate AG1, and the output of the AND gate AG1 is “H”. At some point, switch SWS is conducting.
- Input signals of the clock terminal CLK and the chip select terminal CS of the digital control circuit chip 120 are input to the AND gate AG2, and the output of the AND gate AG2 is supplied to the shift register as a clock signal. That is, when the terminal CS is “H”, the contents of the shift register are shifted in the upper bit direction in synchronization with the clock signal input to the terminal CLK.
- the input signal of the terminal RESET of the digital control circuit chip 120 and the output signal S8 of the demultiplexer DMPX are input to the AND gate AG3.
- the output of the AND gate AG3 is “H”
- the shift register is reset.
- the switch SWR is turned on, and the charges charged in the capacitive elements C1, C2, C3, C4, C5, C6, and C7 are discharged.
- FIG. 5 is a waveform diagram showing an example of state transition of each terminal of the digital control circuit chip 120 and values set in the shift register.
- This example is an example in which the switch SW6 is turned on in order to select the capacitive element C6.
- the terminal CS is “H”
- the terminal DATA is connected to the terminal DATA in synchronization with the clock signal input to the terminal CLK. 1101 "is sequentially input.
- the most significant bit “1” is a bit for making the switch SWS conductive by the output of the AND gate AG1 shown in FIG.
- Subsequent 3-bit data “101” is input to the demultiplexer DMPX, the output signal S6 of the demultiplexer DMPX becomes “H”, and the switch SW6 becomes conductive. Thereafter, when the terminal SET becomes “H”, the switch SWS becomes conductive. As a result, the capacitive element C6 is connected between the terminals C + and C ⁇ .
- FIG. 6A is a perspective view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120.
- the passive circuit chip 110 is connected to the digital control circuit chip 120 via a plurality of solder balls SB. It is a perspective view in the state before doing.
- FIG. 6B is a front view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120.
- a plurality of LGA (Land grid ⁇ array) type terminals T12 in which a plating film such as Ni or Au is coated on Cu are formed on the lower surface of the digital control circuit chip 120.
- the plurality of terminals T11 on the lower surface of the passive circuit chip 110 are terminals in which, for example, Cu is coated with a plating film such as Ni or Au, solder balls are provided on the surface thereof, and BGA (Ball Grid Array) type The terminal is configured.
- a plurality of pads P12 are formed on the upper surface of the digital control circuit chip 120, and the BGA type terminals on the lower surface of the passive circuit chip 110 are connected to the pads P12.
- FIG. 7A is a plan view showing the arrangement of the plurality of terminals T11 of the passive circuit chip 110
- FIG. 7B is a plan view showing the arrangement of the plurality of terminals T12 of the digital control circuit chip 120.
- the pad P12 formed on the upper surface of the digital control circuit chip 120 is not shown.
- the terminals “1”, “2”, “3”, “4”, “5”, “6”, “7” 4 are terminals respectively connected to the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7.
- the terminal “COM” is a terminal to which the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 are commonly connected.
- the terminal “NC” is a non-connection terminal (empty terminal).
- the digital control circuit chip 120 is a chip formed on a Si wafer by a semiconductor process, for example.
- Each switch shown in FIG. 4 is a bidirectional switch circuit in which a p-channel MOS transfer gate and an n-channel MOS transfer gate are connected in parallel.
- the passive circuit chip 110 includes a capacitive element that uses, for example, a sintered body of barium strontium titanate ((Ba x , Sr 1-x ) TiO 3 , hereinafter referred to as “BST”) as a dielectric thin film.
- BST barium strontium titanate
- a thin film dielectric layer and an electrode layer sandwiching the thin film dielectric layer in the stacking direction are formed on one surface of a ceramic substrate by a thin film process.
- a plurality of types of opposing areas of the pair of electrode films sandwiching the thin film dielectric layer in the stacking direction are provided according to the capacitance to be obtained.
- a common electrode is in contact with one surface of the thin film dielectric layer, and a plurality of counter electrodes having different areas are in contact with the other surface.
- the passive circuit chip 110 and the digital control circuit chip 120 are stacked to form an integrated variable capacitance element. Therefore, the current path length between the plurality of passive elements and the switch elements is shortened, and desired filter characteristics can be obtained. In addition, the area occupied by the passive circuit chip 110 and the digital control circuit chip 120 with respect to the circuit board is reduced.
- each chip 120 may be stacked on the passive circuit chip 110, contrary to the stacked structure shown in FIGS. Further, each chip may be a bare chip, but may be various packaged chips.
- FIG. 8A is a perspective view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120 used in the high-speed serial signal equalizer according to the second embodiment.
- FIG. 8B is a front view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120.
- FIG. 9A is a plan view showing the arrangement of the plurality of terminals T11 of the passive circuit chip 110
- FIG. 9B is a plan view showing the arrangement of the plurality of terminals T12 of the digital control circuit chip 120.
- the pad P12 formed on the upper surface of the digital control circuit chip 120 is not shown.
- the terminals “1”, “2”, “3”, “4”, “5”, “6”, “7” 4 are terminals respectively connected to the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7.
- the terminal “COM” is a terminal to which the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 are commonly connected.
- the passive circuit chip 110 is die-bonded to the digital control circuit chip 120, and the pad P12 of the digital control circuit chip 120 and the terminal T11 of the passive circuit chip 110 are wire-bonded via the wire BW. Is done.
- the internal configuration of the digital control circuit chip 120 and the internal configuration of the passive circuit chip 110 are the same as those shown in the first embodiment.
- digital control circuit chip 120 may be stacked on the passive circuit chip 110, contrary to the stacked structure shown in FIGS. 8A and 8B.
- FIG. 10 is a circuit diagram of CTLE 11 of the high-speed serial signal equalizer according to the third embodiment.
- a variable resistance element is provided in addition to the variable capacitance element.
- the CTLE 11 of this embodiment includes an amplifier circuit A1, variable resistance elements VR11 and VR12, resistance elements R21, R22, and R30, variable capacitance elements VC1 and VC2, and a capacitance element Co.
- the variable capacitance elements VC1, VC2, variable resistance elements VR11, VR12, and resistance elements R21, R22 constitute a high pass filter. Further, a low-pass filter is configured by the resistor element R30 and the capacitive element Co.
- the amplifier circuit A1 differentially amplifies the differential signal input to the input terminals RXin + and RXin ⁇ , and outputs an unbalanced signal.
- the resistance values of the variable resistance elements VR11 and VR12 are represented by R11 and R12
- the resistance values of the resistance elements R21 and R22 are represented by R21 and R22, respectively
- the voltage amplification factor of the amplifier circuit A1 is , R21 / R11, R22 / R12.
- the variable resistance elements VR11 and VR12 are provided, the voltage amplification factor can be controlled.
- the cutoff frequency of the high-pass filter is determined by the resistance values R11, R12, R21, R22 and the capacitances of the variable capacitance elements VC1, VC2.
- FIG. 11 is a circuit diagram showing a connection relationship between the passive circuit chip 110 constituting the variable capacitance element VC1 and the variable resistance element VR11 and the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 connected thereto. .
- the passive circuit chip 110 includes a plurality of capacitance elements C1, C2, C3, and C4 and a plurality of resistance elements R1, R2, and R3.
- the plurality of switches SW1, SW2, SW3, SW4, SW5, SW6, and SW7 switch combinations of the plurality of capacitive elements C1, C2, C3, and C4 and the plurality of resistance elements R1, R2, and R3. The same applies to the configuration and operation of the circuits constituting the variable capacitance element VC2 and variable resistance element VR12 shown in FIG.
- two sets of the passive circuit chip 110 and the digital control circuit chip 120 are provided.
- the passive circuit chip 110 and the digital control circuit chip 120 are configured by one passive circuit chip and one digital control circuit chip.
- a circuit portion (other than the passive element control circuit CNT) includes capacitive elements C1, C2, C3, C4, C5, C6, C7 and switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR. 2 sets of circuit portions), and the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR of the two sets of circuit portions may be controlled by the passive element control circuit CNT.
- the two variable capacitance elements VC1 and VC2 shown in FIG. 1 can be configured by a single passive circuit chip and a single digital control circuit chip.
- the single capacitive element is selected from among the multiple capacitive elements.
- the present invention is not limited to this, and the multiple capacitive elements are selectively connected simultaneously. Also good.
- an 8-bit shift register is formed, and the state of the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 is selected by the lower 7 bits of the output, and the output of the most significant bit is input to the AND gate AG1.
- You may comprise as follows.
- a variable capacitance element is configured by selecting a capacitance element by switching a plurality of switches.
- a thin film dielectric layer whose dielectric constant changes depending on an applied voltage is used, and a control voltage is set.
- a variable capacitance element in which the capacitance between the two terminals changes may be configured.
- a resistance voltage dividing circuit for setting the control voltage may be provided in accordance with the states of the plurality of switches shown in FIG.
- variable filter circuit is provided with a capacitive element and a resistive element as passive elements, but an inductive element may be provided.
- CLK Clock terminal
- CNT Passive element control circuit
- Co Capacitance element
- CS Chip select terminals D1, D2, D3, D4 ... D type flip-flop DATA ... Control data input terminal DMPX ... Demultiplexer P12 ... Pads R1, R2, R3 of the digital control circuit chip 120 ... Resistance elements R11, R12, R21, R22, R30 ... Resistance elements RESET ... Reset terminal Rin ... Terminal resistor RXin-, RXin +... input terminals RXo: Output terminals S1, S2, S3, S4, S5, S6, S7, S8 ...
- Output signal SB ... Solder ball SET: set terminals SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR ... switch T11 ... terminal T12 of passive circuit chip 110 ... terminals VC1, VC2 of digital control circuit chip 120 ... variable capacitance elements VR11, VR12 ... Variable resistance element 1 ... Adder 2 ... Sampler 3 ... CDR (Clock Data Recovery) 4 ... DFE (Decision Feedback Equalizer) 10 ... High-speed serial signal equalizer 11 ... CTLE (Continuous-Time Linear Equalizer) 12 ... DTLE (Discrete Time Linear Equalizer) 110: Passive circuit chip 120 ... Digital control circuit chip
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Abstract
A high-speed serial signal equalizer provided in a high-speed serial signal receiving unit and equipped with a filter for improving the frequency characteristic of a received signal. This filter has a variable filter circuit the frequency characteristic of which can be switched and a control signal input unit for inputting a control signal that switches frequency characteristics. The variable filter circuit includes a plurality of passive elements (C1-C7) and switch elements (SW1-SW7) for switching the connection states of the plurality of passive elements. The plurality of passive elements are provided in a passive circuit chip (110) in which a passive circuit is formed, and the switch elements (SW1-SW7) are provided in a digital control circuit chip (120).
Description
本発明は、高速シリアル伝送における受信側で信号改善を行う高速シリアル信号イコライザに関する。
The present invention relates to a high-speed serial signal equalizer that performs signal improvement on the receiving side in high-speed serial transmission.
LVDS(Low Voltage Differential Signaling)や CML(Current Mode Logic)といった高速差動シリアル伝送のインターフェースにおいては、受信側に信号改善のためのイコライザが設けられる。
In high-speed differential serial transmission interfaces such as LVDS (Low Voltage Differential Signaling) and CML (Current Mode Logic), an equalizer for signal improvement is provided on the receiving side.
一般に、高速な差動信号を伝送する線路は、ローパスフィルタ特性を有し、そこを伝搬する信号の高周波成分を大きく減衰させる。その減衰量は、伝送距離が長ければ長いほど、周波数が高ければ高いほど大きくなる。したがって、高速な差動信号を長距離伝送する場合は、符号間干渉(ISI:Inter-Symbol Interference)が大きくなってしまい、符号誤り率が増大する。そのため、伝送信号の受信(レシーバ/デシリアライザ)側に、受信信号の周波数特性を改善するイコライザ(レシーバ・イコライザ)が設けられる。
Generally, a line that transmits a high-speed differential signal has a low-pass filter characteristic, and greatly attenuates a high-frequency component of a signal propagating therethrough. The amount of attenuation increases as the transmission distance increases and the frequency increases. Therefore, when high-speed differential signals are transmitted over long distances, inter-symbol interference (ISI: Inter-Symbol Interference) increases, and the code error rate increases. Therefore, an equalizer (receiver equalizer) for improving the frequency characteristics of the received signal is provided on the reception (receiver / deserializer) side of the transmission signal.
レシーバ・イコライザの基本構造はバンドパスフィルタである。このバンドパスフィルタのハイパス特性域で、伝送線路により減衰された高周波数域を増強し、ローパス特性域でハイパスフィルタによるノイズ成分の増大を抑制する。
The basic structure of the receiver equalizer is a bandpass filter. In the high-pass characteristic region of the band-pass filter, the high-frequency region attenuated by the transmission line is enhanced, and the increase of noise components due to the high-pass filter is suppressed in the low-pass property region.
アナログ回路によるイコライザは、時間軸上連続的な動作であるので、CTLE(Continues Time Linear Equalizer)、と呼ばれ、デジタル回路によるイコライザはビット単位で動作し、時間軸上断続的であるので、DTLE(Discrete Time Linear Equalizer)と呼ばれる。
Since the equalizer by analog circuit is continuous operation on the time axis, it is called CTLE (Continues Time Linear Equalizer), and the equalizer by digital circuit operates bit by bit and is intermittent on the time axis. It is called (Discrete Time Linear Equalizer).
各システム機器が含む集積回路、プリント回路基板および/またはラック間のいくつかの通信チャンネルは長さが様々であり、チャンネルの周波数応答に応じてイコライザの周波数応答を設定可能としたフロントエンド回路が特許文献1に示されている。
Several communication channels between integrated circuits, printed circuit boards and / or racks included in each system equipment vary in length, and there is a front-end circuit that can set the frequency response of the equalizer according to the frequency response of the channel It is shown in Patent Document 1.
高速シリアルインターフェースにおいては、データトラフィックの増加に伴い、データ転送レートも大きくなってきている。そのことに関連して、既に多くのプロコトルが存在し、今後も様々なプロトコルが定められようとしている。
In the high-speed serial interface, the data transfer rate is increasing as the data traffic increases. In connection with that, many protocols already exist, and various protocols are going to be established in the future.
図12は高速シリアルインターフェースの各種プロトコルと1レーンにおけるデータ転送レートとの関係を示す図である。このように、既に多くのプロトコルが存在し、且つデータ転送レートの幅も、例えば数Gbpsから数10Gbpsまで、と広い。
FIG. 12 is a diagram showing the relationship between various protocols of the high-speed serial interface and the data transfer rate in one lane. Thus, many protocols already exist, and the data transfer rate is also wide, for example, from several Gbps to several tens of Gbps.
上記各種のプロコトルのうち所定のプロトコルでデータ伝送を行うには、そのプロコトルに応じた、物理層インターフェース回路が必要である。
In order to transmit data using a predetermined protocol among the above various protocols, a physical layer interface circuit corresponding to the protocol is required.
イコライザの周波数応答特性を変更可能にしておけば、同じ回路構成のイコライザを、すなわち一つのイコライザを、プロトコルの異なる多くの高速シリアルインターフェースに適応させることができる。
If the frequency response characteristics of the equalizer can be changed, an equalizer having the same circuit configuration, that is, one equalizer can be adapted to many high-speed serial interfaces having different protocols.
ところが、イコライザの周波数応答を可変にするために可変容量素子を用いる場合、それをスイッチ等を含む半導体素子に一体的に設けることは困難である。
However, when a variable capacitance element is used to make the frequency response of the equalizer variable, it is difficult to provide it integrally with a semiconductor element including a switch or the like.
本発明の目的は、受信信号の周波数特性を改善するイコライザの周波数応答を可変とし、且つスイッチ等と一体化できるようにして、要求されるプロトコルに応じて周波数応答性をアダプティブに変更できるようにした、高速シリアル信号イコライザを提供することにある。
An object of the present invention is to make the frequency response of an equalizer that improves the frequency characteristics of a received signal variable and to be integrated with a switch or the like so that the frequency response can be changed adaptively according to a required protocol. Another object of the present invention is to provide a high-speed serial signal equalizer.
(1)本発明の高速シリアル信号イコライザは、
高速シリアル信号の受信部に設けられ、受信信号の周波数特性を改善するフィルタを備え、
前記フィルタは、周波数特性を切り替えられる可変フィルタ回路と、前記周波数特性を切り替える制御信号を入力する制御信号入力部とを有し、
前記可変フィルタ回路は、複数の受動素子と、前記複数の受動素子の接続状態を切替えるスイッチ素子と、を含み、
前記複数の受動素子はパッシブ回路が形成されたパッシブ回路チップに設けられ、前記スイッチ素子はデジタル制御回路チップに設けられている、ことを特徴とする。 (1) The high-speed serial signal equalizer of the present invention is
Provided in the high-speed serial signal receiver, equipped with a filter to improve the frequency characteristics of the received signal,
The filter includes a variable filter circuit capable of switching frequency characteristics, and a control signal input unit that inputs a control signal for switching the frequency characteristics,
The variable filter circuit includes a plurality of passive elements, and a switch element that switches a connection state of the plurality of passive elements,
The plurality of passive elements are provided in a passive circuit chip on which a passive circuit is formed, and the switch element is provided in a digital control circuit chip.
高速シリアル信号の受信部に設けられ、受信信号の周波数特性を改善するフィルタを備え、
前記フィルタは、周波数特性を切り替えられる可変フィルタ回路と、前記周波数特性を切り替える制御信号を入力する制御信号入力部とを有し、
前記可変フィルタ回路は、複数の受動素子と、前記複数の受動素子の接続状態を切替えるスイッチ素子と、を含み、
前記複数の受動素子はパッシブ回路が形成されたパッシブ回路チップに設けられ、前記スイッチ素子はデジタル制御回路チップに設けられている、ことを特徴とする。 (1) The high-speed serial signal equalizer of the present invention is
Provided in the high-speed serial signal receiver, equipped with a filter to improve the frequency characteristics of the received signal,
The filter includes a variable filter circuit capable of switching frequency characteristics, and a control signal input unit that inputs a control signal for switching the frequency characteristics,
The variable filter circuit includes a plurality of passive elements, and a switch element that switches a connection state of the plurality of passive elements,
The plurality of passive elements are provided in a passive circuit chip on which a passive circuit is formed, and the switch element is provided in a digital control circuit chip.
上記構成により、可変フィルタ回路は、デジタル制御回路を構成するための半導体チップとは別のパッシブ回路チップに設けられるため、例えば高容量の可変容量素子が構成でき、イコライザの周波数応答変化幅を大きく確保できる。
With the above configuration, since the variable filter circuit is provided in a passive circuit chip different from the semiconductor chip for configuring the digital control circuit, for example, a high-capacity variable capacitance element can be configured, and the frequency response variation width of the equalizer is increased. It can be secured.
(2)前記パッシブ回路チップと前記デジタル制御回路チップとは、回路基板に対して積層配置されていることが好ましい。これにより、複数の受動素子とスイッチ素子との電流経路長が短縮化されて、所期のフィルタ特性が得られる。また、パッシブ回路チップおよびデジタル制御回路チップの、回路基板に対する占有面積が縮小化される。
(2) It is preferable that the passive circuit chip and the digital control circuit chip are stacked on the circuit board. As a result, the current path length between the plurality of passive elements and the switch elements is shortened, and desired filter characteristics can be obtained. Further, the area occupied by the passive circuit chip and the digital control circuit chip with respect to the circuit board is reduced.
(3)前記受動素子は例えば容量素子である。この構成により、複数の容量素子の切り替えによって、可変フィルタの周波数特性が効果的に切り替えられる。
(3) The passive element is, for example, a capacitive element. With this configuration, the frequency characteristics of the variable filter can be effectively switched by switching the plurality of capacitive elements.
(4)前記容量素子は、強誘電体薄膜と当該強誘電体薄膜を挟んで対向する一対の電極膜とを備える薄膜キャパシタであることが好ましい。これにより、高容量の可変容量素子が構成でき、イコライザの周波数応答変化幅を大きく確保できる。
(4) Preferably, the capacitive element is a thin film capacitor including a ferroelectric thin film and a pair of electrode films facing each other with the ferroelectric thin film interposed therebetween. Thereby, a high-capacity variable capacitance element can be configured, and a large frequency response variation width of the equalizer can be secured.
(5)前記デジタル制御回路チップは、出力信号によって前記スイッチ素子の状態を定めるデマルチプレクサと、前記デマルチプレクサの入力に複数ビットのデータを与え、制御データ入力部から制御データを入力し、当該制御データをセットするレジスタと、を備えることが好ましい。この構成により、制御データ入力部から制御データを入力することによって、受動素子の接続状態を容易に切り替えることができる。
(5) The digital control circuit chip provides a demultiplexer that determines the state of the switch element by an output signal, and provides a plurality of bits of data to the input of the demultiplexer, inputs control data from a control data input unit, and performs the control And a register for setting data. With this configuration, the connection state of the passive elements can be easily switched by inputting control data from the control data input unit.
(6)前記可変フィルタ回路は、増幅回路と、前記増幅回路の入力部に接続され、可変容量素子および抵抗素子を含むハイパスフィルタ回路と、前記増幅回路の出力部に接続され、抵抗素子と容量素子とを含むローパスフィルタ回路とを備えることが好ましい。これにより、伝送路で減衰する高周波域が増強され、且つ高周波域のノイズ成分が効果的に抑制される。
(6) The variable filter circuit is connected to an amplifier circuit, a high-pass filter circuit including a variable capacitance element and a resistance element, connected to the input section of the amplifier circuit, and connected to an output section of the amplifier circuit, and includes a resistance element and a capacitor And a low-pass filter circuit including the element. As a result, the high frequency range that attenuates in the transmission path is enhanced, and the noise component in the high frequency range is effectively suppressed.
(7)前記可変フィルタ回路の後段に接続される、デジタルフィードバックイコライザを更に備えていてもよい。この構成により、データ・パターンに応じたイコライジング強度を変えることができ効果的な補償が可能となる。
(7) A digital feedback equalizer connected to a subsequent stage of the variable filter circuit may be further provided. With this configuration, the equalizing intensity according to the data pattern can be changed and effective compensation can be performed.
(8)本発明の高速シリアルインターフェースは、上記(1)から(7)のいずれかに記載の高速シリアル信号イコライザと、前記高速シリアル信号イコライザが接続される差動線路とを有する。
(8) A high-speed serial interface of the present invention includes the high-speed serial signal equalizer described in any one of (1) to (7) above and a differential line to which the high-speed serial signal equalizer is connected.
本発明によれば、受信信号の周波数特性を改善するイコライザの周波数応答を可変とし、且つスイッチ等と一体化できるようにして、要求されるプロトコルに応じて周波数応答性をアダプティブに変更できるようにした、高速シリアル信号イコライザが得られる。
According to the present invention, the frequency response of the equalizer that improves the frequency characteristics of the received signal can be made variable and integrated with a switch or the like so that the frequency response can be changed adaptively according to the required protocol. Thus, a high-speed serial signal equalizer can be obtained.
《第1の実施形態》
図1は第1の実施形態に係る高速シリアル信号イコライザ10およびそれを備える高速シリアルインターフェースの回路図である。この高速シリアル信号イコライザ10は、CTLE(Continuous-Time Linear Equalizer:連続時間線形等化器)11とDTLE(Discrete Time LinearEqualizer:離散時間線形等価器)12とを備え、高速シリアル(データ)信号の受信部に設けられ、受信信号の周波数特性を改善する。つまり、この高速シリアル信号イコライザ10は、入力端子RXin+ ,RXin- から入力される受信信号の符号誤り率が低減するように、その周波数スペクトラムを改善し、出力端子RXoから出力する。図1に示す例では、入力端子RXin+ ,RXin- 間に終端抵抗Rinが接続されている。高速シリアル信号イコライザ10は差動線路に接続される。この高速シリアル信号イコライザ10とそれが接続される差動線路とを含んで高速シリアルインターフェースが構成される。 << First Embodiment >>
FIG. 1 is a circuit diagram of a high-speedserial signal equalizer 10 and a high-speed serial interface including the same according to the first embodiment. The high-speed serial signal equalizer 10 includes a CTLE (Continuous-Time Linear Equalizer) 11 and a DTLE (Discrete Time Linear Equalizer) 12 for receiving a high-speed serial (data) signal. Provided to improve the frequency characteristics of the received signal. That is, the high-speed serial signal equalizer 10 improves the frequency spectrum so as to reduce the code error rate of the received signal input from the input terminals RXin + and RXin−, and outputs it from the output terminal RXo. In the example shown in FIG. 1, a termination resistor Rin is connected between the input terminals RXin + and RXin−. The high-speed serial signal equalizer 10 is connected to the differential line. A high-speed serial interface is configured including this high-speed serial signal equalizer 10 and a differential line to which it is connected.
図1は第1の実施形態に係る高速シリアル信号イコライザ10およびそれを備える高速シリアルインターフェースの回路図である。この高速シリアル信号イコライザ10は、CTLE(Continuous-Time Linear Equalizer:連続時間線形等化器)11とDTLE(Discrete Time LinearEqualizer:離散時間線形等価器)12とを備え、高速シリアル(データ)信号の受信部に設けられ、受信信号の周波数特性を改善する。つまり、この高速シリアル信号イコライザ10は、入力端子RXin+ ,RXin- から入力される受信信号の符号誤り率が低減するように、その周波数スペクトラムを改善し、出力端子RXoから出力する。図1に示す例では、入力端子RXin+ ,RXin- 間に終端抵抗Rinが接続されている。高速シリアル信号イコライザ10は差動線路に接続される。この高速シリアル信号イコライザ10とそれが接続される差動線路とを含んで高速シリアルインターフェースが構成される。 << First Embodiment >>
FIG. 1 is a circuit diagram of a high-speed
CTLE11は、増幅回路A1、抵抗素子R11,R12,R21,R22,R30、可変容量素子VC1,VC2、および容量素子Coを備える。可変容量素子VC1,VC2と抵抗素子R11,R12,R21,R22とによってハイパスフィルタが構成されている。また、抵抗素子R30と容量素子Coとによってローパスフィルタが構成されている。
The CTLE 11 includes an amplifier circuit A1, resistance elements R11, R12, R21, R22, and R30, variable capacitance elements VC1 and VC2, and a capacitance element Co. The variable capacitance elements VC1 and VC2 and the resistance elements R11, R12, R21, and R22 constitute a high pass filter. Further, a low-pass filter is configured by the resistor element R30 and the capacitive element Co.
増幅回路A1は、入力端子RXin+ ,RXin- に入力される差動信号を差動増幅し、非平衡信号を出力する。抵抗素子R11,R12,R21,R22の抵抗値は、それらをR11,R12,R21,R22で表すと、R11=R12、R21=R22の関係にあり、増幅回路A1の電圧増幅率は、R21/R11、R22/R12である。上記ハイパスフィルタのカットオフ周波数は、抵抗素子R11,R12,R21,R22の抵抗値と可変容量素子VC1,VC2のキャパシタンスとによって定まる。また、上記ローパスフィルタのカットオフ周波数は、抵抗素子R30の抵抗値と容量素子Coのキャパシタンスとによって定まる。
The amplifier circuit A1 differentially amplifies the differential signal input to the input terminals RXin + and RXin−, and outputs an unbalanced signal. When the resistance values of the resistance elements R11, R12, R21, and R22 are expressed as R11, R12, R21, and R22, they have a relationship of R11 = R12, R21 = R22, and the voltage amplification factor of the amplifier circuit A1 is R21 / R11 and R22 / R12. The cut-off frequency of the high-pass filter is determined by the resistance values of the resistance elements R11, R12, R21, and R22 and the capacitances of the variable capacitance elements VC1 and VC2. The cut-off frequency of the low-pass filter is determined by the resistance value of the resistance element R30 and the capacitance of the capacitive element Co.
DTLE12は、加算器1、サンプラー2、CDR(Clock Data Recovery)3およびDFE(Decision Feedback Equalizer:判定帰還型等化器)4を備える。DFE4は複数段の遅延回路と、それらの複数タップの出力を加算器1で加算することによってフィードバックし、データ・パターンに応じてイコライザ強度を変える。CDRは時間軸方向の波形の乱れを整形して、ジッタによる影響を低減する。
The DTLE 12 includes an adder 1, a sampler 2, a CDR (Clock Data Recovery) 3, and a DFE (Decision Feedback Feedback Equalizer) 4. The DFE 4 feeds back by adding a plurality of delay circuits and outputs of the plurality of taps by the adder 1, and changes the equalizer strength in accordance with the data pattern. CDR shapes the waveform disturbance in the time axis direction and reduces the influence of jitter.
図2は上記CTLE11の周波数応答の変化の例を示す図である。ここで、通過帯域の中心周波数(ピーク周波数)が2.5GHzである特性FR1は、データ転送レートが5Gbpsである例えばPCIe gen2 の信号に適用する特性である。通過帯域の中心周波数(ピーク周波数)が4GHzである特性FR2は、データ転送レートが8Gbpsである例えばPCIe gen3 の信号に適用する特性である。さらに、通過帯域の中心周波数(ピーク周波数)が8GHzである特性FR3は、データ転送レートが16Gbpsである例えばPCIe gen4 の信号に適用する特性である。
FIG. 2 is a diagram showing an example of changes in the frequency response of the CTLE 11 described above. Here, the characteristic FR1 having a center frequency (peak frequency) of the passband of 2.5 GHz is a characteristic applied to, for example, a PCIe gen2 signal having a data transfer rate of 5 Gbps. A characteristic FR2 having a passband center frequency (peak frequency) of 4 GHz is a characteristic applied to, for example, a PCIe gen3 signal having a data transfer rate of 8 Gbps. Furthermore, the characteristic FR3 having a passband center frequency (peak frequency) of 8 GHz is a characteristic applied to, for example, a PCIe gen4 signal having a data transfer rate of 16 Gbps.
図3(A)は、上記CTLE11を適用する前の、受信信号のアイパターン(アイダイアグラム)の例であり、図3(B)は、上記CTLE11を適用した後の、受信信号のアイパターン(アイダイアグラム)の例である。CTLE11の周波数応答を適切に定めることによって、アイパターンの縦(振幅)の高さ、横(時間軸)の幅のいずれも拡張される。
FIG. 3A shows an example of an eye pattern (eye diagram) of a received signal before applying the CTLE 11, and FIG. 3B shows an eye pattern (eye pattern) of the received signal after applying the CTLE 11. It is an example of an eye diagram. By appropriately determining the frequency response of the CTLE 11, both the height (amplitude) of the eye pattern and the width of the width (time axis) are expanded.
次に、パッシブ回路チップとデジタル制御回路チップの回路構成の例を示す。図4はパッシブ回路チップとデジタル制御回路チップの回路図である。図4において、パッシブ回路チップ110には複数の容量素子C1~C7が形成されている。その他の回路はデジタル制御回路チップ120に形成されている。
Next, an example of the circuit configuration of the passive circuit chip and the digital control circuit chip is shown. FIG. 4 is a circuit diagram of a passive circuit chip and a digital control circuit chip. In FIG. 4, the passive circuit chip 110 is formed with a plurality of capacitive elements C1 to C7. Other circuits are formed in the digital control circuit chip 120.
デジタル制御回路チップ120は、スイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7,SWS,SWR、ANDゲートAG1,AG2,AG3、D型フリップフロップD1,D2,D3,D4、およびデマルチプレクサDMPXを備える。
The digital control circuit chip 120 includes switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR, AND gates AG1, AG2, AG3, D-type flip-flops D1, D2, D3, D4, and a demultiplexer DMPX. Is provided.
図4において、容量素子C1,C2,C3,C4,C5,C6,C7にはスイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7がそれぞれ接続されている。容量素子C1,C2,C3,C4,C5,C6,C7の共通接続部は端子C-に接続されている。スイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7の共通接続部と端子C+との間にはスイッチSWSが挿入されている。
In FIG. 4, switches SW1, SW2, SW3, SW4, SW5, SW6, and SW7 are connected to the capacitive elements C1, C2, C3, C4, C5, C6, and C7, respectively. A common connection portion of the capacitive elements C1, C2, C3, C4, C5, C6, and C7 is connected to the terminal C−. A switch SWS is inserted between the common connection of the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 and the terminal C +.
デジタル制御回路チップ120の端子C+,C-間の回路が、図1に示した可変容量素子VC1または可変容量素子VC2に相当する。図4に示す例では、パッシブ回路チップ110は単一の可変容量素子に対応するので、可変容量素子VC1,VC2を構成するために、図4に示すパッシブ回路チップおよびデジタル制御回路チップを2組設ける。但し、後述するように、1個のパッシブ回路チップと1個のデジタル制御回路チップとで構成することもできる。
The circuit between the terminals C + and C− of the digital control circuit chip 120 corresponds to the variable capacitance element VC1 or the variable capacitance element VC2 shown in FIG. In the example shown in FIG. 4, since the passive circuit chip 110 corresponds to a single variable capacitance element, two sets of the passive circuit chip and the digital control circuit chip shown in FIG. 4 are used to configure the variable capacitance elements VC1 and VC2. Provide. However, as will be described later, it can also be composed of one passive circuit chip and one digital control circuit chip.
上記D型フリップフロップD1,D2,D3,D4は4段接続されて、4ビットのシフトレジスタが構成されている。このシフトレジスタの初段に、端子DATAの入力信号が与えられる。D型フリップフロップD1,D2,D3の出力はデマルチプレクサDMPXのQ1,Q2,Q3入力に入力される。このデマルチプレクサDMPXの出力信号S1,S2,S3,S4,S5,S6,S7は上記スイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7に対する制御信号として与えられる。
The D-type flip-flops D1, D2, D3, and D4 are connected in four stages to form a 4-bit shift register. The input signal of the terminal DATA is given to the first stage of this shift register. The outputs of the D-type flip-flops D1, D2, and D3 are input to the Q1, Q2, and Q3 inputs of the demultiplexer DMPX. Output signals S1, S2, S3, S4, S5, S6 and S7 of the demultiplexer DMPX are given as control signals for the switches SW1, SW2, SW3, SW4, SW5, SW6 and SW7.
ANDゲートAG1には、デジタル制御回路チップ120の端子SETの入力信号と、D型フリップフロップD4(シフトレジスタの終段)の出力信号Q4とが入力され、ANDゲートAG1の出力が“H”であるとき、スイッチSWSは導通する。
The input signal of the terminal SET of the digital control circuit chip 120 and the output signal Q4 of the D flip-flop D4 (end stage of the shift register) are input to the AND gate AG1, and the output of the AND gate AG1 is “H”. At some point, switch SWS is conducting.
ANDゲートAG2には、デジタル制御回路チップ120のクロック端子CLKとチップセレクト端子CSの入力信号が入力され、ANDゲートAG2の出力は上記シフトレジスタにクロック信号として与えられる。つまり、端子CSが“H”であるとき、端子CLKに入力されるクロック信号に同期してシフトレジスタの内容が上位ビット方向へシフトされる。
Input signals of the clock terminal CLK and the chip select terminal CS of the digital control circuit chip 120 are input to the AND gate AG2, and the output of the AND gate AG2 is supplied to the shift register as a clock signal. That is, when the terminal CS is “H”, the contents of the shift register are shifted in the upper bit direction in synchronization with the clock signal input to the terminal CLK.
ANDゲートAG3には、デジタル制御回路チップ120の端子RESETの入力信号と、デマルチプレクサDMPXの出力信号S8とが入力され、ANDゲートAG3の出力が“H”であるとき、上記シフトレジスタはリセットされる。またスイッチSWRが導通して、容量素子C1,C2,C3,C4,C5,C6,C7にチャージされていた電荷が放電される。
The input signal of the terminal RESET of the digital control circuit chip 120 and the output signal S8 of the demultiplexer DMPX are input to the AND gate AG3. When the output of the AND gate AG3 is “H”, the shift register is reset. The Further, the switch SWR is turned on, and the charges charged in the capacitive elements C1, C2, C3, C4, C5, C6, and C7 are discharged.
図5は、デジタル制御回路チップ120の各端子の状態遷移およびシフトレジスタにセットされる値の例を示す波形図である。この例は、容量素子C6を選択するために、スイッチSW6を導通させる例であり、端子CSが“H”である状態で、端子CLKに入力されるクロック信号に同期して、端子DATAに“1101”が順次入力される。最上位ビットの“1”は、図4に示したANDゲートAG1の出力によってスイッチSWSを導通させるためのビットである。それに続く3ビットのデータ“101”がデマルチプレクサDMPXに入力され、デマルチプレクサDMPXの出力信号S6が“H”となってスイッチSW6が導通する。その後、端子SETが“H”になると、スイッチSWSが導通する。これにより、端子C+,C-間に容量素子C6が接続される状態となる。
FIG. 5 is a waveform diagram showing an example of state transition of each terminal of the digital control circuit chip 120 and values set in the shift register. This example is an example in which the switch SW6 is turned on in order to select the capacitive element C6. In a state where the terminal CS is “H”, the terminal DATA is connected to the terminal DATA in synchronization with the clock signal input to the terminal CLK. 1101 "is sequentially input. The most significant bit “1” is a bit for making the switch SWS conductive by the output of the AND gate AG1 shown in FIG. Subsequent 3-bit data “101” is input to the demultiplexer DMPX, the output signal S6 of the demultiplexer DMPX becomes “H”, and the switch SW6 becomes conductive. Thereafter, when the terminal SET becomes “H”, the switch SWS becomes conductive. As a result, the capacitive element C6 is connected between the terminals C + and C−.
このようにして、3ビットの制御データで7通りの容量値を設定する。
In this way, 7 types of capacity values are set with 3-bit control data.
図6(A)は、パッシブ回路チップ110とデジタル制御回路チップ120との積層構造を示す斜視図であり、デジタル制御回路チップ120に対し、複数のはんだボールSBを介してパッシブ回路チップ110を接続する前の状態での斜視図である。図6(B)は、パッシブ回路チップ110とデジタル制御回路チップ120との積層構造を示す正面図である。
FIG. 6A is a perspective view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120. The passive circuit chip 110 is connected to the digital control circuit chip 120 via a plurality of solder balls SB. It is a perspective view in the state before doing. FIG. 6B is a front view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120.
デジタル制御回路チップ120の下面には、例えばCuにNiやAu等のめっき膜を被覆した、LGA(Land grid array)型の複数の端子T12が形成されている。パッシブ回路チップ110の下面の複数の端子T11は例えばCuにNiやAu等のめっき膜が被覆された端子であり、それらの表面にはんだボールが設けられていて、BGA(Ball Grid Array )型の端子が構成されている。デジタル制御回路チップ120の上面には複数のパッドP12が形成されていて、パッシブ回路チップ110の下面の上記BGA型の端子がパッドP12に接続される。
On the lower surface of the digital control circuit chip 120, for example, a plurality of LGA (Land grid 型 array) type terminals T12 in which a plating film such as Ni or Au is coated on Cu are formed. The plurality of terminals T11 on the lower surface of the passive circuit chip 110 are terminals in which, for example, Cu is coated with a plating film such as Ni or Au, solder balls are provided on the surface thereof, and BGA (Ball Grid Array) type The terminal is configured. A plurality of pads P12 are formed on the upper surface of the digital control circuit chip 120, and the BGA type terminals on the lower surface of the passive circuit chip 110 are connected to the pads P12.
図7(A)はパッシブ回路チップ110の複数の端子T11の配置を示す平面図であり、図7(B)はデジタル制御回路チップ120の複数の端子T12の配置を示す平面図である。図7(B)においては、デジタル制御回路チップ120の上面に形成されているパッドP12の図示は省略している。
7A is a plan view showing the arrangement of the plurality of terminals T11 of the passive circuit chip 110, and FIG. 7B is a plan view showing the arrangement of the plurality of terminals T12 of the digital control circuit chip 120. In FIG. 7B, the pad P12 formed on the upper surface of the digital control circuit chip 120 is not shown.
図7(A)に示すパッシブ回路チップ110の複数の端子T11のうち、端子“1”,“2”,“3”,“4”,“5”,“6”,“7”は、図4に示したスイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7にそれぞれ接続された端子である。また、端子“COM”はスイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7が共通接続された端子である。端子“NC”は非接続端子(空き端子)である。
Of the plurality of terminals T11 of the passive circuit chip 110 shown in FIG. 7A, the terminals “1”, “2”, “3”, “4”, “5”, “6”, “7” 4 are terminals respectively connected to the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7. The terminal “COM” is a terminal to which the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 are commonly connected. The terminal “NC” is a non-connection terminal (empty terminal).
図7(B)に示すデジタル制御回路チップ120の複数の端子に付した符号は図4中に示した各端子に付した符号と対応している。
7B corresponds to the reference numerals attached to the terminals shown in FIG. 4. The reference numerals attached to the plurality of terminals of the digital control circuit chip 120 shown in FIG.
デジタル制御回路チップ120は、例えばSiウェハーに半導体プロセスによって形成されたチップである。図4に示した各スイッチそれぞれは、pチャンネルMOSトランスファゲートとnチャンネルMOSトランスファゲートとが並列接続された双方向スイッチ回路である。
The digital control circuit chip 120 is a chip formed on a Si wafer by a semiconductor process, for example. Each switch shown in FIG. 4 is a bidirectional switch circuit in which a p-channel MOS transfer gate and an n-channel MOS transfer gate are connected in parallel.
パッシブ回路チップ110は、例えばチタン酸バリウムストロンチウム((Bax,Sr1-x)TiO3、以下「BST」)の焼結体を誘電体薄膜とする容量素子を備える。例えば、セラミック基板の一方の面に、薄膜誘電体層、およびこの薄膜誘電体層を積層方向に挟む電極層がそれぞれ薄膜プロセスによって形成されたものである。具体的には、薄膜誘電体層を積層方向に挟む一対の電極膜の対向面積は、得るべきキャパシタンスに応じて複数種設けられている。例えば、薄膜誘電体層の一方の面に共通電極が接し、他方の面に、面積がそれぞれ異なる複数の対向電極が接する。
The passive circuit chip 110 includes a capacitive element that uses, for example, a sintered body of barium strontium titanate ((Ba x , Sr 1-x ) TiO 3 , hereinafter referred to as “BST”) as a dielectric thin film. For example, a thin film dielectric layer and an electrode layer sandwiching the thin film dielectric layer in the stacking direction are formed on one surface of a ceramic substrate by a thin film process. Specifically, a plurality of types of opposing areas of the pair of electrode films sandwiching the thin film dielectric layer in the stacking direction are provided according to the capacitance to be obtained. For example, a common electrode is in contact with one surface of the thin film dielectric layer, and a plurality of counter electrodes having different areas are in contact with the other surface.
図6(A)(B)に示したように、パッシブ回路チップ110とデジタル制御回路チップ120とを積層することによって、一体化された可変容量素子が構成される。したがって、複数の受動素子とスイッチ素子との電流経路長が短縮化されて、所期のフィルタ特性が得られる。また、パッシブ回路チップ110およびデジタル制御回路チップ120の、回路基板に対する占有面積が縮小化される。
As shown in FIGS. 6A and 6B, the passive circuit chip 110 and the digital control circuit chip 120 are stacked to form an integrated variable capacitance element. Therefore, the current path length between the plurality of passive elements and the switch elements is shortened, and desired filter characteristics can be obtained. In addition, the area occupied by the passive circuit chip 110 and the digital control circuit chip 120 with respect to the circuit board is reduced.
なお、図6(A)(B)に示した積層構造とは逆に、パッシブ回路チップ110の上にデジタル制御回路チップ120を積層してもよい。また、各チップは、ベアチップであってもよいが、各種のパッケージ化されたチップであってもよい。
Note that the digital control circuit chip 120 may be stacked on the passive circuit chip 110, contrary to the stacked structure shown in FIGS. Further, each chip may be a bare chip, but may be various packaged chips.
《第2の実施形態》
図8(A)は、第2の実施形態に係る高速シリアル信号イコライザに用いる、パッシブ回路チップ110とデジタル制御回路チップ120との積層構造を示す斜視図である。図8(B)は、そのパッシブ回路チップ110とデジタル制御回路チップ120との積層構造を示す正面図である。 << Second Embodiment >>
FIG. 8A is a perspective view showing a laminated structure of thepassive circuit chip 110 and the digital control circuit chip 120 used in the high-speed serial signal equalizer according to the second embodiment. FIG. 8B is a front view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120.
図8(A)は、第2の実施形態に係る高速シリアル信号イコライザに用いる、パッシブ回路チップ110とデジタル制御回路チップ120との積層構造を示す斜視図である。図8(B)は、そのパッシブ回路チップ110とデジタル制御回路チップ120との積層構造を示す正面図である。 << Second Embodiment >>
FIG. 8A is a perspective view showing a laminated structure of the
図9(A)はパッシブ回路チップ110の複数の端子T11の配置を示す平面図であり、図9(B)はデジタル制御回路チップ120の複数の端子T12の配置を示す平面図である。図9(B)においては、デジタル制御回路チップ120の上面に形成されているパッドP12の図示は省略している。
9A is a plan view showing the arrangement of the plurality of terminals T11 of the passive circuit chip 110, and FIG. 9B is a plan view showing the arrangement of the plurality of terminals T12 of the digital control circuit chip 120. In FIG. 9B, the pad P12 formed on the upper surface of the digital control circuit chip 120 is not shown.
図9(A)に示すパッシブ回路チップ110の複数の端子T11のうち、端子“1”,“2”,“3”,“4”,“5”,“6”,“7”は、図4に示したスイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7にそれぞれ接続された端子である。また、端子“COM”はスイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7が共通接続された端子である。
Of the plurality of terminals T11 of the passive circuit chip 110 shown in FIG. 9A, the terminals “1”, “2”, “3”, “4”, “5”, “6”, “7” 4 are terminals respectively connected to the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7. The terminal “COM” is a terminal to which the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 are commonly connected.
図9(B)に示すデジタル制御回路チップ120の複数の端子に付した符号は図4中に示した各端子に付した符号と対応している。
Symbols attached to a plurality of terminals of the digital control circuit chip 120 shown in FIG. 9B correspond to the symbols attached to the terminals shown in FIG.
第2の実施形態では、デジタル制御回路チップ120に対してパッシブ回路チップ110がダイボンディングされ、デジタル制御回路チップ120のパッドP12とパッシブ回路チップ110の端子T11とは、ワイヤーBWを介してワイヤーボンディングされる。
In the second embodiment, the passive circuit chip 110 is die-bonded to the digital control circuit chip 120, and the pad P12 of the digital control circuit chip 120 and the terminal T11 of the passive circuit chip 110 are wire-bonded via the wire BW. Is done.
デジタル制御回路チップ120の内部の構成およびパッシブ回路チップ110の内部の構成は第1の実施形態で示したものと同じである。
The internal configuration of the digital control circuit chip 120 and the internal configuration of the passive circuit chip 110 are the same as those shown in the first embodiment.
なお、図8(A)(B)に示した積層構造とは逆に、パッシブ回路チップ110の上にデジタル制御回路チップ120を積層してもよい。
Note that the digital control circuit chip 120 may be stacked on the passive circuit chip 110, contrary to the stacked structure shown in FIGS. 8A and 8B.
《第3の実施形態》
図10は第3の実施形態に係る高速シリアル信号イコライザのCTLE11の回路図である。本実施形態では、可変容量素子以外に可変抵抗素子を備える。 << Third Embodiment >>
FIG. 10 is a circuit diagram of CTLE 11 of the high-speed serial signal equalizer according to the third embodiment. In the present embodiment, a variable resistance element is provided in addition to the variable capacitance element.
図10は第3の実施形態に係る高速シリアル信号イコライザのCTLE11の回路図である。本実施形態では、可変容量素子以外に可変抵抗素子を備える。 << Third Embodiment >>
FIG. 10 is a circuit diagram of CTLE 11 of the high-speed serial signal equalizer according to the third embodiment. In the present embodiment, a variable resistance element is provided in addition to the variable capacitance element.
本実施形態のCTLE11は、増幅回路A1、可変抵抗素子VR11,VR12、抵抗素子R21,R22,R30、可変容量素子VC1,VC2、および容量素子Coを備える。可変容量素子VC1,VC2と可変抵抗素子VR11,VR12、抵抗素子R21,R22とによってハイパスフィルタが構成されている。また、抵抗素子R30と容量素子Coとによってローパスフィルタが構成されている。
The CTLE 11 of this embodiment includes an amplifier circuit A1, variable resistance elements VR11 and VR12, resistance elements R21, R22, and R30, variable capacitance elements VC1 and VC2, and a capacitance element Co. The variable capacitance elements VC1, VC2, variable resistance elements VR11, VR12, and resistance elements R21, R22 constitute a high pass filter. Further, a low-pass filter is configured by the resistor element R30 and the capacitive element Co.
増幅回路A1は、入力端子RXin+ ,RXin- に入力される差動信号を差動増幅し、非平衡信号を出力する。可変抵抗素子VR11,VR12の抵抗値をそれぞれR11,R12、抵抗素子R21,R22の抵抗値をそれぞれR21,R22で表すと、R11=R12、R21=R22であり、増幅回路A1の電圧増幅率は、R21/R11、R22/R12である。第1の実施形態で図1に示したCTLE11と異なり、可変抵抗素子VR11,VR12を備えているので、上記電圧増幅率を制御できる。上記ハイパスフィルタのカットオフ周波数は、上記抵抗値R11,R12,R21,R22と可変容量素子VC1,VC2のキャパシタンスとによって定まる。
The amplifier circuit A1 differentially amplifies the differential signal input to the input terminals RXin + and RXin−, and outputs an unbalanced signal. When the resistance values of the variable resistance elements VR11 and VR12 are represented by R11 and R12, and the resistance values of the resistance elements R21 and R22 are represented by R21 and R22, respectively, R11 = R12 and R21 = R22, and the voltage amplification factor of the amplifier circuit A1 is , R21 / R11, R22 / R12. Unlike the CTLE 11 shown in FIG. 1 in the first embodiment, since the variable resistance elements VR11 and VR12 are provided, the voltage amplification factor can be controlled. The cutoff frequency of the high-pass filter is determined by the resistance values R11, R12, R21, R22 and the capacitances of the variable capacitance elements VC1, VC2.
図11は、可変容量素子VC1および可変抵抗素子VR11を構成するパッシブ回路チップ110と、それに接続されるスイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7との接続関係を示す回路図である。
FIG. 11 is a circuit diagram showing a connection relationship between the passive circuit chip 110 constituting the variable capacitance element VC1 and the variable resistance element VR11 and the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 connected thereto. .
パッシブ回路チップ110には複数の容量素子C1,C2,C3,C4および複数の抵抗素子R1,R2,R3を備える。複数のスイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7は、複数の容量素子C1,C2,C3,C4と複数の抵抗素子R1,R2,R3との組み合わせを切り替える。図10に示した可変容量素子VC2および可変抵抗素子VR12を構成する回路の構成、動作についても同様である。
The passive circuit chip 110 includes a plurality of capacitance elements C1, C2, C3, and C4 and a plurality of resistance elements R1, R2, and R3. The plurality of switches SW1, SW2, SW3, SW4, SW5, SW6, and SW7 switch combinations of the plurality of capacitive elements C1, C2, C3, and C4 and the plurality of resistance elements R1, R2, and R3. The same applies to the configuration and operation of the circuits constituting the variable capacitance element VC2 and variable resistance element VR12 shown in FIG.
《他の実施形態》
図4に示した例では、パッシブ回路チップ110とデジタル制御回路チップ120との組を2組設けるように構成したが、1個のパッシブ回路チップと1個のデジタル制御回路チップとで構成することも可能である。例えば、図4において、容量素子C1,C2,C3,C4,C5,C6,C7、スイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7,SWS,SWRによる回路部(パッシブ素子制御回路CNT以外の回路部)を2組設けて、この2組の回路部それぞれのスイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7,SWS,SWRをパッシブ素子制御回路CNTで制御すればよい。このことにより、単一のパッシブ回路チップと単一のデジタル制御回路チップとによって、図1に示した2つの可変容量素子VC1,VC2を構成できる。 << Other embodiments >>
In the example shown in FIG. 4, two sets of thepassive circuit chip 110 and the digital control circuit chip 120 are provided. However, the passive circuit chip 110 and the digital control circuit chip 120 are configured by one passive circuit chip and one digital control circuit chip. Is also possible. For example, in FIG. 4, a circuit portion (other than the passive element control circuit CNT) includes capacitive elements C1, C2, C3, C4, C5, C6, C7 and switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR. 2 sets of circuit portions), and the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR of the two sets of circuit portions may be controlled by the passive element control circuit CNT. Thus, the two variable capacitance elements VC1 and VC2 shown in FIG. 1 can be configured by a single passive circuit chip and a single digital control circuit chip.
図4に示した例では、パッシブ回路チップ110とデジタル制御回路チップ120との組を2組設けるように構成したが、1個のパッシブ回路チップと1個のデジタル制御回路チップとで構成することも可能である。例えば、図4において、容量素子C1,C2,C3,C4,C5,C6,C7、スイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7,SWS,SWRによる回路部(パッシブ素子制御回路CNT以外の回路部)を2組設けて、この2組の回路部それぞれのスイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7,SWS,SWRをパッシブ素子制御回路CNTで制御すればよい。このことにより、単一のパッシブ回路チップと単一のデジタル制御回路チップとによって、図1に示した2つの可変容量素子VC1,VC2を構成できる。 << Other embodiments >>
In the example shown in FIG. 4, two sets of the
また、図4に示した例では、複数の容量素子のうち単一の容量素子を選択するように構成したが、これに限らず、複数の容量素子が選択的に同時に接続されるようにしてもよい。例えば、8ビットのシフトレジスタを構成し、そのうち下位7ビットの出力でスイッチSW1,SW2,SW3,SW4,SW5,SW6,SW7の状態を選択し、最上位ビットの出力をANDゲートAG1に入力するように構成してもよい。
Further, in the example shown in FIG. 4, the single capacitive element is selected from among the multiple capacitive elements. However, the present invention is not limited to this, and the multiple capacitive elements are selectively connected simultaneously. Also good. For example, an 8-bit shift register is formed, and the state of the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 is selected by the lower 7 bits of the output, and the output of the most significant bit is input to the AND gate AG1. You may comprise as follows.
また、図4に示した例では、複数のスイッチの切り替えによって、容量素子を選択することで、可変容量素子を構成したが、印加電圧によって誘電率が変化する薄膜誘電体層を用い、制御電圧の設定によって、二つの端子間のキャパシタンスが変化する可変容量素子を構成してもよい。その場合には、図4に示した複数のスイッチの状態に応じて、制御電圧を設定する抵抗分圧回路を設ければよい。
In the example shown in FIG. 4, a variable capacitance element is configured by selecting a capacitance element by switching a plurality of switches. However, a thin film dielectric layer whose dielectric constant changes depending on an applied voltage is used, and a control voltage is set. Depending on the setting, a variable capacitance element in which the capacitance between the two terminals changes may be configured. In that case, a resistance voltage dividing circuit for setting the control voltage may be provided in accordance with the states of the plurality of switches shown in FIG.
また、図1に示した例では、可変フィルタ回路に、受動素子として容量素子や抵抗素子を設けたが、誘導素子を設けてもよい。
In the example shown in FIG. 1, the variable filter circuit is provided with a capacitive element and a resistive element as passive elements, but an inductive element may be provided.
最後に、上述の実施形態の説明は、すべての点で例示であって、制限的なものではない。当業者にとって変形および変更が適宜可能である。本発明の範囲は、上述の実施形態ではなく、特許請求の範囲によって示される。さらに、本発明の範囲には、特許請求の範囲内と均等の範囲内での実施形態からの変更が含まれる。
Finally, the description of the above embodiment is illustrative in all respects and not restrictive. Modifications and changes can be made as appropriate by those skilled in the art. The scope of the present invention is shown not by the above embodiments but by the claims. Furthermore, the scope of the present invention includes modifications from the embodiments within the scope equivalent to the claims.
A1…増幅回路
AG1,AG2,AG3…ANDゲート
BW…ワイヤー
C1,C2,C3,C4,C5,C6,C7…容量素子
CLK…クロック端子
CNT…パッシブ素子制御回路
Co…容量素子
CS…チップセレクト端子
D1,D2,D3,D4…D型フリップフロップ
DATA…制御データ入力端子
DMPX…デマルチプレクサ
P12…デジタル制御回路チップ120のパッド
R1,R2,R3…抵抗素子
R11,R12,R21,R22,R30…抵抗素子
RESET…リセット端子
Rin…終端抵抗
RXin-,RXin+ …入力端子
RXo…出力端子
S1,S2,S3,S4,S5,S6,S7,S8…出力信号
SB…はんだボール
SET…セット端子
SW1,SW2,SW3,SW4,SW5,SW6,SW7,SWS,SWR…スイッチ
T11…パッシブ回路チップ110の端子
T12…デジタル制御回路チップ120の端子
VC1,VC2…可変容量素子
VR11,VR12…可変抵抗素子
1…加算器
2…サンプラー
3…CDR(Clock Data Recovery)
4…DFE(Decision Feedback Equalizer:判定帰還型等化器)
10…高速シリアル信号イコライザ
11…CTLE(Continuous-Time Linear Equalizer:連続時間線形等化器)
12…DTLE(Discrete Time Linear Equalizer:離散時間線形等価器)
110…パッシブ回路チップ
120…デジタル制御回路チップ A1... Amplifier circuits AG1, AG2, AG3... AND gate BW... Wire C1, C2, C3, C4, C5, C6, C7.
CLK: Clock terminal CNT: Passive element control circuit Co: Capacitance element
CS: Chip select terminals D1, D2, D3, D4 ... D type flip-flop
DATA ... Control data input terminal DMPX ... Demultiplexer P12 ... Pads R1, R2, R3 of the digitalcontrol circuit chip 120 ... Resistance elements R11, R12, R21, R22, R30 ... Resistance elements
RESET ... Reset terminal Rin ... Terminal resistor
RXin-, RXin +… input terminals
RXo: Output terminals S1, S2, S3, S4, S5, S6, S7, S8 ... Output signal SB ... Solder ball
SET: set terminals SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR ... switch T11 ... terminal T12 ofpassive circuit chip 110 ... terminals VC1, VC2 of digital control circuit chip 120 ... variable capacitance elements VR11, VR12 ... Variable resistance element 1 ... Adder 2 ... Sampler 3 ... CDR (Clock Data Recovery)
4 ... DFE (Decision Feedback Equalizer)
10 ... High-speedserial signal equalizer 11 ... CTLE (Continuous-Time Linear Equalizer)
12 ... DTLE (Discrete Time Linear Equalizer)
110:Passive circuit chip 120 ... Digital control circuit chip
AG1,AG2,AG3…ANDゲート
BW…ワイヤー
C1,C2,C3,C4,C5,C6,C7…容量素子
CLK…クロック端子
CNT…パッシブ素子制御回路
Co…容量素子
CS…チップセレクト端子
D1,D2,D3,D4…D型フリップフロップ
DATA…制御データ入力端子
DMPX…デマルチプレクサ
P12…デジタル制御回路チップ120のパッド
R1,R2,R3…抵抗素子
R11,R12,R21,R22,R30…抵抗素子
RESET…リセット端子
Rin…終端抵抗
RXin-,RXin+ …入力端子
RXo…出力端子
S1,S2,S3,S4,S5,S6,S7,S8…出力信号
SB…はんだボール
SET…セット端子
SW1,SW2,SW3,SW4,SW5,SW6,SW7,SWS,SWR…スイッチ
T11…パッシブ回路チップ110の端子
T12…デジタル制御回路チップ120の端子
VC1,VC2…可変容量素子
VR11,VR12…可変抵抗素子
1…加算器
2…サンプラー
3…CDR(Clock Data Recovery)
4…DFE(Decision Feedback Equalizer:判定帰還型等化器)
10…高速シリアル信号イコライザ
11…CTLE(Continuous-Time Linear Equalizer:連続時間線形等化器)
12…DTLE(Discrete Time Linear Equalizer:離散時間線形等価器)
110…パッシブ回路チップ
120…デジタル制御回路チップ A1... Amplifier circuits AG1, AG2, AG3... AND gate BW... Wire C1, C2, C3, C4, C5, C6, C7.
CLK: Clock terminal CNT: Passive element control circuit Co: Capacitance element
CS: Chip select terminals D1, D2, D3, D4 ... D type flip-flop
DATA ... Control data input terminal DMPX ... Demultiplexer P12 ... Pads R1, R2, R3 of the digital
RESET ... Reset terminal Rin ... Terminal resistor
RXin-, RXin +… input terminals
RXo: Output terminals S1, S2, S3, S4, S5, S6, S7, S8 ... Output signal SB ... Solder ball
SET: set terminals SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR ... switch T11 ... terminal T12 of
4 ... DFE (Decision Feedback Equalizer)
10 ... High-speed
12 ... DTLE (Discrete Time Linear Equalizer)
110:
Claims (8)
- 高速シリアル信号の受信部に設けられ、受信信号の周波数特性を改善するフィルタを備え、
前記フィルタは、周波数特性を切り替えられる可変フィルタ回路と、前記周波数特性を切り替える制御信号を入力する制御信号入力部とを有し、
前記可変フィルタ回路は、複数の受動素子と、前記複数の受動素子の接続状態を切替えるスイッチ素子と、を含み、
前記複数の受動素子はパッシブ回路が形成されたパッシブ回路チップに設けられ、前記スイッチ素子はデジタル制御回路チップに設けられている、
高速シリアル信号イコライザ。 Provided in the high-speed serial signal receiver, equipped with a filter to improve the frequency characteristics of the received signal,
The filter includes a variable filter circuit capable of switching frequency characteristics, and a control signal input unit that inputs a control signal for switching the frequency characteristics,
The variable filter circuit includes a plurality of passive elements, and a switch element that switches a connection state of the plurality of passive elements,
The plurality of passive elements are provided in a passive circuit chip in which a passive circuit is formed, and the switch element is provided in a digital control circuit chip.
High-speed serial signal equalizer. - 前記パッシブ回路チップと前記デジタル制御回路チップとは、回路基板に対して積層配置されている、請求項1に記載の高速シリアル信号イコライザ。 The high-speed serial signal equalizer according to claim 1, wherein the passive circuit chip and the digital control circuit chip are stacked on a circuit board.
- 前記受動素子は容量素子である、請求項1または2に記載の高速シリアル信号イコライザ。 The high-speed serial signal equalizer according to claim 1 or 2, wherein the passive element is a capacitive element.
- 前記容量素子は、強誘電体薄膜と当該強誘電体薄膜を挟んで対向する一対の電極膜とを備える薄膜キャパシタである、請求項3に記載の高速シリアル信号イコライザ。 The high-speed serial signal equalizer according to claim 3, wherein the capacitive element is a thin film capacitor including a ferroelectric thin film and a pair of electrode films facing each other with the ferroelectric thin film interposed therebetween.
- 前記デジタル制御回路チップは、
出力信号によって前記スイッチ素子の状態を定めるデマルチプレクサと、
前記デマルチプレクサの入力に複数ビットのデータを与え、制御データ入力部から制御データを入力し、当該制御データをセットするレジスタと、
を備える、請求項1から4のいずれかに記載の高速シリアル信号イコライザ。 The digital control circuit chip is:
A demultiplexer for determining the state of the switch element by an output signal;
A register that gives a plurality of bits of data to the input of the demultiplexer, inputs control data from a control data input unit, and sets the control data;
The high-speed serial signal equalizer according to claim 1, comprising: - 前記可変フィルタ回路は、
増幅回路と、
前記増幅回路の入力部に接続され、可変容量素子および抵抗素子を含むハイパスフィルタ回路と、
前記増幅回路の出力部に接続され、抵抗素子と容量素子とを含むローパスフィルタ回路とを備える、請求項1から5のいずれかに記載の高速シリアル信号イコライザ。 The variable filter circuit is:
An amplifier circuit;
A high-pass filter circuit connected to the input section of the amplifier circuit and including a variable capacitance element and a resistance element;
6. The high-speed serial signal equalizer according to claim 1, further comprising: a low-pass filter circuit that is connected to an output unit of the amplification circuit and includes a resistance element and a capacitance element. - 前記可変フィルタ回路の後段に接続されたデジタルフィードバックイコライザを更に備える、請求項1から6のいずれかに記載の高速シリアル信号イコライザ。 The high-speed serial signal equalizer according to any one of claims 1 to 6, further comprising a digital feedback equalizer connected to a subsequent stage of the variable filter circuit.
- 請求項1から7のいずれかに記載の高速シリアル信号イコライザと、前記高速シリアル信号イコライザが接続される差動線路とを有する高速シリアルインターフェース。 A high-speed serial interface comprising: the high-speed serial signal equalizer according to any one of claims 1 to 7; and a differential line to which the high-speed serial signal equalizer is connected.
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