WO2018056100A1

WO2018056100A1 - High-speed serial signal equalizer and high-speed serial interface

Info

Publication number: WO2018056100A1
Application number: PCT/JP2017/032736
Authority: WO
Inventors: 孟明玉山
Original assignee: 株式会社村田製作所
Priority date: 2016-09-26
Filing date: 2017-09-12
Publication date: 2018-03-29

Abstract

A high-speed serial signal equalizer provided in a high-speed serial signal receiving unit and equipped with a filter for improving the frequency characteristic of a received signal. This filter has a variable filter circuit the frequency characteristic of which can be switched and a control signal input unit for inputting a control signal that switches frequency characteristics. The variable filter circuit includes a plurality of passive elements (C1-C7) and switch elements (SW1-SW7) for switching the connection states of the plurality of passive elements. The plurality of passive elements are provided in a passive circuit chip (110) in which a passive circuit is formed, and the switch elements (SW1-SW7) are provided in a digital control circuit chip (120).

Description

High-speed serial signal equalizer and high-speed serial interface

The present invention relates to a high-speed serial signal equalizer that performs signal improvement on the receiving side in high-speed serial transmission.

In high-speed differential serial transmission interfaces such as LVDS (Low Voltage Differential Signaling) and CML (Current Mode Logic), an equalizer for signal improvement is provided on the receiving side.

Generally, a line that transmits a high-speed differential signal has a low-pass filter characteristic, and greatly attenuates a high-frequency component of a signal propagating therethrough. The amount of attenuation increases as the transmission distance increases and the frequency increases. Therefore, when high-speed differential signals are transmitted over long distances, inter-symbol interference (ISI: Inter-Symbol Interference) increases, and the code error rate increases. Therefore, an equalizer (receiver equalizer) for improving the frequency characteristics of the received signal is provided on the reception (receiver / deserializer) side of the transmission signal.

The basic structure of the receiver equalizer is a bandpass filter. In the high-pass characteristic region of the band-pass filter, the high-frequency region attenuated by the transmission line is enhanced, and the increase of noise components due to the high-pass filter is suppressed in the low-pass property region.

Since the equalizer by analog circuit is continuous operation on the time axis, it is called CTLE (Continues Time Linear Equalizer), and the equalizer by digital circuit operates bit by bit and is intermittent on the time axis. It is called (Discrete Time Linear Equalizer).

Several communication channels between integrated circuits, printed circuit boards and / or racks included in each system equipment vary in length, and there is a front-end circuit that can set the frequency response of the equalizer according to the frequency response of the channel It is shown in Patent Document 1.

JP 2007-505576 A

In the high-speed serial interface, the data transfer rate is increasing as the data traffic increases. In connection with that, many protocols already exist, and various protocols are going to be established in the future.

FIG. 12 is a diagram showing the relationship between various protocols of the high-speed serial interface and the data transfer rate in one lane. Thus, many protocols already exist, and the data transfer rate is also wide, for example, from several Gbps to several tens of Gbps.

In order to transmit data using a predetermined protocol among the above various protocols, a physical layer interface circuit corresponding to the protocol is required.

If the frequency response characteristics of the equalizer can be changed, an equalizer having the same circuit configuration, that is, one equalizer can be adapted to many high-speed serial interfaces having different protocols.

However, when a variable capacitance element is used to make the frequency response of the equalizer variable, it is difficult to provide it integrally with a semiconductor element including a switch or the like.

An object of the present invention is to make the frequency response of an equalizer that improves the frequency characteristics of a received signal variable and to be integrated with a switch or the like so that the frequency response can be changed adaptively according to a required protocol. Another object of the present invention is to provide a high-speed serial signal equalizer.

(1) The high-speed serial signal equalizer of the present invention is
Provided in the high-speed serial signal receiver, equipped with a filter to improve the frequency characteristics of the received signal,
The filter includes a variable filter circuit capable of switching frequency characteristics, and a control signal input unit that inputs a control signal for switching the frequency characteristics,
The variable filter circuit includes a plurality of passive elements, and a switch element that switches a connection state of the plurality of passive elements,
The plurality of passive elements are provided in a passive circuit chip on which a passive circuit is formed, and the switch element is provided in a digital control circuit chip.

With the above configuration, since the variable filter circuit is provided in a passive circuit chip different from the semiconductor chip for configuring the digital control circuit, for example, a high-capacity variable capacitance element can be configured, and the frequency response variation width of the equalizer is increased. It can be secured.

(2) It is preferable that the passive circuit chip and the digital control circuit chip are stacked on the circuit board. As a result, the current path length between the plurality of passive elements and the switch elements is shortened, and desired filter characteristics can be obtained. Further, the area occupied by the passive circuit chip and the digital control circuit chip with respect to the circuit board is reduced.

(3) The passive element is, for example, a capacitive element. With this configuration, the frequency characteristics of the variable filter can be effectively switched by switching the plurality of capacitive elements.

(4) Preferably, the capacitive element is a thin film capacitor including a ferroelectric thin film and a pair of electrode films facing each other with the ferroelectric thin film interposed therebetween. Thereby, a high-capacity variable capacitance element can be configured, and a large frequency response variation width of the equalizer can be secured.

(5) The digital control circuit chip provides a demultiplexer that determines the state of the switch element by an output signal, and provides a plurality of bits of data to the input of the demultiplexer, inputs control data from a control data input unit, and performs the control And a register for setting data. With this configuration, the connection state of the passive elements can be easily switched by inputting control data from the control data input unit.

(6) The variable filter circuit is connected to an amplifier circuit, a high-pass filter circuit including a variable capacitance element and a resistance element, connected to the input section of the amplifier circuit, and connected to an output section of the amplifier circuit, and includes a resistance element and a capacitor And a low-pass filter circuit including the element. As a result, the high frequency range that attenuates in the transmission path is enhanced, and the noise component in the high frequency range is effectively suppressed.

(7) A digital feedback equalizer connected to a subsequent stage of the variable filter circuit may be further provided. With this configuration, the equalizing intensity according to the data pattern can be changed and effective compensation can be performed.

(8) A high-speed serial interface of the present invention includes the high-speed serial signal equalizer described in any one of (1) to (7) above and a differential line to which the high-speed serial signal equalizer is connected.

According to the present invention, the frequency response of the equalizer that improves the frequency characteristics of the received signal can be made variable and integrated with a switch or the like so that the frequency response can be changed adaptively according to the required protocol. Thus, a high-speed serial signal equalizer can be obtained.

FIG. 1 is a diagram illustrating a configuration of a high-speed serial signal equalizer 10 and a high-speed serial interface according to the first embodiment. FIG. 2 is a diagram illustrating an example of a change in the frequency response of CTLE 11. FIG. 3A shows an example of an eye pattern of a received signal before applying CTLE 11, and FIG. 3B shows an example of an eye pattern of a received signal after applying CTLE 11. FIG. 4 is a circuit diagram of a passive circuit chip and a digital control circuit chip. FIG. 5 is a waveform diagram showing an example of the state transition of each terminal of the digital control circuit chip 120 and the value set in the shift register. FIG. 6A is a perspective view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120. The passive circuit chip 110 is connected to the digital control circuit chip 120 via a plurality of solder balls SB. It is a perspective view in the state before doing. FIG. 6B is a front view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120. FIG. 7A is a plan view showing the arrangement of the plurality of terminals T11 of the passive circuit chip 110, and FIG. 7B is a plan view showing the arrangement of the plurality of terminals T12 of the digital control circuit chip 120. FIG. 8A is a perspective view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120 used in the high-speed serial signal equalizer according to the second embodiment. FIG. 8B is a front view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120. FIG. 9A is a plan view showing the arrangement of the plurality of terminals T11 of the passive circuit chip 110 according to the second embodiment, and FIG. 9B shows the arrangement of the plurality of terminals T12 of the digital control circuit chip 120. FIG. FIG. 10 is a circuit diagram of CTLE 11 of the high-speed serial signal equalizer according to the third embodiment. FIG. 11 shows a connection relationship between the passive circuit chip 110 constituting the variable capacitance element VC1 and the variable resistance element VR11 according to the third embodiment and the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 connected thereto. FIG. FIG. 12 is a diagram showing the relationship between various protocols of the high-speed serial interface and the data transfer rate in one lane.

<< First Embodiment >>
FIG. 1 is a circuit diagram of a high-speed serial signal equalizer 10 and a high-speed serial interface including the same according to the first embodiment. The high-speed serial signal equalizer 10 includes a CTLE (Continuous-Time Linear Equalizer) 11 and a DTLE (Discrete Time Linear Equalizer) 12 for receiving a high-speed serial (data) signal. Provided to improve the frequency characteristics of the received signal. That is, the high-speed serial signal equalizer 10 improves the frequency spectrum so as to reduce the code error rate of the received signal input from the input terminals RXin + and RXin−, and outputs it from the output terminal RXo. In the example shown in FIG. 1, a termination resistor Rin is connected between the input terminals RXin + and RXin−. The high-speed serial signal equalizer 10 is connected to the differential line. A high-speed serial interface is configured including this high-speed serial signal equalizer 10 and a differential line to which it is connected.

The CTLE 11 includes an amplifier circuit A1, resistance elements R11, R12, R21, R22, and R30, variable capacitance elements VC1 and VC2, and a capacitance element Co. The variable capacitance elements VC1 and VC2 and the resistance elements R11, R12, R21, and R22 constitute a high pass filter. Further, a low-pass filter is configured by the resistor element R30 and the capacitive element Co.

The amplifier circuit A1 differentially amplifies the differential signal input to the input terminals RXin + and RXin−, and outputs an unbalanced signal. When the resistance values of the resistance elements R11, R12, R21, and R22 are expressed as R11, R12, R21, and R22, they have a relationship of R11 = R12, R21 = R22, and the voltage amplification factor of the amplifier circuit A1 is R21 / R11 and R22 / R12. The cut-off frequency of the high-pass filter is determined by the resistance values of the resistance elements R11, R12, R21, and R22 and the capacitances of the variable capacitance elements VC1 and VC2. The cut-off frequency of the low-pass filter is determined by the resistance value of the resistance element R30 and the capacitance of the capacitive element Co.

The DTLE 12 includes an adder 1, a sampler 2, a CDR (Clock Data Recovery) 3, and a DFE (Decision Feedback Feedback Equalizer) 4. The DFE 4 feeds back by adding a plurality of delay circuits and outputs of the plurality of taps by the adder 1, and changes the equalizer strength in accordance with the data pattern. CDR shapes the waveform disturbance in the time axis direction and reduces the influence of jitter.

FIG. 2 is a diagram showing an example of changes in the frequency response of the CTLE 11 described above. Here, the characteristic FR1 having a center frequency (peak frequency) of the passband of 2.5 GHz is a characteristic applied to, for example, a PCIe gen2 signal having a data transfer rate of 5 Gbps. A characteristic FR2 having a passband center frequency (peak frequency) of 4 GHz is a characteristic applied to, for example, a PCIe gen3 signal having a data transfer rate of 8 Gbps. Furthermore, the characteristic FR3 having a passband center frequency (peak frequency) of 8 GHz is a characteristic applied to, for example, a PCIe gen4 signal having a data transfer rate of 16 Gbps.

FIG. 3A shows an example of an eye pattern (eye diagram) of a received signal before applying the CTLE 11, and FIG. 3B shows an eye pattern (eye pattern) of the received signal after applying the CTLE 11. It is an example of an eye diagram. By appropriately determining the frequency response of the CTLE 11, both the height (amplitude) of the eye pattern and the width of the width (time axis) are expanded.

Next, an example of the circuit configuration of the passive circuit chip and the digital control circuit chip is shown. FIG. 4 is a circuit diagram of a passive circuit chip and a digital control circuit chip. In FIG. 4, the passive circuit chip 110 is formed with a plurality of capacitive elements C1 to C7. Other circuits are formed in the digital control circuit chip 120.

The digital control circuit chip 120 includes switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR, AND gates AG1, AG2, AG3, D-type flip-flops D1, D2, D3, D4, and a demultiplexer DMPX. Is provided.

In FIG. 4, switches SW1, SW2, SW3, SW4, SW5, SW6, and SW7 are connected to the capacitive elements C1, C2, C3, C4, C5, C6, and C7, respectively. A common connection portion of the capacitive elements C1, C2, C3, C4, C5, C6, and C7 is connected to the terminal C−. A switch SWS is inserted between the common connection of the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 and the terminal C +.

The circuit between the terminals C + and C− of the digital control circuit chip 120 corresponds to the variable capacitance element VC1 or the variable capacitance element VC2 shown in FIG. In the example shown in FIG. 4, since the passive circuit chip 110 corresponds to a single variable capacitance element, two sets of the passive circuit chip and the digital control circuit chip shown in FIG. 4 are used to configure the variable capacitance elements VC1 and VC2. Provide. However, as will be described later, it can also be composed of one passive circuit chip and one digital control circuit chip.

The D-type flip-flops D1, D2, D3, and D4 are connected in four stages to form a 4-bit shift register. The input signal of the terminal DATA is given to the first stage of this shift register. The outputs of the D-type flip-flops D1, D2, and D3 are input to the Q1, Q2, and Q3 inputs of the demultiplexer DMPX. Output signals S1, S2, S3, S4, S5, S6 and S7 of the demultiplexer DMPX are given as control signals for the switches SW1, SW2, SW3, SW4, SW5, SW6 and SW7.

The input signal of the terminal SET of the digital control circuit chip 120 and the output signal Q4 of the D flip-flop D4 (end stage of the shift register) are input to the AND gate AG1, and the output of the AND gate AG1 is “H”. At some point, switch SWS is conducting.

Input signals of the clock terminal CLK and the chip select terminal CS of the digital control circuit chip 120 are input to the AND gate AG2, and the output of the AND gate AG2 is supplied to the shift register as a clock signal. That is, when the terminal CS is “H”, the contents of the shift register are shifted in the upper bit direction in synchronization with the clock signal input to the terminal CLK.

The input signal of the terminal RESET of the digital control circuit chip 120 and the output signal S8 of the demultiplexer DMPX are input to the AND gate AG3. When the output of the AND gate AG3 is “H”, the shift register is reset. The Further, the switch SWR is turned on, and the charges charged in the capacitive elements C1, C2, C3, C4, C5, C6, and C7 are discharged.

FIG. 5 is a waveform diagram showing an example of state transition of each terminal of the digital control circuit chip 120 and values set in the shift register. This example is an example in which the switch SW6 is turned on in order to select the capacitive element C6. In a state where the terminal CS is “H”, the terminal DATA is connected to the terminal DATA in synchronization with the clock signal input to the terminal CLK. 1101 "is sequentially input. The most significant bit “1” is a bit for making the switch SWS conductive by the output of the AND gate AG1 shown in FIG. Subsequent 3-bit data “101” is input to the demultiplexer DMPX, the output signal S6 of the demultiplexer DMPX becomes “H”, and the switch SW6 becomes conductive. Thereafter, when the terminal SET becomes “H”, the switch SWS becomes conductive. As a result, the capacitive element C6 is connected between the terminals C + and C−.

In this way, 7 types of capacity values are set with 3-bit control data.

FIG. 6A is a perspective view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120. The passive circuit chip 110 is connected to the digital control circuit chip 120 via a plurality of solder balls SB. It is a perspective view in the state before doing. FIG. 6B is a front view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120.

On the lower surface of the digital control circuit chip 120, for example, a plurality of LGA (Land grid 型 array) type terminals T12 in which a plating film such as Ni or Au is coated on Cu are formed. The plurality of terminals T11 on the lower surface of the passive circuit chip 110 are terminals in which, for example, Cu is coated with a plating film such as Ni or Au, solder balls are provided on the surface thereof, and BGA (Ball Grid Array) type The terminal is configured. A plurality of pads P12 are formed on the upper surface of the digital control circuit chip 120, and the BGA type terminals on the lower surface of the passive circuit chip 110 are connected to the pads P12.

7A is a plan view showing the arrangement of the plurality of terminals T11 of the passive circuit chip 110, and FIG. 7B is a plan view showing the arrangement of the plurality of terminals T12 of the digital control circuit chip 120. In FIG. 7B, the pad P12 formed on the upper surface of the digital control circuit chip 120 is not shown.

Of the plurality of terminals T11 of the passive circuit chip 110 shown in FIG. 7A, the terminals “1”, “2”, “3”, “4”, “5”, “6”, “7” 4 are terminals respectively connected to the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7. The terminal “COM” is a terminal to which the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 are commonly connected. The terminal “NC” is a non-connection terminal (empty terminal).

7B corresponds to the reference numerals attached to the terminals shown in FIG. 4. The reference numerals attached to the plurality of terminals of the digital control circuit chip 120 shown in FIG.

The digital control circuit chip 120 is a chip formed on a Si wafer by a semiconductor process, for example. Each switch shown in FIG. 4 is a bidirectional switch circuit in which a p-channel MOS transfer gate and an n-channel MOS transfer gate are connected in parallel.

The passive circuit chip 110 includes a capacitive element that uses, for example, a sintered body of barium strontium titanate ((Ba _x , Sr _1-x ) TiO ₃ , hereinafter referred to as “BST”) as a dielectric thin film. For example, a thin film dielectric layer and an electrode layer sandwiching the thin film dielectric layer in the stacking direction are formed on one surface of a ceramic substrate by a thin film process. Specifically, a plurality of types of opposing areas of the pair of electrode films sandwiching the thin film dielectric layer in the stacking direction are provided according to the capacitance to be obtained. For example, a common electrode is in contact with one surface of the thin film dielectric layer, and a plurality of counter electrodes having different areas are in contact with the other surface.

As shown in FIGS. 6A and 6B, the passive circuit chip 110 and the digital control circuit chip 120 are stacked to form an integrated variable capacitance element. Therefore, the current path length between the plurality of passive elements and the switch elements is shortened, and desired filter characteristics can be obtained. In addition, the area occupied by the passive circuit chip 110 and the digital control circuit chip 120 with respect to the circuit board is reduced.

Note that the digital control circuit chip 120 may be stacked on the passive circuit chip 110, contrary to the stacked structure shown in FIGS. Further, each chip may be a bare chip, but may be various packaged chips.

<< Second Embodiment >>
FIG. 8A is a perspective view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120 used in the high-speed serial signal equalizer according to the second embodiment. FIG. 8B is a front view showing a laminated structure of the passive circuit chip 110 and the digital control circuit chip 120.

9A is a plan view showing the arrangement of the plurality of terminals T11 of the passive circuit chip 110, and FIG. 9B is a plan view showing the arrangement of the plurality of terminals T12 of the digital control circuit chip 120. In FIG. 9B, the pad P12 formed on the upper surface of the digital control circuit chip 120 is not shown.

Of the plurality of terminals T11 of the passive circuit chip 110 shown in FIG. 9A, the terminals “1”, “2”, “3”, “4”, “5”, “6”, “7” 4 are terminals respectively connected to the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7. The terminal “COM” is a terminal to which the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 are commonly connected.

Symbols attached to a plurality of terminals of the digital control circuit chip 120 shown in FIG. 9B correspond to the symbols attached to the terminals shown in FIG.

In the second embodiment, the passive circuit chip 110 is die-bonded to the digital control circuit chip 120, and the pad P12 of the digital control circuit chip 120 and the terminal T11 of the passive circuit chip 110 are wire-bonded via the wire BW. Is done.

The internal configuration of the digital control circuit chip 120 and the internal configuration of the passive circuit chip 110 are the same as those shown in the first embodiment.

Note that the digital control circuit chip 120 may be stacked on the passive circuit chip 110, contrary to the stacked structure shown in FIGS. 8A and 8B.

<< Third Embodiment >>
FIG. 10 is a circuit diagram of CTLE 11 of the high-speed serial signal equalizer according to the third embodiment. In the present embodiment, a variable resistance element is provided in addition to the variable capacitance element.

The CTLE 11 of this embodiment includes an amplifier circuit A1, variable resistance elements VR11 and VR12, resistance elements R21, R22, and R30, variable capacitance elements VC1 and VC2, and a capacitance element Co. The variable capacitance elements VC1, VC2, variable resistance elements VR11, VR12, and resistance elements R21, R22 constitute a high pass filter. Further, a low-pass filter is configured by the resistor element R30 and the capacitive element Co.

The amplifier circuit A1 differentially amplifies the differential signal input to the input terminals RXin + and RXin−, and outputs an unbalanced signal. When the resistance values of the variable resistance elements VR11 and VR12 are represented by R11 and R12, and the resistance values of the resistance elements R21 and R22 are represented by R21 and R22, respectively, R11 = R12 and R21 = R22, and the voltage amplification factor of the amplifier circuit A1 is , R21 / R11, R22 / R12. Unlike the CTLE 11 shown in FIG. 1 in the first embodiment, since the variable resistance elements VR11 and VR12 are provided, the voltage amplification factor can be controlled. The cutoff frequency of the high-pass filter is determined by the resistance values R11, R12, R21, R22 and the capacitances of the variable capacitance elements VC1, VC2.

FIG. 11 is a circuit diagram showing a connection relationship between the passive circuit chip 110 constituting the variable capacitance element VC1 and the variable resistance element VR11 and the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 connected thereto. .

The passive circuit chip 110 includes a plurality of capacitance elements C1, C2, C3, and C4 and a plurality of resistance elements R1, R2, and R3. The plurality of switches SW1, SW2, SW3, SW4, SW5, SW6, and SW7 switch combinations of the plurality of capacitive elements C1, C2, C3, and C4 and the plurality of resistance elements R1, R2, and R3. The same applies to the configuration and operation of the circuits constituting the variable capacitance element VC2 and variable resistance element VR12 shown in FIG.

<< Other embodiments >>
In the example shown in FIG. 4, two sets of the passive circuit chip 110 and the digital control circuit chip 120 are provided. However, the passive circuit chip 110 and the digital control circuit chip 120 are configured by one passive circuit chip and one digital control circuit chip. Is also possible. For example, in FIG. 4, a circuit portion (other than the passive element control circuit CNT) includes capacitive elements C1, C2, C3, C4, C5, C6, C7 and switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR. 2 sets of circuit portions), and the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR of the two sets of circuit portions may be controlled by the passive element control circuit CNT. Thus, the two variable capacitance elements VC1 and VC2 shown in FIG. 1 can be configured by a single passive circuit chip and a single digital control circuit chip.

Further, in the example shown in FIG. 4, the single capacitive element is selected from among the multiple capacitive elements. However, the present invention is not limited to this, and the multiple capacitive elements are selectively connected simultaneously. Also good. For example, an 8-bit shift register is formed, and the state of the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 is selected by the lower 7 bits of the output, and the output of the most significant bit is input to the AND gate AG1. You may comprise as follows.

In the example shown in FIG. 4, a variable capacitance element is configured by selecting a capacitance element by switching a plurality of switches. However, a thin film dielectric layer whose dielectric constant changes depending on an applied voltage is used, and a control voltage is set. Depending on the setting, a variable capacitance element in which the capacitance between the two terminals changes may be configured. In that case, a resistance voltage dividing circuit for setting the control voltage may be provided in accordance with the states of the plurality of switches shown in FIG.

In the example shown in FIG. 1, the variable filter circuit is provided with a capacitive element and a resistive element as passive elements, but an inductive element may be provided.

Finally, the description of the above embodiment is illustrative in all respects and not restrictive. Modifications and changes can be made as appropriate by those skilled in the art. The scope of the present invention is shown not by the above embodiments but by the claims. Furthermore, the scope of the present invention includes modifications from the embodiments within the scope equivalent to the claims.

A1... Amplifier circuits AG1, AG2, AG3... AND gate BW... Wire C1, C2, C3, C4, C5, C6, C7.
CLK: Clock terminal CNT: Passive element control circuit Co: Capacitance element
CS: Chip select terminals D1, D2, D3, D4 ... D type flip-flop
DATA ... Control data input terminal DMPX ... Demultiplexer P12 ... Pads R1, R2, R3 of the digital control circuit chip 120 ... Resistance elements R11, R12, R21, R22, R30 ... Resistance elements
RESET ... Reset terminal Rin ... Terminal resistor
RXin-, RXin +… input terminals
RXo: Output terminals S1, S2, S3, S4, S5, S6, S7, S8 ... Output signal SB ... Solder ball
SET: set terminals SW1, SW2, SW3, SW4, SW5, SW6, SW7, SWS, SWR ... switch T11 ... terminal T12 of passive circuit chip 110 ... terminals VC1, VC2 of digital control circuit chip 120 ... variable capacitance elements VR11, VR12 ... Variable resistance element 1 ... Adder 2 ... Sampler 3 ... CDR (Clock Data Recovery)
4 ... DFE (Decision Feedback Equalizer)
10 ... High-speed serial signal equalizer 11 ... CTLE (Continuous-Time Linear Equalizer)
12 ... DTLE (Discrete Time Linear Equalizer)
110: Passive circuit chip 120 ... Digital control circuit chip

Claims

Provided in the high-speed serial signal receiver, equipped with a filter to improve the frequency characteristics of the received signal,
The filter includes a variable filter circuit capable of switching frequency characteristics, and a control signal input unit that inputs a control signal for switching the frequency characteristics,
The variable filter circuit includes a plurality of passive elements, and a switch element that switches a connection state of the plurality of passive elements,
The plurality of passive elements are provided in a passive circuit chip in which a passive circuit is formed, and the switch element is provided in a digital control circuit chip.
High-speed serial signal equalizer.
The high-speed serial signal equalizer according to claim 1, wherein the passive circuit chip and the digital control circuit chip are stacked on a circuit board.
The high-speed serial signal equalizer according to claim 1 or 2, wherein the passive element is a capacitive element.
The high-speed serial signal equalizer according to claim 3, wherein the capacitive element is a thin film capacitor including a ferroelectric thin film and a pair of electrode films facing each other with the ferroelectric thin film interposed therebetween.
The digital control circuit chip is:
A demultiplexer for determining the state of the switch element by an output signal;
A register that gives a plurality of bits of data to the input of the demultiplexer, inputs control data from a control data input unit, and sets the control data;
The high-speed serial signal equalizer according to claim 1, comprising:
The variable filter circuit is:
An amplifier circuit;
A high-pass filter circuit connected to the input section of the amplifier circuit and including a variable capacitance element and a resistance element;
6. The high-speed serial signal equalizer according to claim 1, further comprising: a low-pass filter circuit that is connected to an output unit of the amplification circuit and includes a resistance element and a capacitance element.
The high-speed serial signal equalizer according to any one of claims 1 to 6, further comprising a digital feedback equalizer connected to a subsequent stage of the variable filter circuit.
A high-speed serial interface comprising: the high-speed serial signal equalizer according to any one of claims 1 to 7; and a differential line to which the high-speed serial signal equalizer is connected.