WO2018054078A1 - 一种直流恒压变换电路及方法 - Google Patents

一种直流恒压变换电路及方法 Download PDF

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Publication number
WO2018054078A1
WO2018054078A1 PCT/CN2017/085231 CN2017085231W WO2018054078A1 WO 2018054078 A1 WO2018054078 A1 WO 2018054078A1 CN 2017085231 W CN2017085231 W CN 2017085231W WO 2018054078 A1 WO2018054078 A1 WO 2018054078A1
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Prior art keywords
circuit
signal
voltage
switch
logic
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PCT/CN2017/085231
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English (en)
French (fr)
Inventor
葛亮
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深圳市中兴微电子技术有限公司
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Publication of WO2018054078A1 publication Critical patent/WO2018054078A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Definitions

  • Embodiments of the present invention relate to switching power supply technologies in the field of integrated circuits, and in particular, to a DC constant voltage conversion circuit and method.
  • the power source is the source of the electronic equipment.
  • the DC/DC converter has a driving chip inside, and realizes a function of DC constant voltage voltage conversion by using a feedback circuit inside the driving chip and a combination of an inductor and a capacitor external to the driving chip.
  • the output voltage is divided by a voltage dividing resistor external to the driving chip, and the divided voltage is transmitted to the inside of the driving chip to generate a pulse frequency modulation ( PFM, Pulse Frequency Modulation) signal.
  • PFM Pulse Frequency Modulation
  • the sampling circuit inside the driving chip collects the divided voltage signal and sends the sampled voltage signal to the error amplifier, and the error amplifier and the clock generating circuit combine to generate a PFM signal, thereby controlling the logic control and the driving circuit to generate a constant voltage. Voltage.
  • the clock generation circuit needs to be specially designed for timing. Special considerations, and the design accuracy directly affects the accuracy of the PFM signal, resulting in increased cost and design difficulty of the driver chip. At the same time, the voltage divider resistor outside the driver chip reduces the integration of the system and increases the cost of the system.
  • the embodiment of the present invention is expected to provide a DC constant voltage conversion circuit and method, which can reduce the cost and design difficulty of the driving chip, improve the integration degree of the system, and reduce the cost of the system.
  • Embodiments of the present invention provide a DC constant voltage conversion circuit, including:
  • a voltage generating circuit connected to the logic control and driving circuit
  • a detection circuit connected to the logic control and driving circuit, the voltage generating circuit and a power source;
  • a signal generating circuit connected to the logic control and driving circuit and the voltage generating circuit
  • the signal generating circuit is configured to convert a previous charge and discharge voltage to generate a first modulated signal
  • the detecting circuit is configured to detect a voltage value of the power source and a current value of the voltage generating circuit, and generate a first logic signal according to the voltage value and the current value;
  • the logic control and driving circuit is configured to change a state of the charge and discharge switch according to the first logic signal and the first modulation signal;
  • the charge and discharge switch includes a first switch and a second switch in different states, configured to control the voltage generating circuit to perform a charging and discharging operation;
  • the voltage generating circuit is configured to perform a charging and discharging operation according to states of the first switch and the second switch, and output a current charging and discharging voltage for use in a next charging and discharging operation.
  • the logic control and driving circuit includes: a trigger circuit connected to the signal generating circuit and the detecting circuit, and a first driving circuit connected to the trigger circuit and the voltage generating circuit ;
  • the trigger circuit is configured to generate a second logic signal according to the first logic signal and the first modulation signal, and output the second logic signal to the first driving circuit;
  • the first driving circuit is configured to control states of the first switch and the second switch according to the second logic signal.
  • the signal generating circuit includes: a ramp generating circuit and a first comparing circuit; the ramp generating circuit is coupled to the voltage generating circuit and the first comparing circuit; and the first comparing circuit Connected to the trigger circuit;
  • the ramp generating circuit is configured to perform a charging and discharging operation according to the previous charging and discharging voltage to generate a ramp signal;
  • the first comparison circuit is configured to compare the ramp signal with a preset reference voltage to output the first modulation signal.
  • the detecting circuit includes: a power-on detecting circuit, a current limiting protection circuit, and a demagnetization detecting circuit; the power-on detecting circuit is connected to the power source and the trigger circuit; and the current limiting protection a circuit and a demagnetization detecting circuit are connected to the trigger circuit and the voltage generating circuit;
  • the power-on detection circuit is configured to detect a voltage value of the power source, determine a third logic signal according to the voltage value, and output the third logic signal to the trigger circuit, where the third logic signal is a logic signal generated by the power-on detection circuit in the first logic signal;
  • the current limiting protection circuit is configured to detect an upper limit current value of the voltage generating circuit, determine a fourth logic signal according to the upper limit current value, and output the fourth logic signal to the a trigger circuit, wherein the fourth logic signal is a logic signal generated by the current limiting protection circuit in the first logic signal;
  • the demagnetization detecting circuit is configured to detect a lower limit current value of the voltage generating circuit, determine a fifth logic signal according to the lower limit current value, and output the fifth logic signal to the trigger circuit, the fifth The logic signal is a logic signal generated by the demagnetization detecting circuit in the first logic signal.
  • the voltage generating circuit is composed of an inductor and a first capacitor, and the first end of the inductor is connected to the charge and discharge switch, the current limiting protection circuit, and the demagnetization protection circuit.
  • the second end of the inductor is connected to the first end of the first capacitor and the ramp generating circuit, the first end of the first capacitor is connected to the ramp generating circuit, and the second end of the first capacitor Connected to the second switch and the ground.
  • the ramp generating circuit is comprised of a second capacitor, a resistor, a current source, and a third switch, the first end of the second capacitor being coupled to the first end of the first capacitor and the a second end of the inductor is connected, and a second end of the second capacitor is connected to the first end of the current source, the first comparison circuit and the third switch, and the first end of the third switch is
  • the current source is coupled to the first driving circuit
  • the second end of the third switch is coupled to the first end of the resistor
  • the second end of the resistor is coupled to the first end of the first capacitor The second end of the inductor is connected.
  • the trigger circuit is composed of a first-level judging circuit, a second-level or a gate circuit, and a three-level trigger circuit;
  • the first level determining circuit includes a first OR gate circuit and a first oscillating circuit
  • the first OR gate circuit is configured to output the first operation signal after the input first modulation signal and the fifth logic signal are ORed;
  • the first oscillating circuit is configured to output the first oscillating signal after oscillating the input third logic signal
  • the secondary OR gate circuit is configured to output a second operation signal after the input first operation signal and the first oscillation signal are ORed;
  • the three-stage trigger circuit is configured to output the first trigger signal to the first driving circuit after the input fourth logic signal and the second operation signal pass the trigger determination;
  • the first driving circuit is configured to output a first control signal and a second control signal according to the input first trigger signal to control a state of the charge and discharge switch.
  • the charge and discharge switch is configured to control the first switch and the second switch to perform an on-off operation according to the first control signal and the second control signal, A switch performs an opposite on/off operation with the second switch.
  • the embodiment of the invention provides a DC constant voltage transformation method, which comprises:
  • the charging and discharging operations on the input voltage according to the comparison result include:
  • the method further includes:
  • the next charging and discharging process is entered, and the current charging and discharging voltage is used as the voltage to be compared with the preset reference voltage for the next time.
  • Embodiments of the present invention provide a DC constant voltage conversion circuit and method, wherein a logic control and driving circuit, a voltage generating circuit connected to the logic control and driving circuit, and the logic control and driving circuit, the voltage generating circuit and Detection circuit for power connection, and with the logic control And a signal generating circuit connected to the driving circuit and the voltage generating circuit; wherein the signal generating circuit is configured to convert the previous charging and discharging voltage to generate a first modulation signal; and the detecting circuit is configured to detect the voltage value and voltage of the power source Generating a current value of the circuit, and generating a first logic signal according to the voltage value and the current value; and a logic control and driving circuit configured to change a state of the charge and discharge switch according to the first logic signal and the first modulation signal, the charge and discharge switch The first switch and the second switch are in different states; the voltage generating circuit is configured to perform a charging and discharging operation according to the states of the first switch and the second switch, and output a current charging and dis
  • the PFM signal is generated by the signal generating circuit composed of the ramp generating circuit and the first comparing circuit, thereby replacing the clock generating circuit and the sample and hold circuit, special considerations for timing are reduced, and the driving chip may not be driven.
  • the externally increase the voltage dividing resistor therefore, can reduce the cost and design difficulty of the driving chip, improve the integration of the system, and reduce the cost of the system.
  • FIG. 1 is a schematic block diagram 1 of a DC constant voltage conversion circuit according to an embodiment of the present invention
  • FIG. 2 is a schematic block diagram 2 of a DC constant voltage conversion circuit according to an embodiment of the present invention
  • FIG. 3 is a schematic block diagram 3 of a DC constant voltage conversion circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic block diagram 4 of a DC constant voltage conversion circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic circuit diagram of a voltage generating circuit of a DC constant voltage conversion circuit according to an embodiment of the present invention
  • FIG. 6 is a schematic circuit diagram of a ramp generating circuit of a DC constant voltage converting circuit according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of a corresponding relationship between a first control signal and a ramp signal in a DC constant voltage conversion circuit according to an embodiment of the present disclosure
  • FIG. 8 is a schematic circuit diagram of a logic control and a driving circuit of a DC constant voltage conversion circuit according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of a DC constant voltage conversion method according to an embodiment of the present invention.
  • an embodiment of the present invention provides a DC constant voltage conversion circuit 1 , which may include:
  • a voltage generating circuit 11 connected to the logic control and driving circuit 10;
  • a detection circuit 12 connected to the logic control and driving circuit 10, the voltage generating circuit 11 and a power source;
  • a signal generating circuit 13 connected to the logic control and driving circuit 10 and the voltage generating circuit 11;
  • the signal generating circuit 13 is configured to convert the previous charge and discharge voltage to generate a first modulated signal.
  • the detecting circuit 12 is configured to detect a voltage value of the power source and a current value of the voltage generating circuit, and generate a first logic signal according to the voltage value and the current value.
  • the logic control and drive circuit 10 is configured to change the state of the charge and discharge switch 14 according to the first logic signal and the first modulation signal.
  • the charge and discharge switch 14 includes a first switch 140 and a second switch 141 in different states, and is configured to control the voltage generating circuit 11 to perform a charge and discharge operation.
  • the voltage generating circuit 11 is configured to perform a charge and discharge operation according to the states of the first switch 140 and the second switch 141, and output a current charge and discharge voltage for use in the next charge and discharge operation.
  • the power supply voltage in the embodiment of the present invention is a direct current voltage.
  • the logic control circuit 10, the detection circuit 12 and the signal generation circuit 13 are integrated on the driving chip, and the voltage generating circuit 11 is a circuit distribution outside the driving chip.
  • the first switch 140 is closed, and when the second switch 141 is turned off, the voltage generating circuit 11 performs a charging operation; the second switch 141 is closed, and when the first switch 140 is turned off, the voltage generating circuit 11 performs a discharging operation.
  • the current charge and discharge voltage outputted by the voltage generating circuit 11 is used as the input voltage of the signal generating circuit 13 to generate the next first modulated signal.
  • the logic control and driving circuit 10 includes: a trigger circuit 100 connected to the signal generating circuit 13 and the detecting circuit 12, and the trigger circuit 100 The first drive circuit 101 to which the voltage generating circuit 11 is connected.
  • the trigger circuit 100 is configured to generate a second logic signal according to the first logic signal and the first modulation signal, and output the second logic signal to the first driving circuit 101.
  • the first driving circuit 101 is configured to control states of the first switch 140 and the second switch 141 according to the second logic signal.
  • the signal generating circuit 13 includes: a ramp generating circuit 130 and a first comparing circuit 131; the ramp generating circuit 130 and the voltage generating circuit 11, the first A comparison circuit 131 is connected; the first comparison circuit 131 is connected to the trigger circuit 100.
  • the ramp generating circuit 130 is configured to perform a charging and discharging operation according to the previous charging and discharging voltage to generate a ramp signal.
  • the first comparison circuit 131 is configured to compare the ramp signal with a preset reference voltage and output the first modulation signal.
  • the current charge and discharge voltage outputted by the voltage generating circuit 11 is used as an input of the ramp generating circuit 130 to generate a ramp signal.
  • the first comparison circuit 131 in the embodiment of the present invention may be a device or circuit that can perform a comparison operation, such as a hysteresis comparator.
  • the preset reference voltage of the first comparison circuit 131 has an error range.
  • the first comparison circuit 131 outputs the original digital signal; when the ramp signal does not exist
  • the first comparison circuit 131 outputs a digital signal opposite to the original digital signal, thereby generating the first modulated signal.
  • the first modulated signal is a PFM signal.
  • the reference voltage VREF of the hysteresis comparator is 5V, and the error range is ⁇ 0.2v
  • the hysteresis comparator The low level signal is output; when the voltage signal generated by the ramp generating circuit 130 is 4.9V, the hysteresis comparator outputs a high level signal.
  • the detecting circuit 12 includes: a power-on detecting circuit 120, a current limiting protection circuit 121, and a demagnetization detecting circuit 122; the power-on detecting circuit 120 and the power source, The trigger circuit 100 is connected; the current limiting protection circuit 121 and the demagnetization detecting circuit 122 are connected to the trigger circuit 100 and the voltage generating circuit 11.
  • the power-on detection circuit 120 is configured to detect a voltage value of the power source, determine a third logic signal according to the voltage value, and output the third logic signal to the trigger circuit 100, the third logic The signal is a logic signal generated by the power-on detection circuit 120 in the first logic signal.
  • the current limiting protection circuit 121 is configured to detect an upper limit current value of the voltage generating circuit 11, determine a fourth logic signal according to the upper limit current value, and output the fourth logic signal to the trigger circuit 100,
  • the fourth logic signal is a logic signal generated by the current limiting protection circuit 121 in the first logic signal.
  • the demagnetization detecting circuit 122 is configured to detect a lower limit current of the voltage generating circuit 11 a value, determining a fifth logic signal according to the lower limit current value, and outputting the fifth logic signal to the trigger circuit 100, wherein the fifth logic signal is the demagnetization detecting circuit in the first logic signal 122 generated logic signal.
  • the power supply voltage value is preset in the driving chip.
  • the driving chip When the driving chip is connected to the power source and the voltage value of the power source reaches the preset power voltage value, it indicates that the driving chip is powered on and generates a power-on completion signal.
  • the power-on detection circuit 120 detects the power-on completion signal, and inputs the power-on completion signal to the logic control and drive circuit 10, and the logic control and drive circuit 10 generates the first conduction.
  • the signal, the first turn-on signal causes the first switch 140 to be closed, the second switch 141 to be turned off, thereby controlling the voltage generating circuit 11 to perform a charging operation, and the current limiting circuit 121 and the demagnetization detecting circuit 122 apply current to the voltage generating circuit 11. The value is detected.
  • the current limiting protection circuit 121 When the current value on the voltage generating circuit 11 reaches the limit current defined by the current limiting protection circuit 121, the current limiting protection circuit 121 outputs a current limiting signal to the logic control and driving circuit 10, and the logic control and driving circuit at this time 10 generating a first closing signal, the first closing signal causes the first switch 140 to be opened, and the second switch 141 is closed, thereby controlling the voltage generating circuit 11 to perform a discharging operation, when the current value on the voltage generating circuit 11 is 0,
  • the demagnetization detecting circuit 122 detects the demagnetization completion waveform generated by the voltage generating circuit 11, and outputs a demagnetization completion signal to the logic control and driving circuit 10, at this time logic System and a driving circuit 10 generates a second on-signal, the second pilot signal so that the first switch 140 is closed, the second switch 141 is turned off, the voltage generating circuit 11 so as to control the charging operation.
  • the voltage generating circuit 11 is composed of an inductor 110 and a first capacitor 111.
  • the first end of the inductor 110 and the charge and discharge switch 14, the current limiting The protection circuit 121 is connected to the demagnetization protection circuit 122.
  • the second end of the inductor 110 is connected to the first end of the first capacitor 111 and the ramp generating circuit 130.
  • the first end of the first capacitor 111 Connected to the ramp generating circuit 130, the second end of the first capacitor 111 is connected to the second switch and the ground.
  • the demagnetization detecting circuit 122 and the current limiting protection circuit 121 detect the current value of the inductance on the voltage generating circuit.
  • the ramp generating circuit 130 is composed of a second capacitor 1300, a resistor 1301, a current source 1302, and a third switch 1303.
  • the first end of the second capacitor 1300 is The first end of the first capacitor 111 is connected to the second end of the inductor 110, the second end of the second capacitor 1300 is opposite to the current source 1302, the first comparison circuit 131, and the third a first end of the switch 1303 is connected, a first end of the third switch 1303 is connected to the current source 1302 and the first driving circuit 101, a second end of the third switch 1303 is connected to the resistor 1301 The first end is connected, and the second end of the resistor 1301 is connected to the first end of the first capacitor 111 and the second end of the inductor 110.
  • the first control signal is at a low level
  • the third switch 1303 is turned off, and the current source 1302 performs a charging operation on the second capacitor 1300, and the ramp generating circuit 130
  • the output voltage gradually rises.
  • the first control signal transitions from a low level to a high level
  • the output voltage of 130 reaches a high threshold
  • the first control signal is at a high level
  • the third switch When closed, the second capacitor 1300 is discharged through the resistor 1301, and the output voltage of the ramp generating circuit 130 gradually decreases.
  • the first control signal transitions from a high level to a low level
  • the output voltage of the 130 drops to a low threshold, that is, a ramp signal is generated ( 130 output voltage).
  • the trigger circuit 100 is composed of a first-level judging circuit 1001, a two-level OR gate circuit 1002, and a three-level flip-flop circuit 1003;
  • the first level determining circuit 1001 includes a first OR gate circuit 10010 and a first oscillating circuit 10011.
  • the first OR circuit 10010 is configured to output a first operation signal after the input first modulation signal and the fifth logic signal are ORed.
  • the first oscillating circuit 10011 is configured to output the first oscillating signal after oscillating the input third logic signal.
  • the secondary OR gate circuit 1002 is configured to output a second operational signal after the input first operational signal and the first oscillation signal are ORed.
  • the three-stage trigger circuit 1003 is configured to output a first trigger signal to the first driving circuit 101 after the input fourth logic signal and the second operation signal pass the trigger determination.
  • the first driving circuit 101 is configured to output a first control signal and a second control signal according to the input first trigger signal to control a state of the charging and discharging switch.
  • the first oscillating circuit 10011 may be a monostable multi-resonant oscillator, and the first oscillating signal outputted through the monostable multi-resonant oscillator is a pulse signal.
  • the three-level trigger circuit 1003 may be a set reset (SR, SetReset) flip-flop.
  • the secondary OR circuit 1002 is connected to the set terminal of the SR flip-flop, and the current limiting protection circuit 121 is connected to the reset end of the SR flip-flop.
  • the reset end When the set end of the SR flip-flop is high level, the reset end is When low, the SR flip-flop outputs a high level.
  • the set terminal of the SR flip-flop is low and the reset terminal is high, the SR flip-flop outputs a low level.
  • the power-on detection circuit 120 detects the power-on completion signal, so that the third logic signal is low level. Jumping to a high level, the third logic signal is converted into a high-level pulse signal input to the secondary or gate circuit through the monostable multi-resonant oscillator, and the secondary or gate circuit outputs a high level, then the SR flip-flop The set terminal is at a high level.
  • the inductor current value does not reach the limit current of the current limiting protection circuit 121, so the fourth logic signal is at a low level, and the SR flip-flop is reset.
  • the SR flip-flop outputs a high level, and after the first driving circuit 101 receives the first trigger signal to a high level, the first switch 140 is controlled to be closed, and the second switch 141 is turned off.
  • the fourth logic signal output by the current limiting protection circuit 121 is changed from a low level to a high level, and the SR flip-flop is reset.
  • the terminal is at a high level.
  • the fifth logic signal is at a low level. Since the voltage generating circuit 11 is in a charging state at this time, the first trigger signal is at a high level, and As shown in FIG. 7, when the first trigger signal is at a high level, the output voltage of the control ramp generating circuit 130 gradually decreases.
  • the first gate circuit 10010 After the hysteresis comparator passes the first modulation signal to a low level, the first gate circuit 10010 outputs the first An operation signal is at a low level. At this time, the first oscillating signal returns to a low level, and both inputs of the two-level OR gate circuit 1002 are at a low level, so the SR flip-flop outputs a low level, the first driving circuit After receiving the first trigger signal to a low level, the first switch 140 is controlled to be turned off, and the second switch 141 is closed.
  • the charge and discharge switch is configured to control the first switch 140 and the second switch 141 to perform an on-off operation according to the first control signal and the second control signal,
  • the first switch 140 and the second switch 141 perform opposite on and off operations.
  • An embodiment of the present invention provides a DC constant voltage conversion method. As shown in FIG. 9, the method may include:
  • S104 Perform a discharging operation when the last charge and discharge voltage is greater than a preset reference voltage.
  • the current charging/discharging voltage is cyclically acquired as the charging/discharging voltage to be compared with the preset reference voltage for the next time, and the flow of S101-S106 is performed.
  • the voltage generation circuit generates the last charge and discharge voltage, and compares the previous charge and discharge voltage with a preset reference voltage to control the voltage generation.
  • the operation of the circuit when the last charge and discharge voltage is less than or equal to the preset reference voltage, the voltage generating circuit performs a charging operation.
  • the voltage generating circuit When the last charge and discharge voltage difference is greater than the preset reference voltage, the voltage generating circuit performs a discharging operation, thereby generating a current charge.
  • the discharge voltage that is, the previous charge and discharge voltage is obtained, and the current charge and discharge voltage is generated based on the charge and discharge operation of the voltage control circuit of the last charge and discharge voltage.
  • the embodiment of the invention can be implemented by a DC constant voltage conversion circuit.
  • the power-on detection circuit 120 detects the power-on completion signal, and inputs the power-on completion signal to the logic control and drive circuit 10, and the logic control and drive circuit 10 generates the first derivative.
  • the pass signal, the first turn-on signal causes the first switch 140 to be closed, the second switch 141 to be turned off, thereby controlling the voltage generating circuit 11 to perform a charging operation, and the current limiting protection circuit 121 and the demagnetization detecting circuit 122 are applied to the voltage generating circuit 11 The current value is detected.
  • the current limiting protection circuit 121 When the current value on the voltage generating circuit 11 reaches the limit current defined by the current limiting protection circuit 121, the current limiting protection circuit 121 outputs a current limiting signal to the logic control and driving circuit 10, and at this time, the logic control and driving The circuit 10 generates a first closing signal, the first closing signal causes the first switch 140 to open, and the second switch 141 to close, thereby controlling the voltage generating circuit 11 to perform a discharging operation when the current value on the voltage generating circuit 11 is zero.
  • the demagnetization detecting circuit 122 detects the demagnetization completion waveform generated by the voltage generating circuit 11, and outputs a demagnetization completion signal to the logic control and driving circuit 10, Series of control and drive circuit 10 generates a second on-signal, the second pilot signal so that the first switch 140 is closed, the second switch 141 is turned off, the voltage generating circuit 11 so as to control the charging operation.
  • the power-on detection circuit 120 detects the power-on completion signal, so that the third logic signal is low-powered.
  • the flat jump becomes a high level, and the third logic signal is jumped through the monostable multi-resonant oscillator into For a high-level pulse signal input to the secondary or gate circuit, the secondary or gate circuit outputs a high level, then the set terminal of the SR flip-flop is at a high level, since the voltage generating circuit 11 is in a state of being charged, the inductor The current value does not reach the limit current of the current limiting protection circuit 121, so the fourth logic signal is low level, then the reset end of the SR flip-flop is low level, then the SR flip-flop outputs a high level, and the first driving circuit 101 receives After the first trigger signal is at a high level, the first switch 140 is controlled to be closed, and the second switch 141 is turned off.
  • the fourth logic signal output by the current limiting protection circuit 121 transitions from a low level to a high level, and the reset end of the SR flip-flop is at a high level, and Since the inductor current value is not 0, the fifth logic signal is at a low level. Since the voltage generating circuit 11 is in a charged state at this time, the first trigger signal is at a high level, and as shown in FIG. 7, the first trigger When the signal is high, the output voltage of the control ramp generating electric 130 gradually decreases. After the hysteresis comparator, the first modulation signal is low, and the first operational signal output by the first OR circuit 10010 is low.
  • the first oscillating signal returns to a low level, and both inputs of the two-level OR circuit 1002 are at a low level, so the SR flip-flop outputs a low level, and the first driving circuit 101 receives the first trigger signal.
  • the first switch 140 is controlled to open and the second switch 141 is closed.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the PFM signal is generated by the signal generating circuit composed of the ramp generating circuit and the first comparing circuit, thereby replacing the clock generating circuit and the sample-and-hold circuit, special considerations for timing are reduced, and may not be outside the driving chip.
  • the voltage dividing resistor is increased, so that the cost and design difficulty of the driving chip can be reduced, the integration degree of the system is improved, and the cost of the system is reduced.

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Abstract

一种直流恒压变换电路（1）和方法，该电路包括：逻辑控制及驱动电路（10）；与逻辑控制及驱动电路连接的电压产生电路（11）和检测电路（12），检测电路与电压产生电路和电源连接；以及与逻辑控制及驱动电路和电压产生电路分别连接的信号产生电路（13）和充放电开关（14）。信号产生电路，配置为对前一次充放电电压进行转换，生成第一调制信号；检测电路，配置为检测电源的电压值和电压产生电路的电流值，并根据电压值和电流值生成第一逻辑信号；逻辑控制及驱动电路，配置为根据第一逻辑信号和第一调制信号更改充放电开关的状态；充放电开关，配置为控制电压产生电路进行充放电操作；电压产生电路，配置为根据充放电开关的状态进行充放电操作，并输出当前充放电电压。

Description

一种直流恒压变换电路及方法
相关申请的交叉引用
本申请基于申请号为201610844467.3、申请日为2016年09月22日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明实施例涉及集成电路领域的开关电源技术，尤其涉及一种直流恒压变换电路及方法。
背景技术
电源是电子设备的源动力，随着电子设备功能越来越多样化，其系统线路也越来越复杂，导致了电子设备对电源的要求也越来越高。为了将电能质量较差的直流电压转换为满足设备要求的质量较高的直流电压，直流电压(DC/DC，Direct Current/Direct Current)转换器应运而生。DC/DC转换器内部有驱动芯片，利用驱动芯片内部的反馈电路和驱动芯片外部的电感、电容的组合，实现直流恒压电压转换的功能。
DC/DC转换器对输入电压利用电感和电容进行充放电之后，将输出电压利用驱动芯片外部的分压电阻进行分压，将分压后的电压传输至驱动芯片的内部来生成脉冲频率调制(PFM，Pulse Frequency Modulation)信号。其中，驱动芯片内部的采样电路对接收到分压电压进行采样之后，将采样到的电压信号传送至误差放大器，误差放大器与时钟产生电路结合生成PFM信号，从而控制逻辑控制及驱动电路产生恒压电压。
然而，采用上述实现方案中，时钟产生电路需要在设计时对时序做特 殊考虑，且设计精度直接影响了PFM信号的精度，导致驱动芯片的成本和设计难度增加，同时，驱动芯片外部的分压电阻使得系统的集成度降低，增加了系统的成本。
发明内容
为解决上述技术问题，本发明实施例期望提供一种直流恒压变换电路及方法，能够降低驱动芯片的成本和设计难度，提升了系统的集成度，减少系统的成本。
本发明实施例的技术方案是这样实现的：
本发明实施例提供一种直流恒压变换电路，包括：
逻辑控制及驱动电路；
与所述逻辑控制及驱动电路连接的电压产生电路；
与所述逻辑控制及驱动电路、所述电压产生电路和电源连接的检测电路；
与所述逻辑控制及驱动电路和所述电压产生电路连接的信号产生电路；
以及与所述逻辑控制及驱动电路和所述电压产生电路连接的充放电开关；其中，
所述信号产生电路，配置为对前一次充放电电压进行转换，生成第一调制信号；
所述检测电路，配置为检测所述电源的电压值和所述电压产生电路的电流值，并根据所述电压值和所述电流值生成第一逻辑信号；
所述逻辑控制及驱动电路，配置为根据所述第一逻辑信号和所述第一调制信号更改充放电开关的状态；
所述充放电开关，包括处于不同状态的第一开关和第二开关，配置为控制所述电压产生电路进行充放电操作；
所述电压产生电路，配置为根据所述第一开关和所述第二开关的状态进行充放电操作，并输出当前充放电电压，以供下一次充放电操作使用。
在发明的其他实施例中，所述逻辑控制及驱动电路包括：与所述信号产生电路和所述检测电路连接的触发电路、与所述触发电路和所述电压产生电路连接的第一驱动电路；
所述触发电路，配置为根据所述第一逻辑信号和所述第一调制信号生成第二逻辑信号，并将所述第二逻辑信号输出至所述第一驱动电路；
所述第一驱动电路，配置为根据所述第二逻辑信号控制所述第一开关和所述第二开关的状态。
在发明的其他实施例中，所述信号产生电路包括：斜坡产生电路和第一比较电路；所述斜坡产生电路与所述电压产生电路、所述第一比较电路连接；所述第一比较电路与所述触发电路连接；
所述斜坡产生电路，配置为根据所述前一次充放电电压执行充放电的操作，生成斜坡信号；
所述第一比较电路，配置为将所述斜坡信号与预设基准电压进行比较，输出所述第一调制信号。
在发明的其他实施例中，所述检测电路包括：上电检测电路、限流保护电路和退磁检测电路；所述上电检测电路与所述电源、所述触发电路连接；所述限流保护电路和退磁检测电路与所述触发电路、所述电压产生电路连接；
所述上电检测电路，配置为检测所述电源的电压值，根据所述电压值确定第三逻辑信号，并将所述第三逻辑信号输出至所述触发电路，所述第三逻辑信号为所述第一逻辑信号中由所述上电检测电路产生的逻辑信号；
所述限流保护电路，配置为检测所述电压产生电路的上限电流值，根据所述上限电流值确定第四逻辑信号，并将所述第四逻辑信号输出至所述 触发电路，所述第四逻辑信号为所述第一逻辑信号中由所述限流保护电路产生的逻辑信号；
所述退磁检测电路，配置为检测所述电压产生电路的下限电流值，根据所述下限电流值确定第五逻辑信号，并将所述第五逻辑信号输出至所述触发电路，所述第五逻辑信号为所述第一逻辑信号中由所述退磁检测电路产生的逻辑信号。
在发明的其他实施例中，所述电压产生电路由电感和第一电容组成，所述电感的第一端与所述充放电开关、所述限流保护电路和所述退磁保护电路连接，所述电感的第二端与所述第一电容的第一端和所述斜坡产生电路连接，所述第一电容的第一端与所述斜坡产生电路连接，所述第一电容的第二端与所述第二开关和接地端连接。
在发明的其他实施例中，所述斜坡产生电路由第二电容、电阻、电流源和第三开关组成，所述第二电容的第一端与所述第一电容的第一端和所述电感的第二端连接、所述第二电容的第二端与所述电流源、所述第一比较电路和所述第三开关的第一端连接，所述第三开关的第一端与所述电流源和所述第一驱动电路连接、所述第三开关的第二端与所述电阻的第一端连接，所述电阻的第二端与所述第一电容的第一端和所述电感的第二端连接。
在发明的其他实施例中，所述触发电路由一级判断电路、二级或门电路和三级触发电路构成；其中，
所述一级判断电路包括第一或门电路和第一震荡电路；
所述第一或门电路，配置为将输入的所述第一调制信号和所述第五逻辑信号经过或运算后，输出第一运算信号；
所述第一振荡电路，配置为将输入的所述第三逻辑信号经过振荡后，输出第一振荡信号；
所述二级或门电路，配置为将输入的所述第一运算信号和所述第一震荡信号经过或运算后，输出第二运算信号；
所述三级触发电路，配置为将输入的所述第四逻辑信号和所述第二运算信号经过触发判定后，输出第一触发信号至所述第一驱动电路；
所述第一驱动电路，配置为根据输入的所述第一触发信号，输出第一控制信号和第二控制信号，以控制所述充放电开关的状态。
在发明的其他实施例中，所述充放电开关，配置为根据所述第一控制信号和所述第二控制信号控制所述第一开关和所述第二开关执行通断操作，所述第一开关与所述第二开关执行相反的通断操作。
本发明实施例提供一种直流恒压变换方法，其中，包括：
获取上一次充放电电压；
将所述上一次充放电电压与预设基准电压进行比较；
根据所述比较结果对电源电压执行相应的充放电操作，生成当前充放电电压，以供下一次获取使用。
在发明的其他实施例中，所述根据所述比较结果对输入电压进行相应的充放电操作，包括：
当所述上一次充放电电压小于等于所述预设基准电压时，进行充电操作；
当所述上一次充放电电压大于所述预设基准电压时，进行放电操作。
在上述方案中，所述生成当前充放电电压之后，所述方法还包括：
进入下一次充放电流程，将所述当前充放电电压作为下一次与所述预设基准电压比较的电压。
本发明实施例提供了一种直流恒压变换电路及方法，其中，逻辑控制及驱动电路、与该逻辑控制及驱动电路连接的电压产生电路、与该逻辑控制及驱动电路、该电压产生电路和电源连接的检测电路、以及与该逻辑控 制及驱动电路和该电压产生电路连接的信号产生电路；其中，信号产生电路，配置为对前一次充放电电压进行转换，生成第一调制信号；检测电路，配置为检测电源的电压值和电压产生电路的电流值，并根据该电压值和该电流值生成第一逻辑信号；逻辑控制及驱动电路，配置为根据第一逻辑信号和第一调制信号更改充放电开关的状态，该充放电开关包括处于不同状态的第一开关和第二开关；电压产生电路，配置为根据第一开关和第二开关的状态进行充放电操作，并输出当前充放电电压，以供下一次充放电操作使用。采用上述技术实现方案，由于通过斜坡产生电路和第一比较电路组成的信号产生电路来生成PFM信号，从而代替了时钟产生电路和采样保持电路，减少了对时序的特殊考虑，且可以不在驱动芯片外部增加分压电阻，因此，能够降低驱动芯片的成本和设计难度，提升系统的集成度，减少系统的成本。
附图说明
图1为本发明实施例提供的一种直流恒压变换电路的结构示意框图一；
图2为本发明实施例提供的一种直流恒压变换电路的结构示意框图二；
图3为本发明实施例提供的一种直流恒压变换电路的结构示意框图三；
图4为本发明实施例提供的一种直流恒压变换电路的结构示意框图四；
图5为本发明实施例提供的一种直流恒压变换电路的电压产生电路的电路示意图；
图6为本发明实施例提供的一种直流恒压变换电路的斜坡产生电路的电路示意图；
图7为本发明实施例提供的一种直流恒压变换电路中的第一控制信号与斜坡信号的对应关系示意图；
图8为本发明实施例提供的一种直流恒压变换电路的逻辑控制及驱动电路的电路示意图；
图9为本发明实施例提供的一种直流恒压变换方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
如图1所示，本发明实施例提供了一种直流恒压变换电路1，该直流恒压变换电路1可以包括：
逻辑控制及驱动电路10；
与所述逻辑控制及驱动电路10连接的电压产生电路11；
与所述逻辑控制及驱动电路10、所述电压产生电路11和电源连接的检测电路12；
与所述逻辑控制及驱动电路10和所述电压产生电路11连接的信号产生电路13；
以及与所述逻辑控制及驱动电路10和所述电压产生电路11连接的充放电开关14；其中，
所述信号产生电路13，配置为对前一次充放电电压进行转换，生成第一调制信号。
所述检测电路12，配置为检测所述电源的电压值和所述电压产生电路的电流值，并根据所述电压值和所述电流值生成第一逻辑信号。
所述逻辑控制及驱动电路10，配置为根据所述第一逻辑信号和所述第一调制信号更改充放电开关14的状态。
所述充放电开关14，包括处于不同状态的第一开关140和第二开关141，配置为控制所述电压产生电路11进行充放电操作。
所述电压产生电路11，配置为根据所述第一开关140和所述第二开关141的状态进行充放电操作，并输出当前充放电电压，以供下一次充放电操作使用。
需要说明的是，本发明实施例中的电源电压为直流电压。
本发明实施例中，逻辑控制电路10、检测电路12和信号产生电路13是集成在驱动芯片上的，电压产生电路11是驱动芯片外部的电路分布。
示例性地，第一开关140闭合，第二开关141断开时，电压产生电路11进行充电操作；第二开关141闭合，第一开关140断开时，电压产生电路11进行放电操作。
本发明实施例中，电压产生电路11输出的当前充放电电压作为信号产生电路13的输入电压来生成下一次的第一调制信号。
在发明的其他实施例中，如图2所示，所述逻辑控制及驱动电路10包括：与所述信号产生电路13和所述检测电路12连接的触发电路100、与所述触发电路100和所述电压产生电路11连接的第一驱动电路101。
所述触发电路100，配置为根据所述第一逻辑信号和所述第一调制信号生成第二逻辑信号，并将所述第二逻辑信号输出至所述第一驱动电路101。
所述第一驱动电路101，配置为根据所述第二逻辑信号控制所述第一开关140和所述第二开关141的状态。
在发明的其他实施例中，如图3所示，所述信号产生电路13包括：斜坡产生电路130和第一比较电路131；所述斜坡产生电路130与所述电压产生电路11、所述第一比较电路131连接；所述第一比较电路131与所述触发电路100连接。
所述斜坡产生电路130，配置为根据所述前一次充放电电压执行充放电的操作，生成斜坡信号。
所述第一比较电路131，配置为将所述斜坡信号与预设基准电压进行比较，输出所述第一调制信号。
本发明实施例中，电压产生电路11输出的当前充放电电压作为斜坡产生电路130的输入，生成斜坡信号。
在发明的其他实施例中，本发明实施例中的第一比较电路131可以为迟滞比较器等可以进行比较操作的器件或电路。
本发明实施例中，第一比较电路131的预设基准电压有一个误差范围，当斜坡信号到达预设基准电压的误差范围内时，第一比较电路131输出原始的数字信号；当斜坡信号没有到达预设基准电压的误差范围内时，第一比较电路131输出与原始数字信号相反的数字信号，从而产生了第一调制信号。
本发明实施例中，第一调制信号为PFM信号。
示例性地，当迟滞比较器的输出为低电平信号，迟滞比较器的基准电压VREF为5V，误差范围为±0.2v时，当斜坡产生电路130生成的电压信号为2V时，迟滞比较器输出低电平信号；当斜坡产生电路130生成的电压信号为4.9V时，迟滞比较器输出高电平信号。
在发明的其他实施例中，如图4所示，所述检测电路12包括：上电检测电路120、限流保护电路121和退磁检测电路122；所述上电检测电路120与所述电源、所述触发电路100连接；所述限流保护电路121和退磁检测电路122与所述触发电路100、所述电压产生电路11连接。
所述上电检测电路120，配置为检测所述电源的电压值，根据所述电压值确定第三逻辑信号，并将所述第三逻辑信号输出至所述触发电路100，所述第三逻辑信号为所述第一逻辑信号中由所述上电检测电路120产生的逻辑信号。
所述限流保护电路121，配置为检测所述电压产生电路11的上限电流值，根据所述上限电流值确定第四逻辑信号，并将所述第四逻辑信号输出至所述触发电路100，所述第四逻辑信号为所述第一逻辑信号中由所述限流保护电路121产生的逻辑信号。
所述退磁检测电路122，配置为检测所述电压产生电路11的下限电流 值，根据所述下限电流值确定第五逻辑信号，并将所述第五逻辑信号输出至所述触发电路100，所述第五逻辑信号为所述第一逻辑信号中由所述退磁检测电路122产生的逻辑信号。
本发明实施例中，驱动芯片中预设电源电压值，当驱动芯片与电源连接之后，电源的电压值达到预设电源电压值时，表示驱动芯片上电完成并产生上电完成信号。
示例性地，如图4所示，上电检测电路120检测到上电完成信号，并将该上电完成信号输入至逻辑控制及驱动电路10，逻辑控制及驱动电路10产生第一次导通信号，第一次导通信号使得第一开关140闭合，第二开关141断开，从而控制电压产生电路11进行充电操作，限流保护电路121和退磁检测电路122对电压产生电路11上的电流值进行检测，当电压产生电路11上的电流值达到限流保护电路121所限定的极限电流时，限流保护电路121输出限流信号至逻辑控制及驱动电路10，此时逻辑控制及驱动电路10产生第一次闭合信号，第一次闭合信号使得第一开关140断开，第二开关141闭合，从而控制电压产生电路11进行放电操作，当电压产生电路11上的电流值为0时，退磁检测电路122检测到电压产生电路11生成的退磁完成波形，并输出退磁完成信号至逻辑控制及驱动电路10，此时逻辑控制及驱动电路10产生第二次导通信号，第二次导通信号使得第一开关140闭合，第二开关141断开，从而控制电压产生电路11进行充电操作。
在发明的其他实施例中，如图5所示，所述电压产生电路11由电感110和第一电容111组成，所述电感110的第一端与所述充放电开关14、所述限流保护电路121和所述退磁保护电路122连接，所述电感110的第二端与所述第一电容111的第一端和所述斜坡产生电路130连接，所述第一电容111的第一端与所述斜坡产生电路130连接，所述第一电容111的第二端与所述第二开关和接地端连接。
本发明实施例中，退磁检测电路122和限流保护电路121检测的是电压产生电路上电感的电流值。
在发明的其他实施例中，如图6所示，所述斜坡产生电路130由第二电容1300、电阻1301、电流源1302和第三开关1303组成，所述第二电容1300的第一端与所述第一电容111的第一端和所述电感110的第二端连接、所述第二电容1300的第二端与所述电流源1302、所述第一比较电路131和所述第三开关1303的第一端连接，所述第三开关1303的第一端与所述电流源1302和所述第一驱动电路101连接、所述第三开关1303的第二端与所述电阻1301的第一端连接，所述电阻1301的第二端与所述第一电容111的第一端和所述电感110的第二端连接。
示例性地，如图7所示，在t0到t1时间段内，第一控制信号为低电平，第三开关1303断开，电流源1302对第二电容1300进行充电操作，斜坡产生电路130的输出电压逐渐上升，当第一控制信号由低电平跳变至至高电平时，130的输出电压达到高阈值；在t1到t2时间段内，第一控制信号为高电平，第三开关闭合，第二电容1300通过电阻1301进行放电，斜坡产生电路130的输出电压逐渐下降当第一控制信号由高电平跳变至低电平时130的输出电压降到低阈值，即产生斜坡信号(130的输出电压)。
在发明的其他实施例中，如图8所示，所述触发电路100由一级判断电路1001、二级或门电路1002和三级触发电路1003构成；其中，
所述一级判断电路1001包括第一或门电路10010和第一震荡电路10011。
所述第一或门电路10010，配置为将输入的所述第一调制信号和所述第五逻辑信号经过或运算后，输出第一运算信号。
所述第一振荡电路10011，配置为将输入的所述第三逻辑信号经过振荡后，输出第一振荡信号。
所述二级或门电路1002，配置为将输入的所述第一运算信号和所述第一震荡信号经过或运算后，输出第二运算信号。
所述三级触发电路1003，配置为将输入的所述第四逻辑信号和所述第二运算信号经过触发判定后，输出第一触发信号至所述第一驱动电路101。
所述第一驱动电路101，配置为根据输入的所述第一触发信号，输出第一控制信号和第二控制信号，以控制所述充放电开关的状态。
本发明实施例中，第一振荡电路10011可以为单稳态多谐振振荡器，经过单稳态多谐振振荡器输出的第一震荡信号为脉冲信号。
本发明实施例中，三级触发电路1003可以为置位复位(SR，SetReset)触发器。
示例性地，二级或门电路1002与SR触发器的置位端连接，限流保护电路121与SR触发器的复位端连接，当SR触发器的置位端为高电平，复位端为低电平时，SR触发器输出高电平，当SR触发器的置位端为低电平，复位端为高电平时，SR触发器输出低电平。
示例性地，结合图4、图7和图8所示，当电源的电压值达到预设电源电压值时，上电检测电路120检测到上电完成信号，使得第三逻辑信号由低电平跳变为高电平，第三逻辑信号经过单稳态多谐振振荡器跳转成为一个高电平的脉冲信号输入二级或门电路，二级或门电路输出高电平，则SR触发器的置位端为高电平，由于电压产生电路11处于正在充电的状态，电感电流值没有达到限流保护电路121的极限电流，所以第四逻辑信号为低电平，则SR触发器的复位端为低电平，则SR触发器输出高电平，第一驱动电路101接收到第一触发信号为高电平之后，控制第一开关140闭合，第二开关141断开。
示例性地，当电感电流值达到限流保护电路的极限电流时，限流保护电路121输出的第四逻辑信号由低电平跳变为高电平，则SR触发器的复位 端为高电平，同时，由于电感电流值不为0，所以第五逻辑信号为低电平，由于电压产生电路11此时处于充电的状态，所以第一触发信号为高电平，且如图7所示，第一触发信号为高电平时，控制斜坡产生电路130的输出电压逐渐下降，经过迟滞比较器后，第一调制信号为低电平，则第一或门电路10010输出的第一运算信号为低电平，此时，第一震荡信号恢复为低电平，二级或门电路1002的两个输入都为低电平，所以SR触发器输出低电平，第一驱动电路101接收到第一触发信号为低电平之后，控制第一开关140断开，第二开关141闭合。
在发明的其他实施例中，所述充放电开关，配置为根据所述第一控制信号和所述第二控制信号控制所述第一开关140和所述第二开关141执行通断操作，所述第一开关140与所述第二开关141执行相反的通断操作。
本发明实施例提供了一种直流恒压变换方法，如图9所示，该方法可以包括：
S101、获取上一次充放电电压。
S102、将上一次充放电电压与预设基准电压进行比较。
S103、当上一次充放电电压小于等于预设基准电压时，进行充电操作。
S104、当上一次充放电电压大于预设基准电压时，进行放电操作。
S105、生成当前充放电电压，以供下一次获取使用。
S106、进入下一次充放电流程，将当前充放电电压作为下一次与预设基准电压比较的电压。
本发明实施例中，在下一次充放电流程时，当前充放电电压作为下一次与预设基准电压进行比较的充放电电压进行循环获取，并执行S101-S106的流程。
需要说明的是，本发明实施例中，通过电压产生电路生成上一次充放电电压，将上一次充放电电压与预设的基准电压进行比较来控制电压产生 电路的操作，当上一次充放电电压小于等于预设基准电压时，电压产生电路进行充电操作，当上一次充放电电压差大于预设基准电压时，电压产生电路进行放电操作，从而产生当前充放电电压，也就是说，获取上一次充放电电压，根据上一次充放电电压控制电压产生电路的充放电操作生成当前充放电电压。
需要说明的是，本发明实施例提供的一种直流恒压变换方法的实现是循环实现的。
下面结合电路进行详细地说明。本发明实施例可以通过一种直流恒压变换电路实现。
需要说明的是，如图4所示，上电检测电路120检测到上电完成信号，并将该上电完成信号输入至逻辑控制及驱动电路10，逻辑控制及驱动电路10产生第一次导通信号，第一次导通信号使得第一开关140闭合，第二开关141断开，从而控制电压产生电路11进行充电操作，限流保护电路121和退磁检测电路122对电压产生电路11上的电流值进行检测，当电压产生电路11上的电流值达到限流保护电路121所限定的极限电流时，限流保护电路121输出限流信号至逻辑控制及驱动电路10，此时逻辑控制及驱动电路10产生第一次闭合信号，第一次闭合信号使得第一开关140断开，第二开关141闭合，从而控制电压产生电路11进行放电操作，当电压产生电路11上的电流值为0时，退磁检测电路122检测到电压产生电路11生成的退磁完成波形，并输出退磁完成信号至逻辑控制及驱动电路10，此时逻辑控制及驱动电路10产生第二次导通信号，第二次导通信号使得第一开关140闭合，第二开关141断开，从而控制电压产生电路11进行充电操作。
需要说明的是，结合图4、图7和图8所示，当电源的电压值达到预设电源电压值时，上电检测电路120检测到上电完成信号，使得第三逻辑信号由低电平跳变为高电平，第三逻辑信号经过单稳态多谐振振荡器跳转成 为一个高电平的脉冲信号输入二级或门电路，二级或门电路输出高电平，则SR触发器的置位端为高电平，由于电压产生电路11处于正在充电的状态，电感电流值没有达到限流保护电路121的极限电流，所以第四逻辑信号为低电平，则SR触发器的复位端为低电平，则SR触发器输出高电平，第一驱动电路101接收到第一触发信号为高电平之后，控制第一开关140闭合，第二开关141断开。
当电感电流值达到限流保护电路的极限电流时，限流保护电路121输出的第四逻辑信号由低电平跳变为高电平，则SR触发器的复位端为高电平，同时，由于电感电流值不为0，所以第五逻辑信号为低电平，由于电压产生电路11此时处于充电的状态，所以第一触发信号为高电平，且如图7所示，第一触发信号为高电平时，控制斜坡产生电130路的输出电压逐渐下降，经过迟滞比较器后，第一调制信号为低电平，则第一或门电路10010输出的第一运算信号为低电平，此时，第一震荡信号恢复为低电平，二级或门电路1002的两个输入都为低电平，所以SR触发器输出低电平，第一驱动电路101接收到第一触发信号为低电平之后，控制第一开关140断开，第二开关141闭合。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、 嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本实施例中，由于通过斜坡产生电路和第一比较电路组成的信号产生电路来生成PFM信号，从而代替了时钟产生电路和采样保持电路，减少了对时序的特殊考虑，且可以不在驱动芯片外部增加分压电阻，因此，能够降低驱动芯片的成本和设计难度，提升系统的集成度，减少系统的成本。

Claims (11)

  1. 一种直流恒压变换电路，包括：
    逻辑控制及驱动电路；
    与所述逻辑控制及驱动电路连接的电压产生电路；
    与所述逻辑控制及驱动电路、所述电压产生电路和电源连接的检测电路；
    与所述逻辑控制及驱动电路和所述电压产生电路连接的信号产生电路；
    以及与所述逻辑控制及驱动电路和所述电压产生电路连接的充放电开关；其中，
    所述信号产生电路，配置为对前一次充放电电压进行转换，生成第一调制信号；
    所述检测电路，配置为检测所述电源的电压值和所述电压产生电路的电流值，并根据所述电压值和所述电流值生成第一逻辑信号；
    所述逻辑控制及驱动电路，配置为根据所述第一逻辑信号和所述第一调制信号更改充放电开关的状态；
    所述充放电开关，包括处于不同状态的第一开关和第二开关，配置为控制所述电压产生电路进行充放电操作；
    所述电压产生电路，配置为根据所述第一开关和所述第二开关的状态进行充放电操作，并输出当前充放电电压，以供下一次充放电操作使用。
  2. 根据权利要求1所述的直流恒压变换电路，其中，所述逻辑控制及驱动电路包括：与所述信号产生电路和所述检测电路连接的触发电路、与所述触发电路和所述电压产生电路连接的第一驱动电路；
    所述触发电路，配置为根据所述第一逻辑信号和所述第一调制信号 生成第二逻辑信号，并将所述第二逻辑信号输出至所述第一驱动电路；
    所述第一驱动电路，配置为根据所述第二逻辑信号控制所述第一开关和所述第二开关的状态。
  3. 根据权利要求2所述的直流恒压变换电路，其中，所述信号产生电路包括：斜坡产生电路和第一比较电路；所述斜坡产生电路与所述电压产生电路、所述第一比较电路连接；所述第一比较电路与所述触发电路连接；
    所述斜坡产生电路，配置为根据所述前一次充放电电压执行充放电的操作，生成斜坡信号；
    所述第一比较电路，配置为将所述斜坡信号与预设基准电压进行比较，输出所述第一调制信号。
  4. 根据权利要求2所述的直流恒压变换电路，其中，所述检测电路包括：上电检测电路、限流保护电路和退磁检测电路；所述上电检测电路与所述电源、所述触发电路连接；所述限流保护电路和退磁检测电路与所述触发电路、所述电压产生电路连接；
    所述上电检测电路，配置为检测所述电源的电压值，根据所述电压值确定第三逻辑信号，并将所述第三逻辑信号输出至所述触发电路，所述第三逻辑信号为所述第一逻辑信号中由所述上电检测电路产生的逻辑信号；
    所述限流保护电路，配置为检测所述电压产生电路的上限电流值，根据所述上限电流值确定第四逻辑信号，并将所述第四逻辑信号输出至所述触发电路，所述第四逻辑信号为所述第一逻辑信号中由所述限流保护电路产生的逻辑信号；
    所述退磁检测电路，配置为检测所述电压产生电路的下限电流值，根据所述下限电流值确定第五逻辑信号，并将所述第五逻辑信号输出至 所述触发电路，所述第五逻辑信号为所述第一逻辑信号中由所述退磁检测电路产生的逻辑信号。
  5. 根据权利要求2所述的直流恒压变换电路，其中，
    所述电压产生电路由电感和第一电容组成，所述电感的第一端与所述充放电开关、所述限流保护电路和所述退磁保护电路连接，所述电感的第二端与所述第一电容的第一端和所述斜坡产生电路连接，所述第一电容的第一端与所述斜坡产生电路连接，所述第一电容的第二端与所述第二开关和接地端连接。
  6. 根据权利要求3所述的直流恒压变换电路，其中，
    所述斜坡产生电路由第二电容、电阻、电流源和第三开关组成，所述第二电容的第一端与所述第一电容的第一端和所述电感的第二端连接、所述第二电容的第二端与所述电流源、所述第一比较电路和所述第三开关的第一端连接，所述第三开关的第一端与所述电流源和所述第一驱动电路连接、所述第三开关的第二端与所述电阻的第一端连接，所述电阻的第二端与所述第一电容的第一端和所述电感的第二端连接。
  7. 根据权利要求4所述的直流恒压变换电路，其中，
    所述触发电路由一级判断电路、二级或门电路和三级触发电路构成；其中，
    所述一级判断电路包括第一或门电路和第一震荡电路；
    所述第一或门电路，配置为将输入的所述第一调制信号和所述第五逻辑信号经过或运算后，输出第一运算信号；
    所述第一振荡电路，配置为将输入的所述第三逻辑信号经过振荡后，输出第一振荡信号；
    所述二级或门电路，配置为将输入的所述第一运算信号和所述第一震荡信号经过或运算后，输出第二运算信号；
    所述三级触发电路，配置为将输入的所述第四逻辑信号和所述第二运算信号经过触发判定后，输出第一触发信号至所述第一驱动电路；
    所述第一驱动电路，配置为根据输入的所述第一触发信号，输出第一控制信号和第二控制信号，以控制所述充放电开关的状态。
  8. 根据权利要求7所述的直流恒压变换电路，其中，
    所述充放电开关，配置为根据所述第一控制信号和所述第二控制信号控制所述第一开关和所述第二开关执行通断操作，所述第一开关与所述第二开关执行相反的通断操作。
  9. 一种直流恒压变换方法，包括：
    获取上一次充放电电压；
    将所述上一次充放电电压与预设基准电压进行比较；
    根据所述比较结果对电源电压执行相应的充放电操作，生成当前充放电电压，以供下一次获取使用。
  10. 根据权利要求9所述的方法，其中，所述根据所述比较结果对输入电压进行相应的充放电操作，包括：
    当所述上一次充放电电压小于等于所述预设基准电压时，进行充电操作；
    当所述上一次充放电电压大于所述预设基准电压时，进行放电操作。
  11. 根据权利要求9或10所述的方法，其中，所述生成当前充放电电压之后，所述方法还包括：
    进入下一次充放电流程，将所述当前充放电电压作为下一次与所述预设基准电压比较的电压。
PCT/CN2017/085231 2016-09-22 2017-05-19 一种直流恒压变换电路及方法 WO2018054078A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW556398B (en) * 2001-03-30 2003-10-01 Champion Microelectronic Corp Current limiting technique for a voltage converter
US6989997B2 (en) * 2003-06-25 2006-01-24 Virginia Tech Intellectual Properties, Inc. Quasi-resonant DC-DC converters with reduced body diode loss
CN102323841A (zh) * 2011-05-06 2012-01-18 杭州矽力杰半导体技术有限公司 一种电流滞环控制电路、电流滞环控制方法以及应用其的直流-直流变换器
CN103947092A (zh) * 2011-10-26 2014-07-23 美高森美公司 用于降压dc/dc转换器的滞后控制
CN105958820A (zh) * 2016-06-07 2016-09-21 广东希荻微电子有限公司 迟滞式控制器pwm和pfm模式下的控制方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW556398B (en) * 2001-03-30 2003-10-01 Champion Microelectronic Corp Current limiting technique for a voltage converter
US6989997B2 (en) * 2003-06-25 2006-01-24 Virginia Tech Intellectual Properties, Inc. Quasi-resonant DC-DC converters with reduced body diode loss
CN102323841A (zh) * 2011-05-06 2012-01-18 杭州矽力杰半导体技术有限公司 一种电流滞环控制电路、电流滞环控制方法以及应用其的直流-直流变换器
CN103947092A (zh) * 2011-10-26 2014-07-23 美高森美公司 用于降压dc/dc转换器的滞后控制
CN105958820A (zh) * 2016-06-07 2016-09-21 广东希荻微电子有限公司 迟滞式控制器pwm和pfm模式下的控制方法

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