WO2018040108A1 - 一种高速低功耗光收发芯片 - Google Patents

一种高速低功耗光收发芯片 Download PDF

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WO2018040108A1
WO2018040108A1 PCT/CN2016/098132 CN2016098132W WO2018040108A1 WO 2018040108 A1 WO2018040108 A1 WO 2018040108A1 CN 2016098132 W CN2016098132 W CN 2016098132W WO 2018040108 A1 WO2018040108 A1 WO 2018040108A1
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data
clock
module
signal
buffer
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PCT/CN2016/098132
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English (en)
French (fr)
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白昀
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飞昂通讯科技南通有限公司
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Priority to PCT/CN2016/098132 priority Critical patent/WO2018040108A1/zh
Publication of WO2018040108A1 publication Critical patent/WO2018040108A1/zh
Priority to US16/292,776 priority patent/US10469173B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/40—Transceivers

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  • the present invention generally relates to an optical transceiver chip for use in optical communication.
  • data is transmitted in the form of optical signals transmitted and received via optical waveguides.
  • a bidirectional optical link is used on the communication device for the bidirectional parallel optical transceiver module used in the link.
  • the optical transceiver produces an optical signal representative of amplitude and/or phase and/or polarization modulation of the data, and then transmits the optical signal on an optical fiber coupled to the transceiver.
  • Each transceiver includes a transmitter side and a receiver side.
  • a laser source produces a laser and an optical coupling system receives the laser and optically couples or images the light onto one end of the fiber.
  • the laser source is typically made of one or more laser diodes that produce light of a particular wavelength or range of wavelengths.
  • An optical coupling system typically includes one or more reflective elements, one or more refractive elements, and/or one or more diffractive elements.
  • the photodiode detects an optical data signal transmitted on the optical fiber and converts the optical data signal into an electrical signal, which is then amplified and processed by circuitry on the receiver side to recover the data.
  • the combination of an optical transceiver connected to each end of the fiber and the fiber itself is commonly referred to as a fiber link.
  • Optical transceiver chips used in the field of optical communication are often fabricated into separate chips by discrete laser drivers, transconductance amplifiers, and clock data restorers, and then integrated by inter-chip signals to achieve overall light. Transceiver function. However, as the field of optical communications becomes faster, especially in optical transceiver chips used in high-speed fiber links (eg, 10 Gigabits per second (Gb/s) and higher), Discrete chip design is far from satisfactory, with high power consumption, slow communication speed and poor anti-interference ability.
  • Gb/s 10 Gigabits per second
  • the present invention provides a four-channel high-speed low-power optical transceiver chip, wherein each channel includes a light emitting module, a light receiving module, and a sharing module, wherein:
  • the light emitting module includes a data buffer, a first clock data restorer, a first data selector, a laser driver, a power controller, a first clock buffer, and a light emitting diode and a first photodiode, wherein: the data buffer Transmitting input data to the first data selector through the first clock data restorer; the first clock buffer is coupled to the first clock data restorer for output of a clock; The first data selector is selected for transmission to the laser driver for data output, and the laser driver converts the digital signal into a voltage signal; the voltage signal is converted into an optical signal by the light emitting diode, and is monitored by the input terminal The first photodiode receives, converts the optical signal into a voltage signal, and inputs the signal to the power controller; the power controller is coupled to the laser driver for feeding back and adjusting a voltage signal output by the laser driver ;
  • the light receiving module includes a second photodiode, a DC bias module, a transconductance amplifier, a feedback resistor, a second clock data restorer, a second clock buffer, a second data selector, and an output driver, wherein: a photodiode that converts the received optical signal into an electrical signal that is used to supply power to the optical receiving module; the transconductance amplifier converts the current signal at the receiving end into a voltage signal for transmission to the a second clock data restorer; the transconductance amplifier is coupled in parallel with the feedback resistor for adjusting an electrical signal in the transconductance amplifier; the second clock data restorer is coupled to the second clock buffer for Outputting a clock signal to the output driver through the second data selector; the output driver converting the voltage signal into a digital signal for output;
  • the sharing module includes a power controller, a DC bias, a logic controller, a serial interface, a memory, and a pseudo-random data generator and a checker; the shared module is both the light emitting module and the light receiving module Provide a communication loop.
  • the invention also provides a single-channel high-speed low-power optical transceiver chip, comprising a light emitting module, a light receiving module and a sharing module, wherein:
  • the light emitting module includes a data buffer, a first clock data restorer, and first data a selector, a laser driver, a power controller, a first clock buffer, and a light emitting diode and a first photodiode, wherein: the data buffer transmits input data to the first data through the first clock data restorer a first clock buffer connected to the first clock data restorer for outputting a clock; the input data is selected by the first data selector and transmitted to the laser driver for data output,
  • the laser driver converts the digital signal into a voltage signal; the voltage signal is converted into an optical signal by the light emitting diode, and is received by the first photodiode of the monitoring input, converting the optical signal into a voltage signal, and inputting to the a power controller; the power controller is coupled to the laser driver for feeding back and adjusting a voltage signal output by the laser driver; the light emitting module is configured as a single channel;
  • the light receiving module includes a second photodiode, a DC bias module, a transconductance amplifier, a feedback resistor, a second clock data restorer, a second clock buffer, a second data selector, and an output driver, wherein: a photodiode that converts the received optical signal into an electrical signal that is used to supply power to the optical receiving module; the transconductance amplifier converts the current signal at the receiving end into a voltage signal for transmission to the a second clock data restorer; the transconductance amplifier is coupled in parallel with the feedback resistor for adjusting an electrical signal in the transconductance amplifier; the second clock data restorer is coupled to the second clock buffer for Outputting a clock signal to the output driver through the second data selector; the output driver converting the voltage signal into a digital signal for output; the light receiving module is configured as a single channel;
  • the sharing module includes a power controller, a DC bias, a logic controller, a serial interface, a memory, and a pseudo-random data generator and a checker; the shared module is both the light emitting module and the light receiving module Provide a communication loop.
  • the power controller comprises a current voltage conversion circuit and a 10-bit clock data recovery circuit.
  • the base current Ibase of the laser driver ranges from 0 to 80 mA; and the drive/modulation current Imod ranges from 0 to 80 mA.
  • the data buffer has a maximum gain value of 30 db and a maximum boost value of 20 db.
  • the interface of the first clock buffer adopts a CML structure and is loaded with 50 ⁇ .
  • the bandwidth of the first clock data restorer ranges from 1 kHz to 200 MHz.
  • the transimpedance amplifier has a gain range of 0-100 db.
  • the second photodiode has a maximum input common mode current of 10 mA.
  • the differential output impedance of the second clock buffer is 100 ⁇ .
  • the output driver has a differential output impedance of 100 ⁇ and a differential output voltage amplitude ranging from 0 to 3.3V.
  • the bandwidth of the second clock data restorer ranges from 1 kHz to 200 MHz.
  • FIG. 1 is a logic diagram showing a single-channel high-speed low-power optical transceiver chip in accordance with the present invention
  • FIG. 2 is a logic diagram showing a four-channel high speed low power optical transceiver chip in accordance with the present invention.
  • FIG. 1 it is a logic diagram of a single-channel high-speed low-power optical transceiver chip of the present invention.
  • the optical transceiver chip includes: a light emitting module, a light receiving module, and a sharing module, wherein:
  • the light emitting module includes a data buffer, a first clock data restorer, a first data selector, a laser driver, a power controller, a first clock buffer, and a light emitting diode and a first photodiode, wherein:
  • the data buffer transmits input data to the first data selector through the first clock data restorer; according to an embodiment of the invention, the data buffer maximum gain value is 30 db, and the maximum boost value is 20db.
  • the first clock buffer is connected to the first clock data restorer for outputting a clock; according to an embodiment of the invention, the interface of the first clock buffer adopts a CML structure with a load of 50 ⁇ , The bandwidth of the first clock data restorer ranges from 1 kHz to 200 MHz.
  • Input data is selected by the first data selector and transmitted to the laser driver for data output, the laser driver converting the digital signal into a voltage signal; according to an embodiment of the invention, the base current of the laser driver
  • the Ibase range is 0-80 mA; the drive/modulation current Imod ranges from 0-80 mA.
  • the voltage signal is converted into an optical signal by the light emitting diode, and received by the first photodiode of the monitoring input, converting the optical signal into a voltage signal, and input to the power controller;
  • the power controller is coupled to the laser driver for feeding back and adjusting a voltage signal output by the laser driver; according to an embodiment of the invention, the power controller comprises a current voltage conversion circuit and 10-bit clock data Recovery circuit
  • the light emitting module is configured as a single channel.
  • the light receiving module includes a second photodiode, a DC bias module, a transconductance amplifier, a feedback resistor, a second clock data restorer, a second clock buffer, a second data selector, and an output driver, wherein:
  • the second photodiode converts the received optical signal into an electrical signal for conducting, and the DC biasing module is configured to supply power to the light receiving module; according to an embodiment of the invention, the second photodiode is The input common mode current is 10mA.
  • the transconductance amplifier converts the current signal at the receiving end into a voltage signal for transmission to the second clock data restorer; according to an embodiment of the invention, the bandwidth of the second clock data restorer ranges from 1 kHz to 200 MHz.
  • the transconductance amplifier is one of the most versatile standard modules in current mode circuits. It converts the input differential voltage into an output current amplifier, so it is a voltage controlled current source (VCCS). Transconductance amplifiers usually have an additional current input to control the transconductance of the amplifier.
  • VCCS voltage controlled current source
  • the high-impedance differential input stage which works with a negative feedback loop, makes the transconductance amplifier similar to a conventional op amp.
  • the transconductance amplifier is coupled in parallel with the feedback resistor for adjusting an electrical signal in the transconductance amplifier; according to an embodiment of the invention, the transimpedance amplifier has a gain range of 0-100 db.
  • the second clock data restorer is coupled to the second clock buffer for outputting a clock; according to an embodiment of the invention, the differential output impedance of the second clock buffer is 100 ⁇ .
  • the output driver converts the voltage signal into a digital signal for output; in accordance with an embodiment of the invention, the output driver has a differential output impedance of 100 ⁇ and a differential output voltage amplitude ranging from 0V to 3.3V.
  • the clock data restorer of the present invention first transmits data serially and then converts the data into an 8b/10b encoding scheme.
  • the encoding process obtains 8-bit data and converts it into a 10-bit symbol.
  • the 8b/10b encoding method can transmit an equal number of 0s and 1s on the data line, thereby reducing intersymbol interference and providing enough data edges for the receiver to lock the phase on the received data stream.
  • the transmitter multiplies the system clock to the transmit bit rate and transmits 8b/10b data on the TX differential pair at that rate.
  • the task of the clock data restorer is first to lock the phase on the RX differential bit stream, then the receiver aligns the data bits according to the recovered clock and then uses the receiver's reference clock for word alignment. Finally, the data is decoded 8b/10b for use by the system.
  • the transmit and receive systems typically have completely separate system clocks. These two clocks are critical in a particular range of variation, which is approximately hundreds of PPMs.
  • the light receiving module is configured as a single channel.
  • the sharing module includes a power controller, a DC bias, a logic controller, a serial interface, a memory, and a pseudo-random data generator and a checker; the shared module is both the light emitting module and the light receiving module Providing a communication loop;
  • the power controller supplies power to the light emitting module and the light receiving module
  • the DC bias is applied to the light receiving module to adjust the DC component of the signal output, that is, Said to move the entire output signal up or down.
  • the application of the logic controller such as the first/second data selector, selects the digital signal by corresponding rules
  • the serial interface is an interface inside or connected to the optical transceiver chip, which can improve the transmission speed
  • the memory is used to store data in the light emitting module and the light receiving module
  • the pseudo-random data generator and checker are used to detect and verify the status of the module, which enhances the stability and accuracy of the circuit operation of each module.
  • FIG. 2 is a schematic diagram showing a logic diagram of a four-channel high-speed low-power optical transceiver chip according to the present invention: the logic principle of the light-emitting module and the light-receiving module is the same as that of the single-channel high-speed low-power optical transceiver chip shown in FIG. 1.
  • Each channel of the four-channel high-speed low-power optical transceiver chip shown in FIG. 2 is provided with a light emitting module, a light receiving module and a shared module, and can simultaneously transmit data through multiple light emitting channels and multiple light receiving channels. , improve the efficiency of data transmission.

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  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

一种单通道高速低功耗光收发芯片,包括光发射模块、光接收模块以及共用模块，其中：光发射模块包括数据缓冲器、第一时钟数据恢复器、第一数据选择器、激光驱动器、功率控制器、第一时钟缓冲器以及发光二极管和第一光电二极管；光接收模块包括第二光电二极管、直流偏置模块、跨导放大器、反馈电阻、第二时钟数据恢复器、第二时钟缓存器、第二数据选择器、输出驱动器；共用模块包括电源控制器、直流偏置、逻辑控制器、串行接口、存储器以及伪随机数据发生器和校验器；共用模块同时为光发射模块和光接收模块提供通信回路。

Description

一种高速低功耗光收发芯片 技术领域
本发明主要涉及在光通信中使用的光收发芯片。
背景技术
在光学通信网络中，经由光学波导发射及接收的光学信号的形式传递数据。更具体地，在通信设备上使用双向光学链路供在所述链路中使用的双向并行光学收发器模块。光学收发器产生表示数据的经振幅及/或相位及/或偏振调制的光学信号，接着在耦合到所述收发器的光纤上发射所述光学信号。每一收发器包含发射器侧及接收器侧。在所述发射器侧上，激光光源产生激光且光学耦合系统接收所述激光并将所述光光学耦合或成像到光纤的一端上。所述激光光源通常由产生特定波长或波长范围的光的一个或一个以上激光二极管制成。光学耦合系统通常包含一个或一个以上反射元件、一个或一个以上折射元件及/或一个或一个以上衍射元件。在所述接收器侧上，光电二极管检测在光纤上发射的光学数据信号并将所述光学数据信号转换成电信号，所述电信号接着由接收器侧的电路放大及处理以恢复数据。在光纤的每一端上连接的光学收发器与光纤本身的组合通常称为光纤链路。
在现有的光通信领域中使用的光收发芯片，往往是通过分立的激光驱动器、跨导放大器和时钟数据恢复器，制作成单独的芯片，然后通过芯片间信号的耦合传送来实现整体的光收发功能。然而，随着光通信领域速度的越来越快，特别是在像高速光纤链路(例如，10千兆位/秒(Gb/s)及更高)中使用的光收发芯片中，这种分立的芯片设计已经远远不能满足需求，其功耗高、通信速度慢、抗干扰能力差。
因此，需要一种能够以相对高的数据速率操作同时实现相对低的功耗的光收发芯片来解决现有技术中的问题。
发明内容
本发明为了解决上述问题，提供了一种四通道高速低功耗光收发芯片，其中，每个通道都包括光发射模块、光接收模块以及共用模块，其中：
所述光发射模块包括数据缓冲器、第一时钟数据恢复器、第一数据选择器、激光驱动器、功率控制器、第一时钟缓冲器以及发光二极管和第一光电二极管，其中：所述数据缓冲器将输入数据通过所述第一时钟数据恢复器传输至所述第一数据选择器；所述第一时钟缓冲器与所述第一时钟数据恢复器连接，用于时钟的输出；输入数据通过所述第一数据选择器选择后传输至所述激光驱动器进行数据输出，所述激光驱动器将数字信号转化为电压信号；所述电压信号通过所述发光二极管转化为光信号，并且由监测输入端的所述第一光电二极管接收，将光信号转化为电压信号，输入至所述功率控制器；所述功率控制器与所述激光驱动器相连接，用于反馈并调整所述激光驱动器输出的电压信号；
所述光接收模块包括第二光电二极管、直流偏置模块、跨导放大器、反馈电阻、第二时钟数据恢复器、第二时钟缓存器、第二数据选择器、输出驱动器，其中：所述第二光电二极管将接收的光信号转化成电信号并导通，所述直流偏置模块用于向所述光接收模块供电；所述跨导放大器将接收端的电流信号转化为电压信号传输至所述第二时钟数据恢复器；所述跨导放大器并联所述反馈电阻，用于调节所述跨导放大器中的电信号；所述第二时钟数据恢复器连接所述第二时钟缓冲器，用于输出时钟；通过所述第二数据选择器将电压信号输入至所述输出驱动器；所述输出驱动器将电压信号转化为数字信号进行输出；
所述共用模块包括电源控制器、直流偏置、逻辑控制器、串行接口、存储器以及伪随机数据发生器和校验器；所述共用模块同时为所述光发射模块和所述光接收模块提供通信回路。
本发明还提供了一种单通道高速低功耗光收发芯片，包括光发射模块、光接收模块以及共用模块，其中：
所述光发射模块包括数据缓冲器、第一时钟数据恢复器、第一数据 选择器、激光驱动器、功率控制器、第一时钟缓冲器以及发光二极管和第一光电二极管，其中：所述数据缓冲器将输入数据通过所述第一时钟数据恢复器传输至所述第一数据选择器；所述第一时钟缓冲器与所述第一时钟数据恢复器连接，用于时钟的输出；输入数据通过所述第一数据选择器选择后传输至所述激光驱动器进行数据输出，所述激光驱动器将数字信号转化为电压信号；所述电压信号通过所述发光二极管转化为光信号，并且由监测输入端的所述第一光电二极管接收，将光信号转化为电压信号，输入至所述功率控制器；所述功率控制器与所述激光驱动器相连接，用于反馈并调整所述激光驱动器输出的电压信号；所述光发射模块设置为单通道；
所述光接收模块包括第二光电二极管、直流偏置模块、跨导放大器、反馈电阻、第二时钟数据恢复器、第二时钟缓存器、第二数据选择器、输出驱动器，其中：所述第二光电二极管将接收的光信号转化成电信号并导通，所述直流偏置模块用于向所述光接收模块供电；所述跨导放大器将接收端的电流信号转化为电压信号传输至所述第二时钟数据恢复器；所述跨导放大器并联所述反馈电阻，用于调节所述跨导放大器中的电信号；所述第二时钟数据恢复器连接所述第二时钟缓冲器，用于输出时钟；通过所述第二数据选择器将电压信号输入至所述输出驱动器；所述输出驱动器将电压信号转化为数字信号进行输出；所述光接收模块设置为单通道；
所述共用模块包括电源控制器、直流偏置、逻辑控制器、串行接口、存储器以及伪随机数据发生器和校验器；所述共用模块同时为所述光发射模块和所述光接收模块提供通信回路。
优选地，所述功率控制器包括电流电压转换电路以及10位时钟数据恢复电路。
优选地，所述激光驱动器的基极电流Ibase范围为0-80mA；驱动/调制电流Imod范围为0-80mA。
优选地，所述数据缓冲器最大增益值为30db，最大boost值为20db。
优选地，所述第一时钟缓冲器的接口采用CML结构，负载50Ω。
优选地，所述第一时钟数据恢复器的带宽范围为1KHZ-200MHZ。
优选地，所述跨阻放大器增益范围为0-100db。
优选地，所述第二光电二极管最大输入共模电流为10mA。
优选地，所述第二时钟缓存器的差分输出阻抗为100Ω。
优选地，所述输出驱动器的差分输出阻抗为100Ω，差分输出电压幅度范围为0-3.3V。
优选地，所述第二时钟数据恢复器的带宽范围为1KHZ-200MHZ。
应当理解，前述大体的描述和后续详尽的描述均为示例性说明和解释，并不应当用作对本发明所要求保护内容的限制。
附图说明
参考随附的附图，本发明更多的目的、功能和优点将通过本发明实施方式的如下描述得以阐明，其中：
图1示意性示出根据本发明的单通道高速低功耗光收发芯片的逻辑图；
图2示意性示出根据本发明的四通道高速低功耗光收发芯片的逻辑图。
具体实施方式
通过参考示范性实施例，本发明的目的和功能以及用于实现这些目的和功能的方法将得以阐明。然而，本发明并不受限于以下所公开的示范性实施例；可以通过不同形式来对其加以实现。说明书的实质仅仅是帮助相关领域技术人员综合理解本发明的具体细节。
在下文中，将参考附图描述本发明的实施例。在附图中，相同的附图标记代表相同或类似的部件。
如图1所示，为本发明的单通道高速低功耗光收发芯片的逻辑图。所述光收发芯片包括：光发射模块、光接收模块以及共用模块，其中：
所述光发射模块包括数据缓冲器、第一时钟数据恢复器、第一数据选择器、激光驱动器、功率控制器、第一时钟缓冲器以及发光二极管和第一光电二极管，其中：
所述数据缓冲器将输入数据通过所述第一时钟数据恢复器传输至所述第一数据选择器；根据本发明的一个实施例，所述数据缓冲器最大增益值为30db，最大boost值为20db。
所述第一时钟缓冲器与所述第一时钟数据恢复器连接，用于时钟的输出；根据本发明的一个实施例，所述第一时钟缓冲器的接口采用CML结构，负载50Ω，所述第一时钟数据恢复器的带宽范围为1KHZ-200MHZ。
输入数据通过所述第一数据选择器选择后传输至所述激光驱动器进行数据输出，所述激光驱动器将数字信号转化为电压信号；根据本发明的一个实施例，所述激光驱动器的基极电流Ibase范围为0-80mA；驱动/调制电流Imod范围为0-80mA。
所述电压信号通过所述发光二极管转化为光信号，并且由监测输入端的所述第一光电二极管接收，将光信号转化为电压信号，输入至所述功率控制器；
所述功率控制器与所述激光驱动器相连接，用于反馈并调整所述激光驱动器输出的电压信号；根据本发明的一个实施例，所述功率控制器包括电流电压转换电路以及10位时钟数据恢复电路；
所述光发射模块设置为单通道。
所述光接收模块包括第二光电二极管、直流偏置模块、跨导放大器、反馈电阻、第二时钟数据恢复器、第二时钟缓存器、第二数据选择器、输出驱动器，其中：
所述第二光电二极管将接收的光信号转化成电信号并导通，所述直流偏置模块用于向所述光接收模块供电；根据本发明的一个实施例，所述第二光电二极管最大输入共模电流为10mA。
所述跨导放大器将接收端的电流信号转化为电压信号传输至所述第二时钟数据恢复器；根据本发明的一个实施例，所述第二时钟数据恢复器的带宽范围为1KHZ-200MHZ。
跨导放大器是电流模式电路中最为通用的标准模块之一,将输入差分电压转换为输出电流的放大器，因而它是一种电压控制电流源(VCCS)。跨导放大器通常会有一个额外的电流输入端，用以控制放大器的跨导。 高阻的差分输入级、可配合负反馈回路进行工作的特性，使得跨导放大器类似于常规运算放大器。
所述跨导放大器并联所述反馈电阻，用于调节所述跨导放大器中的电信号；根据本发明的一个实施例，所述跨阻放大器增益范围为0-100db。
所述第二时钟数据恢复器连接所述第二时钟缓冲器，用于输出时钟；根据本发明的一个实施例，所述第二时钟缓存器的差分输出阻抗为100Ω。
通过所述第二数据选择器将电压信号输入至所述输出驱动器；
所述输出驱动器将电压信号转化为数字信号进行输出；根据本发明的一个实施例，所述输出驱动器的差分输出阻抗为100Ω，差分输出电压幅度范围为0V-3.3V。
本发明的时钟数据恢复器首先串行发送数据，然后将数据转换成8b/10b编码方案。编码处理获得8位数据并将其转换成10位符号。8b/10b编码方式可以在数据线上传送相等数目的0和1，从而减少码间干扰，并提供足够多的数据边沿，以便接收器在收到的数据流上锁定相位。发送器将系统时钟倍频至传送比特率，并以该速率在TX差分对上发送8b/10b数据。
时钟数据恢复器的任务首先是在RX差分位流上锁定相位，然后接收器按照恢复的时钟进行数据位对齐，接着用接收器的参考时钟进行字对齐。最后，将数据进行8b/10b解码，供系统使用。
在时钟数据恢复器系统中，发送和接收系统通常拥有完全独立的系统时钟。这两个时钟在一个特定的变化范围内非常关键，这个范围大约是数百个PPM。
所述光接收模块设置为单通道。
所述共用模块包括电源控制器、直流偏置、逻辑控制器、串行接口、存储器以及伪随机数据发生器和校验器；所述共用模块同时为所述光发射模块和所述光接收模块提供通信回路；
其中，电源控制器为光发射模块和光接收模块供电；
直流偏置应用于光接收模块中，调节信号输出的直流分量，也就是 说将整个输出信号上移或者下移。
逻辑控制器的应用例如第一/二数据选择器，通过相应的规则选择数字信号；
串行接口为光收发芯片内部或与外部连接的接口，可提高传输速度；
存储器用于存储光发射模块和光接收模块中的数据；
伪随机数据发生器和校验器用于检测模块的状态并对其校验，加强了各模块电路工作的稳定性和准确性。
图2示意性示出根据本发明的四通道高速低功耗光收发芯片的逻辑图：光发射模块和光接收模块的逻辑原理与图1所示的单通道高速低功耗光收发芯片相同。如图2所示的四通道高速低功耗光收发芯片的每个通道都设置有光发射模块、光接收模块以及共用模块，可以同时通过多个光发射通道和多个光接收通道进行数据传输，提高了数据传输效率。
所述附图仅为示意性的并且未按比例画出。虽然已经结合优选实施例对本发明进行了描述，但应当理解本发明的保护范围并不局限于这里所描述的实施例。
结合这里披露的本发明的说明和实践，本发明的其他实施例对于本领域技术人员都是易于想到和理解的。说明和实施例仅被认为是示例性的，本发明的真正范围和主旨均由权利要求所限定。

Claims (10)

  1. 一种单通道高速低功耗光收发芯片，其特征在于：包括光发射模块、光接收模块以及共用模块，其中：
    所述光发射模块包括数据缓冲器、第一时钟数据恢复器、第一数据选择器、激光驱动器、功率控制器、第一时钟缓冲器以及发光二极管和第一光电二极管，其中：
    所述数据缓冲器将输入数据通过所述第一时钟数据恢复器传输至所述第一数据选择器；
    所述第一时钟缓冲器与所述第一时钟数据恢复器连接，用于时钟的输出；
    输入数据通过所述第一数据选择器选择后传输至所述激光驱动器进行数据输出，所述激光驱动器将数字信号转化为电压信号；
    所述电压信号通过所述发光二极管转化为光信号，并且由监测输入端的所述第一光电二极管接收，将光信号转化为电压信号，输入至所述功率控制器；
    所述功率控制器与所述激光驱动器相连接，用于反馈并调整所述激光驱动器输出的电压信号；
    所述光发射模块设置为一个通道；
    所述光接收模块包括第二光电二极管、直流偏置模块、跨导放大器、反馈电阻、第二时钟数据恢复器、第二时钟缓存器、第二数据选择器、输出驱动器，其中：
    所述第二光电二极管将接收的光信号转化成电信号并导通，所述直流偏置模块用于向所述光接收模块供电；
    所述跨导放大器将接收端的电流信号转化为电压信号传输至所述第二时钟数据恢复器；所述跨导放大器并联所述反馈电阻，用于调节所述跨导放大器中的电信号；所述第二时钟数据恢复器连接所述第二时钟缓冲器，用于输出时钟；
    通过所述第二数据选择器将电压信号输入至所述输出驱动器；
    所述输出驱动器将电压信号转化为数字信号进行输出；
    所述光接收模块设置为一个通道；
    所述共用模块包括电源控制器、直流偏置、逻辑控制器、串行接口、存储器以及伪随机数据发生器和校验器；所述共用模块同时为所述光发射模块和所述光接收模块提供通信回路。
  2. 一种四通道高速低功耗光收发芯片，其特征在于：每个通道都包括光发射模块、光接收模块以及共用模块，其中：
    所述光发射模块包括数据缓冲器、第一时钟数据恢复器、第一数据选择器、激光驱动器、功率控制器、第一时钟缓冲器以及发光二极管和第一光电二极管，其中：
    所述数据缓冲器将输入数据通过所述第一时钟数据恢复器传输至所述第一数据选择器；
    所述第一时钟缓冲器与所述第一时钟数据恢复器连接，用于时钟的输出；
    输入数据通过所述第一数据选择器选择后传输至所述激光驱动器进行数据输出，所述激光驱动器将数字信号转化为电压信号；
    所述电压信号通过所述发光二极管转化为光信号，并且由监测输入端的所述第一光电二极管接收，将光信号转化为电压信号，输入至所述功率控制器；
    所述功率控制器与所述激光驱动器相连接，用于反馈并调整所述激光驱动器输出的电压信号；
    所述光接收模块包括第二光电二极管、直流偏置模块、跨导放大器、反馈电阻、第二时钟数据恢复器、第二时钟缓存器、第二数据选择器、输出驱动器，其中：
    所述第二光电二极管将接收的光信号转化成电信号并导通，所述直流偏置模块用于向所述光接收模块供电；
    所述跨导放大器将接收端的电流信号转化为电压信号传输至所述第二时钟数据恢复器；所述跨导放大器并联所述反馈电阻，用于调节所述跨导放大器中的电信号；所述第二时钟数据恢复器连接所述第二时钟缓 冲器，用于输出时钟；
    通过所述第二数据选择器将电压信号输入至所述输出驱动器；
    所述输出驱动器将电压信号转化为数字信号进行输出；
    所述共用模块包括电源控制器、直流偏置、逻辑控制器、串行接口、存储器以及伪随机数据发生器和校验器；所述共用模块同时为所述光发射模块和所述光接收模块提供通信回路。
  3. 根据权利要求1或2所述的光收发芯片，其特征在于：所述功率控制器包括电流电压转换电路以及10位时钟数据恢复电路。
  4. 根据权利要求1或2所述的光收发芯片，其特征在于：所述激光驱动器的基极电流Ibase范围为0-80mA；驱动/调制电流Imod范围为0-80mA。
  5. 根据权利要求1或2所述的光收发芯片，其特征在于：所述数据缓冲器最大增益值为30db，最大boost值为20db。
  6. 根据权利要求1或2所述的光收发芯片，其特征在于：所述第一时钟缓冲器的接口采用CML结构，负载50Ω。
  7. 根据权利要求1或2所述的光收发芯片，其特征在于：所述第一时钟数据恢复器的带宽范围为1KHZ-200MHZ。
  8. 根据权利要求1或2所述的光收发芯片，其特征在于：所述跨阻放大器增益范围为0-100db。
  9. 根据权利要求1或2所述的光收发芯片，其特征在于：所述第二光电二极管最大输入共模电流为10mA。
  10. 根据权利要求1或2所述的光收发芯片，其特征在于：所述第二时钟缓存器的差分输出阻抗为100Ω。
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