WO2018038098A1 - Dispositif de mémoire - Google Patents

Dispositif de mémoire Download PDF

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Publication number
WO2018038098A1
WO2018038098A1 PCT/JP2017/029923 JP2017029923W WO2018038098A1 WO 2018038098 A1 WO2018038098 A1 WO 2018038098A1 JP 2017029923 W JP2017029923 W JP 2017029923W WO 2018038098 A1 WO2018038098 A1 WO 2018038098A1
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Prior art keywords
nanocluster
memory device
nanoclusters
charge retention
layer
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PCT/JP2017/029923
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English (en)
Japanese (ja)
Inventor
敦 中嶋
英加 舘田
義夫 渡辺
直之 平田
雄一 根岸
実奈子 佐藤
寛規 角山
高穂 横山
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国立研究開発法人科学技術振興機構
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Definitions

  • the present invention relates to a memory device.
  • This application claims priority on August 22, 2016 based on Japanese Patent Application No. 2016-162048 for which it applied to Japan, and uses the content for it here.
  • Flash memory is known as non-volatile memory.
  • the flash memory has a floating gate and stores charges in the floating gate.
  • the flash memory records data depending on whether or not electric charges are held in the floating gate, and reads data by detecting it.
  • Patent Document 1 describes a memory device using nanodots as a floating gate. By using nanodots, the device is downsized and the operating voltage is reduced.
  • Patent Document 3 describes a memory device that uses fullerenes or clusters as floating gates, and the fullerenes or clusters form a dimer during charge accumulation.
  • Non-Patent Document 1 describes a memory device using carbon nanotubes
  • Non-Patent Document 2 describes a memory device using a nanocomposite material.
  • an organic memory using an organic semiconductor for an active layer is known (see, for example, Patent Document 4 and Patent Document 5).
  • JP 2007-73961 A Japanese Patent No. 5493139 Japanese Patent Laying-Open No. 2015-128192 JP 2008-166710 A JP 2009-538525 A
  • Patent Document 1 and Non-Patent Documents 1 and 2 have a narrow hysteresis width. For this reason, data to be recorded may be rewritten by slight fluctuations in the voltage applied during data writing and rewriting. That is, the memory device described in Patent Document 1 cannot be said to have sufficient data reliability. Even if data can be saved without fail, precise control of the applied voltage is required.
  • nanodots tend to aggregate particles, and physical properties change when they aggregate. For this reason, the memory device characteristics such as the threshold value and the electron holding time vary.
  • the present invention has been made in view of the above circumstances, and an object thereof is to provide a memory device using nanoclusters.
  • the present inventors have found that the hysteresis width can be changed by using nanoclusters in the charge retention layer (floating gate) and changing the number of atoms constituting the nanocluster (hereinafter referred to as cluster size). That is, in order to solve the above problems, the present invention employs the following means.
  • the memory device includes a semiconductor unit, a first insulating layer, a charge holding layer, a second insulating layer, and an electrode in order, and the charge holding layer includes predetermined atoms. It mainly contains a number of nanoclusters.
  • the nanoclusters may be arranged discretely.
  • a nanocluster having a predetermined number of atoms may be 5% or more.
  • the nanocluster may be a metal, an alloy, a metal oxide, a semiconductor, a ceramic, or a composite nanocluster thereof.
  • the constituent unit of the nanocluster may include one or more elements selected from the group consisting of Au, Ag, Pt, Pd, Ti, Al, Ta, Mo, and W. .
  • the nanocluster may be a metal ion inclusion cluster represented by M @ Si.
  • the nanocluster includes a composite nanocluster of Ta and Si, a composite nanocluster of Ti and Si, a composite nanocluster of Ru and Si, a composite nanocluster of Lu and Si, and Mo Either a composite nanocluster of Si or a composite nanocluster of W and Si may be used.
  • the nanocluster may have an organic ligand on a surface thereof.
  • the organic ligand may form a monomolecular film on the surface of the nanocluster.
  • the organic ligand may have a structure represented by a chemical formula RnX.
  • R is an alkyl group, allyl group, alkynyl group, aryl group, alkenyl group, silyl group, aralkyl group or alkoxysilyl group
  • X is sulfur, selenium, phosphorus or nitrogen
  • n is a natural number It is.
  • the nanocluster having the organic ligand may be any one of Au 25 (SR) 18 , Au 38 (SR) 24 , and Au 144 (SR) 60. .
  • the charge retention layer may include a nanocluster film arranged in a layered manner.
  • the second insulating layer may include a fluororesin.
  • the second insulating layer has a water absorption rate of less than 0.02% and an oxygen transmission coefficient of 2.0 ⁇ 10 ⁇ 9 cm 3 ⁇ cm / cm 2 ⁇ s ⁇ . It may be less than cmHg.
  • the surface density of the nanoclusters in the charge retention layer may be 1 ⁇ 10 12 pieces / cm 2 to 3 ⁇ 10 14 pieces / cm 2 .
  • the charge retention layer may have discrete electron levels due to the nanoclusters.
  • FIG. 1 is a schematic cross-sectional view of a memory device according to a first embodiment. It is a cross-sectional schematic diagram of another example of the memory device according to the first embodiment. It is a cross-sectional schematic diagram of another example of the memory device according to the first embodiment. It is a cross-sectional schematic diagram of another example of the memory device according to the first embodiment. It is a cross-sectional schematic diagram of the organic memory which is another example of the memory device concerning 1st Embodiment. It is a schematic diagram for demonstrating LB method. The results of the CV characteristics of the memory devices of Examples 1 to 3 and Comparative Example 1 are shown. The temperature dependency evaluation results of the memory devices of Examples 1 to 3 and Comparative Example 1 are shown. It is the graph which processed the graph of Example 2.
  • FIG. It is a mass spectrum of the nanocluster in the gas phase which produced
  • 1 is a mass spectrum of a sample obtained by column purification of a nanocluster dispersion produced using the method for producing a nanocluster dispersion according to one embodiment of the present invention, (a) is an overall image of the mass spectrum, and (b) is It is the enlarged view which expanded the peak part. It is a high performance liquid chromatograph of single component polystyrene.
  • FIG. 10 is a diagram showing the results of CV characteristics of the memory device of Example 4.
  • FIG. 10 is a diagram showing the results of CV characteristics of the memory device of Example 5.
  • (A) is a CV characteristic of a memory device in which Au 38 (SR) 24 is a single layer or less and constitutes a charge retention layer, and (b) is a charge retention layer with two or three nanoclusters Au 38 (SR) 24 5 is a CV characteristic of a memory device that constitutes.
  • Au 25 (SR) 18 R is C 12 H 25
  • Au 25 (SR) 18 R is C 2 H 4 Ph
  • a CV curve for explaining the concept of the operation principle and a schematic cross-sectional view of the memory device of the present invention are shown.
  • FIG. 1 is a schematic cross-sectional view of a memory device 10 according to the first embodiment.
  • a memory device 10 shown in FIG. 1 includes a semiconductor portion 1, a first insulating layer 2, a charge retention layer 3, a second insulating layer 4, and an electrode 5 in this order.
  • the memory device 10 shown in FIG. 1 has a counter electrode 6 on the surface opposite to the electrode 5.
  • the “prepared in order” configuration means that the semiconductor section, the first insulating layer, the charge retention layer, the second insulating layer, and the electrode take any vertical cross section (a cross section cut up and down in FIG. 1). It is not limited to the configuration provided in order, but means “substantially in order” so that the function of each component is exhibited.
  • the memory device 10 is a storage element that accumulates charges (electrons or holes) in the charge retention layer 3 sandwiched between the first insulating layer 2 and the second insulating layer 4. Electric charges are transferred from the semiconductor unit 1 through the first insulating layer 2 due to a potential difference between the electrode 5 and the counter electrode 6.
  • a known inorganic semiconductor or organic semiconductor can be used as the material constituting the semiconductor portion 1.
  • silicon, polysilicon, or the like can be used as the inorganic semiconductor.
  • organic semiconductor pentacene, polythiophene, rubrene, tetrathiafulvalene, or the like can be used.
  • the electrical resistivity of the semiconductor part 1 is preferably about 1 to 2 ⁇ cm.
  • other components first insulating layer, second insulating layer, charge retention layer, electrode
  • the first insulating layer 2 is an insulating layer that separates the semiconductor portion 1 and the charge retention layer 3.
  • the first insulating layer 2 is electrically a tunnel barrier when electric charges reach the charge holding layer 3 from the semiconductor portion 1. If the potential difference between the electrode 5 and the counter electrode 6 is as large as possible to pass through the tunnel barrier, the charge can reach the charge holding layer 3, and if not so large as to pass through the tunnel barrier, the charge reaches the charge holding layer 3. I can't.
  • the material constituting the first insulating layer (tunnel barrier layer) 2 a known insulating inorganic material or organic material can be used.
  • silicon oxide or the like can be used as the inorganic material.
  • the thickness of the first insulating layer 2 is preferably 5 nm to 50 nm, more preferably 10 nm to 30 nm. If the thickness is too thin, the function as an insulating film cannot be obtained sufficiently, and if the thickness is too thick, the insulating property becomes high and accumulated charges are more difficult to escape, but it is necessary to increase the potential difference for passing through the tunnel barrier. .
  • the memory device is designed so that the organic ligand arranged between the nanocluster and the semiconductor part constitutes the first insulating layer (tunnel barrier layer) Alternatively, even in this case, a first insulating layer (tunnel barrier layer) may be separately provided.
  • the charge retention layer 3 is a portion that retains charges and accumulates data.
  • the charge retention layer 3 includes nanoclusters 30.
  • the nanoclusters 30 included in the charge retention layer 3 mainly have a predetermined number of atoms.
  • the charge retention layer 3 may be composed of only nanoclusters, or may be composed of nanoclusters dispersed in an insulating material, or composed of nanoclusters and organic ligands attached to the surface thereof. It may be.
  • the nanocluster 30 is larger than the atomic molecule and smaller than the bulk solid. Therefore, by using the nanocluster 30 for the charge retention layer 3 of the memory device 10, the memory device 10 can be miniaturized.
  • the nanocluster 30 is an ultrafine particle in which several to several thousand atoms or molecules are assembled. Therefore, the electron levels of the charge retention layer 3 including the nanoclusters 30 are discrete.
  • the charge injected into the charge retention layer 3 is an electron, it is buried in order from the low energy level of the discrete electron level, and when the charge injected into the charge retention layer 3 is a hole, The discrete energy levels are buried in order from the highest energy level. Therefore, when the degree of discreteness of the electron level is sufficiently large, the presence or absence of electrons or holes can be classified for each energy level. That is, it suggests the possibility of multi-valued memory device 10.
  • the nanoclusters 30 included in the charge retention layer 3 mainly include nanoclusters having a predetermined number of atoms.
  • the nanocluster 30 has a large change in properties due to the increase or decrease of one atom. Therefore, the charge retention characteristic is stabilized by mainly including the nanoclusters 30 having the same number of atoms in the charge retention layer 3.
  • a peak is observed when the horizontal axis is the number of nanocluster atoms and the vertical axis is the number (signal intensity).
  • the number of atoms at which the peak occurs is the predetermined number of atoms.
  • the number of peaks that occur is not limited to one.
  • the number of atoms in the nanocluster affects the size of the nanocluster. Therefore, “a nanocluster having a predetermined number of atoms” can be rephrased as “a nanocluster having a uniform cluster size”.
  • the peak of the nanocluster 30 can be confirmed by measuring the nanocluster dispersion used for the preparation of the charge retention layer 3 by thin layer chromatography, high performance liquid chromatography (HPLC) or the like.
  • the portion with the strongest signal intensity is the peak (hereinafter referred to as the first peak).
  • strength of the 1st peak is made into a threshold value, and the part exceeding this threshold value is also a peak. That is, there may be a plurality of peaks.
  • the ratio of nanoclusters having a predetermined number of atoms is preferably 5% or more of the whole nanoclusters, more preferably 10% or more, and more preferably 20% or more. Is more preferable.
  • a nanocluster having a predetermined number of atoms is obtained by aggregating neutral atoms and atomic ions generated by magnetron sputtering in a gas phase. By condensing in the gas phase, the number of atoms constituting the nanocluster is controlled.
  • Patent Document 2 describes a specific method for condensing neutral atoms and atomic ions in the gas phase.
  • the nanoclusters obtained by the above method may be separated by column chromatography, recrystallization method, or the like, and the ratio of nanoclusters having a predetermined number of atoms in the whole nanoclusters 30 may be further increased.
  • the number of nanoclusters having a predetermined number of atoms is 5% or more of the total number of nanoclusters. For example, assuming that there is 100 g of a nanocluster dispersion having a concentration of 1% by weight used when the charge retention layer 3 is produced, the weight of the nanocluster contained in the dispersion is 1 g. Of these, 5% (50 mg) are nanoclusters having a predetermined number of atoms. Since the number of atoms contained in 1 mol of the substance is 6.02 ⁇ 10 23 (Avocado number), the number of nanoclusters having a predetermined number of atoms is about 6.02 ⁇ 10 18 to 6.02 ⁇ 10 19. It becomes.
  • the number of atoms constituting the nanocluster 30 is not particularly limited. It has been experimentally confirmed that the hysteresis width in the CV (capacitance-voltage) characteristic of the memory device 10 increases as the number of atoms constituting the nanocluster 30, that is, the cluster size increases.
  • nanocluster 30 various types can be used as long as they can hold electrons.
  • a nanocluster of a metal, an alloy, a metal oxide, a semiconductor, ceramics, or a composite thereof can be used.
  • metal nanoclusters composed of a single metal element, alloy nanoclusters composed of a plurality of metal elements as constituent elements, semiconductor nanoclusters containing silicon as a constituent element, and the like can be used.
  • the structural unit of the nanocluster 30 preferably contains one or more elements selected from the group consisting of Au, Ag, Pt, Pd, Ti, Al, Ta, Mo, and W.
  • Conductive nanoclusters can in principle generate nanoclusters in the gas phase by sputtering. Among them, those containing these elements are easy to produce, and production has been confirmed experimentally.
  • the nanocluster 30 has an organic ligand on the surface.
  • the organic ligand more preferably forms a monomolecular film on the surface of the nanocluster 30 and covers the surface of the nanocluster 30. The presence of the organic ligand on the surface of the nanocluster 30 avoids aggregation of the nanoclusters 30.
  • the organic ligand portion disposed between the semiconductor portion 1 and the nanocluster 30 among the organic ligands constitutes the first insulating layer 2.
  • the portion of the organic ligand arranged between the electrode 5 and the nanocluster 30 constitutes the second insulating layer 4.
  • the first insulating layer 2 includes only the organic ligand, the layer including the organic ligand, and another insulating material.
  • the second insulating layer 4 may be composed of the organic ligand, and the second insulating layer 4 may be composed of a layer composed of the organic ligand and a layer composed of another insulating material. .
  • the organic ligand preferably has a structure represented by the chemical formula RnX.
  • R is an alkyl group, an allyl group, an alkynyl group, or an aryl group
  • X is sulfur, selenium, phosphorus, or nitrogen
  • n is a natural number.
  • Specific examples include alkanethiolate, arylthiolate, alkaneselenolate, arylselenolate, triarylphosphine and the like.
  • Examples of the nanocluster having an organic ligand include Au 25 (SR) 18 , Au 38 (SR) 24 , Au 144 (SR) 60 , Au 28 (SR) 20 , Au 30 (SR) 18 , and Au 36.
  • R is an alkyl group represented by C 12 H 25
  • S is sulfur.
  • the nanocluster 30 used in the memory device 10 according to the present embodiment there is a metal ion inclusion nanocluster represented by M @ Si.
  • M means a metal ion
  • @ indicates that the metal ion is included.
  • Ta and Si composite nanoclusters Ta and Si composite nanoclusters, Ti and Si composite nanoclusters, Ru and Si composite nanoclusters, Lu and Si composite nanoclusters, Mo and Si composite nanoclusters, W
  • a composite nanocluster of Si and Si is particularly characteristic.
  • Specific examples of the nanocluster 30 include TaSi 16 and TiSi 16 .
  • the neutral atoms or atomic ions constituting these composite nanoclusters have a higher ionization tendency than Ag and are less likely to aggregate in the liquid phase. Therefore, these neutral atoms or atomic ions cannot be generated by a method of aggregating in the liquid phase to generate nanoclusters. That is, as described in Patent Document 2, it can be produced for the first time by using a method of agglomerating in a gas phase to obtain nanoclusters. Therefore, an example of using the composite nanoclusters such TaSi 16, TiSi 16 in the charge holding layer 3 is not known.
  • the nanoclusters 30 in the charge retention layer 3 are arranged in layers to form a nanocluster film.
  • the nanoclusters 30 are arranged in layers, the variation in the charge retention characteristics for each memory device 10 is reduced.
  • FIG. 1 illustrates an example of a nanocluster in which the charge retention layer 3 is arranged in one layer
  • the nanocluster 30 may be stacked in a plurality of layers as in the memory device 11 illustrated in FIG.
  • the surface density of the nanoclusters 30 in the charge retention layer 3 is preferably 1 ⁇ 10 12 pieces / cm 2 to 3 ⁇ 10 14 pieces / cm 2 . This is because the variation from element to element can be reduced by packing the nanoclusters closely.
  • the second insulating layer 4 is an insulating layer that blocks electrons accumulated in the charge retention layer 3 from flowing to the electrode 5.
  • the material used for the second insulating layer 4 may be an inorganic material or an organic material as long as it has insulating properties.
  • a fluororesin when an organic material is used, it is preferable to include a fluororesin.
  • Specific examples of the fluororesin include CYTOP (registered trademark) manufactured by Asahi Glass Co., Ltd.
  • the fluororesin has water repellency and can prevent the second insulating layer 4 from containing water.
  • the specific water absorption rate of the second insulating layer 4 is preferably less than 0.02%.
  • the oxygen permeability coefficient of the second insulating layer 4 is preferably less than 2 ⁇ 10 ⁇ 9 cm 3 ⁇ cm / cm 2 ⁇ s ⁇ cmHg. This is because, in addition to reducing the amount of oxygen that can participate in charge transfer and stabilizing the charge retention amount, it is possible to reduce the chemical change of the charge retention layer due to oxidation. It is important to stabilize device functions.
  • the dielectric constant of the second insulating layer 4 is not too large. If the dielectric constant is too large, it is necessary to unnecessarily increase the voltage in writing and erasing to the charge retention layer, and voltage application becomes difficult. Therefore, an example of the dielectric constant of the second insulating layer 4 is preferably 4.0 or less.
  • the glass transition temperature of the second insulating layer 4 is preferably not too low. If the glass transition temperature is too low, the stable operation may be impaired depending on the temperature of the usage environment of the device. Therefore, it is preferable that it is 80 degreeC or more as an example of the glass transition temperature of the 2nd insulating layer 4. FIG.
  • the electrode 5 and the counter electrode 6 may be made of a known electrode material and are not particularly limited as long as they have conductivity.
  • the electrode 5 may be a gold electrode and the counter electrode 6 may be an aluminum electrode.
  • the counter electrode 6 may be grounded if a potential difference can be generated between the semiconductor portion 1 and the charge retention layer 3.
  • FIG. 3 is a diagram illustrating another example of the memory device according to the present embodiment.
  • the memory device 12 may be configured such that the electrode 5 is divided into a plurality of parts and the electrode 5 a corresponding to each nanocluster 30 is provided.
  • a memory device 13 having a MOSFET structure in which a source electrode 7 and a drain electrode 8 are provided may be used. Further, as shown in FIG.
  • the nanocluster 30 has an organic ligand 31 on the surface
  • the first insulating layer 2 is composed only of the organic ligand
  • the second insulating layer 4 is also composed of the organic ligand.
  • the memory device 14 may be configured by the charge retention layer 3 including the nanocluster 30 and the organic ligand 31 attached to the surface thereof.
  • the first insulating layer 2, the charge retention layer 3, and the second insulating layer 4 are based on the functions of the respective layers, and the layers formed by the nanoclusters 30 having the organic ligands 31 are configured as follows: Virtually assigned to each of the first insulating layer 2, the charge holding layer 3, and the second insulating layer 4, the operating principle of the memory device is the same as that shown in FIGS. .
  • the memory device of the present invention can be said to be a floating gate memory using nanoclusters as a floating gate based on its operating principle.
  • the presence / absence of charge accumulated in the nanocluster is read out by detecting the difference in the magnitude of the current flowing through the source electrode 6 and the drain electrode 7 shown in FIG. Data can be written and read in the same way as a memory.
  • FIG. 18 shows a CV curve for explaining the concept of the operation principle, and a cross-sectional schematic diagram of the memory device of the present invention.
  • the CV curve in FIG. 18 is a case where the semiconductor portion 1 is made of a p-type semiconductor.
  • the two solid curves are the CV curve (L 1 ) when the gate voltage Vgate is swept from 10 V to ⁇ 10 V, and the CV curve (L 2 ) when the gate voltage Vgate is swept from ⁇ 10 V to 10 V, respectively. ).
  • the dotted curve shows a CV curve (L 0 ) when the nanocluster has no charge and is electrically neutral.
  • the CV curve (L 1 ) when the gate voltage Vgate is swept from 10 V to ⁇ 10 V is compared with the CV curve (L 0 ) when the nanocluster has no charge and is electrically neutral.
  • the shift from the CV curve (L 1 ) to the negative voltage side indicates electron emission from the nanocluster, ie, hole injection into the nanocluster.
  • the CV curve (L 2 ) when the gate voltage Vgate is swept from ⁇ 10 V to 10 V is compared with the CV curve (L 0 ) when the nanocluster has no charge and is electrically neutral.
  • the shift from the CV curve (L 1 ) to the positive voltage side indicates electron injection into the nanocluster. If the nanocluster has no charge, such hysteresis does not appear. The larger the hysteresis, the more stable charge can be accumulated and the higher the memory characteristics.
  • the injection (tunneling) of charges into the nanocluster is based on the difference in thickness (based on the thickness of the effective tunnel barrier), via the first insulating film. It can be inferred that there is a case where it is performed and a case where it is performed via the second insulating film.
  • the memory device of the present invention may include a support substrate.
  • the support substrate can be provided between the semiconductor unit 1 and the counter electrode 6 or on the side of the counter electrode 6 that does not include the semiconductor unit 1.
  • a known inorganic material or organic material can be used.
  • the support substrate made of an inorganic material include glass, plastic, quartz, metal foil, undoped silicon and highly doped silicon, and transparent electrode materials such as indium tin oxide (ITO).
  • ITO indium tin oxide
  • the support substrate for organic materials include rigid or flexible materials such as synthetic resins such as polyethylene terephthalate (PET) and polyimide (PI), engineering plastics such as polyacetal (POM), and natural polymers such as cellulose. it can.
  • an organic memory is configured as an example of the memory device of the present invention
  • a manufacturing technique such as a wet process or a printable process cultivated with an organic EL can be used.
  • FIG. 5 shows an example of an organic memory as the memory device of the present invention.
  • the organic memory 100 is attached to the surface of the support substrate 110, the counter electrode 106 disposed on the support substrate 110, the semiconductor portion 101 made of an organic semiconductor formed to cover the counter electrode 106, and the nanocluster 130.
  • the first insulating layer 102 made of a part of the organic ligand 131, the plurality of nanoclusters 130, the charge retention layer 103 made of a part of the organic ligand 131 attached to the surface thereof, and the surface of the nanocluster 130
  • a second insulating layer 104 including a layer 104B made of a part of the attached organic ligand 131 and an insulating layer 104A different therefrom, and an electrode 105 are provided.
  • the support substrate 110 may be made of polyethylene terephthalate (PET) having flexibility.
  • PET polyethylene terephthalate
  • the semiconductor portion 101 made of an organic semiconductor, for example, pentacene, polythiophene, or the like may be used.
  • the insulating layer 104A constituting the second insulating layer 104 for example, a fluororesin may be used.
  • the first insulating layer 102 is made of a part of the organic ligand 131 attached to the surface of the nanocluster 130, but in addition to this, for example, an insulating layer made of fluorine resin or the like is used. You may prepare.
  • the counter electrode 6 is formed on one surface of the semiconductor (semiconductor part 1).
  • the counter electrode 6 can be formed by a known means such as sputtering.
  • the 1st insulating layer 2 is formed in the surface on the opposite side to the surface in which the counter electrode 6 of the semiconductor part 1 was formed.
  • the semiconductor part 1 is an inorganic material
  • the first insulating layer 2 can also be obtained by thermally oxidizing one surface of the semiconductor part 1.
  • the charge retention layer 3 including the nanoclusters 30 is formed on the first insulating layer 2.
  • nanoclusters having a predetermined number of atoms are mainly produced in a gas phase.
  • the nanoclusters generated by the apparatus have a cluster size (number of nanocluster atoms) controlled with extremely high accuracy. “High accuracy” means that the proportion of nanoclusters with a cluster size that represents a representative peak selected from the mass spectrum peaks of nanoclusters generated in the gas phase accounts for 5% or more of the total nanoclusters generated. means.
  • a nanocluster having a predetermined number of atoms protected by an organic ligand can be obtained, for example, using a chemical reduction method.
  • a toluene container containing a phase transfer reagent eg, tetraoctyl ammonium bromide; (C 8 H 17 ) 4 NBr
  • a phase transfer reagent eg, tetraoctyl ammonium bromide; (C 8 H 17 ) 4 NBr
  • a metal precursor eg, chloroauric acid HAuCl 4
  • a protective ligand eg alkanethiol; C n H 2n + 1 SH
  • a reducing reagent for example, sodium borohydride; NaBH 4
  • NaBH 4 sodium borohydride
  • the produced organic protected nanoclusters are fractionated into organic protected nanoclusters having a predetermined number of metal atoms by liquid chromatography, recrystallization method or the like.
  • the nanocluster species to be generated Any material that aggregates in the gas phase may be used, for example, a metal nanocluster whose constituent element is a single metal element, an alloy nanocluster whose constituent element is a plurality of metal elements, a semiconductor nanocluster containing silicon as a constituent element, etc. Can be generated. More specifically, the metal nanoclusters are Pt, Au, Ag, Cu, Cr, Ti, Fe and other nanoclusters, the alloy nanoclusters are CoPt, FePt and other nanoclusters, and the semiconductor clusters are Si, TaSi. TiSi, RuSi, WSi, MoSi, etc. can be generated.
  • the semiconductor cluster includes a metal ion-encapsulated nanocluster represented by M @ Si.
  • nanoclusters cannot be generated unless the ionization tendency is small (easily reduced) and the elements are easy to aggregate. Therefore, nanocluster species represented by M @ Si such as TaSi, TiSi, RuSi, WSi, and MoSi cannot be generated. If the temperature, stirring conditions, additive amount, and the like are different, the distribution of nanocluster sizes becomes wide, and nanoclusters with uniform cluster sizes cannot be obtained efficiently.
  • vapor-phase nanoclusters are collected on a solid substrate.
  • the nanoclusters generated in the gas phase may be collected in a dispersion medium (liquid phase).
  • the dispersion medium on which the nanoclusters are incident When collecting the nanoclusters in the liquid phase, it is preferable to flow the dispersion medium on which the nanoclusters are incident. Nanoclusters are incident on the dispersion medium at a high frequency. Therefore, if the dispersion medium is not flowed, the nanoclusters incident on the dispersion medium may aggregate together in the liquid surface or in the liquid. By causing the dispersion medium on which the nanoclusters are incident to flow, it is possible to suppress the local increase of the nanocluster concentration in the dispersion medium surface and the dispersion medium, and to increase the dispersibility of the nanoclusters.
  • nanoclusters When collecting nanoclusters in the liquid phase, it is the surface of the dispersion that is most likely to aggregate the nanoclusters. This is because the nanoclusters receive resistance when they enter the liquid surface, and the speed of the nanoclusters once decreases on the surface of the dispersion.
  • the dispersion medium when collecting the nanoclusters in the liquid phase, it is preferable to cause the dispersion medium to flow so that the nanocluster density on the surface of the dispersion medium is below the aggregation limit.
  • the aggregation limit means a density at which nanoclusters do not contact each other on the surface of the dispersion medium. For example, when the size of the nanocluster is 1 nm in diameter, if there are 10 14 or more nanoclusters in 1 cm 2 , the nanoclusters come into contact with each other. When the nanoclusters come into contact with each other, they do not aggregate immediately, but when the nanocluster size is 1 nm in diameter, the nanocluster density on the surface of the dispersion medium is preferably 10 14 / cm 2 or less.
  • the nanocluster density on the surface of the dispersion medium is greatly influenced by the incident flux of the nanocluster.
  • the incident flux means the number of nanocluster particles incident on 1 cm 2 per second. If the incident flux is fast, it is preferable to increase the flow rate. If the incident flux is slow, it is not necessary to increase the stirring speed so much. In any case, aggregation of nanoclusters can be further suppressed by flowing the dispersion medium so that the nanocluster density on the surface of the dispersion medium is equal to or less than the aggregation limit.
  • nanoclusters enter the dispersion.
  • the incident amount when the dispersion medium is stationary is 2.8 ⁇ 10 14 particles / sec ⁇ cm 2.
  • the nanocluster density on the surface of the dispersion medium is 10 It can be made 14 or less.
  • the surface speed of the nanocluster dispersion is preferably 20 cm / sec or more, and more preferably 100 cm / sec or more.
  • the method of flowing the dispersion medium on which the nanoclusters are incident is not particularly limited.
  • a stirrer or a rotating body can be used.
  • the dispersion medium for entering the nanocluster use one of the group consisting of chain ether, cyclic ether, chain siloxane, cyclic siloxane, nitriles, haloalkanes, alcohols, amides, sulfoxides and benzene derivatives. Is preferred.
  • These dispersion media have been experimentally confirmed that the nanoclusters do not re-aggregate even if the dispersion liquid after the nanoclusters are dispersed is left for a long time. That is, it can be stably maintained in the state of the nanocluster dispersion.
  • these dispersion media include, for example, polyethylene glycol, polypropylene glycol, methoxypolyethylene glycol as a chain ether, polydimethylsiloxane, polymethylphenylsiloxane as a chain siloxane, and hexamethylcyclotrisiloxane, deca Methylcyclohexasiloxane, cyclic ether as tetrahydrofuran, crown ether, nitriles as acetonitrile or benzonitrile, haloalkanes as chloroform, dichloromethane, alcohols as methanol, ethanol, benzene derivatives as toluene, dichlorobenzene .
  • nanoclusters are generated in the gas phase between the step of generating the nanoclusters in the gas phase and the step of collecting the nanoclusters in the liquid phase.
  • a detection step for confirming that nanoclusters are generated in the gas phase it can be confirmed that atoms or molecules are aggregated in the liquid phase and nanoclusters are not generated.
  • the nanocluster size is dispersed, and it becomes difficult to obtain nanoclusters having a predetermined number of atoms.
  • Whether or not a predetermined nanocluster is generated in the gas phase can be confirmed, for example, by providing a probe plate in the process where the nanocluster generated in the gas phase reaches the dispersion.
  • a probe plate in the process where the nanocluster generated in the gas phase reaches the dispersion.
  • the probe plate is colored when the nanocluster is suitably generated, while the nanocluster is not suitably generated.
  • a transparent film is formed on the probe plate surface.
  • the charge retention layer 3 is formed using the obtained nanocluster 30 having a predetermined number of atoms.
  • the charge retention layer 3 can be produced using a Langmuir-Blodgett (LB) method or a coating method such as spin coating.
  • LB Langmuir-Blodgett
  • spin coating a coating method such as spin coating.
  • the ratio of nanoclusters with a predetermined number of atoms is 5% or more of the whole nanoclusters
  • the ratio of nanoclusters with a predetermined number of atoms constituting the obtained nanocluster dispersion film is , 5% or more of the entire nanocluster.
  • spray coating, dispenser coating, spin coating, knife coating, ink jet coating, screen printing, offset printing, die coating, and the like can be used.
  • the LB method is a method of copying the nanoclusters 30 developed on the water surface onto a substrate.
  • FIG. 6 is a schematic diagram for explaining the LB method.
  • the LB method is a dropping process in which a dispersion liquid in which nanoclusters 30 are dispersed in a solvent is dropped on the liquid surface in the water tank T, and a single film formation in which a monolayer film 31 composed of nanoclusters 30 is formed by volatilizing the solvent. And a transition step of transferring the single layer film 31 onto the temporary support 33. Each step will be specifically described below.
  • a dispersion mainly containing nanoclusters 30 having a predetermined number of atoms obtained by the above-described method is developed on water W stored in a water tank (dropping step). Then, the solvent as the dispersion medium volatilizes, and the nanocluster 30 develops on the water surface.
  • the partition wall 32 is moved closer to the center from the outer periphery of the water tank T on the surface of the water W. Then, the nanocluster 30 developed on the liquid surface of the water W is pushed by the partition wall 32 and gathers at the center of the water tank T. Then, the nanoclusters 30 gathered at the center receive the pressure of the partition walls 32 and spontaneously form a single layer film 31 aligned in a close-packed arrangement (single layer film forming step). The formation of the single layer film 31 can be determined by a change in the surface tension of the partition wall 32.
  • PDMS polydimethylsiloxane
  • the single layer film 31 is transferred from the temporary support 33 onto the first insulating layer 2.
  • a microcontact printing method can be used. In the microcontact printing method, adsorption is performed using the difference in charge between the single-layer film 31 including the nanoclusters 30 and the first insulating layer 2.
  • the single layer film 31 formed on the first insulating layer 2 functions as the charge retention layer 3.
  • the single layer film 31 is transferred onto the temporary support 33, and then the single layer film 31 on the temporary support 33 is transferred onto the first insulating layer 2.
  • the single layer film 31 may be directly transferred onto the first insulating layer 2 without using 33.
  • the spin coating method is the same as a known coating method.
  • the spin coating method it is difficult to obtain a single layer film of the nanoclusters 30, and as shown in FIG. 2, the charge retention layer 3 is a laminate of a plurality of nanoclusters 30.
  • the memory device 10 is obtained by sequentially stacking the second insulating layer 4 and the electrode 5 on the manufactured charge retention layer 3.
  • the second insulating layer 4 is obtained by applying a fluorine-based solvent on the charge retention layer 3 by a known coating method such as spin coating and removing the solvent.
  • the electrode 5 can be formed by a known means such as sputtering or a metal deposition cell (Knudsen cell).
  • manufacturing techniques such as a wet process and a printable process cultivated with organic EL can also be used.
  • a semiconductor portion made of an organic semiconductor such as pentacene or polythiophene can be formed on a supporting substrate by using a wet process, a printable process, or a vapor deposition method cultivated by organic EL.
  • the charge retention layer is formed of nanoclusters, so that the hysteresis width in the CV (capacitance-voltage) characteristic is widened.
  • the hysteresis width can be controlled by changing the nanocluster size (the number of atoms constituting the nanocluster).
  • the memory device can be miniaturized.
  • the memory device according to the present embodiment has a possibility that the memory device has multiple values because the charge retention layer has discrete electronic levels.
  • nanoclusters (nanoclusters with organic ligands) represented by Au 25 (SR) 18 were prepared.
  • R is C 12 H 25 .
  • the nanocluster was produced by the following procedure.
  • a toluene solution containing a phase transfer reagent (tetraoctyl ammonium bromide; (C 8 H 17 ) 4 NBr) was added to an aqueous solution of chloroauric acid (HAuCl 4 ) and stirred. By stirring, AuCl 4- was phase transferred into toluene.
  • the toluene solution was separated by a separatory funnel, and dodecanethiol (C 12 H 25 SH) was added thereto.
  • An aqueous solution of a reducing agent sodium borohydride; NaBH 4
  • Au 25 (SR) 18 was obtained by a recrystallization method.
  • the purity of Au 25 (SR) 18 nanoclusters identified by UV-visible absorption spectroscopy was 95% or higher.
  • a charge retention layer was produced using the nanoclusters thus obtained.
  • the charge retention layer was provided on the first insulating layer of the semiconductor portion.
  • the semiconductor portion was 0.5 mm thick silicon, and the first insulating layer was 20 nm silicon oxide.
  • An aluminum layer was provided as a counter electrode on the opposite side of the surface of the semiconductor portion where the charge retention layer was provided.
  • the charge retention layer was produced using the LB method.
  • the charge retention layer is a single layer film in which one nanocluster is arranged in the thickness direction.
  • the thickness of the charge retention layer is 4.5 nm.
  • the thickness of the charge retention layer was calculated from the sum of these diameters obtained by actually measuring the diameter of the Au nanocluster core by a transmission electron microscope and theoretically obtaining the length of the protective molecule (alkanethiolate). Chloroform was used to disperse the nanoclusters, and a charge retention layer was produced according to the procedure described above. The length of the theoretical protective molecule was determined based on known literature.
  • the second insulating layer was obtained by spin coating CYTOP (registered trademark) manufactured by Asahi Glass Co., Ltd. and heating. Cytop (registered trademark) has a water absorption of 0.01% or less, a dielectric constant of 2.0 to 2.1 (100 Hz to 1 MHz, room temperature), and an oxygen transmission coefficient of 8.34 ⁇ 10 ⁇ 10 cm. 3 ⁇ cm / cm 2 ⁇ s ⁇ cmHg, and the glass transition temperature is 108 ° C. The thickness of the second insulating layer was 150 nm. Finally, a gold film was formed as an electrode on the second insulating layer to manufacture a memory device.
  • CV capactance-voltage
  • the measurement environment was a vacuum ( ⁇ 2 ⁇ 10 ⁇ 3 Pa) at room temperature.
  • the measurement conditions were as follows. Sample size: 5 mm x 5 mm 4 locations (Au electrode 3 ⁇ ) Frequency: 1kHz to 1MHz Amplitude: AC100mV Sweep range: -10V to + 10V Sweep speed: 0.1V increments, each point 0.1V / 2sec
  • Example 2 In Example 2, a memory device was produced in the same manner as in Example 1 except that the nanocluster was Au 38 (SR) 24 . CV evaluation of the obtained memory device was performed. In the charge retention layer, the proportion of nanoclusters (Au38) having a predetermined cluster size in the entire nanocluster was 95% or more, and the thickness of the charge retention layer was 4.7 nm.
  • Example 3 a memory device was fabricated in the same manner as in Example 1 except that the nanocluster was Au 144 (SR) 60 . CV evaluation of the obtained memory device was performed. In the charge retention layer, the proportion of nanoclusters (Au 144 ) having a predetermined cluster size in the entire nanocluster was 95% or more, and the thickness of the charge retention layer was 5.1 nm.
  • Comparative Example 1 a memory device was fabricated in the same manner as in Example 1 except that nanoparticles having a particle size of about 3 nm (AuDT) were used in the charge retention layer without using nanoclusters. CV evaluation of the obtained memory device was performed.
  • FIG. 7 shows the results of the CV characteristics of the memory devices of Examples 1 to 3 and Comparative Example 1.
  • 7 (a) shows the results of Example 1
  • FIG. 7 (b) shows the results of Example 2
  • FIG. 7 (c) shows the results of Example 3
  • FIG. 7 (d) shows the comparative example. 1 result.
  • the vertical axis represents capacitance, and the horizontal axis represents applied voltage.
  • the memory device of Example 1 has a hysteresis width Vth of 0.35V
  • the memory device of Example 2 has a hysteresis width Vth of 1.7V
  • the memory device of Example 3 has a hysteresis width Vth of 0.62V.
  • the memory device of Comparative Example 1 had a hysteresis width Vth of 0.18V.
  • the hysteresis width is narrow when nanoparticles are used. For this reason, data to be recorded may be rewritten by slight fluctuations in the voltage applied during data writing and rewriting. In contrast, the hysteresis width can be increased by using nanoclusters in the charge retention layer.
  • the hysteresis width can be controlled by changing the number of atoms constituting the nanocluster (nanocluster size).
  • FIG. 8 shows the temperature dependence evaluation results of the memory devices of Examples 1 to 3 and Comparative Example 1.
  • the vertical axis is the hysteresis width.
  • FIG. 9 is a graph obtained by processing the graph of Example 2.
  • the graph represented by a dotted line is the same as FIG.
  • the graphs of Example 2 and Example 3 show multistage hysteresis behavior. Therefore, as shown in FIG. 9, the graph can be divided into three. That is, the injection / emission of electrons as carriers can be divided into three stages, suggesting the possibility of multi-leveling in two stages of “0 to 2”.
  • Example 4 the nanocluster was TaSi 16 .
  • TaSi 16 nanoclusters were generated in the gas phase. Nanoclusters generated in the gas phase were incident on a dispersion medium (polyethylene glycol dimethyl ether) stored in a storage container to obtain a nanocluster dispersion. The dispersion was transferred to an argon-substituted glove box, the dispersion medium was removed by recrystallization, and TaSi 16 nanoclusters were isolated. The proportion of TaSi 16 in the entire isolated nanocluster was 50% or more (from the results of elemental analysis and HPLC).
  • FIG. 10 is a mass spectrum of nanoclusters generated in the gas phase. It can be confirmed from the mass spectrum that the nanoclusters generated in the gas phase are TaSi 16 + .
  • FIG. 11 is a high performance liquid chromatogram (HPLC) of a nanocluster dispersion of TaSi.
  • the horizontal axis is the amount of solution supplied to the column, and the vertical axis is the absorbance.
  • As a dispersion medium polyethylene glycol dimethyl ether (PEG, molecular weight of about 250, boiling point of 250 ° C. or higher) substituted with an inert methyl group at the end is used, and TaSi n ⁇ , TaSi n + , and TaSi n ( 0) .
  • PEG polyethylene glycol dimethyl ether
  • the absorbance is measured with a spectrophotometer installed on the other side of the column.
  • a size exclusion column was used for the analysis.
  • the analytical column has a porous structure, and the speed of traveling through the analytical column varies depending on the nanocluster size. Smaller nanoclusters travel slower in the direction of travel, bypassing the interior of the porous structure, compared to larger nanoclusters, and therefore travel at a slower rate. Therefore, at a stage where the supply amount supplied into the analytical column is small, nanoclusters having a relatively large size (mass is large) are confirmed. Thereafter, as the supply amount of the solution increases, the nanocluster size decreases (mass decreases).
  • the HPLC spectrum shown in FIG. 11 represents the abundance ratio of the entire nanocluster included in the dispersion.
  • the horizontal axis represents the elution volume, that is, the cluster size
  • the vertical axis represents the absorbance, that is, the abundance of clusters. From the graph, the maximum peak can be confirmed on the horizontal axis of 8.5 mL (at a solvent supply rate of 0.5 mL / min, 17 minutes after supplying the solvent).
  • FIG. 12 is a mass spectrum of a sample obtained by column purification of a nanocluster dispersion, (a) is an overall image of the mass spectrum, and (b) is an enlarged view in which a peak portion is enlarged.
  • the mass spectra in FIGS. 12A and 12B were measured using the 8.5 mL portion of the sample in FIG.
  • the horizontal axis represents the m / z value obtained by dividing the mass number by the electric charge, and the vertical axis represents the detection intensity.
  • TaSi 13 ⁇ (m / z ⁇ 545 amu) and TaSi 14 ⁇ (m / z ⁇ 574 amu) are obtained.
  • TaSi 15 ⁇ (m / z ⁇ 602 amu) and TaSi 16 ⁇ (m / z ⁇ 630 amu) are generated.
  • These are considered to be dissociation products of TaSi 16 + . That is, the nanocluster showing a representative peak is TaSi 16 + , indicating that TaSi 16 + is included as a main component in the dispersion.
  • Si n ⁇ having a different size and composition has not been observed. That is, it can be confirmed from FIGS. 10 and 12A and 12B that the gas phase nanoclusters are dispersed in the dispersion medium without agglomeration.
  • the proportion of the confirmed nanoclusters (TaSi 16 + ) having a predetermined cluster size in the entire nanoclusters is calculated.
  • the calculation was performed according to the following procedure.
  • FIG. 13 is an HPLC of single component polystyrene.
  • the full width at half maximum of the peak obtained at this time was 0.63 mL, and the peak value was 8.28 mL.
  • Polystyrene having the same molecular weight was used as a standard substance, but it is detected as a peak curve having a certain width in the chromatogram.
  • a single TaSi 16 in the HPLC of the TaSi nanocluster dispersion shown in FIG. 11 should also be detected as a peak curve having a certain width. Therefore, the HPLC shown in FIG. 11 was fitted with a peak curve having a half-value width of 0.63 mL centering on the peak apex.
  • the dotted line in FIG. 11 is the fitting result.
  • the dotted line portion in the HPLC of the TaSi nanocluster dispersion is a peak caused by TaSi 16 . Therefore, the area ratio of the dotted line portion relative to the area of the solid line portion can be converted to the ratio of the confirmed nanoclusters (TaSi 16 + ) having a predetermined cluster size in the entire nanocluster.
  • the proportion of the confirmed nanoclusters (TaSi 16 + ) having a predetermined cluster size in the entire nanoclusters was 57.2%.
  • the obtained nanocluster dispersion was stable, and no nanocluster sedimentation was observed even after the dispersion was allowed to stand for about 6 months. That is, it can be seen that nanoclusters of a predetermined size are uniformly dispersed in this nanocluster dispersion.
  • the obtained dispersion was dispersed in tetrahydrofuran (THF), and a nanocluster multilayer film was produced by spin coating.
  • a nanocluster THF dispersion (10 mg / mL) was spin-coated at 3,000 rpm.
  • a spin coater (apparatus: manufactured by Aiden, model number SC2005) was used for spin coating.
  • the thickness of the charge retention layer obtained by spin coating was 60 nm.
  • the thickness of the charge retention layer was obtained in advance by measuring the relationship between the spin coating conditions and the film thickness with a scanning microscope using a cross-sectional image. Other conditions were the same as in Example 1. CV evaluation of the obtained memory device was performed.
  • Example 5 a memory device was manufactured in the same manner as in Example 4 except that the nanocluster was TiSi 16 .
  • the thickness of the charge retention layer obtained by spin coating was 60 nm. CV evaluation of the obtained memory device was performed.
  • FIG. 14 shows the results of CV characteristics of the memory device of Example 4
  • FIG. 15 shows the results of CV characteristics of the memory device of Example 5.
  • the vertical axis represents capacitance, and the horizontal axis represents applied voltage.
  • the memory device of Example 4 had a hysteresis width Vth of 1.19V
  • the memory device of Example 5 had a hysteresis width Vth of 3.12V.
  • a hysteresis curve could be obtained as the CV characteristic. That is, even when TaSi 16 and TiSi 16 are used for the nanocluster, it functions as a memory device. These nanoclusters can be produced only after they are generated in the gas phase, and no memory device using these nanoclusters has been reported. The center potential of the hysteresis curve could be changed by using these nanoclusters.
  • FIGS. 16 (a) and 16 (b) are respectively the same as in Example 2, but the CV of the memory device in which Au 38 (SR) 24, which is a nanocluster with an organic ligand, is a single layer or less and constitutes a charge retention layer.
  • Each memory device was fabricated in the same manner as in Example 1.
  • the surface pressure in the LB method was 10 mN / m and 25 mN / m, respectively.
  • the hysteresis width Vth is 0.21V and 3.48V, respectively.
  • the hysteresis width could be increased by multilayering the nanocluster layer. It is considered that the multilayering of nanocluster layers contributed to the increase in the amount of accumulated charge and the hysteresis width could be increased. Although the increase in the number of layers does not lead to a monotonous increase in the hysteresis width depending on the type of organic ligand, etc., the hysteresis width, that is, the memory, can be increased by increasing the number of nanocluster layers (or the thickness of the charge retention layer). It was confirmed that the characteristics could be controlled.
  • the multilayering of the nanocluster layer can also be performed by other methods such as a spin coating method.
  • FIG. 17A shows the CV characteristics of the memory device in which Au 25 (SR) 18 (R is C 12 H 25 ), which is the nanocluster with an organic ligand, forms the charge retention layer, as in Example 1.
  • FIG. 17B shows a memory in which Au 25 (SR) 18 (R is C 2 H 4 Ph), which is a different type of nanocluster with an organic ligand, is different from that in FIG. 17A. It is a CV characteristic of a device. Each memory device was fabricated in the same manner as in Example 1.
  • the hysteresis widths Vth are 0.13V and 0.61V, respectively.
  • the hysteresis width could be increased by replacing the organic ligand.
  • the increase in the hysteresis width leads to easy charge injection, and enables low voltage driving. It was confirmed that the hysteresis width, that is, the memory characteristics can be controlled by the type of the organic ligand.
  • SYMBOLS 1 Semiconductor part, 2 ... 1st insulating layer, 3 ... Charge holding layer, 4 ... 2nd insulating layer, 5, 5a ... Electrode, 6 ... Counter electrode, 7 ... Source electrode, 8 ... Drain electrode 10, 11, DESCRIPTION OF SYMBOLS 12, 13 ... Memory device, 30 ... Nano cluster, 31 ... Single layer film, 32 ... Partition, 33 ... Temporary support body, W ... Water, T ... Water tank

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Abstract

L'invention concerne un dispositif de mémoire comprenant, dans cet ordre : une section semi-conductrice (1); une première couche d'isolation (2); une couche de rétention de charge (3); une seconde couche d'isolation (4); et une électrode (5). La couche de rétention de charge comprend principalement un nanoagrégat (30) d'un nombre prédéterminé d'atomes.
PCT/JP2017/029923 2016-08-22 2017-08-22 Dispositif de mémoire WO2018038098A1 (fr)

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US20060252202A1 (en) * 2005-05-09 2006-11-09 Jiyan Dai Process and apparatus for fabricating nano-floating gate memories and memory made thereby
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