WO2018037946A1

WO2018037946A1 - Correcting device

Info

Publication number: WO2018037946A1
Application number: PCT/JP2017/029190
Authority: WO
Inventors: 真吾原田; 秀高加藤; 篤親丹羽; 裕隆村上; センユー
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2016-08-23
Filing date: 2017-08-10
Publication date: 2018-03-01
Also published as: JP2018032942A

Abstract

This technology relates to a correcting device which makes it possible to carry out duty correction with reduced power consumption. This correcting device is provided with: a converting portion which converts an input clock into a prescribed slew rate; a DC component removing portion which removes a DC component from an output from the converting portion; a DC component adding portion which adds a DC component to an output from the DC component removing portion; and a DC component extracting portion which extracts a DC component from an output from the DC component adding portion. The DC component extracting portion is internally provided with a first switch. A second switch is provided between the DC component adding portion and the DC component removing portion. The first switch and the second switch turn off when the clock stops. This technology is applicable, for example, to correcting devices which are included in image capturing elements to correct a clock signal.

Description

Correction device

The present technology relates to a correction device, for example, a correction device that corrects the duty ratio of a clock signal.

A CMOS (Complementary Metal Oxide Semiconductor) type image sensor is known as an image sensor for generating a video signal. In recent years, in order to generate a high-definition and high-frame-rate video signal, DDR (Double Data Rate) is used for the counter of the image sensor.

The DDR counter exchanges data at both rising and falling timings of the input clock signal, and here, count processing is performed at both rising and falling timings of the clock signal CLK1. The counter includes two latches, and the first latch latches data triggered by the rising edge of the clock signal CLK1. The second latch latches data triggered by the falling edge of the clock signal CLK1.

The trigger by which the second latch latches data is desirably a half cycle of the clock signal CLK1, in other words, the duty ratio of the clock signal CLK1 is desirably 50%.

However, in the image pickup device, even if the duty ratio of the clock signal CLK0 is 50% due to the quality of the transistors constituting the image pickup device or the operating voltage for operating the image pickup device, the clock supplied to the counter The duty ratio of the signal CLK1 does not always maintain 50%.

Patent Document 1 proposes that a duty correction circuit is provided to correct duty collapse due to a clock transmission path.

JP 2010-28396 A

As described above, it is not guaranteed that the duty ratio of the clock signal CLK1 supplied to the counter always maintains a desired value due to the quality of the transistor and the operating voltage. It has been proposed to correct the duty ratio by applying technology.

Patent Document 1 proposes to acquire a clock waveform through a smoothing filter for a duty correction amount. According to Patent Document 1, a time corresponding to the time constant of the smoothing filter is required to obtain the duty correction amount. In order to correctly obtain the duty correction amount, it is necessary to increase the time constant of the smoothing filter. Thus, the accuracy of the correction amount and the time constant are in a trade-off relationship.

Also, duty correction is performed using a negative feedback loop, and the correction amount is based on the premise that an input clock is continuously input. If the input clock is input discontinuously and there is a period in which the clock stops, the duty correction amount cannot be maintained, and the negative feedback loop may fall into an unintended state.

The present technology has been made in view of such a situation, and is capable of maintaining a state where duty correction can be performed accurately even when there is a period in which the clock is stopped.

A first correction device according to an aspect of the present technology includes a conversion unit that converts an input clock to a predetermined slew rate, a DC component removal unit that removes a DC component from an output from the conversion unit, and the DC component. A DC component adding unit that adds a DC component to the output from the removing unit; and a DC component extracting unit that extracts a DC component from the output from the DC component adding unit. The second switch is provided between the DC component adding unit and the DC component removing unit, and the clocks of the first switch and the second switch are stopped. When turned off.

A second correction device according to an aspect of the present technology includes a conversion unit that converts an input clock into a predetermined slew rate, a DC component extraction unit that extracts a DC component from an output from the DC component addition unit, A control unit that controls the conversion unit, the conversion unit includes an inverter capable of voltage-controlling each drive capability of the PMOS side and the NMOS side, the control unit controls the drive capability of the inverter, The DC component extraction unit includes a first switch therein, and a second switch is provided between a control input side of the drive capability of the inverter and an output side of the control unit, and the first switch And the second switch is turned off when the clock is stopped.

In the first correction device according to one aspect of the present technology, the input clock is converted into a predetermined slew rate, the DC component is removed, the DC component is added, and the DC component is extracted. A first switch and a second switch are also provided, and the first switch and the second switch are turned off when the clock is stopped. With such a configuration and operation, the duty ratio of the input clock can be corrected.

In the second correction device according to one aspect of the present technology, an input clock is converted into a predetermined slew rate, a DC component is extracted, and the slew rate is controlled. The conversion unit for converting the slew rate includes an inverter capable of controlling the drive capacities of the PMOS side and the NMOS side, and the control unit for controlling the conversion unit controls the drive capability of the inverter. A first switch and a second switch are also provided, and the first switch and the second switch are turned off when the clock is stopped. With such a configuration and operation, the duty ratio of the input clock can be corrected.

According to one aspect of the present technology, it is possible to maintain a state where duty correction can be performed with high accuracy even when there is a period in which the clock is stopped.

It should be noted that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a figure showing composition of one embodiment of an image sensor to which this art is applied. It is a figure which shows the structural example containing a duty correction circuit. It is a figure which shows the 1st structure of a duty correction circuit. It is a figure for demonstrating operation | movement of a duty correction circuit. It is a figure for demonstrating operation | movement of CDS. It is a figure which shows the 2nd structure of a duty correction circuit. It is a figure which shows the other 2nd structure of a duty correction circuit. It is a figure which shows the 3rd structure of a duty correction circuit. It is a figure which shows the 4th structure of a duty correction circuit. It is a figure for demonstrating operation | movement of a duty correction circuit. It is a figure which shows the other 4th structure of a duty correction circuit.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described.

<Configuration of image sensor>
FIG. 1 is a diagram illustrating a configuration of an embodiment of an image sensor to which the present technology is applied. 1 includes a pixel array unit 102 in which pixels 113 are arranged in a matrix of m columns and n rows, a row scanning circuit 103, a column scanning circuit 104, and a clock generation unit 105. A timing control circuit 106 and a counter 107.

In addition, the image sensor 101 is provided with ADC (Analog Digital Converter) 108-0 to ADC 108-m and ADC 108-0 to ADC 108-m provided for each column of the pixel array unit 102 for A / D conversion reference. A reference signal generation unit 109 for supplying a voltage RAMP. Each of the ADC 108-0 to ADC 108-m includes a comparator (REF) 110-0 to a comparator 110-m, and a latch unit 111-0 to a latch unit 111-m.

In FIG. 1, only one row of the latch unit 111-0 to the latch unit 111-m is illustrated, but in actuality, it is assumed that these are arranged side by side in the output bit sorting direction. Therefore, a plurality of sense amplifiers 112 are also arranged corresponding to these.

In the following description, when it is not necessary to individually distinguish the ADCs 108-0 to 108-m, they are simply referred to as ADCs 108, and it is not necessary to individually distinguish the comparators 110-0 to 110-m. The case is referred to as a comparator 110. Furthermore, when it is not necessary to individually distinguish the latch units 111-0 to 111-m, they are referred to as latch units 111.

The clock generation unit 105 generates a clock signal CLK having a predetermined duty ratio. The duty ratio is a ratio of a high width (hereinafter referred to as “H width”) period in one cycle of the clock signal, and is calculated by (H width / cycle of clock signal CLK) × 100. Hereinafter, the low width of the clock signal is referred to as L width.

The timing control circuit 106 generates an internal clock based on the clock signal CLK input from the clock generation unit 105, and generates a row scanning circuit 103, a column scanning circuit 104, ADCs 108-0 to ADC 108 -m, and a reference signal generation unit 109. , Output to the counter 107 or the like.

Further, the timing control circuit adjusts the duty ratio of the clock signal CLK input from the clock generation unit 105 based on the clock signal output to the counter 107 via each block constituting the timing control circuit 106. Hereinafter, the clock signal output from the timing control circuit 106 to the counter 107 is referred to as a clock signal CLKD.

The counter 107 is a DDR (Double Data Rate), and exchanges data at both rising and falling timings of the input clock signal CLKD. Here, the counter 107 performs count processing at both rising and falling timings of the clock signal CLKD, and supplies the count outputs CK1, CK2,..., CKn together with the clock signal CLKD to each latch unit 111 of the ADC 108. It is.

Each pixel 113 in the pixel array unit 102 is connected to a row selection line Hi and a column signal line Vj (i and j are both natural numbers). The row scanning circuit 103 selects a row selection line Hi from which pixel values are to be read out of the row selection lines H0 to Hn. The column scanning circuit 104 selects a column signal line Vj from which a pixel value is to be read in the row selection line Hi selected by the row scanning circuit 103.

The ADC 108 includes a comparator 110 and a latch unit 111, and has an n-bit AD conversion function. The comparator 110 of the ADC 108 compares the reference voltage RAMP input from the reference signal generation unit 109 with the output value of the pixel 113 transmitted through the column signal line Vj, and compares the reference voltage RAMP with the output value of the pixel 113. When the magnitudes match, the phase of the output signal is inverted and output.

The latch unit 111 of the ADC 108 has an n-bit first latch and a second latch as independent storage areas. The latch unit 111 of the ADC 108 uses the output from the counter 107 to continuously count the number of clocks until the output of the comparator 110 changes. When the output of the comparator 110 changes, the latch unit 111 enters the comparison period. The corresponding digital count value is held in the first latch or the second latch. The count value held in the latch unit 111 is scanned by the column scanning circuit 104, and is sequentially drawn out to the two-phase bus lines B1 and B2 to be a differential voltage.

The sense amplifier 112 amplifies and outputs the differential voltage input through the bus line B1 and the bus B2.

<Circuit configuration including duty correction circuit>
According to the present technology, the duty ratio of the clock signal input to the counter 107 included in the image sensor 101 can be adjusted to an appropriate value. Thereby, for example, an operation margin of a circuit operating in DDR represented by the counter 107 can be secured.

Therefore, it is possible to obtain an optimum driving condition for the image sensor 101 even when the characteristics of the image sensor 101 change due to external factors (temperature, voltage change, etc.), deterioration over time, and the like. FIG. 2 illustrates a configuration that can adjust the duty ratio to an appropriate value.

FIG. 2 is a diagram illustrating a partial configuration in the image sensor 101 including a duty correction circuit that adjusts the duty ratio to an appropriate value. The configuration shown in FIG. 2 shows a configuration in which the clock signal CLK output from the clock generation unit 105 is used as the clock of the counter 107 after passing through a repeater on the way.

Transmission from the clock generation unit 105 to the counter 107 is performed by lowering the clock frequency as much as possible. Therefore, the counter 107 employs a double data rate type (DDR) that counts using both rising and falling edges of the clock. Has been.

The duty ratio of the clock signal is preferably 50%. If the duty ratio deviates from 50%, the counter 107 may cause an erroneous count. However, when the in-chip wiring distance from the clock generation unit 105 to the counter 107 is long, an inverter is configured by inserting a repeater by a CMOS inverter (inverters 202-1 to 202-3 in FIG. 2) in the middle. There is a possibility that the duty ratio may be lost as the clock is transmitted due to a difference in capability due to manufacturing variations between PMOS and NMOS.

The duty correction circuit 201 is a circuit that corrects a clock with a correct duty ratio when such a duty ratio is lost.

<Configuration of first duty correction circuit>
FIG. 3 shows the configuration of the duty correction circuit 201. The duty correction circuit 201 shown in FIG. 3 is a first duty correction circuit and is described as a duty correction circuit 201a.

A duty correction circuit 201a shown in FIG. 3 includes an inverter 301, an HPF (High Pass Filter) 302, an LPF (Low Pass Filter) 303, an operational amplifier 304, a reference voltage source 305, inverters 306 to 308, and a phase compensation capacitor 309. . In the duty correction circuit 201a, the HPF 302, the LPF 303, and the operational amplifier 304 form a negative feedback loop.

The HPF 302 includes a capacitor 321 and a resistor 322, and the LPF 303 includes a capacitor 331 and a resistor 332. Note that the HPF 302 and the LPF 303 may have a configuration other than a configuration including a capacitor and a resistor.

The duty correction circuit 201a receives the clock signal CLK generated by the clock generation unit 105. The duty ratio of the clock signal CLK input to the duty correction circuit 201a may be lost. First, the duty correction circuit 201a causes the inverter 301 to slow down the slew rate of the input clock signal CLK. The inverter 301 is an inverter capable of appropriately controlling the output slew rate.

The output from the inverter 301 is supplied to the HPF 302, and the DC component is removed. The HPF 302 is supplied with a DC component from the operational amplifier 304 such that the duty ratio of the finally output clock is 50%. The HPF 302 performs processing for removing a DC component from the clock supplied from the inverter 301 and giving a DC value such that the duty ratio is 50% with the logical threshold value of the inverter 306.

The negative side (-terminal) of the operational amplifier 304 is supplied with a component with a broken duty ratio extracted by the LPF 303 from the clock signal via the inverter 306 and the inverter 307. The positive side (+ terminal) of the operational amplifier 304 is connected to the reference voltage source 305 and supplied with a voltage that is ½ of the voltage VDD. The output terminal of the operational amplifier 304 is connected to the phase compensation capacitor 309 and the HPF 302.

The output power from the operational amplifier 304 is a duty correction amount. As described above, the output from the operational amplifier 304, that is, the duty correction amount is supplied to the HPF 302. The clock signal with the corrected duty ratio is output to the counter 107 (FIG. 2) via an inverter 308 provided as a final clock output buffer.

Referring to FIG. 4, the operation of duty correction circuit 201a shown in FIG. 3 will be described again. 4 shows the clock signal input to the inverter 301, and the second stage of FIG. 4 shows the clock signal output from the inverter 301.

4 shows the clock signal input to the inverter 306 (clock signal output from the HPF 302) in the third stage of FIG. 4, and the output from the inverter 306 in the fourth stage of FIG.

4 is a clock signal having a duty ratio of 40% and a duty ratio collapsed. When such a clock signal is input, the output from the inverter 301 is a clock signal with a sufficiently slow slew rate, as shown in the second stage of FIG.

Such a signal is input to the HPF 302. The HPF 302 removes the DC component from the input clock signal and adds the duty correction amount supplied from the operational amplifier 304, so that the signal as shown in the third part of FIG. 4 is output from the HPF 302 and supplied to the inverter 306. Is done. That is, in this case, a signal whose voltage is lowered by the duty correction amount is supplied to the inverter 306.

The inverter 306 sets the logical threshold value to a value (corresponding to VDD / 2) at which the duty ratio becomes 50%, and performs output that is inverted when the logical threshold value is equal to or lower than the logical threshold value. The clock signal shown in the stage is output.

In this way, the duty correction circuit 201a corrects the duty ratio of the input clock signal and outputs it.

The duty correction circuit 201a smoothes the output waveform of the inverter 307 with the LPF 303, and if the duty ratio is 50%, the operational amplifier 304 uses the fact that the voltage after smoothing becomes VDD / 2. Compared with the reference voltage source 305, the deviation amount of the duty ratio is obtained.

<CDS operation>
By the way, in the image sensor 101 shown in FIG. 1, a signal read from the pixel 113 is subjected to processing by a CDS (Correlated Double Sampling) method. In the CDS method, as shown in FIG. 5, two count periods, a P-phase period and a D-phase period, are provided for reading one pixel.

The first stage of FIG. 5 shows an enable signal indicating the timing at which the reference signal generator 109 supplies the reference signal to the comparator 110 (FIG. 1), and the reference signal generated by the reference signal generator 109 in the second stage. (Ramp signal). The third stage of FIG. 5 shows the waveform of the counter clock in the counter 107.

When the enable signal is turned on, the sweep of the reference signal is started and the count operation of the counter 107 is started. When the voltage of the reference signal falls below the voltage of the input signal, the output signal of the comparator 110 is inverted from the high level to the low level. The counting operation of the counter 107 is stopped at this falling edge. The count value has a one-to-one relationship with the voltage width obtained by sweeping the voltage of the reference signal, and this count value is a result of analog-to-digital (AD) conversion of the input voltage.

Such a counting operation is performed twice in the P-phase period and the D-phase period in reading from one pixel. Since it is not necessary to operate the counter 107 during the period between the P-phase period and the D-phase period, generation of the clock signal in the clock generation unit 105 can be stopped. By stopping the generation of the clock signal in the clock generation unit 105, power consumption can be reduced.

As described with reference to FIG. 4, the duty correction circuit 201 is based on the premise that the clock signal input to the inverter 301 (FIG. 3) is continuously input. The circuit is configured so that the duty ratio can be corrected correctly by continuously inputting clock signals.

On the other hand, as described with reference to FIG. 5, in the period between the P-phase period and the D-phase period, the generation of the clock signal can be stopped and the power consumption can be reduced.

According to the duty correction circuit 201a shown in FIG. 3, the duty ratio can be corrected to a signal with a correct duty ratio as described above. However, if a period for stopping the clock signal is provided, in other words, if there is a period during which the clock signal is not input to the duty correction circuit 201a, the operation of the duty correction circuit 201a may become unstable.

For example, if the clock signal is stopped in a low state and the input is fixed, the output from the inverter 307 and the output from the LPF 303 may become indefinite, and the duty correction amount information may be lost.

For this reason, in order to keep the duty correction amount in the duty correction circuit 201a, it is necessary to continue to generate without stopping the clock signal. Therefore, in the period between the P-phase period and the D-phase period, the generation of the clock signal cannot be stopped, and it is difficult to reduce power consumption in this respect.

Also, it is necessary to wait for the internal time constant from the input of the clock signal until the correct duty-corrected clock signal is obtained. Therefore, it is necessary to supply the clock signal to the duty correction circuit 201a before the actual count starts, and power is consumed accordingly.

For this reason, during the period between the P-phase period and the D-phase period, the power consumption is reduced so that the duty correction amount can be maintained and the duty ratio can be corrected accurately even if the generation of the clock signal is stopped. The duty correction circuit 201 that can be reduced will be described below.

<Configuration of Second Duty Correction Circuit>
FIG. 6 shows another configuration of the duty correction circuit 201. The duty correction circuit 201 illustrated in FIG. 6 is a second duty correction circuit and is described as a duty correction circuit 201b. Parts having the same functions in the duty correction circuit 201b shown in FIG. 6 and the duty correction circuit 201a shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

Similar to the duty correction circuit 201a shown in FIG. 3, the duty correction circuit 201b shown in FIG. 6 includes an inverter 301, an HPF 302, an LPF 303, an operational amplifier 304, a reference voltage source 305, inverters 306 to 308, and a phase compensation capacitor 309. . The HPF 302 includes a capacitor 321 and a resistor 322, and the LPF 303 includes a capacitor 331 and a resistor 332.

6 further includes a switch 401 and a switch 402. The duty correction circuit 201b shown in FIG. The switch 401 is provided in the LPF 303 and is provided between the capacitor 331 and the resistor 332 (between the resistor 332 and the negative side of the operational amplifier 304). The switch 402 is provided on the output side of the operational amplifier 304, is between the operational amplifier 304 and the HPF 302, and is provided between the operational amplifier 304 and the phase compensation capacitor 309.

The switch 401 may be provided between the inverter 307 and the LPF 303 as shown in FIG. Also in the duty correction circuit 201b, the HPF 302, the LPF 303, and the operational amplifier 304 form a negative feedback loop.

The switch 401 and the switch 402 are turned on or off (opened / closed) at the same timing. The switch 401 and the switch 402 are turned on (closed) during the P-phase period and the D-phase period, and are turned off (opened) during the period between the P-phase period and the D-phase period.

In other words, the switch 401 and the switch 402 are closed while the clock signal is generated (while the clock signal is being input), and while the generation of the clock signal is stopped (when the clock signal is stopped being input). Open).

Thus, by providing the

switches

401 and 402 and turning off the

switches

401 and 402 while the clock is stopped, the operational amplifier 304 can hold the duty correction amount while the clock is stopped.

Since the duty correction amount is retained while the clock is stopped, the duty ratio can be corrected using the retained duty correction amount after the clock is stopped. The accuracy of duty ratio correction in the circuit 201b can be maintained.

The opening / closing control of the switch 401 and the switch 402 can be performed by a control signal from an upper layer. The duty correction circuit 201b including the switch 401 and the switch 402 is included in the timing control circuit 106 (FIG. 1), but a signal for controlling opening and closing of the switch 401 and the switch 402 is generated in the timing control circuit 106. Alternatively, it may be supplied from a control unit (not shown).

As described above, the function of holding the duty correction amount can be realized by using the phase compensation capacitor 309 for maintaining stability in the negative feedback loop and by adding the switch 402 to the output side of the operational amplifier 304. it can.

6 and 7, not only the switch 402 but also the switch 401 is provided. However, the provision of the switch 401 more reliably holds the duty correction amount and the duty correction is performed from the following points. Can be.

The output of the operational amplifier 304 has a parasitic capacitance. When the clock signal is restarted after the clock signal is stopped and the switch 402 is returned to the ON state, if the output voltage value of the operational amplifier 304 is greatly deviated, the phase compensation capacitor 309 and the operational amplifier 304 There is a possibility that charge sharing will occur with the output parasitic capacitance.

In order to prevent deviation from the original holding voltage (duty correction amount) due to charge sharing, it is preferable to provide a switch 401 on the input side of the operational amplifier 304.

In the duty correction circuit 201b shown in FIG. 6 or 7, the inverter 306 and the inverter 307 are provided between the HPF 302 and the LPF 303. However, a configuration in which only the inverter 306 is provided (a configuration in which the inverter 307 is omitted) is also possible. good.

When only the inverter 306 is provided between the HPF 302 and the LPF 303, the negative side of the operational amplifier 304 is connected to the reference voltage source 305, and the positive side of the operational amplifier 304 is connected to the LPF 303.

<Configuration of Third Duty Correction Circuit>
FIG. 8 shows still another configuration of the duty correction circuit 201. The duty correction circuit 201 shown in FIG. 8 is a third duty correction circuit and is described as a duty correction circuit 201c. Portions having the same function in the duty correction circuit 201c shown in FIG. 8 and the duty correction circuit 201a shown in FIG. 3 or the duty correction circuit 201b shown in FIG. Omitted.

The duty correction circuit 201c illustrated in FIG. 8 includes the inverter 301, the HPF 302, the LPF 303, the operational amplifier 304, the reference voltage source 305, the inverters 306 to 308, the switch 401, and the switch 402, similarly to the duty correction circuit 201b illustrated in FIG. Prepare.

The HPF 302 is composed of a capacitor 321 and a resistor 322. The LPF 303 includes a capacitor 501 and a resistor 332. The capacitor 501 is provided between the negative input of the operational amplifier 304 and the output of the operational amplifier 304.

The duty correction circuit 201c in the third embodiment is configured by deleting the phase compensation capacitor 309 from the duty correction circuit 201b in the second embodiment. The phase compensation capacitor 309 is shared with the capacitor 501 constituting the LPF 303, and the duty correction circuit 201c is provided.

The switch 401 is provided between the resistor 332 and the operational amplifier 304 (the negative side thereof), similarly to the duty correction circuit 201b shown in FIG. Alternatively, although not illustrated, a configuration provided between the inverter 307 and the LPF 303 may be employed as in the duty correction circuit 201b illustrated in FIG.

The switch 402 is provided on the output side of the operational amplifier 304, and is provided between the operational amplifier 304 and the HPF 302.

As described above, the duty correction circuit 201c according to the third embodiment converts the two capacitors, the phase compensation capacitor 309 of the duty correction circuit 201b according to the second embodiment and the capacitor 331 constituting the LPF 303, into one capacitor 501. The configuration is summarized.

Since the mounting area of the phase compensation capacitor 309 and the capacitor 331 is larger than that of other elements, for example, an element such as the inverter 306, the area of the duty correction circuit 201c can be reduced only by using two capacitors as one capacitor. it can. That is, according to the configuration of the duty correction circuit 201c in the third embodiment, it is possible to reduce the area.

Further, by connecting the capacitor 501 between the negative input of the operational amplifier 304 and the output of the operational amplifier 304, the negative feedback loop can be kept stable, and the LPF 303 can also serve as a capacitor. .

Furthermore, the duty correction circuit 201c in the third embodiment includes a switch 502. The switch 502 is provided at a position where the negative input and the positive input of the operational amplifier 304 are connected. The duty correction circuit 201c in the third embodiment is configured to include three switches, a switch 401, a switch 402, and a switch 502.

As described above, the switch 401 and the switch 402 are opened / closed (on / off) at the same timing. The switch 502 is opened and closed (on / off) at a timing different from that of the

switches

401 and 402.

That is, when the clock signal is not stopped, the switch 401 and the switch 402 are in a closed state (on state), and the switch 502 is in an open state (off state). When the clock signal is stopped, the switch 401 and the switch 402 are opened (off state), and the switch 502 is closed (on state).

During the duty correction amount holding period, that is, the period in which the switch 401 and the switch 402 are turned off, both ends of the capacitor 501 are in the Hi-Z state (high impedance state), and the leakage current is very small. Even in such a case, the voltage value may fluctuate greatly in a short time. Therefore, during the duty correction amount holding period, the switch 502 is turned on to short-circuit the reference voltage source 305 having a voltage of VDD / 2.

This means that if the gain of the operational amplifier 304 is sufficiently high, the two inputs of the operational amplifier 304 are in a virtual short state and become substantially the same potential. That is, after the duty correction is sufficiently performed, the negative side input voltage of the operational amplifier 304 should be sufficiently settled in the vicinity of VDD / 2. Therefore, even if the two inputs are short-circuited when the duty correction amount is maintained. This is because the duty correction voltage (the DC voltage input to the inverter 306) is hardly affected.

It is possible to prevent the voltage value from fluctuating greatly in a short time by providing the switch 502 and closing the switch 502 while the duty correction amount is maintained. As a result, the duty ratio can be corrected in a more stable state.

<Configuration of Fourth Duty Correction Circuit>
FIG. 9 shows still another configuration of the duty correction circuit 201. The duty correction circuit 201 shown in FIG. 9 is a fourth duty correction circuit and is described as a duty correction circuit 201d. Portions having the same function in the duty correction circuit 201d shown in FIG. 9 and the duty correction circuit 201c shown in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

The duty correction circuit 201c illustrated in FIG. 9 is similar to the duty correction circuit 201c illustrated in FIG. 8, an LPF (Low Pass Filter) 303, an operational amplifier 304, a reference voltage source 305,

inverters

307 and 308, a switch 401, and a switch 402. Is provided.

The duty correction circuit 201d in the fourth embodiment has a configuration in which the HPF 102 is deleted from the duty correction circuit 201c in the third embodiment and is replaced with a slew rate adjustment unit 601 that can adjust the drive capability of the inverter 621. Has been. Also in the duty correction circuit 201d, the slew rate adjustment unit 601, the LPF 303, and the operational amplifier 304 form a negative feedback loop.

The slew rate adjusting unit 601 includes a P-channel transistor 611, an N-channel transistor 612, and an inverter 621. The inverter 621 is an inverter corresponding to the inverter 306 included in the duty correction circuit 201c in the third embodiment, for example.

In the duty correction circuit 201d in the fourth embodiment, the inverter 621 corresponding to the inverter 306 has a function of adjusting the slew rate of the input signal. Further, since the slew rate is adjusted by the inverter 621, unlike the inverter 301 in the first to third embodiments, the slew rate is configured by an inverter 301 'that does not adjust the slew rate.

The output (duty correction amount) from the operational amplifier 304 is input to each gate of the P-channel transistor 611 and the N-channel transistor 612 of the slew rate adjusting unit 601. The source of the P-channel transistor 611 is connected to the power supply, and the drain of the N-channel transistor 612 is grounded.

The slew rate adjustment unit 601 includes a P-channel transistor 611 and an N-channel transistor 612 for adjusting drive capability. The P-channel transistor 611 is provided between the inverter 621 and the power supply, and the N-channel transistor 612 includes: It is provided between the inverter 621 and the ground (GND).

The clock signal from the clock generation unit 105 is input to the inverter 621 via the inverter 301 '.

As described above, the clock signal before the duty ratio is corrected is input to the inverter 621, and the duty correction amount from the operational amplifier 304 is supplied to the gates of the P-channel transistor 611 and the N-channel transistor 612, respectively. It is said that. In this configuration, the gate voltage of the P-channel transistor 611 and the gate voltage of the N-channel transistor 612 are controlled by the operational amplifier 304.

Further, the slew rate adjustment unit 601 is configured to be able to adjust the slew rate of the clock signal input to the inverter 621 and correct the duty ratio deviation.

The P-channel transistor 611 is turned on when the duty correction amount from the operational amplifier 304 input to the gate of the P-channel transistor 611 is a correction amount that widens the L width of the clock signal input from the clock generation unit 105. Become. Then, the slew rate of the clock signal input to the inverter 621 is adjusted so as to reduce the duty ratio of the clock signal.

The N-channel transistor 612 is turned on when the duty correction amount from the operational amplifier 304 input to the gate of the N-channel transistor 612 is a correction amount that widens the clock signal H width input from the clock generation unit 105. . Then, the slew rate of the clock signal input to the inverter 621 is adjusted so as to increase the duty ratio of the clock signal.

When the duty correction amount from the operational amplifier 304 is an amount (control signal) for instructing correction to increase the duty ratio, the slew rate adjustment unit 601 reduces the drive capability of the N-channel transistor 612. Correct the duty ratio.

Further, when the duty correction amount from the operational amplifier 304 is an amount (control signal) for instructing correction to reduce the duty ratio, the slew rate adjustment unit 601 reduces the drive capability of the P-channel transistor 611. The duty ratio is corrected.

By adopting such a configuration, a configuration in which the HPF 302 (such as FIG. 8) is deleted can be obtained. By adopting a configuration in which the HPF 302 is deleted, a configuration in which the capacitor 302 and the resistor 322 that configure the HPF 302 are deleted can be achieved, so that the mounting area can be reduced.

Further, the duty correction circuit 201 in the first to third embodiments has a configuration for adjusting the DC value after the HPF 302 as the duty correction. In such a configuration, it is assumed that the waveform of the clock signal supplied to the HPF 302 is sufficiently dull (the waveform of the clock signal is sufficiently dulled by the inverter 301). There is a possibility that the influence on the slew rate becomes large (hereinafter, these fluctuations will be referred to as PVT fluctuations).

On the other hand, the duty correction circuit 201d according to the fourth embodiment has a configuration in which the capacity of the inverter 621 can be directly adjusted, so that the influence on the slew rate due to the PVT fluctuation can be reduced.

The operation of the duty correction circuit 201d shown in FIG. 9 will be described with reference to FIG. In the description with reference to FIG. 10, a case where a clock signal having a duty ratio of less than 50% is corrected to a clock signal having a duty ratio of 50% will be described as an example.

10 shows the clock signal input to the inverter 301, and the second stage of FIG. 10 shows the clock signal output from the inverter 301. The third stage in FIG. 10 shows the clock signal output from the inverter 621, and the fourth stage in FIG. 10 shows the output from the inverter 307.

The clock signal input to the inverter 301 shown in the uppermost stage in FIG. 10 has a duty ratio of 40%, for example, and is a clock signal in a state where the duty ratio has collapsed. When such a clock signal is input, the output from the inverter 301 is output as a signal whose polarity is inverted without changing the duty ratio, as shown in the second stage of FIG.

Such a signal is input to the inverter 621 of the slew rate adjusting unit 601. In this case, the slew rate adjusting unit 601 adjusts the slew rate for increasing the duty ratio from 40% to 50%. In this case, the duty ratio is corrected (the slew rate is adjusted) by reducing the drive capability of the N-channel transistor 612.

A signal as shown in the third stage of FIG. 10 is generated from the slew rate adjustment unit 601 (internal inverter 621) and output to the inverter 307. The signal shown in the third stage of FIG. 10 is a signal in which the slew rate on the falling side of the input signal has become slow.

Although not shown, when the slew rate is adjusted to lower the duty ratio, the duty ratio is corrected (the slew rate is adjusted) by lowering the drive capability of the P-channel transistor 611. In addition, when such adjustment is performed, a signal in which the slew rate on the rising side of the signal input to the slew rate adjustment unit 601 becomes dull is generated and output to the inverter 307.

The inverter 307 sets the logic threshold value to a value (corresponding to VDD / 2) at which the duty ratio becomes 50%, and performs an output in which the value is inverted when the logic threshold value is equal to or less than or equal to 4 in FIG. The clock signal shown in the stage is output.

Thus, the duty correction circuit 201d can correct the duty ratio of the input clock signal and output it.

According to the duty correction circuit 201 in the above-described embodiment, duty correction with reduced power consumption can be performed as described above. In addition, the effects described below can also be obtained.

Although not shown in the configuration of the duty correction circuit 201d illustrated in FIG. 9, a switch 401 may be provided between the inverter 307 and the LPF 303, as in the duty correction circuit 201b illustrated in FIG.

Further, in the configuration of the duty correction circuit 201d shown in FIG. 9, the configuration including the capacitor 501 is the same as the duty correction circuit 201c (FIG. 8) in the third embodiment. However, the duty correction circuit 201d shown in FIG. Similar to the correction circuit 201b (FIG. 6), a configuration including a capacitor 331 and a phase compensation capacitor 309 may be used as in the duty correction circuit 201e shown in FIG.

In order to maintain the analog voltage value, it is necessary to suppress the leakage current flowing through the switch (for example, the switch 401) as small as possible. However, with a normal CMOS switch, a very large amount of leakage current flows especially at high temperatures, and cannot be held for a long time.

Therefore, a transistor with a large L length is used, the gate voltage when turning off the switch is a negative voltage that is lower than the GND level for NMOS, and a high voltage that exceeds the power supply for PMOS. It was necessary to take special measures such as preparing them separately.

According to the present technology, the time may be approximately between the P-phase period and the D-phase period in the CDS system of the image sensor 101, and it is not necessary to hold for a long time. A switch used in the image sensor 101 to which the present technology is applied (the duty correction circuit 201 included in the image sensor 101) can be configured by a very simple and sufficiently small transistor.

According to the present technology, by applying the duty correction circuit to the CDS system counter clock, even when a long distance transmission is performed between the clock generator 105 (FIG. 1) and the counter 107 on the chip, the duty ratio is increased. Can be corrected more appropriately.

In addition, since it has a mechanism capable of holding the duty correction amount, even if a period in which the clock is stopped is provided, the duty ratio can be corrected without indefinite operation when the clock is restarted. In addition, since the clock can be stopped, the power consumption can be reduced according to the present technology.

Note that the present technology can be applied to the image sensor 101 as described above, but the scope of application of the present technology is not limited to the image sensor 101. According to the present technology, since the duty ratio can be corrected, it can be applied to a device that generates and outputs a waveform maintaining the duty ratio.

In this specification, the system represents the entire apparatus composed of a plurality of apparatuses.

It should be noted that the effects described in this specification are merely examples and are not limited, and other effects may be obtained.

Note that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

In addition, this technique can also take the following structures.
(1)
A converter that converts the input clock to a predetermined slew rate; and
A DC component removal unit for removing a DC component from the output from the conversion unit;
A DC component adding unit for adding a DC component to the output from the DC component removing unit;
A DC component extraction unit that extracts a DC component from an output from the DC component addition unit,
The DC component extraction unit includes a first switch inside,
A second switch is provided between the DC component adding unit and the DC component removing unit,
The correction device, wherein the first switch and the second switch are turned off when the clock is stopped.
(2)
The correction device according to (1), wherein the DC component removal unit, the DC component addition unit, and the DC component extraction unit form a negative feedback loop.
(3)
The DC component extraction unit has a capacity and a resistance,
The correction device according to (1) or (2), wherein the first switch is provided between the capacitor and the resistor.
(4)
The DC component extraction unit has a capacity and a resistance,
The correction device according to (1) or (2), wherein the first switch is provided between the resistor and the DC component removing unit.
(5)
The DC component adding unit is composed of an operational amplifier,
The negative input of the operational amplifier is connected to one end of the first switch, the positive input is connected to a voltage source having a voltage half the reference voltage, and the output side of the operational amplifier is connected via the second switch. The correction device according to any one of (1) to (4), connected to the DC component removal unit.
(6)
The correction device according to (5), wherein an output side of the operational amplifier is also connected to a phase compensation capacitor via the second switch.
(7)
The DC component extraction unit has a capacity and a resistance,
The DC component adding unit is composed of an operational amplifier,
One end of the first switch is connected to the resistor, and the other end is connected to a negative input of the operational amplifier.
The correction device according to any one of (1) to (4), wherein the capacitor is provided between a negative input and an output side of the operational amplifier.
(8)
A third switch is further provided between the negative side input and the positive side input of the operational amplifier,
The correction device according to (7), wherein the third switch is turned on when the clock is stopped.
(9)
A converter that converts the input clock to a predetermined slew rate; and
A DC component extraction unit that extracts a DC component from an output from the DC component addition unit;
A control unit for controlling the conversion unit,
The conversion unit includes an inverter capable of voltage control of each drive capability on the PMOS side and the NMOS side,
The control unit controls the drive capability of the inverter;
The DC component extraction unit includes a first switch inside,
Between the control input side of the drive capability of the inverter and the output side of the control unit, a second switch is provided,
The correction device, wherein the first switch and the second switch are turned off when the clock is stopped.
(10)
The correction device according to (9), wherein the control unit voltage-controls the drive capability of the inverter so that a predetermined duty ratio is obtained.
(11)
The correction device according to (9) or (10), wherein the conversion unit, the DC component extraction unit, and the control unit form a negative feedback loop.
(12)
The DC component extraction unit has a capacity and a resistance,
The correction device according to any one of (9) to (11), wherein the first switch is provided between the capacitor and the resistor.
(13)
The DC component extraction unit has a capacity and a resistance,
The correction device according to any one of (9) to (11), wherein the first switch is provided between the resistor and the conversion unit.
(14)
The control unit is composed of an operational amplifier,
The negative input of the operational amplifier is connected to one end of the second switch, the positive input is connected to a voltage source having a voltage half the reference voltage, and the output side of the operational amplifier is connected to the second switch. The correction device according to any one of (9) to (13), connected to an input side of the inverter, a gate of the PMOS, and a gate of the NMOS.
(15)
The correction device according to (14), wherein an output side of the operational amplifier is also connected to a phase compensation capacitor via the second switch.
(16)
The DC component extraction unit has a capacity and a resistance,
The DC component adding unit is composed of an operational amplifier,
One end of the first switch is connected to the resistor, and the other end is connected to a negative input of the operational amplifier.
The correction device according to any one of (9) to (14), wherein the capacitor is provided between a negative side input and an output side of the operational amplifier.
(17)
A third switch is further provided between the negative side input and the positive side input of the operational amplifier,
The correction device according to (16), wherein the third switch is turned on when the clock is stopped.

101 image sensor, 105 clock generator, 106 timing control circuit, 107 counter, 201 duty correction circuit, 301 inverter, 302 HPF, 303 LPF, 304 operational amplifier, 305 reference voltage source, 306 to 308 inverter, 309 phase compensation capacity, 321 Capacity, 322 resistance, 331 capacity, 332 resistance, 401, 402 switch, 501 capacity, 502 switch, 601 slew rate adjustment unit, 611 P-channel transistor, 612 N-channel transistor, 621 inverter

Claims

A converter that converts the input clock to a predetermined slew rate; and
A DC component removal unit for removing a DC component from the output from the conversion unit;
A DC component adding unit for adding a DC component to the output from the DC component removing unit;
A DC component extraction unit that extracts a DC component from an output from the DC component addition unit,
The DC component extraction unit includes a first switch inside,
A second switch is provided between the DC component adding unit and the DC component removing unit,
The correction device, wherein the first switch and the second switch are turned off when the clock is stopped.
The correction apparatus according to claim 1, wherein the DC component removal unit, the DC component addition unit, and the DC component extraction unit form a negative feedback loop.
The DC component extraction unit has a capacity and a resistance,
The correction device according to claim 1, wherein the first switch is provided between the capacitor and the resistor.
The DC component extraction unit has a capacity and a resistance,
The correction device according to claim 1, wherein the first switch is provided between the resistor and the DC component removing unit.
The DC component adding unit is composed of an operational amplifier,
The negative input of the operational amplifier is connected to one end of the first switch, the positive input is connected to a voltage source having a voltage half the reference voltage, and the output side of the operational amplifier is connected via the second switch. The correction device according to claim 1, wherein the correction device is connected to the DC component removal unit.
The correction device according to claim 5, wherein an output side of the operational amplifier is also connected to a phase compensation capacitor via the second switch.
The DC component extraction unit has a capacity and a resistance,
The DC component adding unit is composed of an operational amplifier,
One end of the first switch is connected to the resistor, and the other end is connected to a negative input of the operational amplifier.
The correction device according to claim 1, wherein the capacitor is provided between a negative side input and an output side of the operational amplifier.
A third switch is further provided between the negative side input and the positive side input of the operational amplifier,
The correction device according to claim 7, wherein the third switch is turned on when the clock is stopped.
A converter that converts the input clock to a predetermined slew rate; and
A DC component extraction unit that extracts a DC component from an output from the DC component addition unit;
A control unit for controlling the conversion unit,
The conversion unit includes an inverter capable of voltage control of each drive capability on the PMOS side and the NMOS side,
The control unit controls the drive capability of the inverter;
The DC component extraction unit includes a first switch inside,
Between the control input side of the drive capability of the inverter and the output side of the control unit, a second switch is provided,
The correction device, wherein the first switch and the second switch are turned off when the clock is stopped.
The correction device according to claim 9, wherein the control unit voltage-controls the drive capability of the inverter so that a predetermined duty ratio is obtained.
The correction device according to claim 9, wherein the conversion unit, the DC component extraction unit, and the control unit form a negative feedback loop.
The DC component extraction unit has a capacity and a resistance,
The correction device according to claim 9, wherein the first switch is provided between the capacitor and the resistor.
The DC component extraction unit has a capacity and a resistance,
The correction device according to claim 9, wherein the first switch is provided between the resistor and the conversion unit.
The control unit is composed of an operational amplifier,
The negative input of the operational amplifier is connected to one end of the second switch, the positive input is connected to a voltage source having a voltage half the reference voltage, and the output side of the operational amplifier is connected to the second switch. The correction device according to claim 9, wherein the correction device is connected to an input side of the inverter, a gate of the PMOS, and a gate of the NMOS.
The correction device according to claim 14, wherein an output side of the operational amplifier is also connected to a phase compensation capacitor via the second switch.
The DC component extraction unit has a capacity and a resistance,
The DC component adding unit is composed of an operational amplifier,
One end of the first switch is connected to the resistor, and the other end is connected to a negative input of the operational amplifier.
The correction device according to claim 9, wherein the capacitor is provided between a negative side input and an output side of the operational amplifier.
A third switch is further provided between the negative side input and the positive side input of the operational amplifier,
The correction device according to claim 16, wherein the third switch is turned on when the clock is stopped.