WO2018032407A1

WO2018032407A1 - Storage device and manufacturing method therefor, and data read-write method

Info

Publication number: WO2018032407A1
Application number: PCT/CN2016/095665
Authority: WO
Inventors: 徐挽杰; 张臣雄
Original assignee: 华为技术有限公司
Priority date: 2016-08-17
Filing date: 2016-08-17
Publication date: 2018-02-22
Also published as: CN108028271A; CN108028271B

Abstract

A storage device and a manufacturing method therefor and a data read-write method. A tunneling field effect transistor in the storage device comprises: a semiconductor substrate (1), a channel (67) located on a surface of the semiconductor substrate (1), a source region (6) and a drain region (7), a potential well layer (3), a first gate region (51) and a second gate region (52), the channel (67) being provided with a first surface and a second surface opposite to each other in a first direction, and a third surface and a fourth surface opposite to each other in a second direction; the source region (6) covering the third surface, the drain region (7) covering the fourth surface, and the source region (6) and the drain region (7) being different in doping type; and the potential well layer (3) covering a part of the first surface and extending along the second direction to cover a part of a surface where the potential well layer (3) is provided away from the channel (67), the first gate region (51) covering a part of the first surface and extending along the second direction to cover the part of the surface where the potential well layer (3) is provided away from the channel (67), and the second gate region (52) covering the second surface. The storage device has high reliability, and can perform multiple read-write operations.

Description

Storage device, manufacturing method thereof, and data reading and writing method

Technical field

The present invention relates to the field of data reading and writing technology, and in particular, to a storage device and a manufacturing method thereof, and a data reading and writing method.

Background technique

Memory is an indispensable part of the computer structure. Among them, the non-capacitance Dynamic Random Access Memory (DRAM) has been widely studied due to its large size reduction potential.

The non-capacitor dynamic random access memory includes only one transistor. In specific applications, the "0" state and the "1" state are distinguished according to whether or not a charge is stored in the transistor, and the memory is divided according to the magnitude of the read current when the transistor is turned on. In its corresponding non-capacitor dynamic random access memory data.

However, in the current non-capacitor dynamic random access memory, the charge stored in the transistor is obtained by impact ionization of the drain and the free charge in the source region under the high voltage applied between the gate and the drain, and the impact ionization may damage the transistor. The reliability makes the capacitorless dynamic random access memory unable to perform multiple read and write operations.

Summary of the invention

To solve the above technical problem, an embodiment of the present invention provides a storage device, which has high reliability and can perform multiple read and write operations.

To solve the above problem, the embodiment of the present invention provides the following technical solutions:

In a first aspect, the present invention provides a memory device including a tunneling field effect transistor, the tunneling field effect transistor comprising:

Semiconductor substrate

a channel, on a surface of the semiconductor substrate, having first and second surfaces opposite to each other in a first direction, and third and fourth surfaces opposite to each other in a second direction, the second direction And the first direction is parallel to the surface of the semiconductor substrate, and the second direction is perpendicular to the first direction;

a source region and a drain region on the surface of the semiconductor substrate, disposed opposite to each other in a second direction, the source region covering the third surface, the drain region covering the fourth surface, the source region and The doping type of the drain region is different;

a well layer on the surface of the semiconductor substrate covering at least one surface of the source region in a first direction and a portion of the first surface;

a first gate region on a surface of the semiconductor substrate covering a portion of the first surface and extending in the second direction to cover a portion of the well layer facing away from a surface of the channel, and at a first a direction in which the projection of the first gate region coincides with the projection of the channel;

A second gate region is disposed on a surface of the semiconductor substrate covering the second surface, and in a first direction, a projection of the second gate region coincides with a projection of the channel.

In the memory device provided by the present invention, the doping type of the source region and the drain region of the tunneling field effect transistor are different, so that when a bias voltage is applied to the first gate region, the drain region may be made Free charge flows to the well layer and is stored in the well layer, and when a bias of opposite polarity is applied to the first gate region, free charge in the well layer passes through the source The area is released, the data is read and written in the storage device, the reliability is high, and multiple read and write operations can be performed.

Preferably, the semiconductor substrate is an intrinsic semiconductor or a doped semiconductor having a doping concentration of less than 10 ¹⁷ cm ^-3 ; the well layer is made of germanium or a silicon germanium alloy.

Preferably, the channel is an intrinsic semiconductor or a doped semiconductor having a doping concentration of less than 10 ¹⁷ cm ^-3 .

With reference to the first aspect, in a first possible implementation manner, the well layer is a rectangular structure, and in a third direction, a projection of the well layer does not overlap with a projection of the first gate region The third direction is perpendicular to the surface of the semiconductor substrate.

With reference to the first aspect, in a second possible implementation, the well layer is an L-type structure, and the well layer further covers a portion of the surface of the semiconductor substrate in a third direction, the The three directions are perpendicular to the surface of the semiconductor substrate.

With reference to the first aspect or the foregoing possible implementation manner of the first aspect, in a third possible implementation manner, the method further includes:

A cover layer is disposed on the surface of the well layer to cover at least one surface of the well layer in the first direction.

Preferably, the material of the cover layer is the same as the material of the semiconductor substrate such that the well layer does not undergo stress release.

With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner, when the well layer is an L-type structure, the cover layer further covers the potential well layer in a third direction a surface.

In conjunction with the fourth possible implementation of the first aspect, in a fifth possible implementation, the cover layer extends over the second direction to cover the surface of the semiconductor substrate.

With reference to the first aspect or any one of the foregoing possible implementation manners of the first aspect, in a sixth possible implementation manner, the tunneling field effect transistor is a P-type transistor.

In conjunction with the sixth possible implementation of the first aspect, in a seventh possible implementation, the doping type of the source region is N-type doping; the doping type of the drain region is P-type doping The valence band top of the well layer material is higher than the valence band top of the channel material.

Combining the first aspect or the first possible implementation of the first aspect to the fifth possible implementation In an eighth possible implementation manner, the tunneling field effect transistor is an N-type transistor.

With reference to the eighth possible implementation manner of the first aspect, in a ninth possible implementation manner, the doping type of the source region is P-type doping; and the doping type of the drain region is N-type doping The conduction band layer of the well layer material is lower than the conduction band bottom of the channel material.

In a second aspect, the present invention provides a method of fabricating a memory device, the method comprising:

Providing a semiconductor substrate;

Etching a first side of the first direction of the surface of the semiconductor substrate to form a first exposed region, and forming a well layer in a partial region of the surface of the first exposed region;

Etching a second side of the first direction of the surface of the semiconductor substrate to form a second exposed area, the second side being opposite to the first side;

Forming a first gate region and a second gate region disposed opposite to each other in the first direction in the first exposed region and the second exposed region, wherein the first gate region covers a portion of the surface and portion of the well layer The surface of the first exposed region, the portion of the semiconductor substrate between the first gate region and the second gate region is a channel;

Ion doping the semiconductor substrate on opposite sides of the channel in the second direction to form a source region and a drain region, the source region and the drain region having different doping types, and in the In one direction, the projection of the well layer at least partially overlaps the projection of the source region, and the projection of the drain region does not overlap;

Wherein the first direction and the second direction are both parallel to the surface of the semiconductor substrate, and the first direction and the second direction are perpendicular.

In the memory device fabricated by the fabrication method provided by the present invention, the doping type of the source region and the drain region are different, so that when a bias voltage is applied on the first gate region, the drain region can be made a free charge flows into the well layer, is stored in the well layer, and when a bias of opposite polarity is applied on the first gate region, a free charge in the well layer passes through the source The area is released, the data is read and written in the storage device, the reliability is high, and multiple read and write operations can be performed.

With reference to the second aspect, in a first possible implementation, after forming the well layer in the surface portion of the first exposed region, the method further includes:

A cover layer is formed on the surface of the well substrate facing away from the surface of the semiconductor substrate, the cover layer completely covering a side surface of the well layer facing away from the semiconductor substrate.

With reference to the second aspect, or the first possible implementation manner of the second aspect, in the second possible implementation, after the forming the source region and the drain region, the method further includes:

Forming a first gate electrode electrically connected to the first gate region;

Forming a second gate electrode electrically connected to the second gate region;

Forming a source electrode electrically connected to the source region;

A drain electrode electrically connected to the drain region is formed.

In a third aspect, the present invention provides a data reading and writing method, which is applied to the storage device provided in any of the above possible implementation manners, and the method includes:

Applying a first bias voltage to the first gate region in the memory device, and writing data "1" to the memory device;

Applying a second bias to the first gate region in the memory device, writing data "0" to the memory device;

Applying a third bias voltage to the second gate region and the drain in the storage device to read data stored in the storage device;

Wherein the voltages of the first bias voltage and the second bias voltage are different.

In the storage device applied by the data reading and writing method provided by the present invention, the drain region stores a free charge, and when data is read and written, its flowing charge (hole or electron) is generated by the drain region, that is, The free charge stored in the drain region is generated instead of the impact ionization, so that the memory device has high reliability and can perform multiple read and write operations.

With reference to the third aspect, in a first possible implementation manner, when the tunneling field effect transistor in the memory device is a P-type transistor, the first bias voltage is a negative bias voltage, and the second bias voltage is Positive bias.

With reference to the third aspect, in a second possible implementation manner, when the tunneling field effect transistor in the storage device is an N-type transistor, the first bias voltage is a positive bias voltage, and the second bias voltage is Negative bias.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a schematic structural diagram of a storage device according to an embodiment of the present invention;

2 is a flow chart of a method of fabricating the memory device shown in FIG. 1;

3-12 are cross-sectional views showing steps in the manufacturing process of the memory device shown in FIG. 1;

FIG. 13 is a flowchart of a data reading and writing method according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

An embodiment of the present invention provides a storage device, where the storage device includes a tunneling field effect transistor. As shown in FIG. 1, the tunneling field effect transistor includes:

Semiconductor substrate 1;

a channel 67 on the surface of the semiconductor substrate 1, having a first surface and a second surface opposite to each other in the first direction X, and a third surface opposite to each other in the second direction Y And a fourth surface, the first direction X and the second direction Y are both parallel to the surface of the semiconductor substrate 1, and the second direction Y is perpendicular to the first direction X;

a source region 6 and a drain region 7, the source region 6 and the drain region 7 are located on a surface of the semiconductor substrate 1, and are disposed opposite to each other in the second direction Y, the source region 6 covering the third surface, The drain region 7 covers the fourth surface, and the doping types of the source region 6 and the drain region 7 are different;

a well layer 3, the well layer 3 is located on the surface of the semiconductor substrate 1, covering at least one surface of the source region 6 in the first direction X and a portion of the first surface;

a first gate region 51, the first gate region 51 is located on a surface of the semiconductor substrate 1, covering a portion of the first surface, and extending along the second direction Y to cover a portion of the well layer 3 a surface of the channel 67, and in a first direction X, a projection of the first gate region 51 and the channel 67 coincide;

a second gate region 52, the second gate region 52 is located on a surface of the semiconductor substrate 1, covering the second surface, and in a first direction X, a projection of the second gate region 52 and the trench The projection of the track 67 coincides.

It should be noted that, in the above embodiment, the first gate region includes a gate dielectric layer and a gate electrode layer on a surface of the gate dielectric layer. Similarly, the second gate region also includes a gate dielectric layer and is located The gate electrode layer on the surface of the gate dielectric layer, that is, the first gate region and the second gate region are a stacked structure composed of a gate dielectric layer and a gate electrode layer on the surface of the gate dielectric layer.

Based on the above embodiment, in one embodiment of the present invention, the well layer 3 covers the portion Dividing a surface of the source region in the first direction X, in another embodiment of the invention, the well layer 3 covers a surface of all of the source regions 6 in the first direction X, the present invention This is not limited as long as it is ensured that the projection of the well layer 3 at least partially overlaps the projection of the source region 6 in the first direction X. It should be noted that, in the embodiment of the present invention, the material of the well layer 3 is different from the material of the channel 67. Preferably, the material of the well layer 3 is made of tantalum or silicon germanium alloy, which is not limited by the invention, as the case may be.

On the basis of the above embodiments, in one embodiment of the present invention, the well layer 3 is a rectangular structure, and in the third direction Z, the projection of the well layer 3 and the first gate The projections of the regions 51 do not overlap, and the third direction X is perpendicular to the surface of the semiconductor substrate 1; in another embodiment of the invention, the well layer 3 is an L-type structure, the well layer 3 also covers a portion of the surface of the semiconductor substrate 1 in the third direction Z, which is perpendicular to the surface of the semiconductor substrate 1. The invention is not limited thereto.

It should be noted that, in the embodiment of the present invention, the semiconductor substrate 1 may be an intrinsic semiconductor substrate or a low concentration doped semiconductor substrate, which is not limited by the present invention, as the case may be. And set. Preferably, when the semiconductor substrate 1 is a low concentration doped semiconductor substrate, the doping concentration of the semiconductor substrate 1 is less than 10 ¹⁷ cm ^-3 .

The tunneling field effect transistor provided by the embodiment of the present invention will be described below with reference to specific examples.

Based on the above embodiments, in one embodiment of the invention, the tunneling field effect transistor is a P-type transistor. In the embodiment of the present invention, the doping type of the source region 6 is N-type doping; the doping type of the drain region 7 is P-type doping; the valence band top of the material of the well layer 3 is higher than The valence band of the material of the channel 67 is topped so that when a negative bias is applied to the first gate region 51, the drain region 7 Holes enter the well layer 3 through the channel 67, write "1" to the memory device, and apply a positive bias on the first gate region 51, in the well layer 3 The holes enter the source region 6 through the overlapping region of the well layer 3 and the source region 6, are released at the source region 6, and write "0" to the memory device. Wherein, the valence band top of the material of the well layer 3 is the highest value of the valence band energy of the material of the well layer 3, and the valence band top of the material of the channel 67 is also the valence band of the material of the channel 67. The highest value of energy.

In another embodiment of the invention, the tunneling field effect transistor is an N-type transistor. In the embodiment of the present invention, the doping type of the source region 6 is P-type doping; the doping type of the drain region 7 is N-type doping; the conduction band bottom of the well layer 3 material is lower than The conduction band of the channel 67 material, such that when a positive bias is applied to the first gate region 51, electrons in the drain region 7 enter the well layer 3 through the channel 67, toward Writing "1" in the storage device, when a negative bias is applied to the first gate region 51, electrons in the well layer 3 pass through the well layer 3 and the source region 6 The stacked area enters the source area 6, where it is released, and a "0" is written to the storage device. Wherein, the conduction band bottom of the material of the well layer 3 is the lowest value of the conduction band energy of the material of the well layer 3, and the conduction band bottom of the material of the channel 67 is the conduction band energy of the material of the channel 67 The lowest value.

It should be noted that, in the above embodiment, when a certain bias voltage is applied to the second gate region 52, inter-band tunneling occurs between the source region 6 and the channel 67, when the storage When the data stored in the device is not the same (such as "1" or "0"), the number of holes or electrons in the well layer 3 is different, and correspondingly, between the source region 6 and the channel 67 The tunneling current is also different. Therefore, the storage current in the storage device can be read according to the tunneling current between the source region 6 and the channel 67 when a certain bias voltage is applied to the second gate region 52. The data.

In any of the above embodiments, the semiconductor substrate 1 is different in material from the well layer 3, and different materials have different lattice constants. Therefore, in order to prevent stress release in the well layer 3, On the basis of any of the above embodiments, in one embodiment of the present invention, the tunneling field effect transistor further includes: a cover layer 4, the cover layer 4 is located on the surface of the well layer 3, at least covering the A surface of the well layer 3 in the first direction X is described. Wherein the material of the cover layer 4 and the semi-conductive The material of the bulk substrate 1 is the same so that the well layer 3 does not undergo stress release.

It should be noted that, in the above embodiment, when the well layer 3 is a rectangular structure, the cover layer 4 is also a rectangular structure, and the cover layer 4 is projected in the first direction X. Fully covering the projection of the well layer 3 in the first direction X; when the well layer 3 is an L-shaped structure, the cover layer 4 is also an L-shaped structure, and the cover layer 4 also covers the A surface of the well layer 3 in the third direction Z, that is, the projection of the cover layer 4 in the first direction X completely covers the projection of the well layer 3 in the first direction X, and the cover layer The projection in the third direction Z completely covers the projection of the well layer 3 in the third direction Z.

It should be noted that, in the embodiment of the present invention, the projection of the cover layer 4 in the first direction X covers only the well layer 3 in the first direction X. Projection, and the projection of the cover layer 4 in the third direction Z only covers the projection of the well layer 3 in the third direction Z; in other embodiments of the invention, the cover layer 4 can also Extending to cover the surface of the semiconductor substrate 1 in the second direction, covering a region between the semiconductor substrate 1 and the first gate region 51 and the semiconductor substrate 1 facing the first gate region 51 There is a bare area on one side.

Correspondingly, the embodiment of the present invention further provides a method for fabricating the foregoing storage device, which is applied to the storage device provided by any of the foregoing embodiments. As shown in FIG. 2, the manufacturing method includes:

S101: As shown in FIG. 3, a semiconductor substrate 1 is provided. In the embodiment of the present invention, the semiconductor substrate 1 may be a silicon substrate or a substrate of a III-V semiconductor material, which is not limited by the present invention, as the case may be. The storage device provided by the embodiment of the present invention will be described below by taking the semiconductor substrate 1 as a silicon substrate as an example.

It should be noted that the semiconductor substrate 1 may be an intrinsic semiconductor substrate 1 or a low concentration doped P-type or N-type semiconductor substrate.

S102: etching a first side of the first direction of the surface of the semiconductor substrate 1 to form a first exposed region, and forming a well layer 3 in a partial portion of the surface of the first exposed region. Wherein the first direction is parallel to a surface direction of the semiconductor substrate 1.

Specifically, in an embodiment of the present invention, the first side of the first direction of the surface of the semiconductor substrate 1 is etched to form a first exposed area, and is formed in a partial area of the surface of the first exposed area The well layer 3 includes:

S1021: As shown in FIG. 4, a first mask layer 2 is formed on the surface of the semiconductor substrate 1. Preferably, the first mask layer 2 is formed by a chemical vapor deposition process or a physical vapor deposition process or heat. In the oxidation process or the like, the material of the first mask layer 2 is silicon oxide, silicon nitride or silicon oxynitride, and the like, which is not limited by the present invention, as the case may be.

S1022: as shown in FIG. 5, patterning the first mask layer 2, etching the first mask layer 2, and using the etched first mask layer 2 as a mask The semiconductor substrate 1 is etched to form a first exposed region A, wherein the etching process of the first mask layer 2 and the semiconductor substrate 1 may be a dry etching process or a wet etching process. The etch process is not limited by the present invention, and is determined by the circumstances.

S1023: as shown in FIG. 6 and FIG. 7, depositing a well layer 3 on the surface of the first exposed region A, and etching away part of the well layer 3, only in a surface portion of the first exposed region A A well layer 3 is formed. The material of the well layer 3 is preferably tantalum or a silicon germanium alloy.

On the basis of any of the above embodiments, in an embodiment of the present invention, after the forming the well layer 3 in the surface portion of the first exposed region, the manufacturing method further includes: as shown in FIG. The well layer 3 faces away from the surface of the semiconductor substrate 1 to form a cover layer 4 which completely covers the surface of the well layer 3 facing away from the side of the semiconductor substrate 1, ie, between S102 and S103:

S102-103: forming a cover layer 4 on the surface of the well substrate 3 facing away from the semiconductor substrate 1, the cover layer 4 completely covering the surface of the well layer 3 facing away from the semiconductor substrate 1.

It should be noted that, in this embodiment, the cover layer 4 may cover only the surface of the well layer 3 facing away from the semiconductor substrate 1 or may not only cover the well layer 3 away from the semiconductor. The surface of one side of the substrate 1 also covers the remaining portion of the surface of the first bare region A.

It should be noted that, in the embodiment of the present invention, the material of the cover layer 4 and the semiconductor The material of the substrate 1 is preferably the same to prevent stress release in the well layer 3.

S103: etching a second side of the first direction of the surface of the semiconductor substrate 1 to form a second exposed area, wherein the second side and the first side are opposite to each other in the first direction .

Specifically, in an embodiment of the present invention, as shown in FIG. 9, etching the second side of the first direction of the surface of the semiconductor substrate 1 to form the second exposed area B includes:

Graphically patterning a surface of the first mask layer 2 opposite to the first exposed region A, etching the first mask layer 2, and masking the etched first mask layer 2 The film etches the second side of the first direction of the surface of the semiconductor substrate 1 to form a second exposed region B such that the first exposed area A and the second exposed area B constitute a fin structure. The second side is a side opposite to the first side in the first direction, and the second exposed area B is opposite to the first exposed area A in the first direction.

S104: forming a first gate region 51 and a second gate region 52 disposed opposite to each other in the first direction in the first exposed area A and the second exposed area B, wherein the first gate area 51 covers a portion of the area The surface of the well layer 3 and a portion of the surface of the first exposed A region are described, and the portion of the semiconductor substrate 1 between the first gate region 51 and the second gate region 52 is a channel 67.

Specifically, in an embodiment of the present invention, the first exposed area A and the second exposed area B form a first gate region 51 and a second gate region 52 which are oppositely disposed in the first direction, Wherein the first gate region 51 covers a portion of the surface of the well layer 3 and a portion of the surface of the first exposed region A, and the portion between the first gate region 51 and the second gate region 52 The portion of the semiconductor substrate 1 that is the channel 67 includes:

S1041: forming a gate stack structure 5 in the first exposed area A and the second exposed area B as shown in FIG. 10, the gate stacked structure 5 covering the surface of the remaining first mask layer 2, a first exposed area A portion surface, the well layer 3 surface, and the second exposed area B surface;

S1042: etching the gate stack structure 5 in a second direction, such that the gate stack structure 5 covers only a portion of the surface of the first mask layer 2, the surface of the first exposed region A, Part of the surface of the well layer 3 and the surface of the second exposed area B. Wherein the second direction is parallel to the surface of the semiconductor substrate 1, and the second direction is perpendicular to the first direction.

S105: as shown in FIG. 11, ion doping the semiconductor substrate 1 on opposite sides of the channel 67 in the second direction to form a source region 6 and a drain region 7, the source region 6 and the The doping type of the drain region 7 is different, and in the first direction, the projection of the well layer 3 at least partially overlaps the projection of the source region 6, and does not overlap the projection of the drain region 7. .

Specifically, ion doping is performed on the semiconductor substrate 1 located on opposite sides of the channel in the second direction, and forming the source region 6 and the drain region 7 includes:

S1051: etching the remaining portion of the first mask layer 2 in a second direction;

S1052: using the gate stack structure and the first mask layer 2 covered by the gate stack structure as a mask, spin-coating the photoresist and patterning the first side of the semiconductor substrate 1 in the second direction Ion implantation to form a drain region 7;

S1053: using the gate stack structure and the first mask layer 2 covered by the gate stack structure as a mask, spin-coating the photoresist and patterning and draining the second side of the semiconductor substrate 1 in the second direction. Ion implantation forms a source region 6, wherein the second side in the second direction is the side opposite the first side in the second direction.

It should be noted that, in the embodiment of the present invention, the doping type of the source region 6 and the drain region 7 are different. When the storage device is a P-type transistor, the doping type of the source region 6 is N-type doping; the doping type of the drain region 7 is P-type doping; when the memory device is an N-type transistor, the doping type of the source region 6 is P-type doping; the drain region The doping type of 7 is N-type doping.

It should be noted that, in the embodiment of the present invention, after the source region 6 and the drain region 7 are formed, in the first direction, the projection of the well layer 3 and the source region 6 The projections at least partially overlap, do not overlap the projection of the drain region 7, and the well layer 3 also partially overlaps the channel 67. Wherein, in the first direction, the projection of the well layer 3 and the projection of the source region 6 at least partially overlap may be the projection and the well layer 3 in the first direction The projection part of the source area 6 is intersected The stack may also be such that in the first direction, the projection of the well layer 3 completely covers the projection of the source region 6.

Finally, as shown in FIG. 12, the gate stack structure 5 and the first mask layer 2 covered by the gate stack structure 5 are etched to form first gate regions 51 and second disposed opposite each other in the first direction. Gate region 52. It should be noted that, in other embodiments of the present invention, the gate stack structure 5 and the first mask layer 2 may be further etched in step S4 to form first gate regions 51 and oppositely disposed in the first direction. The second gate region 52, when the source region 6 and the drain region 7 are subsequently formed, a second mask layer is formed, and the second mask layer is used as a mask, and the second mask layer is located on both sides of the channel 67 in the second direction. The semiconductor substrate 1 is subjected to ion implantation, which is not limited in the present invention, as the case may be.

On the basis of any of the above embodiments, in an embodiment of the present invention, the manufacturing method further includes: after the source region 6 and the drain region 7 are formed:

S106: forming a first gate electrode electrically connected to the first gate region 51; forming a second gate electrode electrically connected to the second gate region 52; forming a source electrically connected to the source region 6. An electrode; a drain electrode electrically connected to the drain region 7 is formed.

Specifically, the first gate electrode, the second gate electrode, the source electrode, and the drain electrode may be formed by: forming the first gate region 51 and the second layer An insulating layer of the gate region 52, the source region 6, and the drain region 7; formed in the insulating layer respectively corresponding to the first gate region 51, the second gate region 52, the source region 6 and a contact hole of the drain region 7; depositing a metal in each of the contact holes while forming the first gate electrode, the second gate electrode, the source electrode, and the drain electrode. However, the present invention is not limited thereto. In other embodiments of the present invention, the first gate electrode, the second gate electrode, the source electrode, and the drain electrode may also be formed separately. , depending on the situation.

In summary, in the storage device and the manufacturing method thereof provided by the embodiments of the present invention, the source area 6 Different from the doping type of the drain region 7, so that when a bias voltage is applied to the first gate region 51, the free charge in the drain region 7 can be caused to flow to the well layer 3, and stored in the In the well layer 3, when a bias of opposite polarity is applied to the first gate region 51, free charges in the well layer 3 are released through the source region 6 to realize data in the memory device. Read and write, high reliability, can perform multiple read and write operations.

In addition, the embodiment of the present invention further provides a data reading and writing method, which is applied to the storage device provided by any of the foregoing embodiments. As shown in FIG. 13, the data reading and writing method includes:

S301: applying a first bias to the first gate region in the storage device, and writing data "1" to the storage device;

S302: applying a second bias to the first gate region in the storage device, and writing data "0" to the storage device;

S303: Apply a third bias voltage to the second gate region and the drain in the storage device, and read data stored in the storage device.

It should be noted that, in the embodiment of the present invention, the third bias voltage may be the same as the first bias voltage, or may be different from the first bias voltage, which is not limited by the present invention. Depending on the situation.

On the basis of the above embodiments, in one embodiment of the present invention, when the tunneling field effect transistor in the memory device is a P-type transistor, the first bias voltage is a negative bias voltage, and the second bias The pressure is positively biased. Specifically, when a negative bias is applied on the first gate region, holes in the drain region enter the potential well layer through the channel, and “1” is written into the storage device. When a positive bias is applied to the first gate region, holes in the well layer enter the source region through an overlapping region of the well layer and the source region, and are released in the source region. A "0" is written to the storage device.

In another embodiment of the invention, when the tunneling field effect transistor in the memory device is an N-type transistor, the first bias voltage is a positive bias voltage and the second bias voltage is a negative bias voltage. Specifically, when When a positive bias is applied to the first gate region, electrons in the drain region enter the well layer through the channel, and write "1" to the memory device when the first gate region When a negative bias is applied, electrons in the well layer enter the source region through an overlapping region of the well layer and the source region, are released in the source region, and write to the storage device Enter "0".

In the above embodiment, when a third bias is applied to the second gate region, inter-band tunneling occurs between the source region and the channel, when data stored in the memory device is different (such as "1" or "0"), the number of holes or electrons in the well layer is different, and correspondingly, the tunneling current between the source region and the channel is also different, and therefore, according to When a third bias voltage is applied to the second gate region, a tunneling current between the source region and the channel reads data stored in the memory device.

Thus, in the storage device provided by the embodiment of the present invention, the drain region stores a free charge, and when data is read and written, its flowing charge (hole or electron) is generated by the drain region, that is, The free charge stored in the drain region is generated instead of the impact ionization, so that the memory device has high reliability and can perform multiple read and write operations.

Each part of this manual is described in a progressive manner. Each part focuses on the differences from other parts. The same similar parts between the parts can be referred to each other.

The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments are obvious to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but the scope of the invention.

Claims

A storage device, characterized in that the storage device comprises a tunneling field effect transistor, the tunneling field effect transistor comprising:

Semiconductor substrate

a channel, on a surface of the semiconductor substrate, having first and second surfaces opposite to each other in a first direction, and third and fourth surfaces opposite to each other in a second direction, the second direction And the first direction is parallel to the surface of the semiconductor substrate, and the second direction is perpendicular to the first direction;

a source region and a drain region on the surface of the semiconductor substrate, disposed opposite to each other in a second direction, the source region covering the third surface, the drain region covering the fourth surface, the source region and The doping type of the drain region is different;

a well layer on the surface of the semiconductor substrate covering at least one surface of the source region in a first direction and a portion of the first surface;

a first gate region on a surface of the semiconductor substrate covering a portion of the first surface and extending in the second direction to cover a portion of the well layer facing away from a surface of the channel, and at a first a direction in which the projection of the first gate region coincides with the projection of the channel;

A second gate region is disposed on a surface of the semiconductor substrate covering the second surface, and in a first direction, a projection of the second gate region coincides with a projection of the channel.
The memory device according to claim 1, wherein the well layer is a rectangular structure, and in a third direction, a projection of the well layer does not overlap with a projection of the first gate region. The third direction is perpendicular to the surface of the semiconductor substrate.
The memory device according to claim 1, wherein said well layer is an L-type structure, said well layer further covering a portion of said semiconductor substrate in a third direction, said third The direction is perpendicular to the surface of the semiconductor substrate.
The storage device according to any one of claims 1 to 3, further comprising:

A cover layer is disposed on the surface of the well layer to cover at least one surface of the well layer in the first direction.
The memory device according to claim 4, wherein when said well layer is an L-type structure, said cover layer further covers a surface of said well layer in a third direction.
The memory device according to claim 5, wherein the cover layer extends over the second direction to cover the surface of the semiconductor substrate.
The memory device according to any one of claims 1 to 6, wherein the tunneling field effect transistor is a P-type transistor.
The memory device according to claim 7, wherein the doping type of the source region is N-type doping; the doping type of the drain region is P-type doping; and the price of the well layer material The band top is higher than the valence band top of the channel material.
The memory device according to any one of claims 1 to 6, wherein the tunneling field effect transistor is an N-type transistor.
The memory device according to claim 9, wherein the doping type of the source region is P-type doping; the doping type of the drain region is N-type doping; and the guiding of the well layer material The bottom of the tape is lower than the bottom of the channel material of the channel material.
A manufacturing method of a storage device, characterized in that the manufacturing method comprises:

Providing a semiconductor substrate;

Etching a first side of the first direction of the surface of the semiconductor substrate to form a first exposed region, and forming a well layer in a partial region of the surface of the first exposed region;

Etching a second side of the first direction of the surface of the semiconductor substrate to form a second exposed area, the second side being opposite to the first side;

Forming a first gate region and a second gate region disposed opposite to each other in the first direction in the first exposed region and the second exposed region, wherein the first gate region covers a portion of the surface and portion of the well layer The first a surface of the exposed region, the portion of the semiconductor substrate between the first gate region and the second gate region being a channel;

Ion doping the semiconductor substrate on both sides of the channel in the second direction to form a source region and a drain region, the source region and the drain region are different in doping type, and in the first In a direction, a projection of the well layer at least partially overlaps a projection of the source region, and a projection of the drain region does not overlap;

Wherein the first direction and the second direction are both parallel to the surface of the semiconductor substrate, and the first direction and the second direction are perpendicular.
The method according to claim 11, further comprising: after forming the well layer in the surface portion of the first exposed region;

A cover layer is formed on the surface of the well substrate facing away from the surface of the semiconductor substrate, the cover layer completely covering a side surface of the well layer facing away from the semiconductor substrate.
The manufacturing method according to claim 11 or 12, wherein after the forming of the source region and the drain region, the method further comprises:

Forming a first gate electrode electrically connected to the first gate region;

Forming a second gate electrode electrically connected to the second gate region;

Forming a source electrode electrically connected to the source region;

A drain electrode electrically connected to the drain region is formed.
A data reading and writing method is applied to the storage device according to any one of claims 1 to 10, characterized in that the method comprises:

Applying a first bias voltage to the first gate region in the memory device, and writing data "1" to the memory device;

Applying a second bias to the first gate region in the memory device, writing data "0" to the memory device;

Applying a third bias voltage to the second gate region and the drain in the storage device to read data stored in the storage device;

Wherein the voltages of the first bias voltage and the second bias voltage are different.
The data reading and writing method according to claim 14, wherein when the tunneling field effect transistor in the memory device is a P-type transistor, the first bias voltage is a negative bias voltage, and the second bias voltage is Is positively biased.
The data reading and writing method according to claim 14, wherein when the tunneling field effect transistor in the memory device is an N-type transistor, the first bias voltage is a positive bias voltage, and the second bias voltage is It is a negative bias.