WO2018028218A1 - 一种写数据的方法和装置 - Google Patents

一种写数据的方法和装置 Download PDF

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Publication number
WO2018028218A1
WO2018028218A1 PCT/CN2017/079343 CN2017079343W WO2018028218A1 WO 2018028218 A1 WO2018028218 A1 WO 2018028218A1 CN 2017079343 W CN2017079343 W CN 2017079343W WO 2018028218 A1 WO2018028218 A1 WO 2018028218A1
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Prior art keywords
data
written
write request
lba
controller
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PCT/CN2017/079343
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English (en)
French (fr)
Inventor
李劲松
谭春华
毛宏华
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华为技术有限公司
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Publication of WO2018028218A1 publication Critical patent/WO2018028218A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration

Definitions

  • the present invention relates to the field of data processing technologies, and in particular, to a method and an apparatus for writing data.
  • the host computer and the storage array generally communicate using a small computer system interface (SCSI) protocol.
  • the storage array includes a controller and at least one permanent medium, and the controller includes a processor, a cache, and a cache controller.
  • the method for writing data based on the SCSI protocol is as follows: the host sends a write request to the processor; after receiving the write request, the processor sends the write request to the cache controller; and then the cache controller includes the data included in the write request. Write to the cache. After the processor queries the data to the cache, it will reply to the host with a write response. Subsequently, the cache controller writes the data stored in the cache to the persistent medium.
  • the Abort command is sent to the processor to notify the processor: the host abandons the write request; after receiving the Abort command, the processor queries the Whether the data has been written into the cache; if the data has been written to the cache, the processor replies to the host with the Abort command succeeding, and after receiving the Abort command, the host sends a rewrite request to the processor, wherein the rewrite request is The logical block address (LBA) included is the same as the LBA included in the write request; if the data is not written to the cache, the processor suspends the Abort command, that is, the processor does not respond to the Abort command.
  • LBA logical block address
  • the processor queries that the data is not written into the cache within a preset period of time, the processor does not reply to the host that the Abort command succeeds, which causes the processor to reply to the Abort command successfully timed out; It is stipulated that the host can send a rewrite request to the processor after receiving the Abort command. Therefore, the above method will cause the host to fail to send a rewrite request to the processor before receiving the Abort command.
  • the data is written in the storage space corresponding to the LBA, thereby affecting the continuity of the host service.
  • an implementation is as follows: After receiving the write request sent by the host, the processor immediately returns the Abort command to the host successfully.
  • this may have the following problem: since the cache processor writes data to the permanent medium in chronological order of receiving the data to be written, if the data included in the rewrite request received by the processor is larger than the write request The included data is first written to the cache, which causes the data included in the rewrite request to be written to the persistent medium first than the data included in the write request. In this case, the data included in the rewrite request is written in the request. The included data is overwritten, causing the data stored in the persistent media to be inconsistent with the data actually written to the storage array by the host.
  • Embodiments of the present invention provide a method and apparatus for writing data to at least address the problem of data stored in a persistent medium in a storage array being inconsistent with data actually written by the host to the storage array.
  • a method for writing data includes: receiving, by a controller, a first write request sent by a host, where the first write request includes a first to-be-written data and a logical block address LBA of the first to-be-written data; After receiving the first write request, the controller receives a second write request sent by the host, where the second write request includes the second to-be-written number According to the LBA of the second data to be written, the LBA of the second data to be written is the same as the LBA of the first data to be written; then, the controller adds the first time attribute tag to the first write request and adds the second write request a second time attribute tag, where the first time attribute tag is used to indicate the time when the controller receives the first write request, and the second time attribute tag is used to indicate the time when the controller receives the second write request; The first attribute to be written and the second to-be-written data are sequentially written in the storage space corresponding to the LBA of the first data to be written in the permanent medium.
  • the communication protocol between the host and the storage array may include, but is not limited to, a SCSI protocol.
  • the controller can identify the chronological order of receiving the first to-be-written data and the second to-be-written data according to the first time attribute tag and the second time attribute tag (ie, the order in which the host actually writes data to the storage array) Therefore, the controller may sequentially write the first to-be-written data and the second to-be-written data into the storage space corresponding to the LBA of the first to-be-written data in the permanent medium according to the chronological order, thereby making the permanent medium
  • the data stored in it is consistent with the data that the host actually writes to the storage array.
  • the controller adds a first time attribute tag to the first write request, and adds a second time attribute tag to the second write request, where the controller may include: adding, after receiving the first write request, the first write request a first time attribute tag; after receiving the second write request, adding a second time attribute tag for the second write request.
  • the controller may add a time attribute label to at least one of the first write request and the second write request, so that the controller receives the first write request and the second write request.
  • the order attribute that is, the time attribute tag of the at least one write request is used to indicate that the controller receives the second write request after receiving the first write request.
  • the controller writes the first to-be-written data and the second to-be-written data into the first to-be-written data in the permanent medium according to the first time attribute label and the second time attribute label.
  • the storage space corresponding to the LBA may be replaced by: the cache controller deletes the first data to be written according to the first time attribute label and the second time attribute label, and writes the second data to be written into the permanent medium.
  • the method further includes: receiving, by the controller, an Abort command sent by the host, where the Abort command is used to notify the storage array: the host abandons the first write request; then, the controller returns the Abort command to the host successfully; Then, after the controller replies to the host that the Abort command is successful, the controller receives the second write request. Specifically, if the host does not receive the write response of the first write request replied by the processor within the preset time period, the Abort command is sent to the controller, and the controller can immediately after receiving the Abort command sent by the host.
  • the Abort command is successfully returned to the host (ie, after receiving the Abort command sent by the host, the controller replies to the host with the Abort command successfully if it is not necessary to determine whether the first to-be-written data has been written to the cache).
  • This possible implementation provides a method of writing data in a scenario in which a host communicates with a storage array through an SCSI protocol.
  • the method may include: the first time attribute tag includes a number of times the controller receives the write request of the LBA including the first data to be written; and the second time attribute tag includes the second received by the controller. The number of write requests for the LBA that wrote the data.
  • This optional implementation provides a specific implementation of the time attribute tag, which is of course not limited thereto.
  • the controller includes a processor and a cache; in this case, the controller receiving the first write request sent by the host may include: the processor receiving the first write request sent by the host.
  • the method may further include: the processor determining that there is no package in the LBA set in the cache When the LBA with the first data to be written is included, the LBA of the first data to be written is written into the LBA set; wherein the LBA set includes the LBA included in the write request that satisfies the preset condition; the write request that satisfies the preset condition refers to The write request received by the processor and included in the data to be written is not written to the cache.
  • the controller adds the second time attribute label to the second write request
  • the method may include: adding, by the processor, the second time attribute label to the second write request when querying the LBA that includes the second data to be written in the LBA set .
  • the controller may further include a cache controller, and the controller writes the first to-be-written data and the second to-be-written data in a sequential order according to the first time attribute tag and the second time attribute tag.
  • the storage space corresponding to the LBA of the first data to be written in the medium may include: the cache controller writing the first to-be-written data and the second to-be-written data according to the first time attribute tag and the second time attribute tag.
  • the storage space corresponding to the LBA of the first data to be written in the cache and then the cache controller sequentially writes the first data to be written and the second data to be written to the LBA of the first data to be written in the permanent medium. Corresponding storage space.
  • the cache controller stores the first to-be-written data and the first time attribute tag in a storage space corresponding to the LBA of the first data to be written in the cache, and is in another storage space corresponding to the LBA in the cache.
  • the second to-be-written data and the second time attribute tag are stored.
  • the LBA of the first data to be written corresponds to M storage spaces, M ⁇ 2, and M is an integer; the M storage spaces respectively correspond to the sequence in which the processor receives the write request.
  • the cache controller writes the first to-be-written data and the second to-be-written data into the storage space corresponding to the LBA of the first to-be-written data in the cache according to the first time attribute tag and the second time attribute tag.
  • the method may include: the cache controller stores the first to-be-written data and the second to-be-written data in different storage spaces in the M storage spaces according to the first time attribute label and the second time attribute label.
  • the mechanism for the cache controller to write data is related to the chronological order in which the processor receives the data to be written, and is independent of the chronological order of the data to be written received by the cache controller.
  • the LBA of the first data to be written corresponds to M storage spaces, M ⁇ 2, and M is an integer.
  • the cache controller writes the first to-be-written data and the second to-be-written data into the storage space corresponding to the LBA of the first to-be-written data in the cache according to the first time attribute tag and the second time attribute tag.
  • the method may include: the cache controller stores the first time attribute tag and the second time attribute tag, and stores the first to-be-written data and the second to-be-written data in different storage spaces in the M storage spaces.
  • the mechanism for the cache controller to write data is independent of the chronological order of the processor to receive the data to be written, and is related to the chronological order of the data to be written received by the cache controller.
  • a storage array including a controller and at least one permanent medium; the controller is configured to: receive a first write request sent by the host, where the first write request includes the first to-be-written data and the first to-be-written data a logical block address LBA; after receiving the first write request, receiving a second write request sent by the host, the second write request includes an LBA of the second data to be written and the second data to be written, and an LBA of the second data to be written.
  • the LBA of the first data to be written is the same; the first time attribute tag is added for the first write request, and the second time attribute tag is added for the second write request; the first time attribute tag is used to instruct the controller to receive the first write request.
  • the second time attribute tag is used to indicate the time when the controller receives the second write request; and the first to-be-written data and the second to-be-written data are sequentially written according to the first time attribute tag and the second time attribute tag. LBA of the first data to be written in the permanent medium In the corresponding storage space.
  • the controller may be further configured to: receive an Abort command sent by the host, where the Abort command is used to notify the storage array host to abandon the first write request; and the host returns the Abort command successfully.
  • the controller may be specifically configured to: after replying to the host, the Abort command succeeds, and receive the second write request.
  • the first time attribute tag includes a number of times that the controller receives the write request of the LBA including the first data to be written; and the second time attribute tag includes the LBA that is received by the controller and includes the second data to be written. The number of times the request was written.
  • the controller includes a processor and a cache, and the processor is configured to: receive a first write request sent by the host.
  • the processor may be further configured to: when determining that the LBA in the cache does not include the LBA with the first data to be written, write the LBA of the first data to be written into the LBA set; wherein the LBA set includes the write that meets the preset condition.
  • the LBA included in the request; wherein the write request that satisfies the preset condition refers to a write request received by the processor and the included data to be written is not written to the cache.
  • the processor may be further configured to: add a second time attribute tag to the second write request when querying the LBA that includes the second data to be written in the LBA set.
  • the controller further includes a cache controller, and the cache controller is configured to: write the first to-be-written data and the second to-be-written data into the cache according to the first time attribute tag and the second time attribute tag.
  • the first to-be-written data and the second to-be-written data are sequentially written into the storage space corresponding to the LBA of the first to-be-written data in the permanent medium in the storage space corresponding to the LBA of the first data to be written.
  • the LBA of the first data to be written corresponds to M storage spaces, M ⁇ 2, and M is an integer; the M storage spaces respectively correspond to the sequence in which the processor receives the write request.
  • the cache controller may be configured to: store the first to-be-written data and the second to-be-written data in different storage spaces in the M storage spaces according to the first time attribute label and the second time attribute label.
  • the LBA of the first data to be written corresponds to M storage spaces, M ⁇ 2, and M is an integer.
  • the cache controller may be specifically configured to: store the first time attribute tag and the second time attribute tag, and store the first to-be-written data and the second to-be-written data in different storage spaces in the M storage spaces.
  • the embodiment of the present invention provides a storage array, which can implement the functions performed by the storage array in the foregoing method embodiments, and the functions can be implemented by hardware or by executing corresponding software through hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the structure of the storage array includes a controller, at least one permanent medium and a transceiver connected to the controller, and the processor is configured to support the storage array to perform a corresponding function in the foregoing method.
  • the transceiver is used to support communication between the storage array and other network elements, such as a host.
  • the memory array can also include a memory for coupling with the processor, which stores program instructions and data necessary for the device; wherein the memory can be a permanent medium or any other than the permanent medium A storage device.
  • an embodiment of the present invention provides a communication system, including a host, and any one of the storage arrays described in the above aspects.
  • an embodiment of the present invention provides a computer storage medium for storing computer software instructions for use in the foregoing storage array, and the computer software instructions may include a program designed to perform the above aspects.
  • any of the foregoing storage arrays or computer storage media are provided for performing the method for writing data provided above. Therefore, the beneficial effects that can be achieved can be referred to the corresponding write data provided above. The beneficial effects of the method are not repeated here.
  • FIG. 1 is a schematic structural diagram of a system according to a technical solution provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of interaction of a method for writing data according to an embodiment of the present invention
  • FIG. 3(a) is a schematic diagram of a process of writing data according to an embodiment of the present invention.
  • FIG. 3(b) is a schematic diagram of another process for writing data according to an embodiment of the present invention.
  • FIG. 4(a) is a schematic diagram of another process of writing data according to an embodiment of the present invention.
  • FIG. 4(b) is a schematic diagram of another process for writing data according to an embodiment of the present invention.
  • FIG. 4(c) is a schematic diagram of another process for writing data according to an embodiment of the present invention.
  • FIG. 4(d) is a schematic diagram of another process for writing data according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of interaction of another method for writing data according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a storage array according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another storage array according to an embodiment of the present invention.
  • the technical solution provided by the embodiment of the present invention is applied to the system architecture shown in FIG. 1.
  • the system shown in FIG. 1 includes a host and a storage array, wherein the host is mainly used for controlling operations, and the storage array is mainly used for storing and managing Host related data.
  • the storage array may be a hardware entity with a complete operating system or software. In this embodiment, a hardware entity having a complete operating system is used as an example.
  • the storage array can include a controller and at least one permanent medium.
  • the controller includes a central processing unit (CPU, referred to herein as a "processor"), a cache, and a cache controller.
  • the processor is the control center of the storage array.
  • Cache is a high-speed memory between the central processor and the persistent medium.
  • the cache controller is used to manage the data in the cache. For example, it can be used to write data to the cache and write the data stored in the cache to the permanent medium.
  • Permanent media also known as non-volatile storage media, is characterized by its ability to retain content when power is lost.
  • the communication protocol between the host and the storage array can be the SCSI protocol.
  • the SCSI protocol is a communication protocol based on a C/S (client/server) architecture; wherein the client is also referred to as an initiator for sending to a SCSI target. Request instruction.
  • the host acts as a initiator, and the controller of the storage array acts as a SCSI target.
  • the embodiment of the present invention provides a method and an apparatus for writing data, the basic principle of which is: the controller of the storage array receives the first write request of the LBA including the first data to be written and the first data to be written sent by the host, and After receiving the first write request, receiving a second write request of the LBA including the second to-be-written data and the second to-be-written data; adding a first time attribute tag for the first write request, and adding a second write request a second time attribute tag, wherein the LBA of the first data to be written is the same as the LBA of the second data to be written, the first time attribute tag is used to indicate the time when the controller receives the first write request, and the second time attribute tag is used to indicate The time at which the controller receives the second write request.
  • the controller can recognize that the first waiting is received according to the first time attribute tag and the second time attribute tag.
  • the chronological order of the write data and the second data to be written ie, the order in which the host actually writes data to the storage array
  • the controller can sequentially record the first data to be written and the second data to be written according to the chronological order
  • the data is stored in the storage space corresponding to the LBA of the first data to be written in the permanent medium, so that the data stored in the permanent medium is consistent with the data actually written by the host to the storage array.
  • FIG. 2 it is an interaction diagram of a method for writing data according to an embodiment of the present invention, which is applied to a scenario in which a host sends a write request to a controller, where the method includes:
  • the host sends a first write request to the controller.
  • the first write request includes the first to-be-written data and the LBA of the first to-be-written data.
  • the host sends a second write request to the controller.
  • the second write request includes an LBA of the second to-be-written data and the second to-be-written data, and the LBA of the first to-be-written data is the same as the LBA of the second to-be-written data.
  • the permanent medium may include one or more storage spaces, each storage space corresponding to one physical address, and each physical address corresponds to one LBA.
  • the LBA of the first data to be written in S101 ie, the LBA of the second data to be written in S102
  • the first data to be written may be the same as or different from the second data to be written. This is because the host can modify the data in the storage space corresponding to any LBA written in the permanent medium as needed. It is assumed that the time when the host sends the first write request to the controller is marked as the first time, and the time when the host sends the second write request to the controller is marked as the second time; then, if the time from the first time to the second time In the segment, the host does not modify the data in the storage space corresponding to the LBA of the first data to be written in S101, and the first data to be written is the same as the data to be written in the second time; During the time period, the host modifies the data in the storage space corresponding to the LBA of the first data to be written in S101, and the first data to be written is different from the second data to be written.
  • S103 The controller receives the first write request and the second write request sent by the host, and adds a first write request.
  • a time attribute tag that adds a second time attribute tag to the second write request.
  • the controller after receiving the first write request, adds a first time attribute tag for the first write request; after receiving the second write request, adds a second time attribute tag for the second write request.
  • the controller receives the two write requests including the same LBA sent by the host as an example.
  • the controller may receive the host sending.
  • the first time attribute tag may be any character or character string indicating the time when the controller receives the first write request, for example, may be the number of times the controller receives the write request of the LBA including the first data to be written.
  • the second time attribute tag may be any character or character string indicating the time when the controller receives the second write request, for example, may be the number of times the controller receives the write request of the LBA including the second data to be written.
  • S104 The controller writes the first to-be-written data and the second to-be-written data into the storage corresponding to the LBA of the first to-be-written data in the permanent medium according to the first time attribute label and the second time attribute label. In space.
  • the controller first receives a first write request of an LBA including a first to-be-written data and a first to-be-written data, and adds a first time attribute label to the first write request.
  • the controller receives a second write request of the LBA including the second to-be-written data and the second to-be-written data, and adds a second time attribute tag to the second write request, such that the controller can be based on the first time attribute tag
  • the second time attribute tag identifies a chronological order of receiving the first to-be-written data and the second to-be-written data (ie, a sequence in which the host actually writes data to the storage array), and therefore, the controller may follow the chronological order
  • the first to-be-written data and the second to-be-written data are sequentially written into a storage space corresponding to the LBA of the first to-be-written data in the permanent medium, so that the data stored in the permanent medium and the host are actually in the storage array.
  • the data written is consistent.
  • the controller adds a first time attribute label for the first write request, and adds a second time attribute label for the second write request as an example.
  • the controller may Adding a time attribute tag to at least one of the first write request and the second write request.
  • the foregoing S103 may be replaced by the following steps: the controller receives the first write request and the second write request sent by the host, And adding a time attribute tag to the at least one write request of the first write request and the second write request, wherein the time attribute tag of the at least one write request is used to indicate that the controller first receives the first write request and then receives the second write request.
  • the processor adds a time attribute tag to at least one of the first write request and the second write request, thereby distinguishing that the processor receives the first write request and the first The chronological order of the second write request.
  • the host and the disk array can pre-negotiate whether at least one write request is the first write request (ie, the first write request), the rewrite request (ie, the second write request), or the first write request and rewrite. request.
  • N ⁇ 2 in order to ensure that the data stored in the permanent medium is consistent with the data actually written by the host to the disk array, only the last received by the processor is required to carry the data.
  • the LBA rewrite request adds a time attribute tag to ensure that the cache controller recognizes the last rewrite request received by the processor that carries the LBA, thereby ensuring that the cache controller finally writes the processor to the permanent medium.
  • the received rewrite request carrying the LBA at one time since the processor does not know whether the current rewrite request sent by the host is the last rewrite request (unless the rewrite request is the Nth rewrite request) , Therefore, in general, for the convenience of implementation, a time attribute tag may be added for each rewrite request that carries the LBA; of course, in a specific implementation, the first write request carrying the LBA and each carrying the LBA may also be used.
  • the rewrite request adds a time attribute tag.
  • the controller includes a processor and a cache, wherein the cache may include one or more storage spaces, each storage space corresponding to one physical address, and one or more physical addresses may correspond to one LBA.
  • the method may further include:
  • S101a The host sends an Abort command to the processor to notify the storage array that the host discards the first write request.
  • the SCSI protocol stipulates that after receiving the write request sent by the host and querying that the cache controller has written the data to be written included in the write request to the cache, the processor will reply the write response to the host; if the host is in the preset time period If no write response is received from the processor, the Abort command is sent to the processor.
  • the reason that the host does not receive the write response of the first write request replied by the processor within the preset time period may be any one of the following: the processor has not written the first to-be-written data into the cache; the processor The data is being written to the cache; the processor has written the first to-be-written data to the cache and is replying to the host with a write response to the first write request.
  • S101a may include: sending an Abort command to the processor if the host does not receive a write response to the first write request replied by the processor within a preset time period.
  • S101b The processor receives the Abort command sent by the host, and returns a success of the Abort command to the host.
  • the processor may immediately reply the host with the Abort command successfully; that is, after receiving the Abort command sent by the host, the processor does not need to determine the first to be written. In the case where the data has been written to the cache, the host replies to the Abort command successfully.
  • S102a After receiving the success of the Abort command sent by the processor, the host sends a rewrite request to the processor; wherein the rewrite request may be a second write request.
  • the second write request may also be an overwrite request of the LBA including the second data to be written, which is sent by the host after sending the first write request.
  • the host After receiving the success of the Abort command sent by the processor, the host sends a rewrite request to the processor; if the host does not receive a response to the rewrite request replied by the processor within a preset time period, then the host The Abort command is sent to the processor, and after receiving the success of the Abort command sent by the processor, the host sends a rewrite request to the processor again, and the rewrite request is a second write request.
  • the rewriting request of the LBA including the second to-be-written data is taken as an example.
  • the processor may determine whether the second write request is rewritten as follows.
  • the first pending write request is sent by the processor, and the first pending write data is obtained when the LBA in the cache does not store the LBA of the first data to be written included in the first write request.
  • the LBA write cache wherein the LBA set includes an LBA included in the write request that satisfies the preset condition, and the write request that satisfies the preset condition refers to the received request received by the processor, and the included data to be written is not written into the cache.
  • the processor receives the second write request, it can query whether the LBA of the second data to be written included in the second write request is stored in the cache, and store the second write request in the cache.
  • the LBA including the second data to be written it is determined that the second write request is a rewrite request, wherein the LBA of the first data to be written and the LBA of the second data to be written are the same.
  • the S103 can be implemented in the following two manners based on the optional implementation manner:
  • Optional implementation 1 the processor receives the second write request and queries the cache to store the second write request After the LBA of the second data to be written is requested, a second time attribute tag is added for the second write request.
  • the processor successively receives a write request including LBA1, a write request including LBA2, a write request 3 including LBA2, and a write request 4 including LBA1 in chronological order; then, if the processor is a write request 1
  • the assigned time attribute tag is "1" to indicate that the write request 1 is the first write request received by the processor including LBA1, and the time attribute tag assigned to the write request 4 is "2";
  • the time attribute tag assigned by the write request 2 is "1", and the time attribute tag assigned to the write request 3 is "2", as shown in Table 1.
  • Optional implementation 2 when receiving the second write request, the processor does not query whether the LBA of the second to-be-written data included in the second write request is stored in the cache (ie, it is not required to determine whether the second write request is heavy Write request), adding a second time attribute tag directly to the second write request.
  • the processor successively receives a write request including LBA1, a write request including LBA2, a write request 3 including LBA2, and a write request 4 including LBA1 in chronological order; then, if the processor is a write request 1
  • the time attribute tag assigned is "1" to indicate that the write request 1 is the first write request received by the processor, and the time attribute tags allocated for the write requests 2, 3, and 4 are respectively "2", “3" ",” "4", as shown in Table 2.
  • the maximum value of the time attribute tag in the above optional implementation 1 is determined according to the maximum number of rewrites in the rewriting mechanism, for example, if the maximum number of rewrites in the rewriting mechanism is N, then The maximum value of the time attribute tag is N+1; and the maximum value of the time attribute tag in the above optional implementation 2 is determined according to the total number of write requests sent by the host to the processor, for example, if the host is to the processor The total number of write requests sent is W, and the maximum value of the time attribute tag is W. Generally, W is much larger than N. Therefore, the storage space occupied by each time attribute label in the optional implementation 2 is far larger than the storage space occupied by each time attribute label in the optional implementation 1 above. Therefore, the above optional implementation 2 is applicable to a scenario in which the number of write requests sent by the host to the processor is small.
  • the controller may further include a cache controller.
  • S104 may include:
  • S104a The cache controller writes the first to-be-written data and the second to-be-written data into a storage space corresponding to the LBA of the first to-be-written data in the cache according to the first time attribute tag and the second time attribute tag, and then Writing the first to-be-written data and the second to-be-written data sequentially into the LBA corresponding to the first data to be written in the permanent medium storage.
  • the cache controller stores the first to-be-written data and the first time attribute tag in a storage space corresponding to the LBA of the first data to be written in the cache, and is in another storage space corresponding to the LBA in the cache.
  • the second to-be-written data and the second time attribute tag are stored.
  • the cache controller deletes the first data to be written according to the first time attribute label and the second time attribute label, and writes the second data to be written into the LBA corresponding to the first data to be written in the permanent medium. In storage space.
  • the processor adds a time attribute tag to one of the first write request and the second write request. For example, if the processor adds the first time attribute tag to the first write request, the cache controller stores the first to-be-written data and the first time attribute in a storage space corresponding to the LBA of the first data to be written in the cache. The tag stores the second to-be-written data in another storage space corresponding to the LBA in the cache. If the processor adds a second time attribute tag to the second write request, the cache controller stores the first to-be-written data in a storage space corresponding to the LBA of the first data to be written in the cache, and the LBA in the cache The second storage data and the second time attribute label are stored in the corresponding another storage space.
  • the LBAs in S101 and S102 correspond to M storage spaces, M ⁇ 2, and M is an integer.
  • the value of M may be determined according to the maximum number of rewrites. For example, if the maximum number of rewrites is N, each LBA may correspond to N+1 storage spaces, that is, in the cache, each LBA.
  • the number of corresponding storage spaces can store at least the first write request including the same LBA and the data included in each rewrite request, so as to ensure that the data in the storage space corresponding to the same LBA is not lost every time the cache is written. package.
  • S103 can be implemented in any of the following manners, wherein the following implementations all include the first time attribute tag including the number of times the controller receives the write request of the LBA including the first data to be written, and the second time attribute tag includes the control.
  • the number of times the write request of the LBA including the second data to be written is received by the device is described as an example.
  • Manner 1 The M storage spaces respectively correspond to the chronological order in which the processor receives the write request; the cache controller follows the first time attribute tag and the second time attribute tag, and the LBA and the second to-be-written data in the cache are in the cache.
  • the first to-be-written data and the second to-be-written data are stored in different storage spaces corresponding to the LBAs that write data.
  • the mechanism for the cache controller to write data is related to the chronological order in which the processor receives the data to be written, and is independent of the chronological order of the data to be written received by the cache controller.
  • the first to-be-written data and the second to-be-written data are sorted in the chronological order in which the processor receives the data to be written to obtain a sequence 1: the first to be written.
  • Data, the second to-be-written data; the M storage spaces include the first storage space and the second storage space, and are arranged in a chronological order according to the corresponding processor receiving the write request to obtain the sequence 3: the first storage space, the second storage.
  • the cache controller writes data to the M storage spaces according to the sequence 1, that is, at the first The first to-be-written data is written in the storage space, and the second to-be-written data is written in the second storage space.
  • the chronological order in which the cache controller receives the data to be written is sequence 2: the second data to be written and the first data to be written
  • the cache controller receives the data to be written.
  • the chronological order is still sequence 1.
  • the cache controller sequentially writes the first to-be-written data and the second to-be-written data into the storage space corresponding to the LBA of the first data to be written in the permanent medium, and may include: a cache controller. Root The data to be written in the M storage spaces is sequentially written into the storage space corresponding to the LBA of the first to-be-written data of the permanent medium according to the chronological order of the M storage spaces respectively. For example, based on the above example, the cache controller writes the data to be written (ie, the first data to be written) stored in the first storage space according to the sequence 3 into the storage space corresponding to the LBA of the first to-be-written data of the permanent medium. And writing the data to be written (that is, the second data to be written) stored in the second storage space to the storage space corresponding to the LBA of the first data to be written of the permanent medium.
  • the cache controller deletes the first data to be written, and writes the second data to be written into the storage space corresponding to the LBA of the first data to be written in the permanent medium, which may include: The controller deletes data in the non-last storage space in which the M storage spaces store data according to the chronological order in which the M storage spaces respectively receive the write request, and stores the data in the last storage space in which the data is stored. The data is written into the storage space corresponding to the LBA of the first data to be written of the permanent medium.
  • the cache controller deletes the data to be written (ie, the first data to be written) stored in the first storage space according to the sequence 3, and stores the data to be written stored in the second storage space (ie, the second to be written)
  • the write data is written into the storage space corresponding to the LBA of the first data to be written of the permanent medium.
  • the cache controller stores the first time attribute tag and the second time attribute tag, and stores the first to be written in a different storage space corresponding to the LBA of the first data to be written and the LBA of the second data to be written in the cache. Data and second data to be written.
  • the mechanism for the cache controller to write data is independent of the chronological order of the processor to receive the data to be written, and is related to the chronological order of the data to be written received by the cache controller.
  • first to-be-written data and the second to-be-written data are sorted according to the chronological order in which the processor receives the data to be written to obtain a sequence 1: the first to be written.
  • Data, second to-be-written data; and M storage spaces include a first storage space and a second storage space, and the at least one write request includes a first write request and a second write request.
  • the cache controller may write the first to-be-written data and the first time attribute tag in the first storage space, and write the second to-be-written data and the second time attribute tag in the second storage space; or, Write a second to-be-written data and a second time attribute tag in a storage space, and write the first to-be-written data and the first time attribute tag in the second storage space.
  • the chronological order in which the cache controller receives the data to be written is sequence 2: the second data to be written, the first data to be written, and FIG. 4(c) and FIG. (d) The chronological order in which the cache controller receives the data to be written is still sequence 1.
  • the cache controller sequentially writes the first data to be written and the second data to be written into the storage space corresponding to the LBA of the first data to be written in the permanent medium, and may include: a cache controller.
  • the first to-be-written data and the second to-be-written data are sequentially written into the storage space corresponding to the LBA of the first to-be-written data in the permanent medium according to the first time attribute tag and the second time attribute tag.
  • the cache controller determines the sequence 1 according to the first time attribute tag and the second time attribute tag, and then sequentially writes the first to-be-written data and the second to-be-written data stored in the corresponding storage space according to the sequence 1.
  • the storage space corresponding to the LBA of the first data to be written in the permanent medium may include: a cache controller.
  • the first to-be-written data and the second to-be-written data are sequentially written into the storage space corresponding to the LBA of the first to-be-written data in the permanent medium according to the first time attribute tag and the second
  • the cache controller deletes the first data to be written, and writes the second data to be written into the storage space corresponding to the LBA of the first data to be written in the permanent medium, which may include: Controller root
  • the first to-be-written data is deleted according to the first time attribute tag and the second time attribute tag, and the second to-be-written data is written into the storage space corresponding to the LBA of the first to-be-written data in the permanent medium.
  • the cache controller determines the sequence 1 according to the first time attribute tag and the second time attribute tag, and then deletes the non-last data to be written in the sequence 1 (ie, the first data to be written), and in the sequence 1
  • the last data to be written ie, the second data to be written
  • the controller adds a first time attribute label for the first write request, and adds a second time attribute label for the second write request as an example. It is also possible for the host to add a first time attribute tag for the first write request and a second time attribute tag for the second write request.
  • the foregoing S101-S103 may be replaced by the following steps: the host adds a first time attribute tag for the first write request, adds a second time attribute tag to the second write request, and then sends a first write request to the controller, The second write request, the first time attribute tag, and the second time attribute tag.
  • the host may send the write request and the time attribute tag of the write request to the controller through two messages, or may include the time attribute tag of the write request in the write request and send the message to the controller.
  • the first write request sent by the host to the controller includes the LBA of the first data to be written, the first data to be written and the first time attribute tag
  • the second write request includes the LBA of the second data to be written, and the second The data to be written and the second time attribute tag.
  • FIG. 5 it is a schematic diagram of a method for writing data according to an embodiment of the present invention.
  • the method shown in Figure 5 includes:
  • S501 The host sends a first write request to the processor, where the first write request includes the first to-be-written data and the LBA of the first to-be-written data.
  • S502 The processor receives the first write request, and queries whether the LBA of the first to-be-written data is stored in the cache.
  • S503 The processor adds a first time attribute tag to the first write request.
  • S504 The processor writes the LBA of the first data to be written into the cached LBA set, and sends the first to-be-written data to the cache controller.
  • the time attribute tag is used as an example for the processor to receive the write request including the same LBA. Therefore, if the processor executes S502 and then executes S503 and then executes S504, the processor is the first.
  • the write request adds a first time attribute tag to indicate that the first write request is a write request that the processor receives the LBA including the first data to be written for the first time.
  • the cache controller receives the first data to be written, and writes the first data to be written into the storage space corresponding to the LBA of the first data to be written in the cache according to the first time attribute label.
  • the processor queries that the first to-be-written data has been written into the storage space corresponding to the LBA of the first data to be written in the cache
  • the processor replies with a write response to the host.
  • S507 The processor receives the Abort command and replies to the host that the Abort command succeeds.
  • the host receives the Abort command successfully, and sends a second write request to the processor.
  • the second write request includes an LBA of the second data to be written and the second data to be written.
  • S509 The processor queries whether the LBA of the second data to be written included in the second write request is stored in the cache.
  • S510 The processor adds a second time attribute tag to the second write request, and sends the second to-be-written data to the cache controller.
  • the processor adds a second time attribute tag to the second write request to indicate that the second write request is the second time the processor receives the write request for the LBA including the second data to be written.
  • the cache controller receives the second data to be written, and writes the second data to be written into the storage space corresponding to the LBA of the first data to be written in the cache according to the second time attribute label.
  • S505 and S508-S511 are not limited in the embodiment of the present invention. For example, S505 may be executed first and then S508-S511 may be executed, or S508-S511 may be executed first, then S505 may be executed, or S508-S511 may be executed. S505 is executed at the same time as one step.
  • the cache controller sequentially writes the first to-be-written data and the second to-be-written data into a storage space corresponding to the LBA of the first to-be-written data in the permanent medium.
  • the solution provided by the embodiment of the present invention is mainly introduced from the perspective of interaction between the host and the storage array.
  • the host and the storage array include corresponding hardware structures and/or software modules for performing the respective functions in order to implement the above functions.
  • the present invention can be implemented in a combination of hardware or hardware and computer software in combination with the elements and algorithm steps of the various examples described in the embodiments disclosed herein. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.
  • the embodiment of the present invention may divide the function module into the storage array according to the foregoing method example.
  • each function module may be divided according to each function, or two or more functions may be integrated into one processing module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of the module in the embodiment of the present invention is schematic, and is only a logical function division, and the actual implementation may have another division manner.
  • FIG. 6 shows a possible structural diagram of the memory array involved in the above embodiment.
  • the storage array 6 can include a processing module 602 and a communication module 603.
  • the processing module 602 is configured to control and manage the actions of the storage array 6.
  • the processing module 602 is configured to support the storage array 6 to execute S103 and S104 in FIG. 2; S502, S503, S504, S505, S509, and S510 in FIG. , S511, S512, and/or other processes for the techniques described herein.
  • Communication module 603 is used to support communication between storage array 6 and other network entities, such as communication with the functional modules or network entities shown in FIG. 1 or 5.
  • the storage array 6 may further include a storage module 601 for storing program codes and data of the storage array.
  • the processing module 1302 may include a processor (ie, a CPU) and a cache controller in the system shown in FIG. 1.
  • the processing module 1302 can also be a CPU, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable Logic device, transistor logic device, hardware component, or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure.
  • Processing module 1302 may also be a combination of computing functions, such as one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.
  • the communication module 603 can be a transceiver, Transceiver circuit or communication interface.
  • the storage module 601 can be a cache and a permanent medium in the system shown in FIG. 1, or any other type of memory or a combination of multiple memories.
  • the processing module 602 is a processor and a cache controller in the system shown in FIG. 1
  • the communication module 603 is a transceiver
  • the storage module 601 is a cache and a permanent medium in the system shown in FIG. 1, the embodiment of the present invention
  • the storage array involved can be as shown in FIG.
  • the storage array 7 may include: a processor 701, a cache controller 702, a transceiver 703, a permanent medium 704, a cache 705, and a bus 706; wherein, the processor 701, the cache controller 702, and the transceiver 703
  • the persistent medium 704 and the cache 705 are interconnected by a bus 706; the bus 706 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus.
  • PCI peripheral component interconnect
  • EISA extended industry standard architecture
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 7, but it does not mean that there is only one bus or one type of bus.
  • the steps of the method or algorithm described in connection with the present disclosure may be implemented in a hardware manner, or may be implemented by a processing module executing software instructions.
  • the software instructions may be composed of corresponding software modules, which may be stored in a random access memory (RAM), a flash memory, a read only memory (ROM), an erasable programmable read only memory ( Erasable programmable ROM (EPROM), electrically erasable programmable read only memory (EEPROM), registers, hard disk, removable hard disk, compact disk read only (CD-ROM) or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and the storage medium can be located in an ASIC. Additionally, the ASIC can be located in a core network interface device.
  • the processor and the storage medium may also exist as discrete components in the core network interface device.
  • the functions described herein can be implemented in hardware, software, firmware, or any combination thereof.
  • the functions may be stored in a computer readable medium or transmitted as one or more instructions or code on a computer readable medium.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a general purpose or special purpose computer.

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Abstract

本发明公开了提供一种写数据的方法和装置，涉及数据处理技术领域，用以至少解决永久性介质中存储的数据与主机实际向存储阵列中写入的数据不一致的问题。存储阵列包括控制器和永久性介质；方法包括：控制器接收主机发送的包括第一待写数据和LBA的第一写请求，在接收到第一写请求后，接收主机发送包括第二待写数据和该LBA的第二写请求；为第一写请求添加第一时间属性标签，为第二写请求添加第二时间属性标签，第一时间属性标签用于指示控制器接收第一写请求的时间，第二时间属性标签用于指示控制器接收第二写请求的时间；根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据按照先后顺序写入该LBA所对应的存储空间中。

Description

一种写数据的方法和装置 技术领域
本发明涉及数据处理技术领域，尤其涉及一种写数据的方法和装置。
背景技术
主机与存储阵列之间一般采用小型计算机系统接口(small computer system interface，SCSI)协议进行通信。存储阵列包括控制器和至少一个永久性介质，控制器包括处理器、缓存和缓存控制器。
目前，基于SCSI协议的写数据的方法如下：主机向处理器发送写请求；处理器接收到该写请求之后，向缓存控制器发送该写请求；然后缓存控制器将该写请求中包括的数据写入缓存。处理器查询到该数据存储到缓存之后会向主机回复写响应。后续，缓存控制器会将缓存中存储的该数据写入永久性介质。进一步地，若主机在预设时间段内没有接收到处理器回复的写响应，则向处理器发送Abort命令，以通知处理器：主机放弃该写请求；处理器接收到Abort命令之后，查询该数据是否已被写入缓存；若该数据已被写入缓存，则处理器向主机回复Abort命令成功，主机接收到Abort命令成功之后，向处理器发送重写请求，其中，该重写请求中包括的逻辑区块地址(logical block address,LBA)与该写请求中包括的LBA相同；若该数据没有被写入缓存，则处理器悬挂Abort命令，即：处理器暂不响应Abort命令。
上述方法中，若处理器查询到该数据在预设时间段内没有被写入缓存，则处理器不会向主机回复Abort命令成功，这会导致处理器回复Abort命令成功超时；由于SCSI协议中规定：主机在接收到Abort命令成功之后，才能向处理器发送重写请求，因此，上述方法会导致主机在接收到Abort命令成功之前，不能向处理器发送重写请求，也就是说，不能向该LBA所对应的存储空间内写数据，从而影响主机业务的连续性。
为了解决上述技术问题，一种实现方案如下：处理器在接收到主机发送的写请求后，立即向主机回复Abort命令成功。但是，这样会存在如下问题：由于缓存处理器是按照接收待写数据的时间先后顺序向永久性介质中写数据的，因此，若处理器接收到的重写请求中包括的数据比写请求中包括的数据先被写入缓存，则会导致重写请求中包括的数据比写请求中包括的数据先被写入永久性介质，该情况下，重写请求中包括的数据会被写请求中包括的数据覆盖，从而导致永久性介质中存储的数据与主机实际向存储阵列中写入的数据不一致。
发明内容
本发明的实施例提供一种写数据的方法和装置，用以至少解决存储阵列中的永久性介质中存储的数据与主机实际向存储阵列中写入的数据不一致的问题。
为达到上述目的，本发明的实施例采用如下技术方案：
一方面，提供一种写数据的方法，包括：控制器接收主机发送的第一写请求，其中，第一写请求包括第一待写数据和第一待写数据的逻辑区块地址LBA；在接收第一写请求之后，控制器接收主机发送的第二写请求，其中，第二写请求包括第二待写数 据和第二待写数据的LBA，第二待写数据的LBA和第一待写数据的LBA相同；然后，控制器为第一写请求添加第一时间属性标签，并为第二写请求添加第二时间属性标签，其中，第一时间属性标签用于指示控制器接收第一写请求的时间，第二时间属性标签用于指示控制器接收第二写请求的时间；后续，控制器根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据按照先后顺序写入永久性介质中的第一待写数据的LBA所对应的存储空间中。其中，主机与存储阵列之间的通信协议可以包括但不限于SCSI协议。这样，控制器能够根据第一时间属性标签和第二时间属性标签识别出接收第一待写数据和第二待写数据的时间先后顺序(即：主机实际向存储阵列中写数据的先后顺序)，因此，控制器可以按照该时间先后顺序将第一待写数据和第二待写数据依次写入永久性介质中的第一待写数据的LBA所对应的存储空间中，从而使得永久性介质中存储的数据与主机实际向存储阵列中写入的数据一致。
具体的，控制器为第一写请求添加第一时间属性标签，并为第二写请求添加第二时间属性标签，可以包括：控制器在接收到第一写请求之后，为第一写请求添加第一时间属性标签；在接收到第二写请求之后，为第二写请求添加第二时间属性标签。
需要说明的是，具体实现时，控制器可以为第一写请求和第二写请求中的至少一个写请求添加时间属性标签，即可识别出控制器接收第一写请求和第二写请求的顺序；也就是说，该至少一个写请求的时间属性标签用于表示控制器先接收第一写请求后接收第二写请求。
一种可能的实现方式，控制器根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据按照先后顺序写入永久性介质中的第一待写数据的LBA所对应的存储空间中，可以被替换为：缓存控制器根据第一时间属性标签和第二时间属性标签，删除第一待写数据，并将第二待写数据写入永久性介质中的第一待写数据的LBA所对应的存储空间中。
一种可能的实现方式中，该方法还包括：控制器接收主机发送的Abort命令，其中，Abort命令用于通知存储阵列：主机放弃第一写请求；然后，控制器向主机回复Abort命令成功；接着，控制器在向主机回复Abort命令成功之后，接收第二写请求。具体的，若主机在预设时间段之内没有接收到处理器回复的关于第一写请求的写响应，则向控制器发送Abort命令，控制器在接收到主机发送的Abort命令之后，可以立即向主机回复Abort命令成功(即：控制器在接收到主机发送的Abort命令之后，在不需要确定第一待写数据是否已被写入缓存的情况下，向主机回复Abort命令成功)。该可能的实现方式提供了一种主机与存储阵列之间通过SCSI协议通信的场景中的写数据的方法。
一种可能的实现方式，该方法可以包括：第一时间属性标签包括控制器接收的包括第一待写数据的LBA的写请求的次数；第二时间属性标签包括控制器接收的包括第二待写数据的LBA的写请求的次数。该可选的实现方式提供了一种时间属性标签的具体实现方式，当然不限于此。
一种可能的实现方式，控制器包括处理器和缓存；该情况下，控制器接收主机发送的第一写请求，可以包括：处理器接收主机发送的第一写请求。在处理器接收主机发送的第一写请求之后，该方法还可以包括：处理器确定缓存中的LBA集合中没有包 含与第一待写数据的LBA时，将第一待写数据的LBA写入LBA集合；其中，LBA集合包括满足预设条件的写请求中包括的LBA；满足预设条件的写请求是指处理器接收到的、且所包括的待写数据未写入缓存的写请求。该情况下，控制器为第二写请求添加第二时间属性标签，可以包括：处理器在查询到LBA集合中包含第二待写数据的LBA时，为第二写请求添加第二时间属性标签。该可能的实现方式提供了一种判断第二写请求是否是重写请求的方式，并在确定第二写请求是重写请求的基础上为第二写请求添加第二时间属性标签。
一种可能的实现方式，控制器还可以包括缓存控制器；控制器根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据按照先后顺序写入永久性介质中的第一待写数据的LBA所对应的存储空间中，可以包括：缓存控制器根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据写入缓存中的第一待写数据的LBA所对应的存储空间中；然后，缓存控制器将第一待写数据和第二待写数据依次写入永久性介质中的第一待写数据的LBA所对应的存储空间。具体的，缓存控制器在缓存中的第一待写数据的LBA对应的一个存储空间中存储第一待写数据和第一时间属性标签，并在缓存中的该LBA对应的另一个存储空间中存储第二待写数据和第二时间属性标签。
一种可能的实现方式，在缓存中，第一待写数据的LBA对应M个存储空间，M≥2，M是整数；M个存储空间分别对应处理器接收写请求的先后顺序。该情况下，缓存控制器根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据写入缓存中的第一待写数据的LBA所对应的存储空间中，可以包括：缓存控制器按照第一时间属性标签和第二时间属性标签，在M个存储空间中的不同存储空间中存储第一待写数据和第二待写数据。该可选的实现方式中，缓存控制器写数据的机制与处理器接收待写数据的时间先后顺序有关，与缓存控制器接收到的待写数据的时间先后顺序无关。
一种可能的实现方式，在缓存中，第一待写数据的LBA对应M个存储空间，M≥2，M是整数。该情况下，缓存控制器根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据写入缓存中的第一待写数据的LBA所对应的存储空间中，可以包括：缓存控制器存储第一时间属性标签和第二时间属性标签，并在M个存储空间中的不同存储空间中存储第一待写数据和第二待写数据。该可选的实现方式中，缓存控制器写数据的机制与处理器接收待写数据的时间先后顺序无关，与缓存控制器接收到的待写数据的时间先后顺序有关。
另一方面，提供一种存储阵列，包括控制器和至少一个永久性介质；控制器用于：接收主机发送的第一写请求，第一写请求包括第一待写数据和第一待写数据的逻辑区块地址LBA；在接收第一写请求之后，接收主机发送的第二写请求，第二写请求包括第二待写数据和第二待写数据的LBA，第二待写数据的LBA和第一待写数据的LBA相同；为第一写请求添加第一时间属性标签，并为第二写请求添加第二时间属性标签；第一时间属性标签用于指示控制器接收第一写请求的时间，第二时间属性标签用于指示控制器接收第二写请求的时间；根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据按照先后顺序写入永久性介质中的第一待写数据的LBA 所对应的存储空间中。
一种可能的实现方式，控制器还可以用于：接收主机发送的Abort命令，其中，Abort命令用于通知存储阵列主机放弃第一写请求；向主机回复Abort命令成功。该情况下，控制器具体可以用于：在向主机回复Abort命令成功之后，接收第二写请求。
一种可能的实现方式，第一时间属性标签包括控制器接收的包括第一待写数据的LBA的写请求的次数；第二时间属性标签包括控制器接收的包括第二待写数据的LBA的写请求的次数。
一种可能的实现方式，控制器包括处理器和缓存；处理器用于：接收主机发送的第一写请求。处理器还可以用于：确定缓存中的LBA集合中没有包含与第一待写数据的LBA时，将第一待写数据的LBA写入LBA集合；其中，LBA集合包括满足预设条件的写请求中包括的LBA；其中，满足预设条件的写请求是指处理器接收到的、且所包括的待写数据未写入缓存的写请求。处理器还可以用于：在查询到LBA集合中包含第二待写数据的LBA时，为第二写请求添加第二时间属性标签。
一种可能的实现方式，控制器还包括缓存控制器；缓存控制器用于：根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据写入缓存中的第一待写数据的LBA所对应的存储空间中；将第一待写数据和第二待写数据依次写入永久性介质中的第一待写数据的LBA所对应的存储空间。
一种可能的实现方式，在缓存中，第一待写数据的LBA对应M个存储空间，M≥2，M是整数；M个存储空间分别对应处理器接收写请求的先后顺序。该情况下，缓存控制器具体可以用于：按照第一时间属性标签和第二时间属性标签，在M个存储空间中的不同存储空间中存储第一待写数据和第二待写数据。
一种可能的实现方式，在缓存中，第一待写数据的LBA对应M个存储空间，M≥2，M是整数。该情况下，缓存控制器具体可以用于：存储第一时间属性标签和第二时间属性标签，并在M个存储空间中的不同存储空间中存储第一待写数据和第二待写数据。
又一方面，本发明实施例提供了一种存储阵列，该存储阵列可以实现上述方法实施例中的存储阵列所执行的功能，所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个上述功能相应的模块。
在一种可能的设计中，该存储阵列的结构中包括控制器、与该控制器连接的至少一个永久性介质和收发器，该处理器被配置为支持该存储阵列执行上述方法中相应的功能。该收发器用于支持该存储阵列与其他网元，例如与主机，之间的通信。存储阵列中还可以包括存储器，该存储器用于与处理器耦合，其保存该装置必要的程序指令和数据；其中，该存储器可以是永久性介质，也可以是除该永久性介质之外的任一存储装置。
又一方面，本发明实施例提供了一种通信系统，该系统包括主机，以及上述方面所述的任一种存储阵列。
再一方面，本发明实施例提供了一种计算机存储介质，用于储存为上述存储阵列所用的计算机软件指令，该计算机软件指令可以包含用于执行上述方面所设计的程序。
可以理解地，上述提供的任一种存储阵列或计算机存储介质均用于执行上文所提供的写数据的方法，因此，其所能达到的有益效果可参考上文所提供的相应的写数据的方法中的有益效果，此处不再赘述。
附图说明
图1为本发明实施例提供的技术方案所适用的一种系统架构示意图；
图2为本发明实施例提供的一种写数据的方法的交互示意图；
图3(a)为本发明实施例提供的一种写数据的过程示意图；
图3(b)为本发明实施例提供的另一种写数据的过程示意图；
图4(a)为本发明实施例提供的另一种写数据的过程示意图；
图4(b)为本发明实施例提供的另一种写数据的过程示意图；
图4(c)为本发明实施例提供的另一种写数据的过程示意图；
图4(d)为本发明实施例提供的另一种写数据的过程示意图；
图5为本发明实施例提供的另一种写数据的方法的交互示意图；
图6为本发明实施例提供的一种存储阵列的结构示意图；
图7为本发明实施例提供的另一种存储阵列的结构示意图。
具体实施方式
本发明实施例提供的技术方案应用于如图1所示的系统架构中，图1所示的系统包括主机和存储阵列，其中，主机主要用于控制运算，存储阵列主要用于存储并管理与主机相关的数据。存储阵列可以为具有完整操作系统的硬件实体，也可以为软件，本实施例以存储阵列为具有完整操作系统的硬件实体为例进行说明。存储阵列可以包括控制器与至少一个永久性介质。控制器包括中央处理器(central processing unit，CPU，本文中称为“处理器”)、缓存和缓存控制器。其中，处理器，是存储阵列的控制中心。缓存是介于中央处理器和永久性介质之间的高速存储器，主要用于提升存储的读写性能。缓存控制器用于对缓存中的数据进行管理，示例的，可以用于向缓存中写入数据，并将缓存中存储的数据写入永久性介质中。永久性介质又称非易失性存储介质，其最大特点是断电时，内容仍能保持。
主机与存储阵列之间的通信协议可以是SCSI协议。其中，SCSI协议是一种基于C/S(client/server，客户机/服务器)架构的通信协议；其中，客户机也被称为启动器(initiator)，用于向SCSI目标器(target)发送请求指令。在主机与存储阵列的通信中，一般地，主机充当启动器的角色，存储阵列的控制器充当SCSI目标器的角色。
本发明实施例提供了一种写数据的方法和装置，其基本原理为：存储阵列的控制器接收主机发送的包括第一待写数据和第一待写数据的LBA的第一写请求，并在接收到第一写请求之后，接收包括第二待写数据和第二待写数据的LBA的第二写请求；为第一写请求添加第一时间属性标签，并为第二写请求添加第二时间属性标签，其中，第一待写数据的LBA和第二待写数据的LBA相同，第一时间属性标签用于指示控制器接收第一写请求的时间，第二时间属性标签用于指示控制器接收第二写请求的时间。这样，控制器能够根据第一时间属性标签和第二时间属性标签识别出接收第一待 写数据和第二待写数据的时间先后顺序(即：主机实际向存储阵列中写数据的先后顺序)，因此，控制器可以按照该时间先后顺序将第一待写数据和第二待写数据依次写入永久性介质中的第一待写数据的LBA所对应的存储空间中，从而使得永久性介质中存储的数据与主机实际向存储阵列中写入的数据一致。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。本文中的“第一”和“第二”等是为了更清楚地区分不同的对象，并不做任何其他限定。本文中的“多个”是指两个或两个以上。
下面将结合本发明实施例的说明书附图，对本发明实施例提供的技术方案进行说明。显然，所描述的是本发明的一部分实施例，而不是全部的实施例。
如图2所示，是本发明实施例提供的一种写数据的方法的交互示意图，应用于主机向控制器发送写请求的场景中，该方法包括：
S101:主机向控制器发送第一写请求。其中，第一写请求包括第一待写数据和第一待写数据的LBA。
S102:主机向控制器发送第二写请求。其中，第二写请求包括第二待写数据和第二待写数据的LBA，第一待写数据的LBA与第二待写数据的LBA相同。
假设主机与存储阵列之间协商的针对同一LBA的重写请求的发送次数为N，其中，N≥1，N是整数。那么：若N＝1，则第一写请求是主机向控制器发送的包括第一待写数据的LBA的第一次写请求，第二写请求是主机向控制器发送的包括第二待写数据的LBA的重写请求。若N≥2，则第一写请求可以是主机向控制器发送的包括第一待写数据的LBA的第一次写请求，该情况下，第二写请求可以是主机向控制器发送的包括第二待写数据的LBA的任一次重写请求；或者，第一写请求可以是主机向控制器发送的包括第一待写数据的LBA的第n次重写请求，其中，n可以是小于N的任一值；该情况下，第二写请求可以是主机向控制器发送的包括第二待写数据的LBA的第n+i次重写请求，其中，n+i≤N，i是整数。如果不加说明，下文中均是以N＝1为例进行说明的。
永久性介质可以包括一个或多个存储空间，每个存储空间对应一个物理地址，每个物理地址对应一个LBA。S101中的第一待写数据的LBA(即S102中的第二待写数据的LBA)可以是永久性介质中的任一LBA，即永久性介质中的任一存储空间对应的LBA。
第一待写数据与第二待写数据可能相同，也可能不同。这是因为：主机可以根据需要修改写入永久性介质中的任一LBA所对应的存储空间中的数据。假设将主机向控制器发送第一写请求的时刻标记为第一时刻，将主机向控制器发送第二写请求的时刻标记为第二时刻；那么，若从第一时刻至第二时刻的时间段内，主机未修改写入S101中的第一待写数据的LBA所对应的存储空间中的数据，则第一待写数据与第二待写数据相同；若从第一时刻至第二时刻的时间段内，主机修改了写入S101中的第一待写数据的LBA所对应的存储空间中的数据，则第一待写数据与第二待写数据不同。
S103：控制器接收主机发送的第一写请求和第二写请求，并为第一写请求添加第 一时间属性标签，为第二写请求添加第二时间属性标签。
具体的，控制器在接收到第一写请求之后，为第一写请求添加第一时间属性标签；在接收到第二写请求之后，为第二写请求添加第二时间属性标签。
本实施例中是以控制器接收到主机发送的2个包括同一LBA的写请求为例进行说明的，实际实现时，基于S102中的示例，若N≥2，则控制器可能接收到主机发送的3个或3个以上包括同一LBA的写请求，该情况下，控制器可以在接收到每个包括该LBA的写请求之后，为该写请求添加时间属性标签。
第一时间属性标签可以是任意一种表示控制器接收第一写请求的时间的字符或字符串，例如，可以是控制器接收的包括第一待写数据的LBA的写请求的次数。第二时间属性标签可以是任意一种表示控制器接收第二写请求的时间的字符或字符串，例如，可以是控制器接收的包括第二待写数据的LBA的写请求的次数。
S104：控制器根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据按照先后顺序写入永久性介质中的第一待写数据的LBA所对应的存储空间中。
本发明实施例提供的写数据的方法，控制器先接收主机发送的包括第一待写数据和第一待写数据的LBA的第一写请求，并为第一写请求添加第一时间属性标签，接着，控制器接收包括第二待写数据和第二待写数据的LBA的第二写请求，并为第二写请求添加第二时间属性标签，这样，控制器能够根据第一时间属性标签和第二时间属性标签识别出接收第一待写数据和第二待写数据的时间先后顺序(即：主机实际向存储阵列中写数据的先后顺序)，因此，控制器可以按照该时间先后顺序将第一待写数据和第二待写数据依次写入永久性介质中的第一待写数据的LBA所对应的存储空间中，从而使得永久性介质中存储的数据与主机实际向存储阵列中写入的数据一致。
需要说明的是，本发明实施例均是以控制器为第一写请求添加第一时间属性标签，为第二写请求添加第二时间属性标签为例进行说明的，实际实现时，控制器可以为第一写请求与第二写请求中的至少一个写请求添加时间属性标签，该情况下，上述S103可被替换为如下步骤：控制器接收主机发送的第一写请求和第二写请求，并为第一写请求和第二写请求中的至少一个写请求添加时间属性标签，其中，至少一个写请求的时间属性标签用于表示控制器先接收到第一写请求再接收到第二写请求。
基于S101和S102中的示例，若N＝1，则处理器为第一写请求和第二写请求中的至少一个写请求添加时间属性标签，即可区分出处理器接收第一写请求和第二写请求的时间先后顺序。具体实现时，主机和磁盘阵列可以预先协商好至少一个写请求是第一次写请求(即第一写请求)，重写请求(即第二写请求)，还是第一次写请求和重写请求。
基于S101和S102中的示例，若N≥2，理论上，为了保证永久性介质中存储的数据与主机实际向磁盘阵列中写入的数据一致，只需要对处理器最后一次接收到的携带该LBA的重写请求添加时间属性标签，即可保证缓存控制器识别出处理器最后一次接收到的携带该LBA的重写请求，从而可以保证缓存控制器最后向永久性介质中写入处理器最后一次接收到的携带该LBA的重写请求；实际上，由于处理器不知道主机发送的本次重写请求是否为最后一次重写请求(除非本次重写请求是第N次重写请求)， 因此，一般地，为了实现方便，可以为每个携带该LBA的重写请求均添加时间属性标签；当然，具体实现时，也可以为携带LBA的第一次写请求和每个携带该LBA的重写请求均添加时间属性标签。
可选的，控制器包括处理器和缓存，其中，缓存可以包括一个或多个存储空间，每个存储空间对应一个物理地址，一个或多个物理地址可以对应一个LBA。该情况下，在S101之后，该方法还可以包括：
S101a：主机向处理器发送Abort命令，以通知存储阵列：主机放弃第一写请求。
SCSI协议中规定：处理器接收到主机发送的写请求并查询到缓存控制器已将该写请求中包括的待写数据写入缓存之后，会向主机回复写响应；若主机在预设时间段之内没有接收到处理器回复的写响应，则向处理器发送Abort命令。其中，主机在预设时间段之内没有接收到处理器回复的关于第一写请求的写响应的原因可能是以下任一种：处理器还没有将第一待写数据写入缓存；处理器正在将该数据写入缓存；处理器已将第一待写数据写入缓存，并正在向主机回复关于第一写请求的写响应。
基于此，S101a可以包括：若主机在预设时间段之内没有接收到处理器回复的关于第一写请求的写响应，则向处理器发送Abort命令。
S101b：处理器接收主机发送的该Abort命令，并向主机回复Abort命令成功。
在本发明实施例中，处理器在接收到主机发送的Abort命令之后，可以立即向主机回复Abort命令成功；即：处理器在接收到主机发送的Abort命令之后，在不需要确定第一待写数据是否已被写入缓存的情况下，向主机回复Abort命令成功。
S102a：主机接收到处理器发送的该Abort命令成功之后，向处理器发送重写请求；其中，该重写请求可以是第二写请求。
具体实现时，第二写请求还可以是主机在发送第一写请求之后发送的任一次包括第二待写数据的LBA的重写请求。示例的，主机接收到处理器发送的该Abort命令成功之后，向处理器发送重写请求；若主机在预设时间段之内没有接收到处理器回复的关于重写请求的响应，则会再向处理器发送Abort命令，主机接收到处理器发送的该Abort命令成功之后，向处理器再次发送重写请求，该重写请求是第二写请求。
上述实施例中，均是以第二写请求是包括第二待写数据的LBA的重写请求为例进行说明的，实际实现时，处理器可以按照如下方式确定第二写请求是否为重写请求：处理器在接收到主机发送的第一写请求，且查询到缓存中的LBA集合中没有存储第一写请求包括的第一待写数据的LBA的情况下，将该第一待写数据的LBA写入缓存，其中，LBA集合包括满足预设条件的写请求中包括的LBA，满足预设条件的写请求是指处理器接收到的、且所包括的待写数据未写入缓存的写请求；这样，当处理器接收到第二写请求之后，可以通过查询该缓存中是否存储有第二写请求包括的第二待写数据的LBA，并在确定缓存中存储有第二写请求包括的第二待写数据的LBA的情况下，确定第二写请求为重写请求，其中，第一待写的数据的LBA和第二待写数据的LBA相同。
若时间属性标签包括处理器接收的包括该LBA的写请求的次数，则基于该可选的实现方式，S103可以通过如下两种方式实现：
可选的实现方式1：处理器在接收到第二写请求且查询到缓存中存储有第二写请 求包括的第二待写数据的LBA之后，为第二写请求添加第二时间属性标签。
示例的，假设处理器按时间先后顺序依次连续接收到包括LBA1的写请求1、包括LBA2的写请求2、包括LBA2的写请求3和包括LBA1的写请求4；那么，若处理器为写请求1分配的时间属性标签为“1”，以表示写请求1是处理器接收到的包括LBA1的第一次写请求，则为写请求4分配的时间属性标签为“2”；若处理器为写请求2分配的时间属性标签为“1”，则为写请求3分配的时间属性标签为“2”，如表1所示。
表1
写请求 LBA 时间属性标签
写请求1 LBA1 1
写请求2 LBA2 1
写请求3 LBA2 2
写请求4 LBA1 2
可选的实现方式2：处理器在接收到第二写请求时，不查询缓存中是否存储有第二写请求包括的第二待写数据的LBA(即不需要确定第二写请求是否是重写请求)，直接为第二写请求添加第二时间属性标签。
示例的，假设处理器按时间先后顺序依次连续接收到包括LBA1的写请求1、包括LBA2的写请求2、包括LBA2的写请求3和包括LBA1的写请求4；那么，若处理器为写请求1分配的时间属性标签为“1”，以表示写请求1是处理器接收到的第一次写请求，则为写请求2、3、4分配的时间属性标签分别为“2”、“3”、“4”，如表2所示。
表2
写请求 LBA 时间属性标签
写请求1 LBA1 1
写请求2 LBA2 2
写请求3 LBA2 3
写请求4 LBA1 4
需要说明的是，由于上述可选的实现方式1中时间属性标签的最大值是根据重写机制中的最大重写次数确定的，例如，若重写机制中的最大重写次数为N，则时间属性标签的最大值为N+1；而上述可选的实现方式2中的时间属性标签的最大值是根据主机向处理器发送的写请求的总次数确定的，例如，若主机向处理器发送的写请求的总次数为W，则时间属性标签的最大值为W。一般地，W远大于N，所以，上述可选的实现方式2中的每个时间属性标签所占的存储空间远大于上述可选的实现方式1中的每个时间属性标签所占的存储空间，因此，上述可选的实现方式2适用于主机向处理器发送的写请求的次数较少的场景中。
可选的，控制器还可以包括缓存控制器，该情况下，S104可以包括：
S104a：缓存控制器根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据写入缓存中的第一待写数据的LBA所对应的存储空间中，再将第一待写数据和第二待写数据依次写入永久性介质中的第一待写数据的LBA所对应的 存储空间。
具体的，缓存控制器在缓存中的第一待写数据的LBA对应的一个存储空间中存储第一待写数据和第一时间属性标签，并在缓存中的该LBA对应的另一个存储空间中存储第二待写数据和第二时间属性标签。
可选的，实际实现时，上述S104a可被替换为S104'：
S104'：缓存控制器根据第一时间属性标签和第二时间属性标签，删除第一待写数据，并将第二待写数据写入永久性介质中的第一待写数据的LBA所对应的存储空间中。
需要说明的是，基于处理器为第一写请求和第二写请求中的一个写请求添加时间属性标签。示例的，若处理器为第一写请求添加第一时间属性标签，则缓存控制器在缓存中的第一待写数据的LBA对应的一个存储空间中存储第一待写数据和第一时间属性标签，并在缓存中的该LBA对应的另一个存储空间中存储第二待写数据。若处理器为第二写请求添加第二时间属性标签，则缓存控制器在缓存中的第一待写数据的LBA对应的一个存储空间中存储第一待写数据，并在缓存中的该LBA对应的另一个存储空间中存储第二待写数据和第二时间属性标签。
可选的，在缓存中，S101和S102中的LBA对应M个存储空间，M≥2，M为整数。进一步可选的，可以根据最大重写次数确定M的取值，示例的，若最大重写次数是N，则每个LBA可以对应N+1个存储空间，即：在缓存中，每个LBA对应的存储空间的个数至少能够存储包括同一LBA的第一次写请求和各次重写请求所包括的数据，这样才能保证每次写入缓存的同一LBA对应的存储空间中的数据不丢包。
基于此，S103可以通过以下任一方式实现，其中，以下实现方式均以第一时间属性标签包括控制器接收的包括第一待写数据的LBA的写请求的次数，第二时间属性标签包括控制器接收的包括第二待写数据的LBA的写请求的次数为例进行说明。
方式1：M个存储空间分别对应处理器接收写请求的时间先后顺序；缓存控制器按照第一时间属性标签和第二时间属性标签，在缓存中的第一待写数据的LBA和第二待写数据的LBA对应的不同存储空间中存储第一待写数据和第二待写数据。
该可选的实现方式中，缓存控制器写数据的机制与处理器接收待写数据的时间先后顺序有关，与缓存控制器接收到的待写数据的时间先后顺序无关。
如图3(a)和图3(b)所示，假设按照处理器接收待写数据的时间先后顺序对第一待写数据和第二待写数据进行排序后得到序列1：第一待写数据、第二待写数据；M个存储空间包括第一存储空间和第二存储空间，且按照所对应的处理器接收写请求的时间先后顺序排列后得到序列3：第一存储空间、第二存储空间。那么，缓存控制器向缓存中写数据的过程中，无论缓存接收待写数据的时间先后顺序是否为序列1，缓存控制器均按照序列1向M个存储空间中写数据，即：在第一存储空间中写入第一待写数据，并在第二存储空间中写入第二待写数据。其中，图3(a)中，缓存控制器接收待写数据的时间先后顺序为序列2：第二待写数据、第一待写数据，图3(b)中，缓存控制器接收待写数据的时间先后顺序为仍为序列1。
基于方式1，S104a中，缓存控制器将第一待写数据和第二待写数据依次写入永久性介质中的第一待写数据的LBA所对应的存储空间中，可以包括：缓存控制器根 据M个存储空间分别对应处理器接收写请求的时间先后顺序，将该M个存储空间中存储的待写数据依次写入永久性介质的第一待写数据的LBA所对应的存储空间中。例如，基于上述示例，缓存控制器根据序列3先第一存储空间中存储的待写数据(即第一待写数据)写入永久性介质的第一待写数据的LBA所对应的存储空间中，再将第二存储空间中存储的待写数据(即第二待写数据)写入永久性介质的第一待写数据的LBA所对应的存储空间中。
基于方式1，S104'中，缓存控制器删除第一待写数据，并将第二待写数据写入永久性介质中的第一待写数据的LBA所对应的存储空间中，可以包括：缓存控制器根据M个存储空间分别对应处理器接收写请求的时间先后顺序，删除M个存储空间中存储有数据的非最后一个存储空间中的数据，并将存储有数据的最后一个存储空间中的数据写入永久性介质的第一待写数据的LBA所对应的存储空间中。例如，基于上述示例，缓存控制器根据序列3将第一存储空间中存储的待写数据(即第一待写数据)删除，并将第二存储空间中存储的待写数据(即第二待写数据)写入永久性介质的第一待写数据的LBA所对应的存储空间中。
方式2：缓存控制器存储第一时间属性标签和第二时间属性标签，并在缓存中的第一待写数据的LBA和第二待写数据的LBA对应的不同存储空间中存储第一待写数据和第二待写数据。
该可选的实现方式中，缓存控制器写数据的机制与处理器接收待写数据的时间先后顺序无关，与缓存控制器接收到的待写数据的时间先后顺序有关。
如图4(a)至图4(d)所示，假设按照处理器接收待写数据的时间先后顺序对第一待写数据和第二待写数据进行排序后得到序列1：第一待写数据、第二待写数据；且M个存储空间包括第一存储空间和第二存储空间，至少一个写请求包括第一写请求和第二写请求。那么，在缓存控制器向缓存中写数据的过程中，无论缓存控制器接收待写数据的时间先后顺序为序列1还是序列2(即序列2：第二待写数据、第一待写数据)，缓存控制器均可以在第一存储空间中写入第一待写数据和第一时间属性标签，并在第二存储空间中写入第二待写数据和第二时间属性标签；或者，第一存储空间中写入第二待写数据和第二时间属性标签，并在第二存储空间中写入第一待写数据和第一时间属性标签。其中，图4(a)和图4(b)中，缓存控制器接收待写数据的时间先后顺序为序列2：第二待写数据、第一待写数据，图4(c)和图4(d)，缓存控制器接收待写数据的时间先后顺序为仍为序列1。
基于方式2，S104a中，缓存控制器将第一待写数据和第二待写数据依次写入永久性介质中的第一待写数据的LBA所对应的存储空间中，可以包括：缓存控制器根据第一时间属性标签和第二时间属性标签，将第一待写数据和第二待写数据依次写入永久性介质中的第一待写数据的LBA所对应的存储空间中。基于上述示例，缓存控制器根据第一时间属性标签和第二时间属性标签确定出序列1，然后，按照序列1将对应存储空间中存储的第一待写数据和第二待写数据依次写入永久性介质中的第一待写数据的LBA所对应的存储空间中。
基于方式2，S104'中，缓存控制器删除第一待写数据，并将第二待写数据写入永久性介质中的第一待写数据的LBA所对应的存储空间中，可以包括：缓存控制器根 据第一时间属性标签和第二时间属性标签，删除第一待写数据，并将第二待写数据写入永久性介质中的第一待写数据的LBA所对应的存储空间中。基于上述示例，缓存控制器根据第一时间属性标签和第二时间属性标签确定出序列1，然后，删除序列1中非最后一个待写数据(即第一待写数据)，并将序列1中最后一个待写数据(即第二待写数据)写入永久性介质中的第一待写数据的LBA所对应的存储空间中。
需要说明的是，上文中提供的技术方案中均是以控制器为第一写请求添加第一时间属性标签，为第二写请求添加第二时间属性标签为例进行说明的，实际实现时，还可以由主机为第一写请求添加第一时间属性标签，为第二写请求添加第二时间属性标签。该情况下，上述S101-S103可被替换为如下步骤：主机为第一写请求添加第一时间属性标签，为第二写请求添加第二时间属性标签，然后向控制器发送第一写请求、第二写请求、第一时间属性标签和第二时间属性标签。其中，主机可以通过两条消息向控制器分别发送写请求和该写请求的时间属性标签，也可以将写请求的时间属性标签包括在该写请求中发送给控制器。例如，主机向控制器发送的第一写请求中包括第一待写数据的LBA、第一待写数据和第一时间属性标签，第二写请求中包括第二待写数据的LBA、第二待写数据和第二时间属性标签。
下面通过一个具体的示例对上文提供的写数据的方法进行说明。
如图5所示，为本发明实施例提供的一种写数据的方法交互示意图。图5所示的方法包括：
S501：主机向处理器发送第一写请求，第一写请求包括第一待写数据与第一待写数据的LBA。
S502：处理器接收第一写请求，并查询缓存中是否存储有该第一待写数据的LBA。
若是，则执行S503；若否，则执行S504。
S503：处理器为第一写请求添加第一时间属性标签。
S504：处理器将第一待写数据的LBA写入缓存的LBA集合中，并将第一待写数据发送给缓存控制器。
由于本实施例中是以时间属性标签为处理器接收包括同一LBA的写请求的次数为例进行说明，因此，若处理器在执行S502之后，先执行S503再执行S504，则处理器为第一写请求添加第一时间属性标签以表示第一写请求是处理器第1次接收到包括该第一待写数据的LBA的写请求。
S505：缓存控制器接收第一待写数据，并根据第一时间属性标签将第一待写数据写入缓存中的第一待写数据的LBA所对应的存储空间中。
实际实现时，处理器查询到第一待写数据已写入缓存中的第一待写数据的LBA对应的存储空间中后，会向主机回复写响应。
S506：若主机从发送第一写请求的时刻的预设时间段内，未收到第一写请求对应的写响应，则向处理器发送Abort命令。
S507：处理器接收Abort命令，并向主机回复Abort命令成功。
S508：主机接收Abort命令成功，并向处理器发送第二写请求。第二写请求包括第二待写数据与第二待写数据的LBA。
S509：处理器查询缓存中是否存储有第二写请求包括的该第二待写数据的LBA。
在本实施例中，由于S503中处理器已在缓存中存储了第一待写数据的LBA，而该第二待写数据的LBA与第一待写数据的LBA相同，因此，S509的判断结果为“是”。
S510：处理器为第二写请求添加第二时间属性标签，并将第二待写数据发送给缓存控制器。
基于S504中的示例，在S510中，处理器为第二写请求添加第二时间属性标签以表示第二写请求是处理器第2次接收到包括该第二待写数据的LBA的写请求。
S511：缓存控制器接收第二待写数据，并根据第二时间属性标签将第二待写数据写入缓存中的第一待写数据的LBA所对应的存储空间中。
本发明实施例对S505与S508-S511的先后顺序不进行不限定，例如，可以先执行S505再执行S508-S511，也可以先执行S508-S511再执行S505，还可以在执行S508-S511的任一步骤的同时执行S505。
S512：缓存控制器将第一待写数据和第二待写数据依次写入永久性介质中的第一待写数据的LBA所对应的存储空间中。
上述主要从主机和存储阵列之间交互的角度对本发明实施例提供的方案进行了介绍。可以理解的是，主机和存储阵列为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本发明能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
本发明实施例可以根据上述方法示例对存储阵列进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本发明实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用集成的单元的情况下，图6示出了上述实施例中所涉及的存储阵列的一种可能的结构示意图。存储阵列6可以包括：处理模块602和通信模块603。处理模块602用于对存储阵列6的动作进行控制管理，例如，处理模块602用于支持存储阵列6执行图2中的S103和S104；图5中的S502、S503、S504、S505、S509、S510、S511、S512，和/或用于本文所描述的技术的其它过程。通信模块603用于支持存储阵列6与其他网络实体的通信，例如与图1或图5中示出的功能模块或网络实体之间的通信。存储阵列6还可以包括：存储模块601，用于存储存储阵列的程序代码和数据。
其中，处理模块1302可以包括图1所示的系统中的处理器(即CPU)和缓存控制器。处理模块1302也可以是CPU，数字信号处理器(digital signal processor，DSP)，专用集成电路(application-specific integrated circuit，ASIC)，现场可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本发明公开内容所描述的各种示例性的逻辑方框，模块和电路。处理模块1302也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。通信模块603可以是收发器、 收发电路或通信接口等。存储模块601可以是图1所示的系统中的缓存和永久性介质，或者其他任一种存储器或多种存储器的组合。
当处理模块602为图1所示的系统中的处理器和缓存控制器，通信模块603为收发器，存储模块601是图1所示的系统中的缓存和永久性介质时，本发明实施例所涉及的存储阵列可以如图7所示。
如图7所示，存储阵列7可以包括：处理器701、缓存控制器702、收发器703、永久性介质704、缓存705以及总线706；其中，处理器701、缓存控制器702、收发器703、永久性介质704以及缓存705通过总线706相互连接；总线706可以是外设部件互连标准(peripheral component interconnect，PCI)总线或扩展工业标准结构(extended industry standard architecture，EISA)总线等。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图7中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
结合本发明公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理模块执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(random access memory，RAM)、闪存、只读存储器(read only memory，ROM)、可擦除可编程只读存储器(erasable programmable ROM，EPROM)、电可擦可编程只读存储器(electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于核心网接口设备中。当然，处理器和存储介质也可以作为分立组件存在于核心网接口设备中。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本发明所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本发明的保护范围之内。

Claims (14)

  1. 一种写数据的方法，其特征在于，应用于存储阵列中，所述存储阵列包括控制器和至少一个永久性介质；所述方法包括：
    所述控制器接收主机发送的第一写请求，所述第一写请求包括第一待写数据和所述第一待写数据的逻辑区块地址LBA；
    在接收所述第一写请求之后，所述控制器接收所述主机发送的第二写请求，所述第二写请求包括第二待写数据和所述第二待写数据的LBA，所述第二待写数据的LBA和第一待写数据的LBA相同；
    所述控制器为所述第一写请求添加第一时间属性标签，并为所述第二写请求添加第二时间属性标签；所述第一时间属性标签用于指示所述控制器接收所述第一写请求的时间，所述第二时间属性标签用于指示所述控制器接收所述第二写请求的时间；
    所述控制器根据所述第一时间属性标签和所述第二时间属性标签，将所述第一待写数据和所述第二待写数据按照先后顺序写入所述永久性介质中的所述第一待写数据的LBA所对应的存储空间中。
  2. 根据权利要求1所述的方法，其特征在于，在所述控制器接收到所述第一写请求之后，所述方法还包括：
    所述控制器接收所述主机发送的Abort命令，其中，所述Abort命令用于通知所述存储阵列：所述主机放弃所述第一写请求；
    所述控制器向所述主机回复Abort命令成功；
    所述控制器接收所述第二写请求，包括：
    所述控制器在向所述主机回复Abort命令成功之后，接收所述第二写请求。
  3. 根据权利要求1或2所述的方法，其特征在于，所述第一时间属性标签包括所述控制器接收的包括所述第一待写数据的LBA的写请求的次数；所述第二时间属性标签包括所述控制器接收的包括所述第二待写数据的LBA的写请求的次数。
  4. 根据权利要求3所述的方法，其特征在于，所述控制器包括处理器和缓存；所述控制器接收主机发送的第一写请求，包括：
    所述处理器接收所述主机发送的所述第一写请求；
    在所述处理器接收所述主机发送的所述第一写请求之后，所述方法还包括：
    所述处理器确定所述缓存中的LBA集合中没有包含与所述第一待写数据的LBA时，将所述第一待写数据的LBA写入所述LBA集合；其中，所述LBA集合包括满足预设条件的写请求中包括的LBA；其中，所述满足预设条件的写请求是指所述处理器接收到的、且所包括的待写数据未写入所述缓存的写请求；
    所述控制器为所述第二写请求添加第二时间属性标签，包括：
    所述处理器在查询到所述LBA集合中包含所述第二待写数据的LBA时，为所述第二写请求添加第二时间属性标签。
  5. 根据权利要求4所述的方法，其特征在于，所述控制器还包括缓存控制器；所述控制器根据所述第一时间属性标签和所述第二时间属性标签，将所述第一待写数据和所述第二待写数据按照先后顺序写入所述永久性介质中的所述第一待写数据的LBA所对应的存储空间中，包括：
    所述缓存控制器根据所述第一时间属性标签和所述第二时间属性标签，将所述第一待写数据和所述第二待写数据写入所述缓存中的所述第一待写数据的LBA所对应的存储空间中；
    所述缓存控制器将所述第一待写数据和所述第二待写数据依次写入所述永久性介质中的所述第一待写数据的LBA所对应的存储空间。
  6. 根据权利要求5所述的方法，其特征在于，在所述缓存中，所述第一待写数据的LBA对应M个存储空间，M≥2，M是整数；所述M个存储空间分别对应所述处理器接收写请求的先后顺序；
    所述缓存控制器根据所述第一时间属性标签和所述第二时间属性标签，将所述第一待写数据和所述第二待写数据写入所述缓存中的所述第一待写数据的LBA所对应的存储空间中，包括：
    所述缓存控制器按照所述第一时间属性标签和所述第二时间属性标签，在所述M个存储空间中的不同存储空间中存储所述第一待写数据和所述第二待写数据。
  7. 根据权利要求5所述的方法，其特征在于，在所述缓存中，所述第一待写数据的LBA对应M个存储空间，M≥2，M是整数；
    所述缓存控制器根据所述第一时间属性标签和所述第二时间属性标签，将所述第一待写数据和所述第二待写数据写入所述缓存中的所述第一待写数据的LBA所对应的存储空间中，包括：
    所述缓存控制器存储所述第一时间属性标签和所述第二时间属性标签，并在所述M个存储空间中的不同存储空间中存储所述第一待写数据和所述第二待写数据。
  8. 一种存储阵列，其特征在于，包括控制器和至少一个永久性介质；所述控制器用于：
    接收主机发送的第一写请求，所述第一写请求包括第一待写数据和所述第一待写数据的逻辑区块地址LBA；
    在接收所述第一写请求之后，接收所述主机发送的第二写请求，所述第二写请求包括第二待写数据和所述第二待写数据的LBA，所述第二待写数据的LBA和第一待写数据的LBA相同；
    为所述第一写请求添加第一时间属性标签，并为所述第二写请求添加第二时间属性标签；所述第一时间属性标签用于指示所述控制器接收所述第一写请求的时间，所述第二时间属性标签用于指示所述控制器接收所述第二写请求的时间；
    根据所述第一时间属性标签和所述第二时间属性标签，将所述第一待写数据和所述第二待写数据按照先后顺序写入所述永久性介质中的所述第一待写数据的LBA所对应的存储空间中。
  9. 根据权利要求8所述的存储阵列，其特征在于，
    所述控制器还用于：接收所述主机发送的Abort命令，其中，所述Abort命令用于通知所述存储阵列所述主机放弃所述第一写请求；向所述主机回复Abort命令成功；
    所述控制器具体用于：在向所述主机回复Abort命令成功之后，接收所述第二写请求。
  10. 根据权利要求8或9所述的存储阵列，其特征在于，所述第一时间属性标签 包括所述控制器接收的包括所述第一待写数据的LBA的写请求的次数；所述第二时间属性标签包括所述控制器接收的包括所述第二待写数据的LBA的写请求的次数。
  11. 根据权利要求10所述的存储阵列，其特征在于，所述控制器包括处理器和缓存；
    所述处理器用于：接收所述主机发送的所述第一写请求；
    所述处理器还用于：确定所述缓存中的LBA集合中没有包含与所述第一待写数据的LBA时，将所述第一待写数据的LBA写入所述LBA集合；其中，所述LBA集合包括满足预设条件的写请求中包括的LBA；其中，所述满足预设条件的写请求是指所述处理器接收到的、且所包括的待写数据未写入所述缓存的写请求；
    所述处理器还用于：在查询到所述LBA集合中包含所述第二待写数据的LBA时，为所述第二写请求添加第二时间属性标签。
  12. 根据权利要求11所述的存储阵列，其特征在于，所述控制器还包括缓存控制器；
    所述缓存控制器用于：根据所述第一时间属性标签和所述第二时间属性标签，将所述第一待写数据和所述第二待写数据写入所述缓存中的所述第一待写数据的LBA所对应的存储空间中；将所述第一待写数据和所述第二待写数据依次写入所述永久性介质中的所述第一待写数据的LBA所对应的存储空间。
  13. 根据权利要求12所述的存储阵列，其特征在于，在所述缓存中，所述第一待写数据的LBA对应M个存储空间，M≥2，M是整数；所述M个存储空间分别对应所述处理器接收写请求的先后顺序；
    所述缓存控制器具体用于：按照所述第一时间属性标签和所述第二时间属性标签，在所述M个存储空间中的不同存储空间中存储所述第一待写数据和所述第二待写数据。
  14. 根据权利要求13所述的存储阵列，其特征在于，在所述缓存中，所述第一待写数据的LBA对应M个存储空间，M≥2，M是整数；
    所述缓存控制器具体用于：存储所述第一时间属性标签和所述第二时间属性标签，并在所述M个存储空间中的不同存储空间中存储所述第一待写数据和所述第二待写数据。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109375868A (zh) * 2018-09-14 2019-02-22 网宿科技股份有限公司 一种数据存储方法、调度装置、系统、设备及存储介质

Families Citing this family (3)

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CN106250322B (zh) * 2016-08-12 2019-11-19 华为技术有限公司 一种写数据的方法和装置
CN106802939B (zh) * 2016-12-30 2020-04-03 华为技术有限公司 一种解决数据冲突的方法和系统
CN111581247B (zh) * 2019-10-01 2022-04-01 上海忆芯实业有限公司 数据管理器、时序数据库及信息处理系统

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101458932A (zh) * 2007-12-13 2009-06-17 株式会社东芝 用于以顺序访问的方式将数据写入盘驱动器的方法和设备
CN101477445A (zh) * 2008-01-03 2009-07-08 国际商业机器公司 用于写前读存储控制器指令的装置、系统和方法
CN103186537A (zh) * 2011-12-27 2013-07-03 腾讯科技（北京）有限公司 一种基于索引排序的数据读写方法及装置
CN103488431A (zh) * 2013-09-10 2014-01-01 华为技术有限公司 一种写数据方法及存储设备
CN103678149A (zh) * 2013-12-19 2014-03-26 华为技术有限公司 数据处理的方法及设备
CN104484332A (zh) * 2014-11-11 2015-04-01 珠海天琴信息科技有限公司 一种嵌入式系统中读写数据的方法及装置
CN106250322A (zh) * 2016-08-12 2016-12-21 华为技术有限公司 一种写数据的方法和装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006221487A (ja) * 2005-02-14 2006-08-24 Hitachi Ltd リモートコピーシステム
WO2010071661A1 (en) * 2008-12-18 2010-06-24 Lsi Corporation Method for implementing multi-array consistency groups using a write queuing mechanism
CN101702113B (zh) * 2009-11-23 2011-02-16 成都市华为赛门铁克科技有限公司 写操作处理方法和装置
US9251055B2 (en) * 2012-02-23 2016-02-02 Kabushiki Kaisha Toshiba Memory system and control method of memory system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101458932A (zh) * 2007-12-13 2009-06-17 株式会社东芝 用于以顺序访问的方式将数据写入盘驱动器的方法和设备
CN101477445A (zh) * 2008-01-03 2009-07-08 国际商业机器公司 用于写前读存储控制器指令的装置、系统和方法
CN103186537A (zh) * 2011-12-27 2013-07-03 腾讯科技（北京）有限公司 一种基于索引排序的数据读写方法及装置
CN103488431A (zh) * 2013-09-10 2014-01-01 华为技术有限公司 一种写数据方法及存储设备
CN103678149A (zh) * 2013-12-19 2014-03-26 华为技术有限公司 数据处理的方法及设备
CN104484332A (zh) * 2014-11-11 2015-04-01 珠海天琴信息科技有限公司 一种嵌入式系统中读写数据的方法及装置
CN106250322A (zh) * 2016-08-12 2016-12-21 华为技术有限公司 一种写数据的方法和装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109375868A (zh) * 2018-09-14 2019-02-22 网宿科技股份有限公司 一种数据存储方法、调度装置、系统、设备及存储介质

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