Classifications

• • A—HUMAN NECESSITIES
  • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
  • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
  • A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
  • A61B8/52—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves
  • A61B8/5215—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves involving processing of medical diagnostic data
  • A61B8/5238—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves involving processing of medical diagnostic data for combining image data of patient, e.g. merging several images from different acquisition modes into one image
  • A61B8/5246—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves involving processing of medical diagnostic data for combining image data of patient, e.g. merging several images from different acquisition modes into one image combining images from the same or different imaging techniques, e.g. color Doppler and B-mode
• • A—HUMAN NECESSITIES
  • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
  • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
  • A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
  • A61B8/52—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves
  • A61B8/5207—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves involving processing of raw data to produce diagnostic data, e.g. for generating an image
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
  • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
  • G01S15/88—Sonar systems specially adapted for specific applications
  • G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
  • G01S15/8906—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques
  • G01S15/8909—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques using a static transducer configuration
  • G01S15/8915—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques using a static transducer configuration using a transducer array
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
  • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
  • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
  • G01S7/52017—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging
  • G01S7/52019—Details of transmitters
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
  • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
  • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
  • G01S7/52017—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging
  • G01S7/52085—Details related to the ultrasound signal acquisition, e.g. scan sequences
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
  • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
  • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
  • G01S7/52017—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging
  • G01S7/52085—Details related to the ultrasound signal acquisition, e.g. scan sequences
  • G01S7/52095—Details related to the ultrasound signal acquisition, e.g. scan sequences using multiline receive beamforming

Definitions

• This invention relates to medical diagnostic ultrasound systems and, in particular, to front-end circuitry with both pulsers and linear amplifiers for driving elements of a transducer array.
• the front-end of an ultrasound system is that part of the system which communicates with an
• the ultrasound probe controlling the transmission of ultrasound from the probe transducer and receiving and initially processing the returning echo signals from the transducer.
• the front-end circuitry also controls related processing such as TGC amplification of the echo signals, digitization and at least some portion of the beamforming process. It is desirable that most of this circuitry be fabricated in
• conventional ID (one dimensional) array size is 128 elements, although probes with 192 and 256 elements are in use, and 2D probes for 3D imaging have many thousands of transducer elements.
• microbeamformers are a necessity to enable use of an efficiently sized cable, although the front-end circuitry is still generally used for probe control and final beamformation .
• the front-end circuitry prefferably provides a full range of capabilities, able to operate probes requiring pulse transmission and those using shaped waveform transmission, as well as those with multiline capability. It is further desirable that digitization be done prior to beamformation so that a digital beamformer can be used for all imaging applications. These requirements impose challenges for the number and layout of integrated circuit components, as they result in an increasing pin count for the integrated circuit components.
• multiplexing but multiplexing generally reduces performance and so the need to efficiently operate a
• 128-element array probe is minimally a desired requirement. It is an object of the present
• an integrated circuit front-end for an ultrasound system which provides premium performance for a 128-element array transducer probe with IC packages having a reduced pin count for efficient configuration, packaging and p.c. board layout, and with consideration of the various types of fabrication required for ICs of different voltages and capabilities.
• front-end circuitry for an ultrasound system which comprises a beamformer FPGA integrated circuit, transmit ICs with both pulse transmitters and linear waveform transmitters, transmit control and receiver ICs, and analog-to- digital converter (ADC) ICs. Only the transmit ICs require high voltages, and the transmit/receive switches are integrated in the transmit ICs,
• the transmitters can be trimmed to adjust the pulse slew rates, enabling the transmission of pulses with low harmonic frequency content and thus better harmonic images.
• Waveform data for both the linear and pulser transmitters is stored in the transmit control and receiver ICs, saving pins on the FPGA, which is the conventional source of this data.
• the ADCs couple digital echo data to the FPGA for beamforming over serial bus lines, saving additional FPGA pins over a conventional parallel data arrangement.
• both pulser and linear waveform transmit capabilities in the transmit ICs enables the use of both types of transmitters in the formation of a multi-mode image, such as use of the pulsers for Doppler beams and linear transmitters for B mode beams in the formation of a colorflow image.
• FIGURE 1 illustrates in block diagram form the configuration of the ICs of an ultrasound system front-end constructed in accordance with the
• FIGURE 2 is a schematic illustration of a transmit IC integrating both a pulser and a linear waveform transmitter and a transmit-receive switch on the same IC in accordance with the principles of the present invention.
• FIGURE 3 is a block diagram and schematic illustration of a transmit control and receiver IC constructed in accordance with the principles of the present invention.
• FIGURE 4 is a flowchart illustrating the
• FIGURE 5 is a flowchart illustrating acquisition of echo signals for a colorflow image using both the pulser and linear waveform transmitters of the ultrasound system front-end circuitry of FIGURES 1-3.
• FIGURE 6 illustrates in block diagram form an ultrasound system using the front-end circuitry of FIGURES 1-3.
• FIGURE 1 the ICs of an ultrasound system front-end constructed in accordance with the principles of the present invention are shown in block diagram form.
• a beamformer FPGA A beamformer FPGA
• field programmable gate array 10 communicates with the system backend, receiving commands for a
• the FPGA 10 is configured to perform digital beamforming of received echo signals as is known in the art. Beamforming comprises receiving echo signals received by elements of a transducer array and respectively delaying the echoes to bring them into time and phase coherency, then summing them. In essence, echoes received by different elements of the array transducer from a common point in an image field are combined to produce a coherent beamformed echo signal. Analog beamformers use delay lines to delay echo signals for combining, but a digital beamformer can use a variety of delay
• Pat. 6,315,723 (Robinson et al . ) , for example.
• the echo signals which are beamformed by the FPGA 10 are produced by ADCs 18 and stored in DRAM memory.
• the FPGA then extracts the data from memory as needed and beamforms the data into digital coherent echo signals, which are then communicated to the ultrasound system backend for further processing and image formation.
• the DRAM memory may comprise separate memory ICs which are electrically coupled to the FPGA 10.
• the DRAM memory is integral to the same IC package as the FPGA.
• integrated IC devices can be fabricated as an
• Another packaging approach is to vertically stack the FPGA chip and the memory chip(s) on a p.c. board, which minimizes the packaging size (i.e., the length and width) and the footprint occupied by the chips on the circuit board.
• This approach while achieving the objective of board size reduction, will not achieve one of the objects of the present invention, which is to reduce the number of pins required for the IC package, as external package pins will still be needed for the data bus, clock signal, and control lines (e.g., address lines) between the FPGA and memory ICs.
• a preferred implementation of the present invention is to package both the FPGA device and DRAM chips in the same IC package so that the connections between them can be made internal to the package, reducing and freeing up external pins on the FPGA package for other uses, such as connections to other ICs of the front-end.
• the FPGA In response to the commands for a particular transmit-receive imaging sequence, the FPGA
• each transmit control and receiver IC 16 receives control data for operation of thirty- two elements of the transducer array.
• receive control data For a preferred implementation for a 128-element transducer array, each transmit control and receiver IC 16 receives control data for operation of thirty- two elements of the transducer array. Thus, four transmit control and receiver ICs 16 are required for operation of a 128-element array.
• Each transmit control and receiver IC 16 responds by producing the transmit data for thirty-two elements of the array.
• Each IC 16 also comprises thirty-two receive signal paths including preamplifiers and TCG control for the same thirty-two elements.
• the transmit control and receiver ICs produce both pulse control signals and linear waveform signals for each transducer element.
• the transmit control and receiver ICs output a linear waveform signal for a linear transmitter and transmit control data for a pulser for each transducer element which is coupled to linear and pulser transmitter ICs 14. Also coupled to the linear and pulser
• transmitter ICs are control signals to control transmitter parameters such as transmitter gain and enable signals.
• Signal lines are also connected between the transmit control and receiver ICs 16 and the linear and pulser transmitter ICs 14 to couple received echo signals back to the TGC controlled preamplifiers of the receive signal path in the ICs 16.
• each linear and pulser transmitter IC 14 comprises a pulser and linear transmitter and a transmit/receive (T/R) switch for two transducer elements 12.
• T/R transmit/receive
• the T/R switches are closed to couple received signals back to the receive signal paths of the transmit control and receiver ICs.
• the T/R switches are opened to isolate the receive signal path from transmit high voltages.
• high voltages are needed only for the linear and pulser transmitter ICs 14, and the transmit control and receiver ICs are entirely low voltage ICs as they are completely isolated from the high voltages of transmission and have no high voltage requirement.
• Echo signals received from the linear and pulser transmitter ICs 14 are amplified with TGC gain control by preamplifiers in the receive signal paths of the transmit control and receiver ICs 16 and coupled to ADC ICs 18.
• each ADC IC 18 comprises eight ADCs for the echo signals received from eight elements of the array.
• transmit control and receiver IC 16 is coupled to four ADC ICs 18.
• the digitized echo signals of eight transducer elements are coupled back to the FPGA 10 from each ADC IC 18 by time multiplexing over a serial receive data line (Serial Rx Data) , where the digitized echo signal data is stored in the DRAM memory for use by the FPGA in beamformation .
• Serial Rx Data serial receive data line
• the number of pins required on the FPGA IC is reduced, and by time multiplexing the digitized echo signals of eight ADCs onto the same serial data line for each ADC IC, the number of pins required on the FPGA is further reduced; only sixteen serial data lines are required for the preferred implementation for a 128-element array.
• serial Rx Data serial receive data line
• each serial data line is implemented as a differential pair of conductors operating in accordance with the JESD204B serial data bus format.
• FIGURE 2 illustrates the circuitry of a linear and pulser transmitter IC 14 in schematic detail. Since each IC 14 in the preferred implementation operates two transducer elements 12, the circuitry of FIGURE 2 is replicated twice in an IC for two
• Digital data Dig. In defines the characteristics of high voltage drive pulses produced by a pulser 50 for pulse transmission by a transducer element 12, and is applied with timing appropriate for the steering and focusing of the transmit beam to which signals from a particular element contribute.
• the Dig. In data is interpreted by pulse logic 52 to control the pulser 50 for production of a two-level pulse (e.g., zero and one), a three-level pulse, or a seven-level pulse.
• the Dig. In data comprises one bit (zero or one) for a two-level pulse, two bits for a three-level pulse, and three bits for a seven-level pulse.
• An analog waveform DAC In is coupled to a pin of the IC 14 for
• the low voltage DAC In waveform is amplified by an amplifier 56 with selectable gain and produces a waveform which is further amplified by a high power linear transmitter
• the linear transmitter 54 which drives the transducer element.
• the linear transmitter 54 is powered by high voltages +HVL and - HVL applied to pins of the IC 14 (not shown) .
• transmitter 54 are coupled to the same output pin of the IC 14, to which the transducer element 12 is connected. Transmit control data (Tx Control Data) received prior to a transmission period by transmit control logic 58 determines which transmitter is to be used, the pulser 50 or the linear transmitter 54, by generation of enable signals Pen and Len for each transmitter.
• the pulser enable signal Pen is coupled to the pulse logic 52 and the linear transmitter enable signal Len is coupled to the amplifier 56.
• a gain control signal generated by the transmit control logic is also applied to the amplifier 56 for gain determination .
• a T/R switch 60 is also integrated on IC 14 for each transducer element 12.
• the preferred T/R switch contains one single pole, single throw switch TR 0 in series with the receive signal path from transducer element 12 and another single pole, single throw switch TRi shunting the signal path to ground.
• the switches are operated in complementary fashion by the TR control signal generated by the transmit control logic 58.
• the TR 0 switch is open and the TRi switch is closed to isolate the receive signal path of the transmit control and receiver IC 16 from high voltages.
• the TR 0 switch is closed and the Ri switch is open to couple the received echo signals to the receive signal path by way of output line RcvOut .
• the pulser 50 in a preferred implementation is commonly used for harmonic signal operation, in which harmonic frequency signals developed in the body either by tissue or contrast agents are stimulated by pulse transmission and received by the transducer array for imaging or other diagnosis.
• harmonic signals received by the transducer array it is desirable that the transmitted pulses themselves contain as little high frequency content as possible, which would otherwise result in reception of signals in the harmonic frequency band which originate from the ultrasound system and not the body.
• the transmitted pulses it is desirable for the transmitted pulses to be as
• the drive transistors of the pulser 50 can be controllably trimmed to equalize the rise and fall characteristics of transmitted pulses.
• One way to do this is indicated at 72, which is to controllably change the size of a drive transistor.
• the drive transistors can be
• the sizes of the drive transistors can be controllably adjusted during manufacture or testing of the ultrasound system and test pulses applied and measured until symmetrically balanced pulses with minimal harmonic frequency content are produced.
• the slew rate characteristics could also be adjusted in the field, if desired.
• the electrical load of the transducer element seen by the pulser can also affect the rise and fall characteristics of applied drive pulses.
• a newly developed probe may have a
• EPROM can be read by the FPGA and coupled to the linear and pulser transmitter IC 14 to reset the trimming of the pulser transistors for better
• a complementary pair of power transistors such as MOSFETS 76 and 78 in FIGURE 2 are generally driven by a pair of low power drive transistors coupled to their gate electrodes, which are generally operated as a balanced pair.
• drive transistors have bias currents which can be trimmed using switchable parallel resistors 74 coupled to the transistor voltage supply as shown in FIGURE 2. By adding more resistors in parallel between the supply voltage and an electrode of a drive transistor, the transistor operation is altered so that it will become more conductive, or more conductive earlier in response to a drive signal.
• the rise time of the positive power transistor 76 is increased corresponding, increasing the slew rate of a positive-going transmit pulse.
• the performance of the pulser can be adjusted to exhibit substantially identical rise times for both positive-going and negative-going pulses and pulse edges.
• FIGURE 3 is a block diagram and schematic drawing of the circuitry of one of the transmit control and receiver ICs 16 of FIGURE 1.
• Each IC 16 of FIGURE 1 contains the components illustrated in
• FIGURE 3 for thirty-two transducer elements, and so the circuitry of FIGURE 3 is replicated thirty-two times in each IC for a 128-element array transducer.
• the transmit circuitry shown at the top of the drawing comprises a transmit data memory which is an n-byte digital memory 82 containing data sequences for a plurality of different pulser pulse sequences and linear transmit waveforms.
• Transmit and receive control logic 80 receives control data (TxRx Control Data, FIGURE 1) from the FPGA 10 which defines the transmit pulses and waveforms and the TGC control characteristic for the transmit components and receive signal path of the front-end circuitry.
• an address register 84 addresses the memory locations for the n bytes of the appropriate transmit pulse or waveform stored in the memory 82.
• the sequence of pulse or waveform data is read out of memory 82 and applied to pulser logic 86 and to digital-to-analog converter (DAC) 88.
• the pulser logic 86 responds to this data by outputting a sequence of digital data bytes of the appropriate bit length for the desired pulser waveform, which is applied to the pulser input of a linear and pulser transmitter IC 14 (Dig. In) .
• This data sequence generally of a length of hundreds of bytes, depending on the clock frequency and desired transmit pulse resolution, causes the pulser to transmit the desired pulse shape and duration.
• the transmit and receive control logic 80 When data for a linear waveform is read out of the memory 82, the sequence of data bytes is converted into a linearly varying analog waveform by the DAC 88, which is applied to the linear transmitter (DAC In) .
• the transmit and receive control logic 80 also outputs control data for control of the other parameters of a transmit pulse or waveform (Tx Control Data) including the enable bits for control of pulser or linear
• T/R switch 60 is shown at the bottom of FIGURE 3.
• the echo signals (RcvOut) are applied to a first preamplifier 90 with a gain controlling TGCi resistor which is switched into circuit by a switch 92 at a time determined by the control data received by the transmit and receive control logic 80.
• the output of preamplifier 90 is coupled to a second gain stage 94, which includes a second switchable feedback resistor TGC 2 for a second stage of TGC control.
• the TGC 2 resistor is switched into circuit by a switch 96, also controlled by a signal generated by the transmit and receive control logic 80. This is followed by a third preamplifier 98.
• the amplified echo signals at the output of preamplifier 98 are coupled to an ADC IC 18 for digitization in the form of a complementary pair, RcvOut P produced by a further inverting preamplifier 99, and RcvOut N produced by
• the preamplifier 98 After digitization by an ADC of one of IC chips 18, the digitized echo data is coupled to the FPGA 10 for beamformation by means of a serial data bus (Serial Rx Data) . It is seen that the components and signals of the transmit control and receiver ICs 16 are all low voltage components and signals, enabling these ICs to be fabricated using an efficient low voltage CMOS process.
• step 102 information defining the scanning sequence is sent from the backend of the ultrasound system to the FPGA 10.
• step 102 the FPGA 10 sends transmit and receive control data to the transmit control and receiver ICs 16.
• the ICs 16 in turn send transmit control data to the linear and pulser transmitter ICs 14 in step 106, and also condition the receive signal path for the desired TGC operation in step 108.
• the transmit waveforms are produced in the transmit control and receiver ICs 16 and applied to the enabled pulser or linear transmitter of a linear and pulser transmitter
• the echo signals are coupled through T/R switches 60 to the receive signal paths of the transmit control and receiver ICs 16, where TGC amplification is applied.
• the amplified echo signals are then applied to the ADC ICs, which convert them to digital signal samples in step 112.
• the digital echo signal samples are then sent to the FPGA 10 in step 114 over the serial data lines for beamformation in the FPGA.
• the scanning sequence of FIGURE 4 can be further defined to produce a multi-mode image, such as a colorflow image, using both pulsers and linear transmitters to acquire the different modes of echo signals as shown in FIGURE 5.
• operation begins with the communication of the desired colorflow scanning sequence from the backend of the ultrasound system to FPGA 10 in step 122.
• control data for transmission and reception of Doppler beams for Doppler (motion) echo data and B mode beams for B mode (structural) echo data is sent to the transmit control and receiver ICs 16 (TxRx Control Data) .
• transmit control data for the pulsers and linear amplifiers is sent to the linear and pulser transmitter ICs 14 (Tx Control Data) .
• the receive control data is used to control the TGC
• step 1208 digital data from the n- byte memories 82 is processed by the pulser logic of ICs 16 and coupled to the inputs of the pulsers 50 in the ICs 14 for transmission of a pulsed Doppler beam by the array elements 12.
• the echoes received in response to a Doppler beam are coupled from the transducer elements by way of the T/R switches 60 of ICs 14 to the TGC preamplifiers of the receive signal paths of ICs 16.
• the amplified echo signals (RcvOut P,N) are coupled to the ADC ICs 18 where they are converted to digital signal samples in step 132.
• the digital Doppler echo signal samples are sent (Serial Rx Data) to the FPGA DRAM memory for temporary storage in step 134 in preparation for beamforming by the FPGA into coherent echo signals received along each Doppler scanline.
• DACs 88 For B mode scanlines a sequence of digital waveform bytes is coupled to DACs 88 from the n-byte memories, which produce linearly varying waveforms for B mode transmission.
• the waveforms (DAC In) are applied at appropriate times to the inputs of the amplifiers 56 for the linear transmitters 54 of ICs 14, which drive the elements of the transducer array to transmit a B mode waveform beam in step 130.
• echoes are returned from structural (e.g., tissue) matter of the subject and received by the transducer elements 12.
• the received B mode echo signals are coupled by way of T/R
• the amplified B mode echoes are coupled to the ADC ICs 18 (RcvOut P,N) where they are converted to digital B mode echo signal samples in step 132 and forwarded to the DRAM memory of FPGA 10 (Serial Rx Data) for temporary storage and beamformation .
• Doppler processing requires an ensemble of echo signals acquired over time from each point in the image field, the number of Doppler pulses exceeds the number of B mode pulses, with multiple Doppler beams being transmitted at different times along each scanline direction.
• the timing and degree of Doppler and B mode interleave is determined as is known in the art in consideration of the range of tissue motion or blood flow velocities to be detected (I.e, Nyquist sampling rule, ) with Doppler echoes of an ensemble being acquired over greater time intervals for measurement of lower velocities.
• the number of Doppler transmissions used to acquire a Doppler ensemble is dependent on considerations such as the desired accuracy of the flow and motion information.
• ultrasound images including colorflow images, is shown in block diagram form in FIGURE 6.
• a probe 100 having, in this example, a transducer array 12 of 128 elements is coupled to the IC front end shown in FIGURE 1, in particular the transducer element pins of the linear and pulser transmitter ICs 14.
• the beamformer of the FPGA produces scanlines of coherent echo signals in response to pulse and waveform beams transmitted across the image field.
• a second system beamformer 140 may be used to perform some of or specialized beamforming, such as the completion of beamformation from partial beamformed sums produced by the FPGA beamformer.
• the FPGA beamformer will be sufficient for all beamforming, even for those requiring complex computations such as multiline beamforming. This is particularly the case when functions commonly performed in an FPGA such as the storage of pulse and waveform characteristics and their processing is offloaded to other components, as it is in the exemplary front-end configuration of FIGURE 1.
• the pulse and waveform data is stored in the n-byte memories 82 of the transmit control and receiver ICs, where they not only eliminate this functionality from the FPGA but also bring it closer to the transmitter
• an FPGA can be, as its name states, field programmable, firmware can be used to reconfigure the logic elements in the FPGA into a single 128 channel beamformer for some imaging procedures, or into 2x, 4x, 8x, or even higher order multiline beamformers for the production of multiple receive beams in response to a single transmit event in other imaging procedures.
• firmware can be used to reconfigure the logic elements in the FPGA into a single 128 channel beamformer for some imaging procedures, or into 2x, 4x, 8x, or even higher order multiline beamformers for the production of multiple receive beams in response to a single transmit event in other imaging procedures.
• the use of the FPGA configuration described above has
• the digital coherent echo signals resulting from beamformation are processed by a signal processor
• the processed signals are applied to a B mode processor 144, where the B mode echo signals are amplitude detected and further processed for B mode image formation.
• the processed signals are also applied to a Doppler processor where ensembles of Doppler echo signals are processed to estimate the Doppler shift (frequency) of flow or motion at points in the image field. For a colorflow image the Doppler frequencies are used to look up color values in a color data table so that the Doppler-measured motion can be displayed in corresponding colors.
• the Doppler and B mode scanlines are coupled to an image processor 150, where they are combined by scan conversion into overlays for an image of the desired display format, e.g., sector, linear or 3D.
• the resultant B mode, colorflow, color Doppler, or other multi-mode image is displayed on an image display 40.
• the ultrasound system coordinates the overall control of the ultrasound system, such as commanding the front-end circuitry to acquire B mode and Doppler echo signals for a desired imaging scan sequence definition, and controlling the B mode processor, the Doppler processor, and the image processor of the backend to process and combine these echo signals into a displayed colorflow or other image.
• ultrasound system for example, the modules, or components and controllers therein, also may be implemented as part of one or more computers or microprocessors.
• the computer or processor may include a computing device, an input device, a display unit and an interface, for example, for accessing the Internet.
• the computer or processor may include a microprocessor.
• the microprocessor may be connected to a communication bus, for example, to access a PACS system.
• the computer or processor may also include a memory.
• the memory devices described above may include Random Access Memory (RAM) and Read Only Memory (ROM) .
• the computer or processor further may include a storage device, which may be a hard disk drive or a removable storage drive such as a floppy disk drive, optical disk drive, solid-state thumb drive, and the like.
• the storage device may also be other similar means for loading computer programs or other instructions into the computer or processor .
• the term "computer” or “module” or “processor” may include any processor-based or microprocessor-based system including systems using microcontrollers, reduced instruction set computers (RISC) , ASICs, logic circuits, and any other circuit or processor capable of executing the functions described herein.
• RISC reduced instruction set computers
• ASICs ASICs
• logic circuits logic circuits, and any other circuit or processor capable of executing the functions described herein.
• the above examples are exemplary only, and are thus not intended to limit in any way the definition and/or meaning of these terms.
• the computer or processor executes a set of instructions that are stored in one or more storage elements, in order to process input data.
• the storage elements may also store data or other information as desired or needed.
• the storage element may be in the form of an information source or a physical memory element within a processing machine .
• the set of instructions may be in the form of a software program.
• the software may be in various forms such as system software or application software and which may be embodied as a tangible and non-transitory computer readable medium. Further, the software may be in the form of a collection of separate programs or modules, a program module within a larger program or a portion of a program module.
• the software also may include modular programming in the form of object-oriented programming.
• processing of input data by the processing machine may be in response to operator commands, or in response to results of previous processing, or in response to a request made by another processing machine .

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• 2017
  • 2017-07-26 US US16/321,201 patent/US11364014B2/en active Active
  • 2017-07-26 WO PCT/EP2017/068829 patent/WO2018024556A1/en not_active Ceased
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  • 2017-07-26 JP JP2019505375A patent/JP7059252B6/ja active Active
  • 2017-07-26 EP EP17746055.7A patent/EP3494405B1/en active Active

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