WO2018020051A1

WO2018020051A1 - Signal flow-based computer program with direct feedthrough loops

Info

Publication number: WO2018020051A1
Application number: PCT/EP2017/069322
Authority: WO
Inventors: Peter Priller; Florian PÖLZLBAUER
Original assignee: Avl List Gmbh; Kompetenzzentrum - Das Virtuelle Fahrzeug, Forschungsgesellschaft Mbh
Priority date: 2016-07-29
Filing date: 2017-07-31
Publication date: 2018-02-01
Also published as: JP7127015B2; EP3491517A1; EP3491517B1; US20200380182A1; JP2019526853A; US11720722B2; AT518909A2

Abstract

The aim of the invention is to provide a method for controlling the course of a signal flow-based computer program on a computing unit of a technical system in order to control, regulate, automate, or simulate a technical function of the technical system, in particular in order to develop a vehicle or a vehicle component, wherein the signal flow-based computer program consists of interconnected software components and has at least one DF loop. According to the invention, this is achieved by the following method steps: a) identifying the at least one DF loop and the DF components which form the at least one DF loop, each said DF component instantaneously imaging at least one DF input signal present at at least one component input onto at least one output signal present at at least one component output, whereby the at least one DF input signal and the at least one output signal are part of the at least one DF loop, b) determining the maximum possible change of the values of the DF input signals for each unit of time from at least one property of the respective DF input signal, c) activating a delay element in front of the component input where a DF input signal is present whose value has the smallest maximum possible change, and d) running the computer program in accordance with the connection of the software components ascertained in steps a) to c).

Description

Signal flow based computer program with direct feedthrough loops

The subject invention relates to a method for controlling the sequence of a signal-flow-based computer program on a computing unit of a technical system for controlling, regulating, automating or simulating a technical function of the technical see system, in particular for the development of a vehicle or a vehicle component, said Signal flow-based computer program consists of interconnected software components and has at least one DF loop. Furthermore, the invention relates to a method for controlling, regulating, automating or simulating a technical function of a technical installation by means of such a signal flow-based computer program and a computer program product implementing these methods and a computer-readable medium having such a computer program product.

In the arithmetic unit of a technical system, one or more input variables of the technical system are usually mapped to one or more output variables of the technical system by a signal flow-based computer program. The technical equipment may e.g. constitute a test stand that controls, regulates, automates or simulates a technical function, or part of it. In particular, a simulation of the technical function has several advantages: A simulation can be repeated as often as desired and direct measurements on the technical system, eg. on a test bench, are not necessary. In a signal flow-based computer program, it is known that it is necessary to determine in advance the execution order of software components of the computer program prior to the execution of the computer program. Subsequently, the software components of the computer program are executed in the execution of the computer program according to the determined execution order. This is usually done cyclically and at fixed intervals, possibly even in real time. The individual software components of the computer program usually form at least one input signal at a component input to at least one output signal at a component output. Of course, software components without component input or component output are also possible, but such software components are not relevant to the following problem. The software components are thus connected to one another via their component inputs and / or component outputs, so that overall the signal flow-based computer program, or a part thereof, results as the sum of the software components involved and their connection.

The signal flow-based computer program is thus basically treated in three phases: creation of the individual software components of the computer program and connection to the computer program, determination of a processing order of the software program Components, and subsequently the execution of the computer program according to the determined execution order of the software components. The phases of the creation of the software components and the determination of the execution order of these are usually carried out "offline", ie before the actual execution of the computer program.

However, there may be a problem in determining the execution order of the software components when software components form a loop, that is, a feedback. In a loop, a component output of a considered software component is typically fed back directly or via other software components to a component input of the same software component. Thus, a loop represents a cyclic signal path. Thus, if there are software components in a loop which have multiple component inputs and component outputs, the loop is of course only formed via one component input and one respective component output of the respective software components. Of course, there may also be multiple loops, with which multiple component inputs of a software component together with a component output of this software component can form multiple loops. In this case, the software component maps several input signals to an output signal. It is also possible to form several loops via one component input and several component outputs of this one software component. In this case, the software component maps an input signal to a plurality of output signals. An image of multiple input signals to a plurality of output signals by a software component and the formation of multiple loops is conceivable. However, for each individual loop only the component input and the component output of the software component forming the considered loop are relevant. Of course, mapping of the component input to the component output may also be accomplished by other parameters, e.g. another component input of the same component.

A loop may have software components that have a so-called "non-direct-feedthrough" (NDF) property. This means that changes in the input signal at the considered component input of the NDF component do not immediately and in the same cycle of the execution of the computer program affect the output signal at the associated component output of this software component. An NDF loop thus contains at least one software component which, as part of the loop, maps an N DF input signal present at at least one component input onto at least one output signal present at at least one component output. It is therefore the software component together with the at least one NDF input signal and the associated output signal part of the NDF loop. There are some methods of treatment known from signal flow based computer programs with NDF loops. For example, the well-known Simulink software from The MathWorks for modeling systems handles NDF loops so that input signals present at an NDF input are simply ignored in determining the execution order of the software components. On the other hand, US 8,849,641 B1 makes it possible to automatically determine the execution order of the software components of NDF loops.

In contrast, a direct-feedthrough property of a component input of a software component means that changes in the input signal at the considered component input in the same cycle affect an output signal at the associated component output of that software component, resulting in a Such a software component, which instantaneously maps a DF input signal at a component input to an output signal at a component output, is hereafter referred to as a DF component A DF loop exists when all software components, The DF loop contains only the DF input signals at the component inputs and the output signals at the component outputs of the DF components that span the DF loop. Input signals affect the A directly and in the same cycle output signals at the associated component output of the considered DF component. Of course, the DF components, which have DF input signals and output signals as part of the loop, may also have NDF input signals or DF input signals that are not part of the considered loop, but part of another DF loop, an NDF loop or no loop at all. Important for the property of a DF loop is that there are no NDF components in the signal path of the DF loop for mapping NDF input signals to output signals.

If at least one DF loop consisting of DF components is available in the computer program, special methods must be used to find the DF components of the DF loop. For this purpose, the methods of "depth-first search" (DFS) or "breadth-first search" (BFS) should be mentioned in particular. These methods represent known algorithms from Graphene theory. In the case of the DFS method, all predecessor nodes are visited starting from a start node. Predecessor nodes are nodes of which the respective node is dependent (eg, by the necessary data flow), which are thus located in a first pre-level. Proceeding further from the first predecessor nodes in the first pre-level, one goes to its predecessor node (second pre-level). This is repeated until there is no predecessor node left, or one arrives at a node which has already been visited in the course of the search. In this case, a cyclic dependency is considered given. The traversed search path thus contains those nodes that represent the loop. The DFS method always visits a predecessor node of the vertex, so you first go "deep" until no predecessor exists. In the BFS method, all predecessor nodes of the current pre-level are first visited (one goes "wide"), and then one more step into the depth.

There are also algorithms which solve loop finding somewhat more efficiently than just mentioned methods, with DBJohnson (1975), "Finding all the elementary cocktails of a directed graph" in Siam J. Comput, Vol.4, No1 and H. Lui and J. Wang (2006), "A New Way to Enumerate Cycles in Graph", State Key Lab of Intelligent Technology and Systems Department of Computer Science and Technology, Tsinghua University Beijing 100084, China.

Methods for identifying DF loops are thus known, but the resolution of the DF loops usually requires intervention by the user. In the US

2005/0060129 A1, the execution order of the software components is changed in order to solve the DF loop. These are loops that come about through hierarchical models within the software components and no longer exist after transformation into a flat model - that is, that they are not real DF loops and that in US 2005/0060129 A1 solution is not applicable to DF loops in the conventional sense.

In M.Benedikt and FR Holzinger (2016), "Automated Configuration for Non-Iterative Co-Simulation" describes the automated configuration of a non-iterative co-simulation, where each software component is calculated within its own solver Software component is its own local simulation time The execution order of the software components is dynamically determined and adapted at runtime of the co-simulation, always calculating the software component whose local simulation time is the oldest eg at the simulation time t = 0), the software component which has the least number of component inputs is calculated, but this method is not applicable if all software components run in the same processor and have the same simulation time.

If DF loops of a signal flow based computer program are not handled, the execution order of the software components is not unique due to the cyclic dependency of the DF components in the DF loop and the computer program can not be executed. For the processing of the signal flow-based computer program with a DF loop, therefore, the DF loop must be resolved in order to obtain the Processing order of the software components, including the DF components.

It is therefore the object of the present invention to realize a method for processing a signal flow-based computer program which has at least one direct feedthrough loop.

This object is achieved by a method for controlling the sequence of a signal flow-based computer program on a computing unit of a technical installation for controlling, automating or simulating a technical function of the technical installation, in particular for developing a vehicle or a vehicle component. Components and has at least one DF loop, consisting of the following steps, solved:

a) identifying the at least one DF loop and the DF components that form the at least one DF loop, the DF components each having at least one DF input signal applied to at least one component input undelayed on at least one output signal applied to at least one component output whereby the at least one DF input signal and the at least one output signal are part of the at least one DF loop, b) determining the maximum possible change per unit time of the values of the DF input signals from at least one property of the respective DF input signal,

c) adding a delay element in front of those component input to which a DF input signal is applied whose value has the least possible maximum change,

d) executing the computer program after the connection of the software components determined in step a) to c).

Furthermore, the object is achieved by a method for controlling, regulating, automating or simulating a technical function of a technical installation, in particular for developing a vehicle or a vehicle component, by means of a signal flow-based computer program, wherein the computer program consists of interconnected software components, at least one Comprising DF loop and is executed on a computing unit of the technical system, comprising the following steps: a) identifying the at least one DF loop and the DF components forming the at least one DF loop, the DF components respectively at least one DF input signal applied to at least one component input to at least one output signal applied to at least one component output. instantaneously map the signal with which the at least one DF input signal and the at least one output signal are part of the at least one DF loop, b) determining the maximum possible change per unit time of the values of the DF input signals from at least one property of the respective DF input signal, c) adding a delay element in front of those component input to which a DF input signal is applied whose value has the least possible maximum change, d) executing the computer program after the connection of the software components determined in step a) to c) in order to obtain the technical Control, regulate, automate or simulate the function of the technical system.

Each DF component has at least one component input and at least one component output. At least one DF input signal is applied to each DF component on at least one component input, and at least one output signal is present on at least one component output of this DF component. By connecting these component inputs and component outputs, the output of a DF component is fed to another DF component where it is applied as a DF input signal and again mapped to an output signal. This is done until a DF loop is formed. Several DF components, or one component input and one component output of the DF components, thus span a DF loop. If there are multiple DF loops, DF components or their component input and / or component output can also be part of multiple loops.

The software components contained in the signal flow-based computer program, in particular DF components, are thus already created or modified in steps a) to c) before the processing of the signal flow-based computer program and the execution order of the software components including DF components is determined.

The delay generated by the delay element thus represents in the processing of the signal flow-based computer program for the respective current clock step in step d) a separation of the associated DF loop before the component input of the relevant DF input signal. Thus, the relevant DF loop for the current clock step resolved at this point and was virtually changed to a NDF loop. By inserting delay elements at the position determined, a DF loop is thus converted into an NDF loop. The output signal that is generated by the preceding DF component is provided to the subsequent DF component only after a delay as a DF input signal. The resulting NDF loop can then be handled using best practices. During the execution of the computer program in the current clock step, the generated delay reads in the value of the DF output signal of the preceding DF component of a previous clock step - for example in the case of the delay by one clock step, the value of the previous clock step. Essential for the determination of which component input is provided with a delay element, is the determination of the maximum possible change of the value of the at least one (undelayed) DF input signal of this component input from at least one property of the DF within a time unit, eg a clock step. input signal. The strength with which the value of a DF input signal could change on a DF component is commonly referred to as the maximum signal dynamic of the DF input signal, which is why the term signal dynamics is used for "maximum possible change in value" In the signal flow-based computer program, only one DF loop with a DF component, the DF output of which is fed back to the DF input of the same DF component, is trivially provided with a delay element, whereupon the signal flow-based computer program However, if there are multiple DF components with DF input signals in a DF loop, the signal dynamics of the existing DF input signals will be determined, the component input to which a DF input signal with the lowest signal dynamics will be applied provided with a delay element and thus the one DF loop to egg NDF loop changed. If several DF input signals with the same signal dynamics occur in one loop, a component input having one of these DF input signals is provided with the delay element.

The signal dynamics of the at least one DF input signal can each be evaluated with a penalty value, after which the penalty values are compared.

In principle, to release a DF loop, that DF input signal should be delayed, causing the delay to produce the least error at the output of the signal flow-based computer program. In order to determine these respective errors caused by delaying the individual DF input signals at the output of the signal flow based computer program, theoretically, the component inputs at which the DF input signals of the DF components forming the DF loops during execution of the DF loop can signal flow-based computer program can be interrupted individually. Thereupon, the DF input signals causing the least error at the output could be determined. For example, the deviation of the signal at the output without delay of the DF input signals from the signal at the output with interruption of the considered DF input signal would be referred to as an error. So it would be determined how big the error could be at the output if the DF Input signal at the component input of the considered DF component is delayed by at least one clock step, so as mentioned, the DF loop applies to the considered component input in the current clock step as cut open. The disadvantage, however, is that with this method the signal dynamics of the DF input signals at the component inputs could only be determined during the execution of the computer program. Since this information is needed to determine the execution order of the software components, in particular the DF components in the signal flow-based computer program before the actual execution of the signal flow-based computer program, before the execution of the computer program, an estimate (or approximation) of the signal dynamics of the DF input signals the DF components take place. Subsequently, the component input to which the DF input signal with the lowest estimated signal dynamics is applied is selected, and a delay element 1 / z is inserted before the component input. If penalty values are used, the greater the estimated signal dynamics, the higher the penalty value. High estimated signal dynamics would result in a large error in the event of a delay.

By having a DF element at the location of the component input with the DF input signal having the least signal dynamic, the DF loop has been converted to an NDF loop. If further DF loops are present in the computer program, these can also be treated by the method according to the invention or by other methods (for example manually).

However, it is also possible to repeat the method step c), that is to say the addition of the delay element before the DF input signal whose value has the lowest signal dynamics, in order to convert another DF loop into an NDF loop. The DF loops are thus successively separated at the location of the DF input signals with the lowest signal dynamics. This can be done until there is no DF loop in the computer program, which can be used to solve arbitrarily nested DF loops. This means that any DF loops have been resolved, ie converted to NDF loops, and thus all cyclic data dependencies have been eliminated. The resolution of the DF loops is again dependent on the signal dynamics of the (non-delayed) DF input signals within a clock step. Of course it is also possible to solve the other DF loops in a different way than just described. It should be noted that the DF input signals that previously belonged to a DF loop, but which were resolved, ie converted to the NDF loop, and then are not part of a (further) DF loop, no longer represent DF input signals. Thus, the signal dynamics of these former DF input signals are not relevant for further treatment or resolution of the possibly still present DF loops. If DF input signals with the same signal dynamics occur in several DF loops in each case, In the first step, a component input having one of these DF input signals with the same signal dynamics is provided with the delay element. In a further step, a further component input (another remaining DF loop) having one of these DF input signals (with the same signal dynamics) is provided with a delay element - of course only if the DF input signal is still active after the first step DF input signal is. Of course, it would also be possible to separate two independent DF loops simultaneously by providing in each DF loop the component input with the DF input signals with the lowest signal dynamics within the respective loop with a delay element. The execution order of the computer program results ultimately from the connection of the software components and now only contains signals in NDF loops.

When using penalty values, ie after the DF input signals of the DF component have been provided with penalty values, the DF input signal with the lowest penalty value is determined and the associated component input is provided with a delay element, whereby the relevant DF Loop is split. After determining the next undelayed DF input signal (which is still part of another DF loop) with the next higher penalty value, the associated component input is again provided with a delay element, thus separating the further DF loop, etc. Method step b) becomes advantageously carried out once in the process. It is not necessary to redetermine the signal dynamics of the still undelayed DF input signals, but it is also possible. However, it should be noted that the optimality of the solution could possibly no longer be guaranteed by redetermining the signal dynamics. However, the presence of DF loops and DF components as described in method step a) can be checked at arbitrary times. Especially after handling a DF input signal according to the method according to the invention, it may be helpful (especially in the case of interleaved DF loops) to re-identify the remaining DF loops, DF components and DF input signals of the computer program.

In determining the signal dynamics of the at least one DF input signal, additional information about the considered DF input signal is used. A DF input signal generally represents a physical quantity. From this can be estimated in many cases, the expected signal dynamics of the DF input signal. Advantageously, the signal dynamics of the respective DF input signal are determined on the basis of the physical unit (eg temperature, current intensity, distance, etc.) of the respective DF input signal. The use of a physical unit is particularly advantageous since the physical unit is static, ie even before the execution of the Computer program is known and also used in many computer programs alike. Each physical unit (which is derived, for example, from the SI units) is hereby advantageously provided with estimated errors or signal dynamics, which in turn results in an estimated error if that input signal were to be delayed. These relationships arise from the fact that certain quantities (such as temperature, distance) change slowly, whereas other quantities (such as current intensity, light intensity) can change rapidly. Furthermore, the signal dynamics of the respective DF input signal can be estimated from the data type of the respective DF input signal. This is to be used especially if no physical unit is defined for DF input signals, or if the DF input signal has no unit (eg an enum variable). For example, the data type of the DF input signal may be represented by Boolean, Integer, or Float, where the signal dynamics of Boolean is greater than Integer and Float has the least dynamics. Furthermore, the data type bandwidth (eg 8, 16, 32, 64 bit) could be included in the estimation of the signal dynamics. In a test bench, there may be even more information about the DF

Input signals available, for example, which physical area can accept a signal. Also from this signal range, a maximum rate of change can be estimated and used to calculate the signal dynamics of the at least one DF input signal.

Advantageously, a mix of unit and data type of DF input signals is used to determine the signal dynamics of the at least one DF input signal, since this allows a more accurate approximation.

NDF loops are advantageously taken into account by ignoring NDF input signals at an NDF component input. Thus, only the DF loops of relevance and must be treated according to the invention.

The subject invention will be explained in more detail below with reference to Figures 1 to 3d, which show by way of example, schematically and not by way of limitation advantageous embodiments of the invention. It shows

1 shows an exemplary direct feedthrough loop

2 shows a signal flow-based computer program with a non-direct feedthrough

loop

3a shows a signal flow-based computer program with two nested direct feedthrough loops

FIG. 3b shows the signal flow-based computer program whose direct feedthrough loops are provided with penalty values 3 c shows the signal flow-based computer program with a direct feedthrough loop converted to a non-direct feedthrough loop

3d shows the signal flow-based computer program with both direct feedthrough loops converted to a non-direct feedthrough loop

1 shows by way of example a technical system 3 with a computing unit 2, which executes a concrete exemplary embodiment of a signal flow-based computer program 1. The technical system 3, for example, a test stand for a vehicle or a vehicle component (internal combustion engine, powertrain, etc.) as a DUT with a computing unit 2, for example, as part of an electronic control of the test stand on which the signal-flow-based computer program 1 is executed to to control, regulate, automate or simulate a technical function of the test bench, in particular to carry out a defined test run on the test bench with the test object.

The arithmetic unit 2 has an input E via which the signal flow-based computer program 1 is supplied with a nominal rotational speed n_setpoint. Furthermore, the arithmetic unit has an output A, via which the computer program 1 outputs an actual rotational speed nj ^' st. The signal flow-based computer program 1 has the software components P-controller KP, controlled system KR, speed sensor KS and conversion component KK, which form a DF loop. The signal flow-based computer program 1 thus forms a closed control loop for regulating the controlled system KR in this exemplary embodiment. The target speed n_soll is supplied to the P-controller KP. The P controller outputs a current I as manipulated variable, which provides the controlled system KR as an input signal. The controlled system KR supplies the actual rotational speed n_act, which is present at the output A. In addition, the component output of the controlled system KR is fed back via the rotational speed sensor KS and the conversion component KK to the component input of the P controller KP and thus to the input E. The rotational speed sensor KS thus receives the actual rotational speed n_act at the component input and outputs a voltage U proportional to the actual rotational speed njst which is applied to the component input of the converter component KK. The conversion component KK in turn converts the voltage U to a speed n, which is fed back to the input E and thus the component input of the P-controller KP. Thus, the setpoint speed n_setpoint and the speed n are applied to the P controller KP. Since none of the components KP, KR, KS, KK have a delay element 1 / z (in discrete-time notation after z-transformation), a DF loop is present.

2 represents a technical system 3 with a computer unit 2 on which a more abstract, generalized signal flow-based computer program 1 is executed. Therein are some output signals A1, A2, A3, A4 at the component outputs of the software components K1, K2, K3 , K4 in each case with input signals E2, E2 ', E3, E4 to the component nenteneingängen the software components K1, K2, K3, K4 connected via the signal paths shown as arrows. An output signal A1, A2, A3, A3 ', A4 of a software component K1, K2, K3, K4 can thus, depending on the connection, an input signal E1, E2, E2', E3, E4 another software component K1, K2 Be K3, K4. A software component K1, K2, K3, K4 forms part of the signal flow-based computer program 1 and all software components K1, K2, K3, K4 and their interconnection via the signal paths form the signal flow-based computer program 1. A software component K1, K2 , K3, K4 may be any mathematical, analytical, empirical or physical model in arbitrary coding or any software code and maps the at least one component input to the associated at least one component output of the software component K1, K2, K3, K4. In the course of the signal flow-based computer program 1, an input signal E1, E3, E4, or even two or more input signals E2, E2 'to an output signal A1, A2, is processed in a clock step of the processing of each software component K1, K2, K3, K4. A4, or even on several output signals A3, A3 ', shown. As mentioned, the number of input signals E1, E2, E2 ', E3, E4 and output signals A1, A2, A3, A3', A4 per software component K1, K2, K3, K4 can be arbitrary. The signal flow-based computer program 1 receives the input signal E1 at the first software component K1 via the input E of the arithmetic unit 2 and outputs an output signal A3 'to the output A of the arithmetic unit 2 via a component output of the last software component K3. The component output of the software component K1 is connected to the component input of the software component K2, whereby the software component K2 receives an output signal A1 as an input signal E2 from the software component K1. The component output of the software component K2 is further connected to the input of the software component K3, whereby the software component K3 receives an output signal A2 as an input signal E3. As can be seen, an NDF loop is formed via the software component K4 as a feedback between the components K3 and K2, which is indicated by the delay symbol 1 / z. An output signal A3 of the software component K3 is therefore delayed by one clock step t of the processing of the signal flow-based computer program 1. Thus, the output signal A3 of the software component K3 is not used as the input signal E4 of the software component K4 in the current clock step t but from the previous clock step t-1, whereby the mapping of the input signal E4 to the output signal A4 is delayed by the software component K4 , The mapping is therefore based on the output signal A3 of the software component K3 from the previous clock t-1. This is the property of an NDF loop. The execution order of the input signals E1, E2, E2 ', E3, E4, and output signals A1, A2, A3, A3', A4 of the software components K1, K2, K3, Κ4 according to the pattern output signal at time t A (t) = mapping by software components of the input signal at time t K {E (t)} would be:

A1 (t) = K1 {E1 (t)}

E2 (t) = A1 (t)

A2 (t) = K2 {[E2 (t), E 2 '(t)]}

E3 (t) = A2 (t)

E2 '(t) = A4 (t)

A3 (t) = K3 '{E3 (t)}

E4 (t) = A3 (t-1)

A4 (t) = {K4 E4 (t)}

A = K3 '{E3 (t)}

The valid sequential execution order of the software components K1, K2, K3, K4 would therefore be K1, 1 / z, K4, K2, K3 or alternatively also 1 / z, K4, K1, K2, K3. In this case, it is only important that the delay element 1 / z is processed before the software component K4 and that furthermore the software component K1 and the software component K4 are processed before the software component K2. Trivially, the software component K3 is processed last in this example.

If, on the other hand, the software component K4 were a DF component, then the output signal A3 of the software component K3 would not be delayed by the delay element 1 / z. Thus, in the same clock step t, the input signal E4 corresponding to the output signal A3 of the software component K3 would be applied to the software component K4. However, the output signal A2 of the software component K2, which corresponds to the input signal E3 of the software component K3, is required to determine the output signal A3 of the software components K3, which leads to a cyclic dependency and thus a DF loop is present. Thus, the software components K2, K3 and K4 would be DF components, since the DF input signals A2, A3, A4 are present as part of a DF loop at their component inputs, the DF input signals Ε2 ', E3 and E4 and at their component outputs would. Note that the component input with the input signal E2 is not part of the DF loop, since it does not span a DF loop.

Such a DF loop is separated according to the invention by determining the maximum possible change per unit time of the values of the DF input signals of the DF components (forming the loop) from at least one property of the respective DF input signal. There is a delay element 1 / z before the component input to which the input at least one DF input signal whose value has the lowest maximum possible change per unit time, applied, switched. This converts the DF loop to an NDF loop.

However, when multiple DF loops occur, multiple signal paths generally need to be delayed at the appropriate locations. 3a shows a signal flow-based computer program 1 executed on a computer 2 with the software components K1, K2, K3, K4, K5, K6, wherein two interleaved DF loops are formed. The inputs E ', E "of the computer program 1 are respectively connected to the component inputs of the software components K1, K2, which thus receive the input signals E1, E2 The component outputs of the software components K1, K2 are connected to the component inputs of the software The component output of the software component K3 is in turn connected to the component input of the software component K4, whereby the software component K4 receives the output signal A3 of the software components K4, K3, K3 The component output of the software component K4 is connected to the component input of the software component K5, whereby the latter receives the output signal A4 of the software component K4, the input signal E5, via a non-delayed feedback the component outputs of the software component K5 in turn with further inputs n of the components K3, K4 connected, with which they receive the output signals A5, A5 'of the software component K5 as further input signals Ε3', E4 ". Thus, two DF loops A and B are formed by these undelayed feedbacks. The DF loop A is formed by the DF components K3, K4 and K5 with the DF input signals Ε3 ', E4' and E5. The DF loop B is formed by the DF components K4 and K5 with the DF input signals E5 and E4 ", the DF input signal E3 ', the output signal A3, the DF input signal E4', the output signal A4, the DF Input signal E4 ", the DF input signal E5, the output signal A5 and the output signal A5 'thus span two DF loops, ie they are part of the two DF loops. For example, input signals E3 and E4 do not form a DF loop, and thus are not part of the DF loop, although they are part of DF components K3 and K4. Of course, input signals that are not part of the DF loop in this sense may affect output signals of a DF component, but are not essential to the inventive determination of the signal dynamics or separation of DF loops. In addition, a component output of the software component K5 is connected to the component input of the software component K6, with which the software component K6 receives the output signal A5 "of the software component K5 as the input signal E6 Furthermore, the component output of the software component K6 with the Output A of the arithmetic unit 2 connected. In order to determine which of the signal paths of the DF loops A and B are to be cut (first), the values of the DF input signals E3 ', E4', E5, E4 "of the DF components K3, K4, K5 of the DF Loops A and B, according to the invention, are examined for signal dynamics, ie, the maximum possible change per unit time of the value of the DF input signal, in this case within one clock step t, and valued with a penalty A low penalty value means eg a low signal dynamic. For example, the values for the penalty as shown in Fig. 3b in the signal paths, wherein the DF input signal E4 'at the component input of the DF component K4 obviously compared to the DF input signal E4 "at a component input of the DF component K4, the DF input signal E3 'of the component input of the DF

Component K3, as well as the DF input signal E5 of the component input of the DF component K5 have low signal dynamics, since the DF input signal E4 'has the penalty value of one (versus penalty values of two, three, and five, respectively).

For example, the penalty values may result from the data type of the values of the DF input signal, e.g. with the definition of the Penalty values: Boolean: 9, Byte: 7, Integer: 5, Float: 1. The reason for this is that the value of a float value per unit of time can change significantly less than the value of a Boolean Value, whereby the possible signal dynamics of a float value is smaller. The penalty values may also be determined by the physical unit of the DF input signals, e.g. with the definition of the Penalty values: Temperature: 1, mass flow: 3, revolutions per minute: 5, pressure: 7. A physical interpretation of the DF input signals is used. In a technical system, the temperature will be able to change much more slowly than the pressure, which means that the signal dynamics can be reduced. It is also possible to combine various criteria for determining the penalty values. So, for example, first the mood of the physical unit and then within a physical unit a further subdivision according to the data type.

The signal path with the lowest penalty value of one, ie the DF input signal E4 ', is thus separated, in this case between the DF component K3 and K4. This means that the output signal A3 of DF component K4 is delayed by one clock step t and is available as input signal E4 '. Thus, the DF input signal E4 'becomes an NDF input signal, whereby the former DF loop A is now an NDF loop. However, the DF input signal E5 remains a DF input signal which continues to form the DF loop B.

The DF loop B can now be treated in a further step, preferably also after process step 1 c). Thus, in the remaining DF loop B, the signal path with the lowest penalty value is determined-in FIG. 3c, therefore, the penalty value of two on the signal path from the output signal A5 to the DF input signal E4 " higher penalty value of five on the signal path from the DF output signal A4 to the DF input signal E5. Accordingly, the output signal A5 is delayed by one clock step t and is available to the DF component K4 as an NDF input signal E4 "at this delayed clock step t. Thus, the former DF loop B now likewise represents an NDF loop. that the input signal E4 of the DF component K4 does not have to be separated because it is not linked to the DF loop or is not part of the DF loop, so the signal dynamics of the input signal E4 need not be determined at all.

Note that splitting a DF loop does not mean that the DF components that formed the DF loops will automatically become NDF components with respect to all component inputs and component outputs, as shown in Fig. 3b i.V.m. 3a with reference to the DF component K4 with the DF input signals E4, E4 'and E4. "This would only be the case if these DF components do not form another DF loop, ie no further component inputs with DF input signals, If a DF loop has been split, only the DF input signals that had formed the DF loop will become NDF input signals - other DF input signals being another DF loop remain DF input signals, as this other DF loop will remain (pending any further resolution thereof).

According to FIG. 3d, no DF loops are present after the signal paths have been separated. If there were more DF loops, next the signal paths with the next higher dynamic would be separated by inserting a delay 1 / z. In this way, the cyclic dependencies are resolved and the signal flow-based computer program can be processed according to the order of execution fixed thereby. It is self-evident that the past values of the delayed input signals must be buffered. The method can be used to resolve all DF loops of the signal flow-based computer program 1. For this purpose, the signal dynamics of the at least one DF input signal E3 ', E4', E4 ", E5 is determined and then before the component input, at which the DF input signal E3 ', E4', E4", E5, which has the lowest signal dynamics, is applied a delay element 1 / z connected and thus delayed by at least one clock step t until no DF loop in signal flow-based computer program 1 longer exists.

For the signal flow based computer program 1, it is important that all DF loops be resolved to determine the execution order. For the present invention, however, it is sufficient if at least one of these DF loops is resolved by the method described above. The other DF loops can work with others as well Methods are resolved. Preferably, however, of course, all DF loops are resolved by the method according to the invention.

Likewise, it is not always necessary to delay by one clock step t (1 / z), but another delay can also be selected. In general, therefore, a delay element 1 / z ^{N is} inserted in order to resolve a DF loop.

Claims

claims

1 . Method for controlling the sequence of a signal flow-based computer program (1) on a computer unit (2) of a technical system (3) for controlling, regulating or automating a technical function of the technical system (3), in particular for developing a vehicle or a vehicle component the computer program (1) consists of interconnected software components (K1, K2, K3, K4, K5, K6) and has at least one DF loop, comprising the following steps: a) identifying the at least one DF loop and the DF Components (K3, K4, K5) which form the at least one DF loop, the DF components (K3, K4, K5) each having at least one DF input signal applied to at least one component input on at least one applied to at least one component output Imaging the output signal without delay, whereby the at least one DF input signal and the at least one output signal part of the at least one DF loop s ind,

b) determining the maximum possible change per unit time of the values of the DF input signals (Ε3 ', Ε4', E4 ", E5) from at least one property of the respective DF input signal (Ε3 ', Ε4', E4", E5),

c) adding a delay element (1 / z ^N ) before that component input to which a DF input signal (Ε3 ', Ε4', E4 ", E5) is applied whose value has the least possible maximum change,

d) executing the computer program 1 after the connection of the software components determined in step a) to c).

2. Method for controlling, regulating, automating or simulating a technical function of a technical system (3), in particular for developing a vehicle or a vehicle component, by means of a signal flow-based computer program (1), wherein the computer program (1) consists of interconnected software Components (K1, K2, K3, K4, K5, K6), has at least one DF loop and on a computing unit (2) of the technical system (3) is executed, consisting of the following steps:

a) identifying the at least one DF loop and the DF components (K3, K4, K5) forming the at least one DF loop, wherein the DF components (K3, K4, K5) each comprise at least one at least one component input instantaneously map applied DF input signal to at least one output signal applied to at least one component output, whereby the at least one DF input signal and the at least one output signal are part of the at least one DF loop,

d) execution of the computer program 1 according to the determined in step a) to c) connection of the software components to control the technical function of the technical system (3), regulate, automate or simulate.

3. The method of claim 1 or 2, wherein the step c) is repeated until no DF loop in the computer program (1) is present.

4. The method of claim 2, wherein before each repetition of step c), the step a) is repeated.

5. The method according to any one of claims 1 to 4, wherein the possible change in the value of the at least one DF input signal (Ε3 ', Ε4', E4 ", E5) each evaluated with a penalty value and the penalty values are compared.

6. The method according to any one of claims 1 to 5, wherein the possible change in the value of the DF input signals (Ε3 ', Ε4', E4 ", E5) based on a physical unit of the respective DF input signals (Ε3 ', Ε4', E4 ", E5).

7. The method according to any one of claims 1 to 6, wherein the possible change in the value of the DF input signals (Ε3 ', Ε4', E4 ", E5) based on a data type of the respective DF input signals (Ε3 ', Ε4', E4" , E5).

8. Computer program product containing instructions that, when executed on a control device, in particular an electronic control of a test bench, perform a method according to one of claims 1 to 7.

9. A computer readable medium on which a computer program product according to claim 8 is stored.