DE102021133786A1 - Configuration of a SIL simulation of an ECU running on a computer - Google Patents

Abstract

According to the invention, a method for configuring a SIL simulation of a control unit running on a computer is provided, with software models for the control unit having a plurality of tasks being installed on the computer for the SIL simulation of the control unit, which run in a predetermined cycle with a predetermined period between the individual clock times are processed, and the computer has a plurality of processor cores on which a plurality of virtual machines are running, each processing predetermined tasks, with the following method steps:a) determining sporadic model components and periodic model components of the software models,b ) Creation of a group of parallelizable tasks from the periodic model parts of the software models,c) determination of the individual clock times of the parallelizable tasks up to the smallest common multiple of all periods between the clock times of the parallelizable tasks,d) determination of the calculation duration of the individual tasks at their respective clock times ande) determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores on the basis of the determined smallest common multiple of all periods between the clock times of the tasks that can be parallelized and the calculated calculation duration of the individual tasks at their respective clock times in such a way that the computing time of the SIL simulation is minimal. This provides a way of keeping the computing time of a SIL test as short as possible.

Description

The invention relates to a method for configuring a SIL simulation of a control unit running on a computer, software models for the control unit having a plurality of tasks being installed on the computer for the SIL simulation of the control unit Clock times having clock are processed, and the computer has a plurality of processor cores on which a plurality of virtual machines running, each processing predetermined tasks.

A virtual control unit, a so-called V-ECU, is software that simulates a real control unit or part of a real control unit in a simulation scenario. Generally speaking, VPUs (virtual processing units) are used here when a processor-operated device is simulated on a computer using a software model.

Different V-ECU versions cover a large range of variants - from very simple versions to a complete version that contains all the components of a real control unit: The simplest form of a V-ECU has only one component for each function. In a more complex version, the V-ECU contains several linked software components, for example the complete functionality of a control unit. In the automotive sector, for example, this also includes the AUTOSAR Runtime Environment (RTE) and the operating system for realistic task scheduling. If required, selected software components can be added to simulate bus communication or NVRAM. A V-ECU becomes even more realistic when the real base software code is added, which is also used in the production code. A V-ECU thus contains components of application and basic software and therefore offers functionalities that are comparable to those of real control units. It is used, for example, for validation during a computer-based simulation.

Since real control unit hardware is not used when using a V-ECU, the simulation can be carried out faster than in real time, so that the analysis of the simulated control unit can be carried out very quickly and conveniently.

Software functions, V-ECUs or complete V-ECU networks can be simulated and tested using software-in-the-loop tests (SIL tests) in computer-based simulations. As mentioned above, this can be done in real time or even faster and highly parallel.

Software development processes for classic automotive applications, such as powertrain or brake systems, through to e-drive applications and functions for autonomous driving, can be significantly accelerated using SIL tests through virtual testing and validation. A DUT (device under test) can be conveniently simulated on a computer, it can be connected to physically based models and test scripts can be easily reused later on hardware-in-the-loop (HIL) systems.

For SIL tests, the choice of hardware and model topology has a significant impact on the execution speed of the simulation with the same result. There are many parameters that can be changed, so that a user must have a great deal of knowledge about the simulator, its hardware and the model topology in order to be able to efficiently process a SIL test on a computer.

Proceeding from this, it is the object of the invention to provide a possibility of keeping the computing time of a SIL test as short as possible.

This object is solved by the subject matter of patent claim 1. Preferred developments can be found in the dependent claims.

1. a) Ermitteln sporadischer Modellanteile und periodischer Modellanteile der Software-Modelle,
2. b) Erstellen einer Gruppe parallelisierbarer Tasks aus den periodischen Modellanteilen der Software-Modelle,
3. c) Bestimmen der einzelnen Taktzeitpunkte der parallelisierbaren Tasks bis zum kleinsten gemeinsamen Vielfachen aller Perioden zwischen den Taktzeitpunkten der parallelisierbaren Tasks,
4. d) Ermitteln der Berechnungsdauer der einzelnen Tasks zu ihren jeweiligen Taktzeitpunkten und
5. e) Ermitteln der Verteilung der Tasks auf die einzelnen virtuellen Maschinen und der Verteilung der virtuellen Maschinen auf die einzelnen Prozessorkerne auf der Grundlage des bestimmten kleinsten gemeinsamen Vielfachen aller Perioden zwischen den Taktzeitpunkten der parallelisierbaren Tasks und der ermittelten Berechnungsdauer der einzelnen Tasks zu ihren jeweiligen Taktzeitpunkten derart, dass die Rechenzeit der SIL-Simulation minimal ist.

According to the invention, a method for configuring a SIL simulation of a control unit running on a computer is provided, with software models for the control unit having a plurality of tasks being installed on the computer for the SIL simulation of the control unit clocks having consecutive clock times are processed, and the computer has a plurality of processor cores on which a plurality of virtual machines run, each of which processes predetermined tasks, with the following method steps:

1. a) Determination of sporadic model parts and periodic model parts of the software models,
2. b) Creation of a group of parallelizable tasks from the periodic model parts of the software models,
3. c) determining the individual clock times of the tasks that can be parallelized up to the smallest common multiple of all periods between the clock times of the tasks that can be parallelized,
4. d) determining the calculation duration of the individual tasks at their respective cycle times and
5. e) Determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores on the basis of the determined smallest common multiple of all periods between the clock times of the tasks that can be parallelized and the calculated calculation time of the individual tasks at their respective clock times that the computing time of the SIL simulation is minimal.

The invention achieves a particularly efficient selection and use of the hardware. If the degree of parallelism in the recurring points in time is low, this can indicate a system that is not optimally utilized or the degree of parallelism in the most frequent events can provide an indication of the required computing cores. The longest task to be calculated per cycle time determines the minimum value of the calculation length and indicates how long the calculation length would remain, even with hardware optimization. If it is determined in step e) that the existing configuration does not lead to a minimum computing time, a reconfiguration is proposed according to the invention.

It also applies that a plurality of processor cores can be provided by a plurality of single-core processors or by a multi-core processor or by a plurality of multi-core processors. The period between the individual clock times determines the clock rate.

If it is stated here that software models for the control unit are installed on the computer for the SIL simulation of the control unit, then these software models represent a virtual image of the control unit, with the software models matching input signals and/or input values Deliver output signals or output values, specifically as they would be delivered by the control device if corresponding input signals and/or input values were applied to it.

• f) Umkonfigurieren der Software-Modelle entsprechend der in Schritt e) ermittelten Verteilung der Tasks auf die einzelnen virtuellen Maschinen und der Verteilung der virtuellen Maschinen auf die einzelnen Prozessorkerne.

According to a preferred embodiment of the invention, the method has the additional step:

• f) reconfiguration of the software models according to the distribution of the tasks to the individual virtual machines determined in step e) and the distribution of the virtual machines to the individual processor cores.

In step f), the reconfiguration determined in step e) is thus implemented.

• Auslagern eines Teils der SIL-Simulation auf wenigstens einen weiteren Computer, wenn die Anzahl der Tasks die Anzahl der Prozessorkerne des bisher für die SIL-Simulation verwendeten Computers übersteigt.

Furthermore, it is preferred that step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores includes the following reconfiguration:

• Outsourcing part of the SIL simulation to at least one other computer if the number of tasks exceeds the number of processor cores of the computer previously used for the SIL simulation.

Because the communication effort is known from the software models, it can be calculated exactly where the separation is optimal: Here, each possibility of separation can be offset against the communication effort and the parallelization gains.

• Ändern der Periode einer bestimmten Task auf eine größere Periode, vorzugsweise auf die nächstgrößere Periode.

Furthermore, according to a preferred embodiment of the invention, it is provided that step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores includes the following reconfiguration:

• Changing the period of a given task to a larger period, preferably the next larger period.

This can be indicated when the calculation of a task has no inputs and outputs at the same clock times. The cycle times at which parallel calculations can be made make up too little of the total calculation time, so that the parallel calculation has hardly any influence on the total calculation time. However, better coordinated periods can have a positive effect on the calculation speed.

• Aufteilen eines rechenintensiveren Tasks in wenigstens zwei weniger rechenintensive Tasks.

With regard to a reconfiguration, different approaches are possible. According to a preferred development of the invention, however, it is provided that step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores includes the following reconfiguration:

• Splitting a more computationally intensive task into at least two less computationally intensive tasks.

This can be indicated when the tasks have a different computing load, so that the gains from parallelization have little impact.

• Wechseln auf schnellere Prozessorkerne.

As part of a possible reconfiguration, it is preferably also provided that step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores includes the following reconfiguration:

• Switch to faster processor cores.

Within the scope of the invention, changes are therefore also possible which mean a change in the hardware.

• Zusammenlegen wenigstens eines Teils der Tasks, die miteinander kommunizieren.

Furthermore, a preferred embodiment of the invention provides that step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores includes the following reconfiguration:

• Consolidate at least part of the tasks that communicate with each other.

If bus simulation and port communication are also taken into account, suggestions can also be made in the opposite direction.

• Zuweisen wenigstens eines weiteren Prozessorkerns zu einer virtuellen Maschine.

Furthermore, according to a preferred development of the invention, it is provided that step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores includes the following reconfiguration:

• Allocating at least one additional processor core to a virtual machine.

The invention also relates to a non-volatile, computer-readable storage medium with a computer program stored thereon which, when executed on a processor, brings about a method according to one of the preceding claims.

• a) Ermitteln sporadischer Modellanteile und periodischer Modellanteile der Software-Modelle,
• b) Erstellen einer Gruppe parallelisierbarer Tasks aus den periodischen Modellanteilen der Software-Modelle,
• c) Bestimmen der einzelnen Taktzeitpunkte der parallelisierbaren Tasks bis zum kleinsten gemeinsamen Vielfachen aller Perioden zwischen den Taktzeitpunkten der parallelisierbaren Tasks und
• g) Visualisieren der Tasks, die zu einem jeweiligen Taktzeitpunkt auszuführen sind.

In addition, within the scope of the invention, a method for configuring a SIL simulation of a control unit running on a computer is provided, with software models for the control unit having a plurality of tasks being installed on the computer for the SIL simulation of the control unit are processed at a predetermined clock rate with a predetermined period between the individual clock times, and the computer has a plurality of processor cores on which a plurality of virtual machines are running, each of which is processing predetermined tasks, with the following method steps:

• a) Determination of sporadic model parts and periodic model parts of the software models,
• b) Creation of a group of parallelizable tasks from the periodic model parts of the software models,
• c) Determination of the individual clock times of the tasks that can be parallelized up to the smallest common multiple of all periods between the clock times of the tasks that can be parallelized and
• g) Visualizing the tasks that are to be executed at a given cycle time.

Within the scope of the invention, however, it is not mandatory that the method already initiates a reconfiguration. Even the visualization of the tasks that are to be executed at a particular cycle time can be helpful for a user during configuration.

• d) Ermitteln der Berechnungsdauer der einzelnen Tasks zu ihren jeweiligen Taktzeitpunkten, wobei
• in Schritt g) des Visualisierens der Tasks, die zu einem jeweiligen Taktzeitpunkt auszuführen sind, zusätzlich die jeweilige Berechnungsdauer der einzelnen Tasks visualisiert wird.

The method described above preferably has the following additional method step:

• d) determining the calculation duration of the individual tasks at their respective clock times, where
• in step g) of the visualization of the tasks that are to be executed at a particular cycle time, the respective calculation duration of the individual tasks is also visualized.

The invention is explained in more detail below using a preferred exemplary embodiment with reference to the drawings.

• 1 ein Ablaufdiagramm eines Verfahrens gemäß einem ersten bevorzugten Ausführungsbeispiel der Erfindung,
• 2 ein Ablaufdiagramm eines Verfahrens gemäß einem zweiten bevorzugten Ausführungsbeispiel der Erfindung,
• 3 ein Ablaufdiagramm eines Verfahrens gemäß einem dritten bevorzugten Ausführungsbeispiel der Erfindung,
• 4 eine Visualisierung im Rahmen des zweiten bevorzugten Ausführungsbeispiels der Erfindung und
• 5 eine Visualisierung im Rahmen des dritten bevorzugten Ausführungsbeispiels der Erfindung.

Show in the drawings

• 1 a flowchart of a method according to a first preferred embodiment of the invention,
• 2 a flowchart of a method according to a second preferred embodiment of the invention,
• 3 a flowchart of a method according to a third preferred embodiment of the invention,
• 4 a visualization within the scope of the second preferred exemplary embodiment of the invention and
• 5 a visualization within the framework of the third preferred exemplary embodiment of the invention.

Out of 1 a flow chart for a method according to a first preferred embodiment of the invention can be seen. This is a method for configuring a SIL simulation of a control unit running on a computer, with software models for the control unit having a plurality of tasks being installed on the computer for the SIL simulation of the control unit, which run in a predetermined cycle are processed with a predetermined period between the individual clock times, and the Computer has a plurality of processor cores on which a plurality of virtual machines running, each processing predetermined tasks.

In a first method step a), sporadic model parts and periodic model parts of the software models are determined. This is followed by step b) of creating a group of parallelizable tasks from the periodic model parts of the software models. Now, in step c), the individual clock times of the tasks that can be parallelized are determined up to the smallest common multiple of all periods between the clock times of the tasks that can be parallelized. In step d), the calculation duration of the individual tasks is determined at their respective cycle times.

In step e), the tasks can then be distributed to the individual virtual machines and the distribution of the virtual machines to the individual processor cores on the basis of the determined smallest common multiple of all periods between the clock times of the tasks that can be parallelized and the calculated calculation time of the individual tasks determine at their respective clock times in such a way that the computing time of the SIL simulation is minimal. A reconfiguration is also taken into account, according to which part of the SIL simulation is outsourced to at least one additional computer if the number of tasks exceeds the number of processor cores of the computer previously used for the SIL simulation. Furthermore, in step e) such a reconfiguration is also taken into account, which includes changing the period between the individual clock times to the longest period between identical parallelizable tasks. Possible further reconfigurations include splitting a more computationally intensive task into at least two less computationally intensive tasks, switching to faster processor cores, merging at least a portion of those tasks that communicate with one another, and allocating at least one additional processor core to a virtual machine.

Finally, in step f) the actual reconfiguration of the software models takes place according to the distribution of the tasks to the individual virtual machines determined in step e) and the distribution of the virtual machines to the individual processor cores.

Within the scope of the invention, however, it is not mandatory that the method already initiates a reconfiguration. How out 2 As can be seen, an alternative method according to a second preferred embodiment is designed as follows.

This is also a method for configuring a SIL simulation of a control unit running on a computer, with software models for the control unit having a plurality of tasks being installed on the computer for the SIL simulation of the control unit Clock are processed with a predetermined period between the individual clock times, and the computer has a plurality of processor cores on which a plurality of virtual machines running. The steps a) to c) are basically the same as in the first preferred embodiment of the invention.

In a first method step a), sporadic model parts and periodic model parts of the software models are determined. This is followed by step b) of creating a group of parallelizable tasks from the periodic model parts of the software models. Now, in step c), the individual clock times of the tasks that can be parallelized are determined up to the smallest common multiple of all periods between the clock times of the tasks that can be parallelized. However, this is followed by a step g) in which the tasks that are to be executed at a particular cycle time are initially only visualized. Even such a visualization can be useful for a user in the configuration under discussion here.

The method according to the second preferred embodiment of the invention described above can also be designed as in 3 shown. This third preferred exemplary embodiment of the invention provides, after step c), a step d) in which the calculation times of the individual tasks are determined at their respective clock times. To this extent, step g) is modified compared to the second preferred exemplary embodiment of the invention in that the visualization of the tasks that are to be executed at a particular clock time also includes the respective calculation duration of the individual tasks.

Possible configurations of the preferred exemplary embodiments of the invention described above are discussed in detail below.

The methods described above consist of several parts, namely, for example, an analysis of the system, an automatic profiling of the system, which means that the program code is run through a simulation so that the utilization of the system is recognizable, a visualization of the system and the profile and the issue of improvement suggestions for a higher throughput. In doing so, a wesent Another aspect can be the determination of the best possible virtual machine in terms of runtime costs.

During the simulation, the individual models run parallel to a certain extent. The concrete load distribution takes place via the operating system via concurrent processes. By synchronizing the models, the simulation ensures that the result always remains the same. The degree of parallelization is limited by the number of available processor cores and the number of sub-models. According to the exemplary embodiments described here, it is envisaged, for example, to analyze the model, to measure partial runtimes of the model in the simulation, to visualize them and then to propose instructions on how to increase the computing speed.

In the case of HIL simulators, the load distribution is created manually; in the case of PC-based simulators, the load distribution is carried out implicitly by the operating system. There are very different parameters that influence the speed of the overall simulation. For a given simulation system, the simulation speed of a simulation is close to the optimum with regard to the execution speed, among other things due to the automatic load distribution. Therefore, speeding up the system should aim to change the simulated system or hardware. The complex acting parameters that influence the parallelizability are known in principle to the simulator and should be analyzed using the methods described here and presented to the user in a comprehensible manner.

In a discrete, event-based simulation, simulation is only carried out at times when there is something to be calculated. Simulation parts without causal dependency can be calculated simultaneously without falsifying the result. This is generally at the same virtual point in time.

mit ± ηs als maximale Beschleunigung durch Paralellisierung, t_S als sequentieller Programmanteil, t_p als paralleler Programmanteil und np als Anzahl der Recheneinheiten gibt es zum Beispiel keine Parameter zur Abbildung der Einzelprogrammlaufzeiten und Gruppen von parallelisierbaren Teilprogrammen.When parallelizing such processes, the literature usually assumes, for the sake of simplicity, that the parts that can be parallelized are the same and the number of computing units is significantly lower than the tasks to be computed in parallel. In the formula of Ahmdahl's law ( Gene Amdahl: Validity of the Single Processor Approach to Achieving Large-Scale Computing Capabilities. In: AFIPS Conference Proceedings. 30, 1967, pp. 483-485 ) $$n_S=\frac{T}{t_S+\frac{t_P}{n_P}}$$

with ± ηs as the maximum acceleration through parallelization, t _S as the sequential program part, t _p as the parallel program part and np as the number of processing units, there are, for example, no parameters for mapping the individual program runtimes and groups of parallelizable part programs.

In the present case, a classification between sequential model parts and parts that can be parallelized on a task basis is to be determined by means of a static analysis. Periodic tasks from different VPUs should be considered parallelizable, sporadic ones not. All possible times up to the smallest common multiple of all periods are to be determined from all periodic tasks. Periodic tasks are shown separately. The tasks that have to be calculated in each case are determined for these points in time. The visualization of this data is already helpful for a user and schematically in 4 shown.

Out of 4 the tasks A, B and C can be seen, which are executed at the respective clock times. The clock times are spaced 1 ms apart. Task A takes 1 ms, task B 2 ms and task C 3 ms. In this concrete example, the tasks are distributed relatively well. However, outliers such as an additional task that is calculated every 10 microseconds would be noticed immediately and could prompt a proposal to calculate the frequently calculated task periodically.

This visualization can be provided before the actual simulation. During the simulation, the calculation time of the tasks per point in time is determined and accumulated by observing and measuring it. The measurement result is not falsified due to the virtual simulation time. The data is visualized as in 5 shown. The representation in 5 essentially corresponds to the representation in 4 , where the computing load or real computing time for a respective task is indicated by the height of the box describing the respective task.

• - Mit einer virtuellen Maschine mit mehr Prozessorkernen kann die Simulation prozentual um ein bestimmtes maximales Maß beschleunigt werden kann.
• - Die Simulation kann nicht durch mehr Prozessorkerne beschleunigt werden kann.
• - Die Modelle weisen eine sehr unterschiedliche Rechenlast auf, so dass die Gewinne durch Parallelisierung kaum einen Einfluss haben.
• - Es hat Vorteile, das größte Modell in zwei kleinere zu teilen.
• - Die Zeitpunkte, an denen parallel gerechnet werden kann haben einen zu geringen Anteil an der Gesamtrechenzeit, so dass die Parallelberechnung kaum einen Einfluss auf die Gesamtrechenzeit hat. Besser abgestimmte Perioden können die Rechengeschwindigkeit positiv beeinflussen.
• - Die Simulation kann noch durch schnellere Prozessorkerne beschleunigt werden.
• - Sofern auch Bussimulation und Portkommunikation mit visualisiert werden, könnten auch Vorschläge in umgekehrter Richtung abfallen: Tasks, die intensiv miteinander kommunizieren und dabei für sich genommen sehr wenig Rechenzeit verbrauchen, könnten auch zusammengelegt werden.

In a representation as in 5 shown, the sporadic tasks would also appear and be specially marked to determine the difference of the static system analysis to the real runtime analysis. If a sporadic task is executed periodically, the user would be informed that it makes sense to convert it into a real periodic task. A proposal is determined, for example as follows:

• - With a virtual machine with more processor cores, the simulation can be accelerated by a certain maximum percentage.
• - The simulation cannot be accelerated with more processor cores.
• - The models have a very different computing load, so that the gains from parallelization have hardly any influence.
• - There are advantages to splitting the largest model into two smaller ones.
• - The points in time at which parallel calculations can be made have too small a share of the total calculation time, so that the parallel calculation has hardly any influence on the total calculation time. Better tuned periods can positively affect computation speed.
• - The simulation can be accelerated with faster processor cores.
• - If bus simulation and port communication are also visualized, suggestions could also be made in the opposite direction: Tasks that communicate intensively with one another and, taken individually, consume very little computing time, could also be combined.

• Auf einem Prozessor mit 6 Prozessorkernen sollen virtuelle Maschinen laufen, die unterschiedliche Simulationläufe so schnell wie möglich durchlaufen. Optimal für eine sequenzielle Abarbeitung wäre eine virtuelle Maschine mit 4 Prozessorkernen. Wenn man jedoch 3 virtuelle Maschinen mit jeweils 2 Prozessorkernen nutzt, wird die jeweilige Simulation selbst zwar etwas langsamer, aber nur so wenig, dass die Tatsache, dass 3 virtuelle Maschinen gleichzeitig laufen können, die Sache mehr als ausgleicht. Wenn 6 virtuelle Maschinen mit nur einem Prozessorkerne genutzt werden würden, würde sehr viel Overhead durch das Scheduling im Betriebssystem entstehen, so dass die Gesamtberechnung langsamer wäre als die mit 3 virtuelle Maschinen. Für die Speichernutzung gelten entsprechende Überlegungen.

A slightly different approach is used to optimize costs with regard to the virtual machines. There is a problem to be solved here, which is made clear by the following example:

• Virtual machines are to run on a processor with 6 processor cores, which run through different simulation runs as quickly as possible. A virtual machine with 4 processor cores would be ideal for sequential processing. However, if you use 3 virtual machines, each with 2 processor cores, the respective simulation itself will slow down a bit, but only so little that the fact that 3 virtual machines can run at the same time more than makes up for it. If 6 virtual machines with only one processor core were used, there would be a lot of overhead due to the scheduling in the operating system, so that the overall calculation would be slower than with 3 virtual machines. Similar considerations apply to memory usage.

• Auf jeder virtuellen Maschine einer bestimmten Auswahl wird das Modell einen kurzen Moment ausgeführt. Während der Simulation wird die Berechnungsdauer der Tasks pro Zeitpunkt ermittelt und akkumuliert. Dies erfolgt so lange, bis die Daten ausreichen, um die Ausführungszeiten hochzurechnen. Wenn für jede virtuelle Maschine die Kosten bekannt sind, kann damit die ökonomisch günstigste virtuelle Maschine bestimmt werden. Ganz besonders bei Cloud-Anwendungen ist es bevorzugt, als Zielfunktion die Kosten für unterschiedliche virtuelle Maschinen zu integrieren.

To carry out such a cost optimization, proceed as follows:

• On each virtual machine of a given selection, the model runs for a brief moment. During the simulation, the calculation time of the tasks per point in time is determined and accumulated. This is done until there is enough data to extrapolate execution times. If the costs are known for each virtual machine, the most economical virtual machine can be determined. In the case of cloud applications in particular, it is preferred to integrate the costs for different virtual machines as a target function.

• „Das Modell enthält folgende Tasks, die gleichzeitig berechnet werden können: VPU 1: Task 1 rechnet 0,43 ms und VPU 2: Task 3 rechnet 4,9 ms. Dem Simulator stehen 4 Prozessorkerne zur Verfügung. Durch eine Aufteilung in zwei Teile könnte die Gesamtsimulation um maximal 50 % schneller werden, abhängig vom Kommunikationsbedarf der VPUs durch Ports der VPUs.“

The procedures described here can therefore visualize the situation and provide instructions for action. A user uses a simulation system, for example with a V-ECU and an environment model. He uses the simulation on a computer with 4 processor cores. Because he wants to achieve a shorter response time for his test without affecting the test results, he decides to investigate possibilities for parallelization. To do this, he uses the methods described here and can receive visualizations as described above and, for example, the following instructions:

• “The model contains the following tasks, which can be calculated simultaneously: VPU 1: Task 1 calculates 0.43 ms and VPU 2: Task 3 calculates 4.9 ms. The simulator has 4 processor cores available. By splitting it into two parts, the overall simulation could be speeded up by a maximum of 50%, depending on the communication needs of the VPUs through ports of the VPUs.”

• „Das Modell enthält folgende Tasks, die gleichzeitig berechnet werden können: VPU 1: Task 1 rechnet 0,43 ms, VPU 3: Task 3 rechnet 2,9 ms, VPU 4: Task 3 rechnet 2,8 ms. Durch eine besser ausgeglichene Aufteilung der Rechenzeit der VPU ist keine weitere Verbesserung möglich, weil für eine weitere Teilung zu wenig Prozessorkerne zur Verfügung stehen.“

The customer now divides VPU 2 into VPU 3 and VPU 4 and uses the method again. This time the instructions are different:

• “The model contains the following tasks, which can be calculated simultaneously: VPU 1: Task 1 calculates 0.43 ms, VPU 3: Task 3 calculates 2.9 ms, VPU 4: Task 3 calculates 2.8 ms. No further improvement is possible with a better balanced division of the computing time of the VPU, because there are not enough processor cores available for further division.”

• - Wenn es bei einer V-ECU in einer bestimmten Periode viele auffällig kurze Berechnungen und eine lange Berechnung gibt, sollte man die Taktperiode anpassen.
• - Wenn die Singlecore-Performance des aktuellen Rechners unter einem bestimmten Wert liegt, kann man den Wechsel auf potentere Hardware vorschlagen und auch die zu erwartende Leistungssteigerung angeben.
• - Wenn die Anzahl der VPUs kleiner ist als die Anzahl der Prozessorkerne, kann man mitteilen, dass mehr Prozessorkerne nicht zu einer Beschleunigung führen werden.
• - Wenn die Anzahl der VPUs größer ist als die Anzahl der Prozessorkerne, kann man mitteilen, wie sich eine Erhöhung der Prozessorkerne maximal auswirken würde.
• - Wenn die Berechnung eines Modells keine Eingänge und Ausgänge im gleichen Takt besitzt, liegt es nahe, dass es zu oft berechnet wird. Man kann eine Änderung als Taktfrequenz die niedrigste Taktfrequenz der verbundenen Modelle vorschlagen.
• - Zur Bestimmung der Maximalgeschwindigkeit: Man kann die kleinsten gemeinsamen Vielfachen der Taktfrequenz berechnen und der Parallelitätsgrad angeben. Daraus ergeben sich folgende Regeln für eine absehbare Anzahl an wiederkehrenden Zeitpunkten:
  • - Wenn ein Modell an einem wiederkehrenden Zeitpunkt mehr als doppelt so viel Zeit benötigt, als die anderen, würde sich eventuell eine Modellteilung lohnen.
  • - Wenn der Parallelitätsgrad in den wiederkehrenden Zeitpunkten gering ist, kann das auf ein nicht optimal ausgelastetes System hinweisen bzw. der Parallelitätsgrad in den häufigsten Ereignissen kann einen Hinweis auf die benötigten Rechenkerne ergeben.
  • - Das längste zu berechnende Modell pro Zeitpunkt bestimmt den Minimalwert der Rechenlänge und verrät, wie lang die Rechenlänge trotz Hardwareoptimierung bleiben wird.
• - Wenn die Anzahl der Modelle die Anzahl der Kerne übersteigt, kann man auch eine Co-Simulation auf zwei oder noch mehr Rechnern durchführen. Weil die Kommunikationskosten durch das Modell bekannt sind, kann man genau berechnen, wo die Trennung optimal ist: Hier kann man jede Auftrennungsmöglichkeit einmal mit den Kommunikationskosten und den Parallelisierungsgewinnen gegenrechnen.
• - Wenn der Speicherverbrauch zur Laufzeit einen bestimmten Wert übersteigt, sollte dieser als Nadelöhr angegeben werden.
• - Unter Nutzung von Hypervisortechnologie wird sukzessive dem Simulator ein Rechenkern entzogen und die Simulationsgeschwindigkeit berechnet.
  • - Der Maximalwert bei der Rechengeschwindigkeit wird für die Einzelgeschwindigkeit empfohlen.
  • - Der Maximalwert aus dem Quotienten von Rechengeschwindigkeit und der Anzahl der Prozessorkerne wird als optimale Ausstattung in der Cloud empfohlen.

For the sake of completeness, some rules are shown below as examples that can be used with the methods described here:

• - If there are many conspicuously short calculations and one long calculation in a V-ECU in a certain period, the clock period should be adjusted.
• - If the single-core performance of the current computer is below a certain value, you can suggest switching to more powerful hardware and also state the expected increase in performance.
• - If the number of VPUs is less than the number of processor cores, it can be said that more processor cores will not lead to acceleration.
• - If the number of VPUs is greater than the number of processor cores, one can report the maximum effect of increasing the processor cores.
• - If the calculation of a model does not have inputs and outputs in the same cycle, it is likely that it is calculated too often. One can suggest a change as clock frequency the lowest clock frequency of the connected models.
• - To determine the maximum speed: You can calculate the least common multiple of the clock frequency and specify the degree of parallelism. This results in the following rules for a foreseeable number of recurring points in time:
  • - If a model needs more than twice as much time than the others at a recurring point in time, it might be worth splitting the model.
  • - If the degree of parallelism in the recurring points in time is low, this can indicate a system that is not optimally utilized or the degree of parallelism in the most frequent events can provide an indication of the required computing cores.
  • - The longest model to be calculated per point in time determines the minimum value of the calculation length and reveals how long the calculation length will remain despite hardware optimization.
• - If the number of models exceeds the number of cores, you can also run a co-simulation on two or more computers. Because the communication costs are known from the model, you can calculate exactly where the separation is optimal: Here you can offset each possible separation with the communication costs and the parallelization gains.
• - If the memory consumption at runtime exceeds a certain value, this should be specified as a bottleneck.
• - Using hypervisor technology, a calculation core is successively removed from the simulator and the simulation speed is calculated.
  • - The maximum value in the calculation speed is recommended for the single speed.
  • - The maximum value from the quotient of computing speed and the number of processor cores is recommended as the optimal configuration in the cloud.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Non-patent Literature Cited

• Gene Amdahl: Validity of the Single Processor Approach to Achieving Large-Scale Computing Capabilities. In: AFIPS Conference Proceedings. 30, 1967, pp. 483-485

Claims (11)

Method for configuring a SIL simulation of a control unit running on a computer, software models for the control unit having a plurality of tasks being installed on the computer for the SIL simulation of the control unit, which are processed in a predetermined clock cycle having periodically consecutive clock times and the computer has a plurality of processor cores on which a plurality of virtual machines are running, each of which processes predetermined tasks, with the following method steps: a) Determination of sporadic model parts and periodic model parts of the software models, b) Creation of a group of parallelizable tasks from the periodic model parts of the software models, c) determining the individual clock times of the tasks that can be parallelized up to the smallest common multiple of all periods between the clock times of the tasks that can be parallelized, d) determining the calculation duration of the individual tasks at their respective cycle times and e) Determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores on the basis of the determined smallest common multiple of all periods between the clock times of the tasks that can be parallelized and the calculated calculation time of the individual tasks at their respective clock times that the computing time of the SIL simulation is minimal. procedure after claim 1 , with the following additional method step: f) reconfiguration of the software models according to the distribution of the tasks to the individual virtual machines determined in step e) and the distribution of the virtual machines to the individual processor cores. procedure after claim 1 or 2 , wherein step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores comprises the following reconfiguration: Outsourcing part of the SIL simulation to at least one additional computer if the number of Tasks exceeds the number of processor cores of the computer previously used for the SIL simulation. Method according to one of the preceding claims, wherein step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores comprises the following reconfiguration: Changing the period of a specific task to a larger period. Method according to one of the preceding claims, wherein step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores comprises the following reconfiguration: Splitting a more computationally intensive task into at least two less computationally intensive tasks. Method according to one of the preceding claims, wherein step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores comprises the following reconfiguration: Switch to faster processor cores. Method according to one of the preceding claims, wherein step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores comprises the following reconfiguration: Consolidate at least part of the tasks that communicate with each other. Method according to one of the preceding claims, wherein step e) of determining the distribution of the tasks to the individual virtual machines and the distribution of the virtual machines to the individual processor cores comprises the following reconfiguration: Allocating at least one additional processor core to a virtual machine. Non-volatile, computer-readable storage medium with a computer program stored thereon which, when executed on a processor, brings about a method according to one of the preceding claims. A method for configuring a SIL simulation of a control unit running on a computer, software models for the control unit with a plurality of tasks being installed on the computer for the SIL simulation of the control unit, which run in a predetermined cycle with a predetermined period between the are processed at individual clock times, and the computer has a plurality of processor cores on which a plurality of virtual machines run, each of which processes predetermined tasks, with the following method steps: a) determining sporadic model components and periodic model components of the software models, b) creating a group of parallelizable tasks from the periodic model parts of the software models, c) determining the individual clock times of the parallelizable tasks up to the smallest common multiple of all periods between the clock times of the parallelizable tasks and g) visualizing the tasks at a respective clock time are to be carried out. procedure after claim 10 , with the following additional method step: d) determining the calculation time of the individual tasks at their respective cycle times, wherein in step g) of visualizing the tasks that are to be executed at a respective cycle time, the respective calculation time of the individual tasks is also visualized.

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