WO2018006970A1

WO2018006970A1 - Semiconductor power stack of a modular multilevel converter

Info

Publication number: WO2018006970A1
Application number: PCT/EP2016/066194
Authority: WO
Inventors: Ilknur COLAK
Original assignee: Abb Schweiz Ag
Priority date: 2016-07-07
Filing date: 2016-07-07
Publication date: 2018-01-11

Abstract

The present disclosure relates to a stack of semiconductor switches of a phase leg 2 of a Modular Multilevel power Converter (MMC) 1, wherein semiconductor switches of a first cell 3a of the phase leg are stacked in an order of: 1) S1, 2) S2, 3) start-up switch Dcl, 4) S3, 5) S4. The S switches S1, S2, S3 and S4 are the switches of a full-bridge circuit of the first cell, and the start-up switch is a switch in a start-up circuit in the first cell.

Description

SEMICONDUCTOR POWER STACK OF A MODULAR

MULTILEVEL CONVERTER

TECHNICAL FIELD

The present disclosure relates to a stack of semiconductor switches of a phase leg of a Modular Multilevel Converter.

BACKGROUND

A Modular Multilevel power Converter (MMC), also known as Chain-Link Converter (CLC), comprises a plurality of converter cells, or converter sub- modules, serially connected in converter branches, or phase legs, that in turn may be arranged in a star, delta, direct or indirect converter topology. Each converter cell comprises, in the form of a half-bridge or full-bridge circuit, a capacitor for storing energy and power semiconductor switches such as insulated gate bipolar transistor (IGBT) devices, gate-turn-off thyristor (GTO) devices, integrated gate commutated thyristor (IGCT) devices, or Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices for connecting the capacitor to the converter branch with one or two polarities. MMCs may be used in electric power transmission systems such as Static Synchronous Compensator (STATCOM), Frequency Converters in direct or indirect topology and High-Voltage Direct Current (HVDC) transmission and rail applictions.

High-voltage MMCs are large structures which are typically arranged in its own room, in a container, in a building, or in a converter hall. The

semiconductor switches of cells of a phase leg are arranged on top of each other in a power stack of the converter.

Today's power electronics converters achieve high voltage and high power ratings by using the modular multilevel converters where the submodules are serially connected in the converter branches or phase legs to reach the required high voltage level. Each converter submodules or cells are built in the form of half bridge or full bridge topologies where the cell comprise power semiconductor switches, DC link capacitors for storing the energy and a switching unit to bypass the DC link capacitor in case of cell failure.

In modular multilevel converters, switching losses can be dominant in comparison to conduction losses where the parasitic inductances have a big influence on semiconductor switching waveforms and the losses. Stray inductances in the Direct Current (DC) side or in the Alternating Current (AC) side of the switching loops are responsible for the voltage transients on the bus and the voltage spikes at semiconductor turn-off (V_tr = -Lstray di/dt). When the switching semiconductor is turned on these inductances charge up and when it is turned off the inductances discharge causing an overvoltage on the semiconductor. A higher stray inductance not only increases the inductive voltage drop (which may take the semiconductor into avalanche) at the semiconductor terminals but also affects the current rise speed (di/dt) itself.

On the other hand, the stray inductances on the current commutation loops need to be equalized to avoid unbalances in switching losses and junction temperatures between the switching semiconductors.

SUMMARY

Each component in the submodule (also called cell) and their electrical connections have parasitic inductance that contributes to the inductance of the commutation loops in the cell. The connections between the components, therefore, the placement of the components in the cell and the sequence of the components in the cell power stack are also relevant to be able to provide the minimum stray inductance on the commutation loops, as well as the selection of the component types in the circuit. On the other hand, the cell semiconductor placement should provide also minimum stray inductance on the bypass loop, so that the bypass semiconductor switch will short the circuit and take over the failure current in case of failure, so that the other

semiconductors in the cell will not be harmed. The present disclosure is based on a study to reduce the switching loop areas and thus the stray inductances. Problems posed include:

To reduce the stray inductance and their negative impacts in the power stack, such as

a. Higher and longer voltage spikes on the semiconductor terminals, b. High switching losses,

c. Electromagnetic interference.

2. To have an equal parasitic inductance between the commutation loops, so that

a. Unequal power dissipation and thermal losses between the semiconductors can be prevented.

3. To find an optimum semiconductor sequence in the power stack to balance the parasitic inductances between the commutation loops and the bypass path, so that

a. The bypass switch will take over the fault current and the main

semiconductor switches will survive when there is a fault.

According to an aspect of the present invention, there is provided a stack of semiconductor switches of a phase leg 2 of a Modular Multilevel power Converter (MMC) 1, wherein semiconductor switches of a first cell 3a of the phase leg are stacked in an order of: 1) Si, 2) S2, 3) start-up switch Del, 4) S3, 5) S4. The S switches Si, S2, S3 and S4 are the switches of a full-bridge circuit of the first cell, and the start-up switch is a switch in a start-up circuit in the first cell.

This order of stacked semiconductor switches of a cell has been shown to reduce the stray inductance in the cell. It is to be noted that any feature of any of the aspects may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any of the other aspects. Other objectives, features and advantages of the enclosed embodiments will be apparent from the following detailed disclosure, from the attached dependent claims as well as from the drawings. Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a/an/the element, apparatus, component, means, step, etc." are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated. The use of "first", "second" etc. for different features/components of the present disclosure are only intended to distinguish the features/components from other similar features/components and not to impart any order or hierarchy to the features/components.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be described, by way of example, with reference to the accompanying drawings, in which: Fig 1 is a schematic illustration of an embodiment of an MMC, in accordance with the present invention.

Fig 2 is a schematic circuit diagram of an embodiment of a modular converter cell, in accordance with the present invention.

Fig 3 is a schematic circuit diagram of two series connected modular converter cells of the embodiment presented in figure 2, in accordance with the present invention.

Fig 4 schematically presents an example of a power stack with non-optimal semiconductor sequence according to the present study.

Fig 5 schematically presents another example of a power stack with non- optimal semiconductor sequence according to the present study.

Fig 6 schematically presents an example of a power stack with preferred semiconductor sequence, in accordance with the present invention. DETAILED DESCRIPTION

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown.

However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description.

Figure l is a schematic circuit diagram of an embodiment of an MMC l, e.g. a high-voltage MMC. The MMC l may be used in rail applications and in electric power transmission systems such as STATCOM, Frequency

Converters in direct or indirect topology or HVDC transmission. One or more (high-voltage) phases, u, v and w having respective currents ii, 12 and 13 are input to the converter 1 via input lines, e.g. via bushings through a wall of the room or building in which the converter 1 is located. In this example the MMC is in delta configuration with three phase legs 2, but any other configuration and number of phase legs is also possible with embodiments of the present invention. Each phase leg 2 comprises a plurality of cascaded (series connected) cells (also called sub-modules) 3. The currents in the converter 1 are referred to as "i", while the voltages are referred to as "U" in the figure, in combination with arrows indicating directions.

The cells 3 may be of any suitable type, e.g. half-bridge or full-bridge, but the present invention is particularly relevant for full-bridge cells (also called H- bridge or bipolar cells) comprising a power storing device and a plurality of semiconductor switches.

Figure 2 illustrates an example of a cell 3. The cell comprises a power storing device, here in the form of a DC-link capacitor Cc. The cell also comprises four (main) semiconductor switches S, forming the full-bridge (H-bridge) topology in the cell. The semiconductor switches of the full-bridge are conventionally named in the figures and text of the present disclosure as Si switch, S2 switch, S3 switch and S4 switch. When the switches Si and S4 are closed and S2 and S3 are open, a positive voltage will be applied. By opening Si and S4 switches and closing S2 and S3 switches, this voltage is reversed. Each of the S switches may comprise e.g. an IGBT, GTO, IGCT, or MOSFET, possibly in combination with an antiparallel one-direction

conducting/blocking component such as a diode. In the example of figure 2, each S switch comprises an IGCT and antiparallel diode. However, in some embodiments, e.g. IGBTs may be preferred instead of IGCTs.

The cell 3 also comprises a bypass switch. The bypass switch is typically also a semiconductor switch, in the example of the figure, a thyristor Thy. Further, the example cell of figure 2 comprises a start-up circuit for powering the cell during start-up of the cell. This start-up circuit also comprises a

semiconductor switch Del (herein called start-up switch) which may be a one- directional component, which is configured for blocking current in one direction but being able to, under certain circumstances, conducting current in the other direction, here in the form of a diode Del. In the example of figure 2, the start-up circuit is a so called clamp circuit, which implies that the one-directional component Del is a clamp diode. Also comprised in the clamp circuit are other components, which are not semiconductor switches, such as the clamp capacitor Ccl, a clamp resistance Rs, and a clamp inductor Ls. The converter cell 3 thus comprises six semiconductor switches, S1-S4 of the full-bridge, the bypass switch Thy, and the start-up switch Del. Although the bypass switch does not have to comprise a thyristor, and the start-up switch does not have to comprise a diode, the references Thy and Del are used in the figures and the throughout the text of the present disclosure. It is the order of these semiconductor switches in the power stack of the converter leg 2 which is the subject of the present invention, to reduce stray inductances etc., especially when stacked together with the corresponding semiconductor switches of a second cell 3 connected in series.

Figure 3 illustrates a circuit diagram with two series connected cells 3, a first cell 3a and a second cell 3b, in a phase leg 2 of the converter 1. The phase leg 2 may comprise any number of cells 3, but the first and second cells 3a and 3b are series connected directly to each other (there is a galvanic connection between the first and second cells), and to simplify the figure, only the first and second cells are shown as making up the phase leg.

Figure 3 also shows the references for the different connection points in each cell 3 which will hence forth be used. A is the first terminal of each cell 3, e.g. the input terminal if switches S2 and S3 are open, while B is the second terminal, e.g. the output terminal if switches S2 and S3 are open. C is the connection point of a node of the bypass switch, Thy, a node of the start-up circuit, Del, (and the positive node of the full bridge DC-link) and D is the connection point of the cathode of said bypass switch, Thy, the clamp capacitor's terminal, Ccl, (and the negative node of the full-bridge DC-link). The connection point E is within the start-up circuit and connected to the power stack externally, and thus generally not relevant to the present invention. Initially the two power stack sequences shown in figures 4 and 5 were built and tested. The results showed that the stray inductance in the switching loops were not the same for the two different sequences. IGCTs were used in the S switches.

As mentioned above, using proper type of components in the cell 3 which have low stray inductance and reorganizing the semiconductor sequence in the power stack may reduce the stray inductance in the commutation loops of the cell.

As a first step, different semiconductor sequences were tested to find the optimum sequence that allows high symmetry between the commutation loops, ease of assembly and low parasitic inductance on the bypass path.

While trying different sequences, the parasitic inductances were measured and compared for four different commutation loops in the cell.

The commutation loops will now be discussed. Loop A - The closed loop through the S3, S4, Del and Ccl components.

During the stray inductance measurement tests the components of the cell were arranged as below:

- Si, S2 and Thy components are replaced with insulators.

- S3, S4 and Del components are replaced with short circuiting material.

- Rs and Ls are disconnected from Del.

- Ccl is disconnected and measurement is done between Ccl (DC minus) to Rs.

Loop B - The loop which is created by Si, S2, Del and Ccl components. During the stray inductance measurement tests the components of the cell were arranged as below:

- Si, S2 and Del components are replaced with short circuiting material.

- S3, S4 and Thy components are replaced with insulators.

- Ccl and Rs are disconnected from Del.

- Ccl is disconnected and measurement is done between Ccl (DC minus) to Rs.

Loop C - The closed loop through the Si, S2 and Cc components.

- Si, S2 and Del components are replaced with short circuiting material.

- S3, S4 and Thy components are replaced with insulators.

- Ccl and Rs are disconnected from Del.

- Cc is shorted.

- Ls is connected to Del and the measurement is done between Ls and Cc. Loop D - The loop through components Ccl, Rs and Cc.

- Si, S2 and Thy components are replaced with insulators.

- S3, S4 and Del components are replaced with short circuiting material. - Rs and Ls are disconnected from Del.

- Ccl is disconnected and measurement is done between Ccl (DC minus) to Rs.

In the second step, the following actions are taken to reduce the components internal parasitic inductances and their negative impacts in the power stack: a. Press pack semiconductors are used in the cell power stacks since they each present a low stray inductance and resistance in its internal power circuit. b. Laminated bus-bars are used for the power inter connections. c. The number of screwed connections is minimized. d. The number of insulators in the power stack is minimized.

The resulting preferred power stack sequence of semiconductor switches for two series connected converter cells 2 is shown in figure 6. The

semiconductor switches of both the first and second cells 3a and 3b are placed next to (e.g. on top of) each other in the same stack. The sequence of the stack of figure 6 is, in the direction from bottom to top of the stack: first cell Thy-Si-S2-Dcl-S3-S4, and second cell Si-S2-Dcl-S3-S4-Thy. Insulators are used to separate adjacent semiconductor switches in the stack, between S2 and Del of the first cell 3a, between S4 of the first cell and Si of the second cell, and between S2 and Del of the second cell 3b. Additionally, there are typically heatsinks between each two semiconductor switches of the stack. A stack is often substantially vertical, which adjacent semiconductor switches positioned on top of each other in a single vertical column, but the stack may in some embodiments be substantially horizontal with the adjacent semiconductor switches positioned on next to each other in a single horizontal row. The semiconductor switches, preferably all of the

semiconductor switches, of a first cell 3a are positioned one after another in the same stack, and in some embodiments the semiconductor switches, preferably all of the semiconductor switches, of a second cell 3b are positioned one after another in the same stack as the first cell 3a, with an insulator separating the semiconductor switches of the first cell 3a from the semiconductor switches of the second cell 3b. The stack may comprise semiconductor switches of any number of cells, with insulators separating the semiconductor switches of different cells. The sequence of figure 6 has at least the following advantages:

- The stray inductance and its negative impacts in the power stack is reduced.

- The parasitic inductances between the current commutation passes are equalized, hence the unequal power dissipation and thermal losses between the semiconductors are reduced. - The parasitic inductances between the commutation loops and the bypass path over the bypass switch are optimized to increase the chance of protecting the semiconductor switches S of the full-bridge during bypass firing.

In some embodiments, each of the S switches Si, S2, S3 and S4, i.e. the switches forming the full-bridge of the cell, comprises an IGCT. The S switch may e.g. consist of an IGCT and an antiparallel diode.

In some embodiments, especially when the first and/or second cell 3a and 3b each comprise a start-up circuit in the form of a clamp circuit, the start-up switch Del comprises a clamp diode. In some embodiments, the stack of semiconductor switches of the first cell 3a and/or of the second cell 3b also comprises a bypass switch Thy. The bypass switch may conveniently be or comprise a thyristor. The bypass switch is preferably positioned either first or last among the semiconductor switches of the cell 3a and/or 3b. Thus, the order in the stack of the semiconductor switches of the first and/or second cell 3a and/or 3b may be either bypass switch Thy-Si-S2-startup switch DCI-S3-S4, or Si-S2-startup switch DCI-S3- S4-bypass switch Thy, in order to further reduce the stray inductances. The semiconductor switch stack may comprise the (e.g. all) semiconductor switches of a plurality of cells 3, e.g. of both the first cell 3a and of a second cell 3b. The semiconductor switches of the second cell 3b may be positioned in the stack in the same order as the corresponding semiconductor switches of the first cell 3a, at least regarding the full-bridge semiconductor switches Si, S2, S3 and S4, and start-up switch Del.

In a preferred embodiment, to further reduce the stray inductances, the sequence order of the full-bridge (switching) semiconductors Si, S2, S3 and S4 is the same in both the first and second cells 3a and 3b, but the position of the bypass switch Thy are mirrored as per figure 6. Thus, the order of the semiconductor switches of the two cells may be as follows:

0) bypass switch of the first cell,

1) Si of the first cell,

2) S2 of the first cell,

3) start-up switch of the first cell,

4) S3 of the first cell,

5) S4 of the first cell,

6) Si of the second cell,

7) S2 of the second cell,

8) start-up switch of the second cell,

9) S3 of the second cell,

10) S4 of the second cell,

11) bypass switch of the second cell.

Semiconductor switches of further cell(s) may also be included in the same stack, before or after the above specified sequence of semiconductor switches.

The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims. 

Claims

1. A stack of semiconductor switches of a phase leg (2) of a Modular Multilevel power Converter, MMC, (1), wherein semiconductor switches of a first full-bridge cell (3a) of the phase leg are stacked in an order of: 1) Si,

2) S2,

3) start-up switch (Del),

4) S3,

5) S4; wherein the S switches (Si, S2, S3, S4) are the switches of a full-bridge circuit of the first cell (3a); and wherein the start-up switch is a switch in a start-up circuit in the first cell.

2. The stack of claim 1, wherein each of the S switches (Si, S2, S3, S4) comprises an integrated gate commutated thyristor, IGCT.

3. The stack of claim 1 or 2, wherein the start-up switch (Del) comprises a clamp diode.

4. The stack of any preceding claim, wherein the stack of semiconductor switches of the first cell (3a) also comprises a bypass switch (Thy).

5. The stack of claim 4, wherein the bypass switch (Thy) is positioned before the Si switch to form a stack order of:

0) bypass switch,

1) Si,

2) S2,

3) start-up switch,

4) S3,

5) S4; or after the S4 switch to form a stack order of: 1) Si,

2) S2,

3) start-up switch,

4) S3,

5) S4;

6) bypass switch.

6. The stack of claim 4 or 5, wherein the bypass switch (Thy) comprises a thyristor.

7. The stack of any preceding claim, wherein the order is from the bottom and up in the stack.

8. The stack of any preceding claim, wherein the stack further comprises semiconductor switches of a second full-bridge cell (3b), stacked in an order of:

1) Si,

2) S2,

3) start-up switch (Del),

4) S3,

5) S4.

9. The stack of claim 8, wherein both the first and the second cell (3a, 3b) comprises a bypass switch (Thy), wherein the bypass switch of the first cell is positioned before the before the Si switch of the first cell (3a), and the bypass switch of the second cell (3b) is positioned after the S4 switch of the second cell, to form a stack order of: o) bypass switch of the first cell,

1) Si of the first cell,

2) S2 of the first cell,

3) start-up switch of the first cell,

4) S3 of the first cell,

5) S4 of the first cell, 6) Si of the second cell,

7) S2 of the second cell,

8) start-up switch of the second cell,

9) S3 of the second cell,

10) S4 of the second cell,

11) bypass switch of the second cell.