WO2018006928A1 - Techniques d'évaluation des performances d'une conception de matériel électronique sur un serveur de simulation informatique - Google Patents

Techniques d'évaluation des performances d'une conception de matériel électronique sur un serveur de simulation informatique Download PDF

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Publication number
WO2018006928A1
WO2018006928A1 PCT/EP2016/065664 EP2016065664W WO2018006928A1 WO 2018006928 A1 WO2018006928 A1 WO 2018006928A1 EP 2016065664 W EP2016065664 W EP 2016065664W WO 2018006928 A1 WO2018006928 A1 WO 2018006928A1
Authority
WO
WIPO (PCT)
Prior art keywords
thread
worker
computer simulation
threads
execution
Prior art date
Application number
PCT/EP2016/065664
Other languages
English (en)
Inventor
Ori Chalak
Zuguang WU
Libing ZHENG
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to PCT/EP2016/065664 priority Critical patent/WO2018006928A1/fr
Priority to CN201680085135.XA priority patent/CN109416642A/zh
Publication of WO2018006928A1 publication Critical patent/WO2018006928A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/522—Barrier synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/02—CAD in a network environment, e.g. collaborative CAD or distributed simulation

Abstract

L'invention concerne un procédé (100) d'évaluation des performances d'une conception de matériel électronique sur un serveur de simulation informatique comprenant une pluralité de cœurs de traitement, le procédé comprenant : la partition (101) d'une simulation informatique (110) de la conception de matériel électronique parmi une pluralité de fils de travail (111, 112, 113) pour une exécution parallèle sur la pluralité de cœurs de traitement du serveur de simulation informatique ; la fourniture (102) d'un élément de planification (114) pour commander la progression de la pluralité de fils de travail (111, 112, 113) ; et l'exécution (103) de l'élément de planification (114) et de la pluralité de fils de travail (111, 112, 113) sur la pluralité de cœurs de traitement pour évaluer une performance de la conception de matériel électronique sur le serveur de simulation informatique, une exécution de la pluralité de fils de travail (111, 112, 113) étant mutuellement verrouillée (121, 122) avec une exécution de l'élément de planification (114).
PCT/EP2016/065664 2016-07-04 2016-07-04 Techniques d'évaluation des performances d'une conception de matériel électronique sur un serveur de simulation informatique WO2018006928A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/EP2016/065664 WO2018006928A1 (fr) 2016-07-04 2016-07-04 Techniques d'évaluation des performances d'une conception de matériel électronique sur un serveur de simulation informatique
CN201680085135.XA CN109416642A (zh) 2016-07-04 2016-07-04 计算机模拟服务器上的电子硬件设计的性能评估技术

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2016/065664 WO2018006928A1 (fr) 2016-07-04 2016-07-04 Techniques d'évaluation des performances d'une conception de matériel électronique sur un serveur de simulation informatique

Publications (1)

Publication Number Publication Date
WO2018006928A1 true WO2018006928A1 (fr) 2018-01-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2016/065664 WO2018006928A1 (fr) 2016-07-04 2016-07-04 Techniques d'évaluation des performances d'une conception de matériel électronique sur un serveur de simulation informatique

Country Status (2)

Country Link
CN (1) CN109416642A (fr)
WO (1) WO2018006928A1 (fr)

Citations (1)

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US6766517B1 (en) * 1999-10-14 2004-07-20 Sun Microsystems, Inc. System and method for facilitating thread-safe message passing communications among threads in respective processes
US7496494B2 (en) * 2002-09-17 2009-02-24 International Business Machines Corporation Method and system for multiprocessor emulation on a multiprocessor host system
US7401334B2 (en) * 2002-12-20 2008-07-15 International Business Machines Corporation Method, apparatus and computer program product for managing message flow in a multithreaded, message flow environment
WO2012093496A1 (fr) * 2011-01-07 2012-07-12 富士通株式会社 Procédé de planification multitâche et système de processeur multicœur

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150058859A1 (en) * 2013-08-20 2015-02-26 Synopsys, Inc. Deferred Execution in a Multi-thread Safe System Level Modeling Simulation

Non-Patent Citations (6)

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Title
"IFIP Advances in Information and Communication Technology", vol. 310, 1 January 2009, ISSN: 1868-4238, article RAUF SALIMI KHALIGH ET AL: "Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling", pages: 149 - 158, XP055234827, DOI: 10.1007/978-3-642-04284-3_14 *
ANDREW OVER ET AL: "A Comparison of Two Approaches to Parallel Simulation of Multiprocessors", PERFORMANCE ANALYSIS OF SYSTEMS & SOFTWARE, 2007. ISPASS 2007. IEE E INTERNATIONAL SYMPOSIUM ON, IEEE, PI, 1 April 2007 (2007-04-01), pages 12 - 22, XP031091884, ISBN: 978-1-4244-1081-1 *
BRINGMANN OLIVER ET AL: "The next generation of virtual prototyping: Ultra-fast yet accurate simulation of HW/SW systems", 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), EDAA, 9 March 2015 (2015-03-09), pages 1698 - 1707, XP032765878, DOI: 10.7873/DATE.2015.1105 *
CHRISTOPH SCHUMACHER ET AL: "parSC", 2010 IEEE/ACM/IFIP INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS (CODES+ISSS 2010) : SCOTTSDALE, ARIZONA, USA, 24 - 29 OCTOBER 2010, 1 January 2010 (2010-01-01), Piscataway, NJ, pages 241, XP055352384, ISBN: 978-1-60558-905-3, DOI: 10.1145/1878961.1879005 *
EZUDHEEN P ET AL: "Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines", PRINCIPLES OF ADVANCED AND DISTRIBUTED SIMULATION, 2005. PADS 2005. WO RKSHOP ON MONTEREY, CA, USA 01-03 JUNE 2005, PISCATAWAY, NJ, USA,IEEE, 1730 MASSACHUSETTS AVE., NW WASHINGTON, DC 20036-1992 USA, 22 June 2009 (2009-06-22), pages 80 - 87, XP058191459, ISSN: 1087-4097, ISBN: 978-0-7695-3713-9, DOI: 10.1109/PADS.2009.25 *
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