WO2018005838A1

WO2018005838A1 - Chemically assembled two-dimensional junctions

Info

Publication number: WO2018005838A1
Application number: PCT/US2017/040063
Authority: WO
Inventors: Xiang Zhang; Mervin W. ZHAO; Yu YE
Original assignee: The Regents Of The Universtiy Of California
Priority date: 2016-06-30
Filing date: 2017-06-29
Publication date: 2018-01-04

Abstract

Embodiments are generally directed to large-scale spatially controlled synthesis of two-dimensional transistors. Conductive graphene serves as a growth mask that semiconducting molybdenum disulfide nucleates at the edges. Such chemically assembled atomic transistors exhibit high transconductance (10 μS), on-off ratios (~10⁶), and mobility (-17 cm² V^-1s^-1). Two-dimensional logic circuits may be assembled, such as a heterostructure NMOS inverter with a high voltage gain, up to 70, enabled by the precise site selectivity from atomically thin conducting and semiconducting crystals.

Description

CHEMICALLY ASSEMBLED TWO-DIMENSIONAL JUNCTIONS

Cross- Reference to Related Application

[0001] This application claims the benefit of U.S. Provisional Patent Application Serial No. 62/356,946, titled CHEMICALLY ASSEMBLED TWO-DIMENSIONAL JUNCTIONS and filed on June 30, 2016, the content of which is fully incorporated by reference herein.

Statement of Federal Rights

[0002] This invention was made with government support under Grant Number

EFMA1542741 and DGE1106400 awarded by the National Science Foundation and Grant Number N00014- 16- 1-2232 awarded by the Office of Naval Research. The government has certain rights in the invention.

Technical Field

[0003] The disclosed technology relates generally to new semiconductor technologies, particularly to the growth and assembly of electrical junctions with two-dimensional crystals (e.g., graphene and M0S2).

Background

[0004] Moore's law projects that integrated electronics will soon require sub- 10 nm transistors. With silicon, this task becomes extremely challenging as the transistor's channel thickness becomes greater than the channel's length, ultimately leading to difficult electrostatic control via the transistor gates. The chemical synthesis of nanomaterials such as inorganic nanowires and carbon nanotubes were aimed at addressing this issue, but utilizing them in electrical devices requires precise placement and orientation using complex fabrication techniques. The fabrication to create sophisticated electronic circuitry using these materials remains difficult or impractical. Recently emerging crystalline two-dimensional (2D) materials may provide an elegant solution to the problematic scaling in silicon transistors with their ultimate atomic thickness. Graphene, the first widely studied 2D crystal, is a semi-metal with a massless carrier dispersion, high mobility, and easily-tunable Fermi level. While single-layer graphene lacks an electronic band-gap, rendering it unsuitable for transistor channels (e.g., because it cannot easily be turned "off), the excellent conductive properties make it suitable for the interconnections and wiring of next generation electronic devices.

[0005] Recently, semiconducting transition metal dichalcogenides (TMDCs), such as molybdenum disulfide (MoS₂), have found some success as a single-layer transistor. While early works using single-layer TMDCs relied on the "Scotch tape" method of

micromechanical exfoliation, considerable efforts have established the chemical vapor deposition (CVD) of various TMDCs. For example, CVD-grown lateral heterostructures which utilize two different TMDCs have been able to create atomically sharp p-n junctions. While lateral heterostructures using wide-gap insulators and conductors, e.g., h-BN and graphene, have also been grown, there has not yet been a demonstration of the spatially controlled synthesis of conductor-semiconductor heterostructures, which is a necessary step toward full atomically-thin circuitry.

[0006] Next-generation electronics call for new materials beyond silicon for increased functionality, performance, and scaling in integrated circuits. Carbon nanotubes and semiconductor nanowires are at the forefront of these materials, but have challenges due to the complex fabrication techniques required for large-scale applications. Two-dimensional gapless graphene and semiconducting transition metal dichalcogenides have emerged as promising electronic materials due to their atomic thickness, chemical stability and scalability, but difficulties in the assembly of two-dimensional electronic structures arise in the precise spatial control over the metallic and semiconducting atomic thin films. Ultimately, this impedes the maturity of integrating atomic elements in modern electronics.

Summary

[0007] Using chemical vapor deposition (CVD), a single layer of semiconducting M0S2 can be grown onto the edges of highly conductive single-layer graphene and fill empty channels in a large scale. This serves a two-fold purpose: 1) graphene as a growth mask enables the selective growth of a single-layer semiconductor for arbitrary circuits writing, and 2) graphene enables a more efficient contact to the M0S2 with a lower contact resistance than traditional metals. Heterostructures using graphene and M0S2 can advantageously form all two-dimensional transistors and circuits using materials compatible with wafer scalability and processes.

[0008] Graphene-MoS2 structures can be used as transistor building blocks for future two- dimensional electronics. These two materials are both chemically stable, and wafer-scale growths are well-established. Two-dimensional materials are a major material candidate in the development of next-generation electronics due to the scaling problem in traditional bulk semiconductors.

Brief Description of the Drawings

[0009] FIGURES 1A-1F illustrate exemplary images and spectral characterizations of graphene-MoS2 heterostructure in accordance with the disclosed technology.

[0010] FIGURES 2A-2E illustrate exemplary electron microscopy characterizations of the graphene-MoS2 junction in accordance with the disclosed technology.

[0011] FIGURES 3A-3F illustrate exemplary room temperature electrical transport measurements of the graphene-MoS2 heterostructure transistor in accordance with the disclosed technology in accordance with the disclosed technology.

[0012] FIGURES 4A-4C illustrate an example of demonstrating logic through a

heterostructure inverter in accordance with the disclosed technology in accordance with the disclosed technology.

Detailed Description

[0013] FIGURES 1A-1F illustrate exemplary images and spectral characterizations of graphene-MoS2 heterostructure in accordance with certain embodiments of the disclosed technology. FIGURE 1A illustrates a scheme of the heterostructure growth process in which graphene is first etched into channels and then M0S2 begins to nucleate around the edges and within the channel. On the edges, M0S2 forms a thicker overlap junction with graphene, and the further growth results in MoS 2 completely filling the channels. FIGURE IB illustrates a scanning electron microscope image of the chemically grown M0S2 between the graphene' s edges. The image shows a large scale of coverage, millimeter in scale. In areas without graphene, the growth of triangular domains can be seen on the right of the image. FIGURE 1C illustrates an otical image of the heterostructure wherien, within the narrow channel, the M0S2 completely fills the area between the graphene. Thicker areas can be observed around the graphene's edges, indicative of the nucleation of the M0S2 areas (e.g., denoted by the black arrows). The dashed box represents the area used for the spectral mapping in the following figures.

[0014] FIGURE ID illustrates a Raman mapping using the integrated peak intensities from 1500 to 1700 cm-i. Graphene's Raman signature is the G-peak centered near 1600 cm-i. The mapping shows that only the contact areas are graphene. The same results can be observed from integrating the intensities around graphene's 2D peak, e.g., centered near 2700 cm-i. FIGURE IE illustrates a Raman mapping using the integrated peak intensities from 380 to 415 cm-i in which the M0S2 has two distinct Raman peaks, e.g., E2_g and Ai_g, centered near 385 and 410 cm-i, respectively. These Raman modes support the finding that the crystalline region inside the grown region is indeed M0S2. FIGURE IF illustrates a photoluminescence mapping of the emission from M0S2 centered at 660 nm. The M0S2 transitions from an indirect to direct band-gap semiconductor when it is thinned down to a single layer, showing high emission only in areas without graphene.

[0015] Embodiments of the disclosed technology generally include chemically assembling heteroj unctions using graphene-MoS2-graphene heterostructures, as illustrated by FIGURE 1A. Unlike previous reports which rely on transferring and physically assembling transistors using these 2D crystals, these embodiments may include chemically growing these transistors in a large scale. Effectively injecting current from the graphene through the M0S2 has demonstrated an NMOS inverter for logic operations, using such heterostructure transistors.

[0016] To chemically assemble the heterostructures, single-layer graphene is first transferred onto a silica substrate, as the growth and transfer techniques of graphene are now common in a large scale. Channels within the graphene can be opened up by way of oxygen plasma etching. The graphene having empty channels on silica can then be placed into a quartz tube for the seed-promoted CVD growth of single-layer M0S2. Fabrication on graphene previous to the growth results in dangling bonds and lithographic residues, causing a high density of M0S2 nucleation at the edges. The lack of new chemical bonding and crystalline mismatch between these two crystals results in nanometer-scale overlap junctions between the two atomic crystals. Preferential growth within the S1O2 channels results in the merging of individual domains which forms a continuous, polycrystalline single-layer of M0S2, which is consistent with the observations that can be made in large area CVD growth on bare substrates.

[0017] Using solid precursors, heterostructures can be grown that have millimeter-sized coverage, as illustrated by FIGURE IB, where the uniform single-layer MoS2 can be observed within defined channels from the etched graphene. From optical microscopy, triangular M0S2 grains can be observed along the graphene, indicating that the edge serves as a site for the crystal nucleation. In addition, FIGURE 1C illustrates an optical image of the heterostructure with brighter nucleation regions (e.g., represented by black arrows) along the junction between the graphene and the M0S2, which is consistent with previous reports.

[0018] In order to confirm the existence of the proposed heterostructure, Raman spectroscopy mapping can be performed. FIGURE ID illustrates graphene areas preserving their Raman signature after the growth, e.g., as seen from either the G or 2D peak, indicating that the growth process is non-destructive to graphene. Additionally, using the E2_g and Ai_g modes of the M0S2, the boundaries of M0S2 growth can be clearly delineated, as illustrated by FIGURE IE. Within the channel regions, the Raman spectra is able to confirm the single-layer nature of the grown M0S2. Larger peak differences and higher intensities correspond to the thicker nucleation centers (e.g., denoted by black arrows). These findings can be confirmed by the photoluminescence (PL) mapping of the channel, as illustrated by FIGURE IF.

[0019] Since single-layer M0S2 possesses a direct band-gap, strong emission centered at around 670 nm can be detected in agreement to the findings observed from the Raman spectra. The weaker areas of PL signal also correspond well to the higher intensities in the M0S2 Raman signals, which shows the thicker M0S2 regions (e.g., denoted by black arrows). The PL energy and peak width as well as the Raman spectra of the M0S2 within the heterostructure are consistent with the reports of CVD M0S2 on S1O2 substrates, indicating that the presence of graphene does not influence the relative strain and doping levels of the M0S2. Additionally, the M0S2 within the channel is a uniform single-layer, with the exception of sparse multilayer patches which occur near the nucleation centers in the channel and around the edges. The optical spectroscopy results agree well with the microscopy image, showing the same thicker areas.

[0020] FIGURES 2A-2E illustrate exemplary electron microscopy characterizations of the graphene-MoS2 junction in accordance with the disclosed technology. FIGURE 2A illustrates a Falsecolor DF-TEM overlay that shows the M0S2 is continuous and polycrystalline at the MoS2-graphene junction. The M0S2 grains shows random orientations with respect to graphene. FIGURE 2B illustrates a corresponding diffraction pattern from the region in FIGURE 2A that indicates the graphene is single crystal. The four-colored circles indicate distinct grain orientations of the M0S2 used to create the false-color map in FIGURE 2A.

[0021] FIGURE 2C illustrates an ADFSTEM image of the graphene-MoS2 junction that shows -100-200 nm overlap. The graphene edge can be identified by the image intensity, which is proportional to Ζγ, where Z is the atomic number and 1.3 < γ < 2. Inset is the corresponding intensity line profile from the white dashed line across the junction. FIGURE 2D illustrates an EELS elemental map of graphene, M0S2 and the junction that shows S and C edges. The graphene signature in the o* peak shows up on the graphene and the junction, while only amorphous carbon (π*) from polymer residue shows up on the M0S2. FIGURE 2E illustrates an EELS elemental map of graphene (e.g., yellow) and M0S2 (e.g., red) that confirms the overlapped junction.

[0022] The crystallinity of the grown single layer MoS2 as well as the junction between the M0S2 and the graphene using transmission electron microscopy (TEM) can be evaluated. The dark-field TEM (DF-TEM) images illustrated by FIGURE 2A can be used to create a false- color map of the M0S2 grains in the heterostructure, using the diffraction pattern (e.g., as illustrated by FIGURE 2B). The selected area contains a single grain of graphene, as indicated by graphene' s diffraction spots in FIGURE 2B. The color-mapped grains of M0S2 in FIGURE 2A indicate that the growth of M0S2 along the graphene edge is independent of the graphene lattice orientation. This is not unexpected, as the graphene fabrication results in the edges being random and containing many defects. Coupled with optical microscopy images, the MoS2 grain size along the edges of the graphene is ~1 μιη.

[0023] Furthermore, annular dark field (ADF-) STEM is able to provide high-resolution images of the graphene-MoS2junction (e.g., as illustrated by FIGURE 2C). An intensity plot from a line profile in the image (e.g., inset of FIGURE 2C) is able to elucidate that the junction is a -100 nm overlap of single layer M0S2 on top of graphene. In addition, the further growths of secondary and tertiary patches of M0S2 can be observed close to the graphene edge, though not nucleating within the graphene surface. This confirms that nucleation of the M0S2 occurs at the edges of the graphene, with defects of the graphene- M0S2 junction allowing for multilayer patches to grow on top. While the junction illustrated by FIGURE 2C is an overlap junction and not atomically sharp, there is still a significant barrier to the further growth of M0S2 on graphene. This is clearly seen from FIGURE 2A, where larger grains terminate near the boundary between the graphene and M0S2 and multilayer patches do not grow into the graphene region (e.g., as illustrated by FIGURE 2C).

[0024] The nature of this overlap can be probed using electron energy loss spectroscopy (EELS) which provides the compositional and bonding information in the heterostructure. From the EELS spectrum illustrated by FIGURE 2D, the carbon K-edge can be used to identify graphene, while distinct molybdenum and sulfur edges can be used for M0S2. Using the distinct graphene signature (σ*) and the sulfur edges for M0S2, a compositional map may be created (e.g., as illustrated by FIGURE 2E). Within the overlapped region, the lack of additional new peaks as well as the retention of graphene and M0S2 signatures confirms that the overlap is a van der Waals he teroj unction without the formation of additional covalent bonding in the energies probed.

[0025] The nucleation of the M0S2 (e.g., a three-atom-thick crystal), occurs from graphene' s one-atom-thick edges. Thus far, lateral heterostructures between van der Waals crystals have shared similar lattice constants, or chemistries. Heterostructures grown using two different TMDCs show that there is typically a preference for lateral epitaxy which is accompanied by vertical growth as time increases. In the case with graphene and M0S2, the lattice mismatch (e.g., in-plane and out-of-plane), as well as distinct chemical differences, inhibits in-plane bonding and epitaxy, leading to the formation of an overlap junction. The results indicate a significant reduction in the nucleation energy barrier of M0S2 at the edges of graphene compared to graphene' s surface.

[0026] Lithographically opening up channels on graphene causes defects and dangling bonds while leaving residue at the edges. This leads to increased nucleation accompanied by slight surface growth of M0S2 which forms a van der Waals overlapped junction. Similar reports are found in CVD graphene, as an overlap of similar width forms during the growth of graphene - graphene junctions. Growth on the graphene is limited due to the difficulty in vertical epitaxy of MoS2 on graphene, as large crystalline areas require unique growth conditions not present in this growth. Additionally, the hydrophilic S1O2 surface (e.g., due to the oxygen plasma treatment to etch the graphene) has a higher affinity for the growth seed' s transport, especially compared to the hydrophobic graphene surface. Thus, the growth process may be summarized as edge-nucleation and the formation of an overlap junction encouraged by graphene' s defects, combined with MoS 2 "filling" through seeded growth on hydrophilic areas.

[0027] The heterostructure can utilize graphene as a metallic electrode to inject current into the M0S2. Transistors fabricated using physically transferred graphene-MoS2 heterostructures have demonstrated that graphene is an efficient electrical contact material. Due to the tuning of graphene' s Fermi level, graphene contact can reduce the contact barrier and form ohmic contacts with M0S2. An inherent challenge in the use of single-layer M0S2 IS due to the typical Schottky-limited transport, as the CVD M0S2 results in the contact resistance (Rc) ranging from -50-200 kQ- μιη. Hence, the electrical properties which result from the nucleation along the graphene edges is expected to play a crucial role in the electrical transport characteristics of these heterostructure transistors. [0028] FIGURES 3A-3F illustrate exemplary room temperature electrical transport measurements of the graphene-MoS2 heterostructure transistor in accordance with the disclosed technology. FIGURE 3A illustrates an optical image of a field-effect transistor device array fabricated from a single growth. FIGURE 3B illustrates typical source-drain current- voltage curves measured at differing top-gate voltages. Below a source-drain bias of 1 V, linear ohmic behavior is observed suggesting an efficient electrical contact between the graphene and M0S2. Current saturation is achieved at a bias voltage of 1.5 V. FIGURE 3C illustrates a typical source-drain current curve measured by altering the top-gate voltage for a source-drain voltage of 1 V. From the curve, an on-off ratio for the heterostructure transistor can be estimated to be approximately 10⁶. The inset shows the transconductance of the heterostructure under VDS = 1 V, reaching a peak of 10 μ8. From the curve, the room temperature field-effect mobility can be estimated to be -20 cm² V ¹ s ¹ for the device.

[0029] FIGURE 3D illustrates a histogram of the device mobility performed on 100 devices yielding a mobility of 17.2 ± 3.9 cm² V ¹ s ¹. FIGURE 3E illustrates the field effect mobilities from FIGURE 3D as a function of the transistor lengths. In the example, two growths were performed to give the red and blue data points. The mobilities across different growths both hover in the 15-20 cm² V ¹ s ¹ range, showing that both the channel length as well as growth conditions do not have a large impact on the field effect mobility. FIGURE 3F illustrates the contact resistance of the heterostructure device and the graphene only control devices (e.g., after the growth and fabrication processes) extracted using the transfer length method. The inset illustrates the typical transfer length method for both the complete heterostructure (e.g., VDS = 0.2 V) and graphene (e.g., VDS = 0.01 V) at VTG - Vih - 4 V. The total contact resistance of the heterostructure reaches a minimum at approximately -11 kQ- μιη with graphene' s contact resistance at 1 kQ^m, thus yielding a graphene-MoS2 contact resistance of -10 kQ- μιη.

[0030] The field-effect transistor (FET) performance of the typical graphene-MoS2-graphene structure is measured at room temperature (e.g., optical images of devices illustrated in FIGURE 3 A). The I-V curves show linear behavior at small source-drain voltages, confirming the ohmic contact between the graphene and the single-layer M0S2 film (e.g., as illustrated by FIGURE 3B). In addition, the source-drain current saturates at a larger source- drain voltage (e.g., 1.5 V), a crucial parameter for reaching maximum possible operating speeds and maximizing the intrinsic transistor gain. Through electrical transport

measurements, the heterostructure exhibits typical n-type channel characteristics. [0031] FIGURE 3C illustrates the top-gate dependence for the heterostructure FET under bias voltages of 1 V. The turn-on voltage can be measured at around -1.5 V, indicative of a relatively high electron-doping concentration. These measurements show that the

heterostructure exhibits a high on/off current ratio of ~10⁶, a peak transconductance close to 10 μ8, and a corresponding carrier concentration of 5.6xl0¹² cm^~2. 100 devices were measured and a field effect mobility of 17.2 ± 3.9 cm² V ¹ s ¹ was extracted (e.g., as illustrated by FIGURE 3D), comparable to reports of physically transferred heterostructures. In addition, the mobility across various channel lengths yields similar values of 15-20 cm² V ¹ s ¹ in FIGURE 3E, indicating the mobility does not vary with channel length.

[0032] In order to determine the contact resistance (Rc) between graphene and M0S2 the transfer length method may be used to extract the length-dependent resistance in both the complete heterostructure as well as our graphene samples, after the growth and fabrication (e.g., inset of FIGURE 3F). The total Rc (e.g., metal-graphene-MoS2) can be plotted across the gate voltage in FIGURE 3F, showing the minimum Rc at high gate voltages when the device turns on is approximately -11 kQ- μιη, with the graphene-metal Rc corresponding to ~ 1 kQ- μιη. Thus, Rc ~ 10 kQ- μηι can be extracted for the graphene-MoS2 contact. While multilayer M0S2 and graphene may have a much lower contact resistance due to the electronic structure changes leading to improved electrical properties, the results can be markedly reduced from the contact resistances of physically transferred CVD monolayer M0S2 and graphene, which report Rc - 100 kQ- μιη. Hence, it is demonstrated that the chemically synthesized graphene-MoS2 structure reduces the contact resistance of traditional metal- contacted CVD monolayer M0S2, while preserving the mobilities achieved from the physically transferred heterostructures in a scalable method.

[0033] FIGURES 4A-4C illustrate an example of demonstrating logic through a

heterostructure inverter in accordance with certain embodiments of the disclosed technology. FIGURE 4A illustrates an example of an inverter circuit. Using two n-type transistors to create an inverter, the bottom transistor (load) can be under a driving voltage while the top transistor (driver) can be grounded. The load's gate and the common electrode can be read through as the output voltage. The input voltage can be applied through the driver' s gate. At low input voltages, the driver can be turned-off and the output voltage can be read as the driving voltage (e..g, "1"). At higher input voltages, the system can invert and the output voltage can become zero, as the driver turns on (e.g., "0").

[0034] FIGURE 4B illustrates inverter transfer characteristics for driving voltages of 1, 2, and 4 V, showing the inversion behavior at a threshold voltage of around -1.7 V. As can be seen in FIGURE 4A, low input voltages yield an output voltage equal to the driving voltage. After crossing the threshold, the output voltage can be read as 0. FIGURE 4C illustrates the absolute differential of the inverter curves giving the voltage gain. At a driving voltage of 4 V, an extremely high voltage gain of 70 can be achieved, which is among the highest in TMDC inverters.

[0035] To demonstrate additional applicability, two-dimensional atomic logic circuitry of an inverter (e.g., a NOT gate, as illustrated by FIGURE 4A) can be assembled using these heterostructures. FIGURE 4B illustrates the static voltage transfer characteristics of the heterostructure NMOS inverter with driving voltages of 1, 2, and 4 V with clear inverting behavior. At low Vin, starting at -2.5 V, Vout can be consistently at the level of VDD. Once Vin reaches around a threshold of -1.7 V, Vout can quickly switch to zero and maintain this voltage up to Vin = 0 V. The heterostructure inverter can also yield an extremely high voltage gain, reaching 70 for VDD = 4 V (e.g., as illustrated by FIGURE 4C), which is one of the highest among all the inverter gates made from TMDC materials. As demonstrated by the logic, the control over arbitrary designed patterns can lay the foundation for fully grown atomic computing.

[0036] A key difference between the disclosed technology and an independent work which also reported the growth of similar heterostructures using graphene and MoS is in the lower contact resistance reported here (10 kQ- μιη), compared to ref. 44 (300 kQ- μιη). This ultimately leads to the order of magnitude higher inverter gain (70, compared with 6 in ref. 44). The dark-field TEM results (e.g., as illustrated by FIGURE 2A) can confirm that the M0S2 grains have no orientation preference to graphene and the EELS (e.g., as illustrated by FIGURES 2D-2E) results definitively indicate the junction is of van der Waals nature without new bonding. Finally, the device statistics prove this method' s scalability and repeatability, thus making it desirably suitable for future applications.

[0037] The disclosed technology has successfully demonstrated chemically assembled heterostructures composed of single layers of conductive graphene and semiconducting M0S2. Large-area coverage, over a millimeter in size, and functionality can be achieved due to the dual nature of graphene as a growth template and an electrical contact. Using over 100 heterostructure FETs, it has been shown that these devices have on/off ratios of 106 and mobilities centered around 17 cm² V ¹ s ¹ and up to -30 cm² V ¹ s ¹. These transistors are advantageously suitable for inverters that have voltage gains up 70. It is envisioned that these heterostructures can form ballistic transistors in the short-channel limit with high

performance, thus enabling the development of alternatives to silicon technologies. Coupled with the industrial wafer-scale compatibility of graphene and M0S2 growths, the spatial control over the synthesis of 2D conductor-semiconductor heterostructures paves the way for next-generation electronics and computing.

[0038] In certain embodiments, wafer-scale wet-transferred graphene may be used.

Photolithography may be used to define a variety of channel lengths in the graphene, e.g., using PMMA and I- line as a photoresist. Oxygen plasma can then be used to etch away the opened channels in the graphene. The photoresist can be washed away using acetone and then annealed in an A1/H2 environment for two hours at 300 °C, for example.

[0039] The heterostructure growth can be performed following a procedure similar to reports of seeded CVD M0S2 growth. The chemical seed PTAS (e.g., perylene-3,4,9, 10- tetracarboxylic acid tetrapotassium salt) can be dispersed into water to create a solution corresponding to approximately 20 μΜ, where 5 μΐ. of the solution can be placed onto the substrate with graphene and then blown off using nitrogen, for example. Approximately 18 mg of solid molybdenum trioxide powder can be placed in an alumina crucible at the center of the furnace while 16 mg of solid sulfur can be placed upstream at a lower temperature. The substrate containing the graphene patterns can be placed directly above the M0O3 powder. The temperature can be increased to 650°C at a rate of 15°C/min and kept at 650°C for five minutes, for example. High purity argon can be used as a carrier gas to first flush the tube for five minutes, and a rate of 5 SCCM can be used during the growth. Following the growth, the furnace can be opened and argon can be flushed at a high flow rate to rapidly cool the sample.

[0040] The heterostructures can cover approximately 20-30% of the chip exposed to the M0O3 powder, typically further away from the center, where unwanted bulk over-growths occur. The length of the growth region can be limited by the chip and precursor length within the crucible, typically resulting in total heterostructure areas of approximately 2 cm in length and 1-2 mm in width. The heterostructure growths can be grown on different chips with different channel lengths as well. Given a stable growth of single-layer MoS2 on SiC with high coverage, the M0S2 IS typically able to successfully grow within the graphene channels.

[0041] A sample can be coated with polypropylene carbonate (PPC). The Si/SiC substrate can be etched by 1M KOH solution at 90°C. The film supported by the PPC can be rinsed in deionized water three times, 10 minutes for each time, and transferred to a QUANTIFOIL holey carbon TEM grid, for example. Afterwards, the sample can be baked in a vacuum (e.g., 10^"7 Torr) at 350°C for 5 hours to remove the PPC. The sample can be baked again in an ultrahigh vacuum bake-out system for 8 hours at 130°C to further clean polymer residue before loading into STEM, for example.

[0042] For the fabrication of field-effect transistors, Pd/Au (10/80 nm) contacts on the graphene for current injection can be defined by electron-beam lithography, followed by electron beam evaporation. An atomic layer deposition (ALD) of 20 nm ZrC can be used for the top-gate dielectric, and afterwards an additional top-gate electrode (Pd/Au) can be defined on top of the M0S2 channel.

[0043] Having described and illustrated the principles of the invention with reference to illustrated embodiments, it will be recognized that the illustrated embodiments may be modified in arrangement and detail without departing from such principles, and may be combined in any desired manner. And although the foregoing discussion has focused on particular embodiments, other configurations are contemplated.

[0044] Consequently, in view of the wide variety of permutations to the embodiments that are described herein, this detailed description and accompanying material is intended to be illustrative only, and should not be taken as limiting the scope of the invention. What is claimed as the invention, therefore, is all such modifications as may come within the scope and spirit of the following claims and equivalents thereto.

Claims

What is claimed is:

1. A method, comprising:

providing an insulating substrate;

etching graphene on the insulating substrate with exposed patterns;

causing molybdenum disulfide to nucleate at edges of the graphene and within open areas; and

causing the molybdenum disulfide to form a thicker overlap junction with the graphene at the edges.

2. The method of claim 1, wherein the insulating substrate includes silica.

3. The method of claim 1, further comprising forming a transistor with two- dimensional crystals from the graphene and the molybdenum disulfide.

4. The method of claim 3, further comprising forming a circuit that includes the transistor.

5. The method of claim 4, wherein the circuit is an inverter circuit.

6. The method of claim 5, further comprising using two n-type transistors to create the inverter circuit.

7. The method of claim 1, wherein the open areas include a plurality of channels.

8. The method of claim 7, further comprising the molybdenum disulfide completely filling the channels.

9. The method of claim 7, further comprising using photolithography to define a variety of channel lengths corresponding to the plurality of channels.

10. The method of claim 1, wherein the graphene includes wafer-scale wet- transferred graphene.

11. The method of claim 1, wherein the etching includes oxygen plasma etching.

12. The method of claim 1, wherein causing the molybdenum disulfide to nucleate includes using chemical vapor deposition (CVD) to grow a layer of the molybdenum disulfide on the substrate.

13. An electrical component, comprising:

an insulating substrate;

graphene etched on the insulating substrate with exposed patterns; and

molybdenum disulfide (M0S2) nucleated at edges of the graphene and within open areas and forming a thicker overlap junction with the graphene at the edges.

14. The electrical component of claim 13, wherein the electrical component is a transistor.

15. The electrical component of claim 13, wherein the electrical component is an inverter circuit.

16. The electrical component of claim 15, wherein the inverter circuit includes two n-type transistors.

17. The electrical component of claim 13, wherein the insulating substrate includes silica.

18. The electrical component of claim 13, further comprising two-dimensional crystals.

19. The electrical component of claim 13, wherein the graphene includes wafer- scale wet-transferred graphene.

20. The electrical component of claim 13, wherein the open areas include a plurality of channels.

21. The electrical component of claim 13, further comprising two-dimensional graphene-MoS2-graphene heteroj unctions.