WO2018004648A1 - Appareils, systèmes et procédés associés à une cellule magnétoélectrique comprenant un nanocomposite magnétoélectrique - Google Patents

Appareils, systèmes et procédés associés à une cellule magnétoélectrique comprenant un nanocomposite magnétoélectrique Download PDF

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Publication number
WO2018004648A1
WO2018004648A1 PCT/US2016/040680 US2016040680W WO2018004648A1 WO 2018004648 A1 WO2018004648 A1 WO 2018004648A1 US 2016040680 W US2016040680 W US 2016040680W WO 2018004648 A1 WO2018004648 A1 WO 2018004648A1
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layer
magnetoelectric
metal
coupled
nanocomposite
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PCT/US2016/040680
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English (en)
Inventor
Sasikanth Manipatruni
Dmitri E. Nikonov
Ian A. Young
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Intel Corporation
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Priority to PCT/US2016/040680 priority Critical patent/WO2018004648A1/fr
Publication of WO2018004648A1 publication Critical patent/WO2018004648A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Magnetic active materials

Definitions

  • Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to apparatuses, systems, and methods associated with a magnetoelectric cell that includes a magnetoelectric nanocomposite.
  • Magnetoelectric cells such as cells including magnetic tunnel junctions (MTJs) are used in magnetic memory (e.g., magnetic random access memory (MRAM) and logic applications. Current is passed through the magnetoelectric cell, causing spin-transfer torque to switch the magnetization of a free magnet layer of the cell. This switching process is relatively slow (e.g., over 10 nanoseconds (ns)) and requires relatively high energy (e.g., greater them 100 femtojouies (fJ)).
  • MRAM magnetic random access memory
  • fJ femtojouies
  • Figure 1 A schematically illustrates a perspective view of a magnetoelectric ceil in accordance with some embodiments.
  • Figure 1 B schematically illustrates a top cross-sectional view of the magnetoelectric cell of Figure 1 A in a plane of the free magnet layer, in accordance with some embodiments.
  • Figure 2 schematically illustrates a magnetic memory cell, in accordance with some embodiments.
  • Figure 3 schematically illustrates a memory array including a plurality of the magnetic memory ceils of Figure 2, in accordance with some embodiments.
  • FIG. 4 schematically illustrates another magnetic memory ceil, in accordance with some embodiments.
  • FIGS SA-SC schematically illustrate perspective views of magnetoeiectric nanocomposite structures having different geometries, in accordance with some embodiments.
  • Figures 6A and 6B illustrate a side cross-sectional view and a top view, respectively, of an elongate portion of ferromagnetic material that may be included in the magnetoeiectric nanocomposite structure of Figure 5A, in accordance with some embodiments, Figures 6A and 6B further showing the crystalline structure of the elongate portion of ferromagnetic material.
  • Figure 7 is a flow diagram illustrating a process for fabricating a magnetoeiectric cell, in accordance with some embodiments.
  • Figure 8 schematically illustrates an example system that may include an IC device as described herein, in accordance with some embodiments.
  • a magnetoeiectric ceil may include a magnetic tunnel junction that includes a fixed magnet layer and a free magnet layer.
  • the magnetoeiectric ceil may further include a
  • magnetoeiectric nanocomposite layer e.g., between the magnetoeiectric nanocomposite layer and the free magnet layer.
  • nanocomposite layer may include a ferromagnetic material and a ferroelectric material.
  • the metal layer may include a heavy metal, such as tantalum, tungsten, or platinum.
  • a voltage may be applied to the magnetoeiectric nanocomposite layer and a current may be passed through the metal layer.
  • the voltage applied to the magnetoeiectric nanocomposite may change the magnetic anisotropy of the free magnet layer by 90 degrees (e.g., from in-plane to out-of-plane).
  • the current passed through the metal layer may apply spin Hall torque to the free magnet layer to force the free magnet layer to go to the parallel state (e.g., low resistance state) or the anti-parallel state (e.g., high resistance state) when the voltage is removed.
  • the state to which the magnetoelectric ceil is programmed may be based on a polarity/direction of the current through the metal layer.
  • the magnetoelectric ceil and associated switching technique may consume significantly less energy than prior magnetoelectric cells and switching
  • Embodiments also include magnetic memory cells and memory arrays that include the magnetoelectric cells described herein.
  • phrase “A and/or B” means (A), (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • Coupled may mean one or more of the following. “Coupled” may mean thai two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.
  • directly coupled may mean that two or more elements are in direct contact.
  • the phrase "a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.
  • direct contact e.g., direct physical and/or electrical contact
  • indirect contact e.g., having one or more other features between the first feature and the second feature
  • circuitry may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
  • ASIC Application Specific Integrated Circuit
  • FIG. 1 A illustrates a magnetoelectric cell 100 (hereinafter "ceil 100") in accordance with various embodiments.
  • the cell 100 may include a stack of layers coupled between a first electrode 102 and a second electrode 104.
  • ceil 100 may include a free magnet layer 106 and a fixed magnet layer 108.
  • a dielectric layer 1 10 may be disposed between the free magnetic layer 106 and the fixed magnetic layer 108.
  • the free magnet layer 108, fixed magnet layer 108, and dielectric layer 1 10 may form a magnetic funnel junction (MTJ).
  • the free magnet layer 106 and fixed magnet layer 108 may be formed of a ferromagnetic material, such as a cobalt iron boron alloy (CoFeB).
  • the dielectric layer 1 10 may be an oxide or other suitable dielectric material. For example, in some
  • the dielectric layer 1 10 may be magnesium oxide (MgO).
  • the magnetization of the fixed magnet layer is the magnetization of the fixed magnet layer
  • the magnetization of the free magnet layer 106 may be switched between a parallel state and an anti-parallel state, as further discussed below.
  • the magnetization (e.g., magnetic moment) of the free magnet layer 106 may be oriented in a first direction (e.g. , a first horizontal direction in a plane of the free magnet layer 106) parallel to the magnetization of the fixed magnet layer 108.
  • the magnetization of the free magnet layer 106 may be oriented in a second direction (e.g., a second horizontal direction in the plane of the free magnet layer 106) that is opposite the first direction and anti-parallel to the magnetization of the fixed magnet layer.
  • the ceil 100 has a higher resistance between the electrodes 102 and 104 in the anti-parallel state than in the parallel state, thus enabling the state of the cell 100 to be read (e.g., using a sense amplifier).
  • This property of the ceil 100 may enable the cell 100 to be used as a memory cell, e.g., as shown in Figures 2 and 3 and further discussed below, in other embodiments, the ceil 100 may be used in other applications, such in logic circuitry.
  • the first direction and second direction may be along a first planar axis (e.g. , easy axis or long axis) within a plane of the free magnet layer 106.
  • first direction may be substantially into the page as shown in Figure 1 A
  • second direction may be substantially out of the page as shown in Figure 1 A
  • the first and second directions may be along a first planar axis (e.g., easy axis) within the plane of the free magnet layer.
  • a first dimension of the free magnet layer along the first planar axis may be greater than a second dimension of the free magnet layer along a second planar axis that is perpendicular to the first planar axis within the plane of the free magnet layer.
  • the first planar axis may be referred to as the easy axis or long axis
  • the second planar axis may be referred to as the hard axis or short axis. This relationship may make the two stable magnetization states of the free magnet layer be aligned on the first planar axis (e.g., in the first direction or the second direction).
  • Figure 1 B illustrates a top cross-sectional view of the ceil 100 in a plane of the free magnet layer 106.
  • the free magnet layer 106 may have an elliptical cross-sectional shape, as shown. In other embodiments, the free magnet layer 106 may have a different cross-sectional shape, such as rectangular.
  • the free magnet layer 106 may have a first planar axis 124 and a second planar axis 126.
  • the first dimension of the free magnet layer 106 along the first planar axis 124 may be longer than the second dimension of the free magnet layer 106 along the second planar axis 126.
  • the first and second directions may be along the first planar axis 124 in opposite directions (e.g., down and up, respectively, as shown in Figure 1 B).
  • the cell 100 may include an
  • the antiferromagnetic (AFM) layer 1 12 coupled to the fixed magnet layer 108 (e.g., disposed between the fixed magnet layer 108 and the first electrode 102) to enforce the fixed magnetization of the fixed magnet layer 108.
  • the AFM layer 1 12 may be formed of an antiferromagnetic material, such as IrMn.
  • the cell 100 may include one or more additional layers disposed between the AFM layer 1 12 and the fixed magnet layer 108.
  • a cobalt iron (CoFe) layer 1 14 and a ruthenium (Ru) layer 1 18 may be disposed between the AFM layer 1 12 and the fixed magnet layer 108.
  • the CoFe layer 1 14 and the Ru layer 1 16 may force the AFM layer 1 12 and fixed magnet layer 108 to have opposite magnetizations, in order to prevent stray magnetic fields.
  • Other materials and/or layers may be used in other embodiments.
  • the cell 100 may further include a magnetoelectric nanocomposite layer 1 18 disposed between the free magnet layer 106 and the second electrode 104.
  • the cell 100 may further include a metal layer 120 disposed between the nanocomposite layer 1 18 and the free magnet layer 106.
  • the nanocomposite layer 1 18 and metal layer 120 may enable the magnetization of the free magnet layer 106 to be switched in a unique manner that uses significantly less energy and/or time than prior magnetoelectric cells and switching techniques.
  • the nanocomposite layer 1 18 may include a ferromagnetic material 1 19 and a ferroelectric material 121 .
  • the ferromagnetic material 1 19 may be, for example, CoFe 2 0 4 (CFO), NiFe 2 0 4 (NFO), Fe 3 0 4 , La 1-x Sr x Mn0 3 (LSMO) and/or another suitable ferromagnetic material.
  • the ferroelectric material 121 may be, for example, BaTi0 3 (BTO), PbTi0 3 (PTO), Pb(Zr,Ti)0 3 (PZT), BiFe0 3 (BFO), and/or another suitable ferroelectric material.
  • the ferromagnetic material 1 19 and ferroelectric material 121 may have any suitable geometry within the
  • nanocomposite layer 1 18.
  • Figures 5A-5C illustrate some potential geometries of nanocomposite layers that may be used for the nanocomposite layer 1 18, in accordance with various embodiments.
  • the metal layer 120 may be any suitable metal that can provide a spin Hall torque when current is passed through the metal layer 120.
  • the metal layer 120 may include tantalum (Ta), tungsten (W), or platinum (Pt).
  • the ceil 100 may further include one or more metal portions 122a-b coupled to the metal layer 120 to facilitate current being passed through the metal layer 120,
  • the metal portions 122a-b may also be referred to as metal contacts 122a-b in some embodiments.
  • the metal portions 122a-b may be formed of a different metal than the metal layer 120, such as a metal that is more conductive than the metal layer 120,
  • the metal portions 122a-b may be formed of copper.
  • the metal portions 122a-b may be adjacent the metal layer 120 in a direction along the second planar axis of the free magnet layer 108.
  • the current flowing through the metal layer 120 may be perpendicular to the first planar axis on which the stable magnetization states of the free magnet layer 106 are aligned.
  • a voltage may be applied to the nanocomposite layer 1 18 and a current may be passed through the metal layer 120, in various embodiments, when a voltage is applied to the nanocomposite layer 1 18, the polarization in the ferroelectric material 121 may be switched.
  • the charge density may change at the interface between the ferromagnetic material 1 19 and the ferroelectric material 121 .
  • the change in charge density may cause a change in the magnetic anisotropy (e.g., the direction of the magnetic moment) of the nanocomposite layer 1 18,
  • the anisotropy of the nanocomposite layer may change by 90 degrees.
  • the magnetic moment of the nanocomposite layer 1 18 may change from being in the first or second horizontal direction (e.g., info the page or out of the page) to being in a vertical direction (e.g., up or down).
  • the free magnet layer 106 may be magnetically locked to the nanocomposite layer 1 18 (e.g., by exchange effect and/or dipole fields). Accordingly, the magnetic moment of the free magnet layer 106 may also change to being in a vertical direction (e.g., up or down).
  • the nanocomposite layer 1 18 may be a piezoelectric that applies a strain to the free magnet layer 106 (e.g., via the metal layer 120) in response to the applied voltage.
  • the strain may cause the anisotropy of the free magnet layer 106 to change.
  • the current passed through the metal layer may be a piezoelectric that applies a strain to the free magnet layer 106 (e.g., via the metal layer 120) in response to the applied voltage.
  • the strain may cause the anisotropy of the free magnet layer 106 to change.
  • the spin Hall effect may cause the electrons having spins that point into the page to gather at a top region of the metal layer 120 (e.g., at an interface between the metal layer 120 and the free magnet layer 106) and the electrons having spins that point out of the page to gather at a bottom region of the metal layer 120 (e.g., at an interface between the metal layer 120 and the nanocomposite layer 1 18).
  • the resulting spin Hall torque generated by the metal layer 120 may encourage the magnetization of the free magnet layer 106 to stabilize to the first horizontal direction (e.g., into the page) when the voltage is removed from the nanocomposite layer 1 18.
  • the spin Hail effect may cause the electrons having spins that point out of the page to gather at a top region of the metal layer 120 (e.g., at an interface between the metal layer 120 and the free magnet layer 106) and the electrons having spins that point into the page to gather at a bottom region of the metal layer 120 (e.g., at an interface between the metal layer 120 and the nanocomposite layer 1 18).
  • the resulting spin Hall torque generated by the metal layer 120 may encourage the magnetization of the free magnet layer 106 to stabilize to the second horizontal direction (e.g., out of the page) when the voltage is removed from the nanocomposite layer 1 18.
  • the cell 100 may be set to the parallel state or the anti- parallel state based on the direction of the current passed through the metal layer 120.
  • Figure 2 illustrates a memory cell 200 in accordance with various embodiments.
  • the memory cell 200 may include a ceil 100 and bitlines 230, 232, and 234.
  • the bitlines 230 and 232 may be referred to as write bitlines 230 and 232
  • the bitline 234 may be referred to as read bifiine 234.
  • the cell 100 may include a metal portion 122a but may not include a metal portion 122b as shown in Figure 1A.
  • nanocomposite layer 1 18, metal layer 120, and electrode 104 are shown in Figure 1 A as having a diameter that is greater than a diameter of other layers of the cell 100 (e.g., the free magnet layer 106, fixed magnet layer 108, etc.), the nanocomposite layer 1 18, metal layer 120, and electrode 104 are shown in Figure 2 as having substantially the same diameter as other layers of the ceil 100.
  • the bitline 230 of memory cell 200 may be coupled to the electrode 104 (e.g., by a selector transistor 238 coupled between the bitline 230 and the electrode 104).
  • a gate terminal of the selector transistor 236 may be coupled to a wordline 238 to selectively pass a voltage at the bitline 230 to the electrode 104.
  • the bitline 232 may be coupled to the metal portion 122a (e.g., by a selector transistor 240 coupled between the bitline 232 and the metal portion 122a).
  • a gate terminal of the selector transistor 240 may be coupled to a wordline 242 to selectively pass a voltage at the bitline 232 to the metal portion 122a when the wordline 242 is active.
  • the bitline 234 may be coupled to the electrode 102.
  • the wordlines 238 and 242 may be active to turn the selector transistors 236 and 240 on.
  • the wordlines 238 and 242 may be coupled to one another to receive a same wordline signal. In other embodiments, the wordlines 238 and 242 may receive separate wordline signals.
  • a voltage difference may be applied between the bitline 230 and the bitline 232, thereby applying a voltage to the nanocomposite layer 1 18 and passing a current through the metal layer 120.
  • the memory cell 200 may be programmed to the anti-parallel state or the parallel state based on the polarity of the voltage difference between the bitline 230 and the bitline 232.
  • the bitline 230 may be set to a ground voltage (e.g., 0 Volts) and the bitline 232 may be set to a positive voltage.
  • a second logic value e.g., logic 1
  • the bitline 232 may be set to a ground voltage (e.g., 0 Volts) and the bitline 230 may be set to a positive voltage.
  • the amount of energy consumed by the write process may be significantly less for the memory ceil 200 than for prior magnetic memory cells.
  • the current used by the write process may be lower, and the duration of the write current may also be lower than that used by write processes for prior magnetic memory ceils. Accordingly, the memory ceil 200 may consume significantly less power than prior magnetic memory cells.
  • the wordline 242 may be active to turn on the selector transistor 240.
  • a voltage difference may be placed between the bitline 232 and the bitline 234.
  • a sense amplifier (not shown) may be coupled to the memory cell 200 to read the logic value stored by the memory cell 200 (e.g., based on the current through the cell 100).
  • Figure 3 illustrates a memory array 300 that includes a plurality of memory cells 200, in accordance with various embodiments.
  • the memory ceils 200 are coupled to common bitiines 330, 332, and 334, and separate wordiines 338 and 342.
  • the memory array 300 may include any suitable number and/or arrangement of the memory ceils 200.
  • the memory array 300 may include a two-dimensional or three-dimensional arrangement of memory cells 200.
  • FIG. 4 illustrates another memory cell 400, in accordance with various embodiments.
  • Memory ceil 400 includes a ceil 100 and bitiines 430, 432, 434, and 435. Accordingly, memory cell 400 includes four bitiines, while memory cell 200 includes three bitiines. For ease of understanding, not all layers of the cell 100 are labeled in Figure 4.
  • Bitline 430 is coupled to the electrode 104 by a selector transistor 438.
  • Bitline 432 may be coupled to the metal portion 122a, and bitline 435 may be coupled to the metal portion 122b.
  • a current may be passed between the metal portions 122a and 122b through the metal layer 120 by applying either (i) a positive voltage on 432 and a voltage lower than 432 on 435 or (ii) a positive voltage on 435 and a voltage lower than 435 on 432. .
  • bitline 432 and bitline 430 may apply a positive voltage to the nanocomposite layer 1 18 for case (i) and a negative voltage to the nanocomposite layer 1 18 for case (ii).
  • the nanocomposite layer 1 18 of the ceil is the nanocomposite layer 1 18 of the ceil
  • Figures 5A, 5B, and 5C illustrate magnetoelectric nanocomposite structures 500, 520, and 540, respectively, in accordance with various
  • the magnetoelectric nanocomposite structures 500, 520, and/or 540 may be used for the nanocomposite layer 1 18 of the cell 100.
  • magnetoelectric nanocomposite structure 500 may include a nanocomposite layer 502 on a substrate 504.
  • nanocomposite layer 502 includes ferromagnetic portions 508 in a three- dimensional matrix of ferroelectric material 508.
  • the ferromagnetic portions 508 may be referred to as "zero-dimensional" (OD) since the dimensions of the ferromagnetic portions 506 are relatively small in ail directions compared with the dimensions of the three-dimensional matrix of ferroelectric material 508.
  • the magnetoelectnc nanocomposite structure 500 may be referred to as having a "0-3" geometric phase.
  • the magnetoelectnc nanocomposite structure 520 may include a nanocomposite layer 522 on a substrate 524.
  • the nanocomposite layer 522 may include layers 526 and 528 of ferroelectric material interspersed with layers 530 and 532 of ferromagnetic material, it will be appreciated that the nanocomposite layer 522 may include any suitable number of layers of the ferroelectric material and/or ferromagnetic material.
  • the layers 526, 528, 530, and 534 may be referred to as two-dimensional. Accordingly, the magnetoelectnc nanocomposite structure 520 may be referred to as having a "2-2" geometric phase.
  • the magnetoelectnc nanocomposite structure 540 may include a nanocomposite layer 542 on a substrate 544.
  • the nanocomposite layer 542 may include elongate portions of ferromagnetic material 546 in a three-dimensional matrix of ferroelectric material 548.
  • the elongate portions of ferromagnetic material 546 may be referred to as "one-dimensional," since they are significantly longer in one dimension than in the other two dimensions. Accordingly, the magnetoeiectric nanocomposite structure 540 may be referred to as having a "1 -3" geometric phase.
  • the elongate portions of ferromagnetic material 546 may have any suitable cross-sectional shape, such as circular or polygonal.
  • Table 1 illustrates values of a direct magnetoeiectric coefficient (a d ) or a converse magnetoeiectric coefficient (a c ) for some example magnetoeiectric nanocomposite layers (e.g., combinations of ferromagnetic material and ferroelectric material and corresponding phases), in accordance with various embodiments.
  • Phase Magnetoelectric cs d fio mif!svolts a c fin Oersted naoocomposste per Oersted centimeter per centimeter volt ((Oe x fmV/fcm x Oe)) em)/V))
  • Figures 6A and 6B illustrate a side view and a top view of an elongate portion 600 of ferromagnetic material, in accordance with various embodiments.
  • the elongate portion 600 may be, for example, CoFe 2 0 4 (CFO).
  • the elongate portion 600 may be used for the elongate portions of ferromagnetic material 546 of nanocomposite structure 540.
  • Figures 6A and 6B show the crystalline structure of the elongate portion 600 in various dimensions and regions of the elongate portion 800.
  • FIG. 7 is a flow diagram illustrating a process 700 that may be used to form a magnetoeiectric cell (e.g., magnetoelectric ceil 100) as described herein, in accordance with various embodiments.
  • a magnetoeiectric cell e.g., magnetoelectric ceil 100
  • the process 700 may include forming a magnetoelectric nanocomposite layer (e.g., magnetoelectric nanocomposite layer 1 18) including a ferroelectric material and a ferromagnetic material.
  • the magnetoelectric nanocomposite layer may be formed, for example, using molecular beam epitaxy or pulsed laser deposition processing fools.
  • the process 700 may include forming a metal layer (e.g., metal layer 120) on the magnetoeiectric nanocomposite layer.
  • a metal layer e.g., metal layer 120
  • the process 700 may include forming a free magnet layer (e.g., free magnet layer 106) on the metal layer.
  • the process 700 may include forming a dielectric (e.g. , dielectric layer 1 10) on the free magnet layer.
  • the process 700 may include forming a fixed magnet layer (e.g. , fixed magnet layer 708) on the dielectric.
  • a fixed magnet layer e.g. , fixed magnet layer 708
  • FIG. 8 illustrates an example computing device 800 that may employ the apparatuses and/or methods described herein (e.g. , ceil 100, memory ceil 200, memory array 300, memory cell 400, and/or a magnetoeiectric cell fabricated by the process 700), in accordance with various embodiments.
  • computing device 800 may include a number of components, such as one or more processor(s) 804 (one shown) and at least one communication chip 806. I n various embodiments, the one or more processor(s) 804 each may include one or more processor cores, in various embodiments, the at least one
  • communication chip 806 may be physically and electrically coupled to the one or more processor(s) 804. in further implementations, the communication chip 806 may be part of the one or more processor(s) 804.
  • computing device 800 may include printed circuit board (PCB) 802.
  • PCB printed circuit board
  • the one or more processor(s) 804 and communication chip 806 may be disposed thereon. In alternate embodiments, the various components may be coupled without the employment of PCB 802.
  • computing device 800 may include other components that may or may not be physically and electrically coupled to the PCB 802. These other components include, but are not limited to, memory controller 805, volatile memory (e.g. , dynamic random access memory (DRAM) 808), non-volatile memory such as read only memory (ROM) 810, flash memory 812, storage device 81 1 (e.g.
  • volatile memory e.g. , dynamic random access memory (DRAM) 808
  • non-volatile memory such as read only memory (ROM) 810
  • flash memory 812 e.g.
  • the processor 804 may be integrated on the same die with other components (e.g. , communication chip 806, memory controller 805, flash 812, DRAM 808, and/or graphics processor 818) to form a System on Chip (SoC).
  • SoC System on Chip
  • the one or more processor(s) 804, flash memory 812, and/or storage device 81 1 may include associated firmware (not shown) storing programming instructions configured to enable computing device 800, in response to execution of the programming instructions by one or more processor(s) 804, to practice all or selected aspects of the methods described herein. In various embodiments, these aspects may additionally or alternatively be implemented using hardware separate from the one or more processor(s) 804, flash memory 812, or storage device 81 1 .
  • one or more components of the computing device 800 may include the magnetoelectric ceil 100, memory cell 200, memory array 300, memory ceil 400, and/or a magnetoelectric cell fabricated by the process 700 described herein.
  • the magnetoelectric cell 100, memory ceil 200, memory array 300, memory cell 400, and/or a magnetoelectric cell fabricated by the process 700 may be included in one or more of the DRAM 808, flash memory 812, ROM 810, and/or storage device 81 1 .
  • the memory controller 805 may control the write process and/or read process as described herein.
  • the memory controller 805 may apply voltages to respective bitlines and/or wordiines of the magnetic memory array as described herein.
  • the communication chips 808 may enable wired and/or wireless communications for the transfer of data to and from the computing device 800.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic
  • the communication chip 806 may implement any of a number of wireless standards or protocols, including but not limited to IEEE 702.20, Long Term Evolution (LTE), LTE Advanced (LTE-A), General Packet Radio Service (GPRS), Evolution Data Optimized (Ev-DO), Evolved High Speed Packet Access (HSPA+), Evolved High Speed Downlink Packet Access (HSDPA+), Evolved High Speed Uplink Packet Access (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Worldwide Interoperability for Microwave Access (WiMAX), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 800 may include a plurality
  • communication chip 806 may be dedicated to longer range wireless
  • communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the computing device 800 may be a laptop, a netbook, a notebook, an uitrabook, a smartphone, a computing tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an
  • the computing device 800 may be any other electronic device that processes data.
  • Example 1 is a magnetoelectric ceil comprising: a fixed magnet layer; a free magnet layer; a dielectric coupled between the fixed magnet layer and the free magnet layer; a magnetoelectric nanocomposite layer; and a metal layer coupled between the magnetoelectric nanocomposite layer and the free magnet layer.
  • Example 2 is the magnetoelectric ceil of Example 1 , wherein the magnetoelectric nanocomposite includes a ferroelectric material and a
  • Example 3 is the magnetoelectric ceil of Example 2, wherein the ferromagnetic material includes CoFe204 (CFO), NiFe204 (NFO), Fe304, or La1 -xSrxMn03 (LSMO).
  • Example 4 is the magnetoelectric cell of Example 3, wherein the ferroelectric material includes BaTiOS (BTO), PbTiOS (PTO), Pb(Zr,Ti)03 (PZT), or BiFeOS (BFO).
  • Example 5 is the magnetoelectric ceil of Example 2, wherein the magnetoelectric nanocomposite layer includes portions of the ferromagnetic material in a three-dimensional matrix of the ferroelectric material.
  • Example 8 is the magnetoelectric ceil of Example 2, wherein the magnetoelectric nanocomposite layer includes layers of the ferromagnetic material interspersed with layers of the ferroelectric material.
  • Example 7 is the magnetoelectric ceil of Example 2, wherein the magnetoelectric nanocomposite layer includes elongate portions of the
  • Example 8 is the magnetoelectric ceil of Example 1 , wherein the metal layer includes tantalum, tungsten, or platinum.
  • Example 9 is the magnetoelectric ceil of any one of Examples 1 to 8, further comprising a metal portion coupled to the metal layer to pass current through the metal layer, wherein the metal portion includes a different metal than the metal layer.
  • Example 10 is the magnetoelectric cell of Example 9, wherein a first dimension of the free magnet layer along a first planar axis within a plane of the free magnet layer is greater than a second dimension of the free magnet layer along a second planar axis within the plane of the free magnet layer, wherein the second planar axis is perpendicular to the first planar axis, and wherein the metal portion is coupled to the metal layer adjacent to the metal layer in a direction of the second planar axis.
  • Example 1 1 is the magnetoelectric cell of Example 9, wherein the free magnet layer is to be placed in a parallel state or an anti-parallel state based on a direction of the current passed through the metal layer.
  • Example 12 is the magnetoelectric cell of Example 1 1 , wherein the magnetoelectric nanocomposite layer is coupled to a first write bitline, wherein the metal portion is coupled to a second write bitline, and wherein the current is to pass between the first write bitline and the second write bitline.
  • Example 13 is the magnetoelectric cell of Example 12, wherein the first write bitline is coupled to a first end of the magnetoelectric cell, and wherein the magnetoelectnc cell further comprises a read bitline coupled to a second end of the magnetoelectnc cell that is opposite the first end.
  • Example 14 is the magnetoelectnc cell of Example 1 1 , wherein the metal portion is a first metal portion coupled to a first side of the metal layer, wherein the magnetoelectnc cell further includes a second metal portion coupled to a second side of the metal layer opposite the first side, wherein the
  • magnetoelectnc nanocomposite layer is coupled to a first write bitline, wherein the first metal portion is coupled to a second write bitline, wherein the second metal portion is coupled to a third write bitline, and wherein the current is to pass between the second write bitline and the third write bitline.
  • Example 15 is a method for forming a magnetoelectnc cell, the method comprising: forming a magnetoeiectric nanocomposite layer including a ferroelectric material and a ferromagnetic material; forming a metal layer on the magnetoeiectric nanocomposite layer; forming a free magnet layer on the metal layer; forming a dielectric on the free magnet layer; and forming a fixed magnet layer on the dielectric.
  • Example 18 is the method of Example 15, wherein the ferromagnetic material includes CoFe204 (CFO), NiFe204 (NFO), Fe304, or La1 ⁇ xSrxMn03 (LSMO).
  • CFO CoFe204
  • NFO NiFe204
  • LSMO La1 ⁇ xSrxMn03
  • Example 17 is the method of Example 15, wherein the ferroelectric material includes BaTi03 (BTO), PbTi03 (PTO), Pb(Zr,Ti)03 (PZT), or BiFeOS (BFO).
  • the ferroelectric material includes BaTi03 (BTO), PbTi03 (PTO), Pb(Zr,Ti)03 (PZT), or BiFeOS (BFO).
  • Example 18 is the method of Example 15, wherein the magnetoeiectric nanocomposite layer includes portions of the ferromagnetic material in a three-dimensional matrix of the ferroelectric material.
  • Example 19 is the method of Example 15, wherein the magnetoeiectric nanocomposite layer includes layers of the ferromagnetic material interspersed with layers of the ferroelectric material.
  • Example 20 is the method of Example 15, wherein the magnetoeiectric nanocomposite layer includes elongate portions of the
  • Example 21 is the method of Example 15, wherein the metal layer includes tantalum, tungsten, or platinum.
  • Example 22 is the method of any one of Examples 15 to 21 , further comprising forming a metal portion adjacent to the metal layer and coupled to the metal layer to pass current through the metal layer, wherein the metal portion includes a different metal than the metal layer.
  • Example 23 is the method of Example 22, further comprising forming a first bitline coupled to the magnetoelectric nanocomposite layer, and forming a second bitline coupled to the meta! portion.
  • Example 24 is a system comprising: a memory controller; and a memory array coupled to the memory controller.
  • the memory array includes a plurality of magnetoelectric memory cells, wherein individual magnetoelectric memory cells include: a magnetic tunnel junction including a fixed magnet layer and a free magnet layer; a metal layer coupled to the free magnet layer; a magnetoelectric nanocomposite layer coupled to the metal layer,
  • the magnetoelectric nanocomposite layer including a ferroelectric material and a ferromagnetic material; and a metal contact adjacent to the metal layer and coupled to the metal layer, wherein the metal contact includes a different metal than the metal layer.
  • Example 25 is the system of Example 24, wherein the metal layer includes tantalum, tungsten, or platinum, and wherein the metal contact has a greater conductivity than the metal layer.
  • Example 28 is the system of Example 24, wherein the memory array further comprises a first write bitline coupled to the magnetoelectric
  • nanocomposite layer and a second write bitline coupled to the metal contact wherein the memory controller is to cause a voltage difference between the first write bitline and a second write bitline during a write operation to write a bit to the magnetoelectric memory ceil.
  • Example 27 is the system of Example 24, wherein the metal contact is a first metal contact, wherein the individual magnetoelectric memory cells further include a second metal contact coupled to the metal layer, wherein the memory array includes: a first write bitline coupled to the magnetoelectric nanocomposite; a second write bitline coupled to the first metal contact; and a third write bitline coupled to the second metal contact.
  • Example 28 is the system of Example 27, wherein, during a write operation, the memory controller is to cause a voltage to be applied to the magnetoelectric nanocomposiie via the first write bitline and a current to be passed between the second write bitline and the third write bitline through the metal layer, wherein a logic value written to the memory cell by the write operation is based on a direction of the current through the metal layer.
  • Example 29 is the system of any one of Examples 24 to 28, further comprising a processor coupled to the memory controller.
  • Example 30 is the system of Example 29, further comprising a display coupled to the processor.
  • Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the "and” may be “and/or”).
  • some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments.
  • some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

Selon divers modes de réalisation, la présente invention concerne des appareils, des procédés et des systèmes associés à des cellules magnétoélectriques. Une cellule magnétoélectrique peut comprendre une jonction tunnel magnétique qui comprend une couche magnétique fixe et une couche magnétique libre. La cellule magnétoélectrique peut en outre comprendre une couche de nanocomposite magnétoélectrique et une couche métallique couplée entre la couche de nanocomposite magnétoélectrique. Pour programmer la cellule magnétoélectrique à un état parallèle ou à un état antiparallèle, on peut appliquer une tension à la couche de nanocomposite magnétoélectrique et faire circuler un courant à travers la couche métallique. Des modes de réalisation concernent également des cellules de mémoire magnétique et des matrices de mémoire qui comprennent les cellules magnétoélectriques décrites ci-dessus. D'autres modes de réalisation peuvent être décrits et/ou revendiqués.
PCT/US2016/040680 2016-07-01 2016-07-01 Appareils, systèmes et procédés associés à une cellule magnétoélectrique comprenant un nanocomposite magnétoélectrique WO2018004648A1 (fr)

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