WO2018004616A1 - Barrière de texture cristalline dans la conception d'un empilement formant jonction tunnel magnétique perpendiculaire (pmtj) - Google Patents

Barrière de texture cristalline dans la conception d'un empilement formant jonction tunnel magnétique perpendiculaire (pmtj) Download PDF

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Publication number
WO2018004616A1
WO2018004616A1 PCT/US2016/040479 US2016040479W WO2018004616A1 WO 2018004616 A1 WO2018004616 A1 WO 2018004616A1 US 2016040479 W US2016040479 W US 2016040479W WO 2018004616 A1 WO2018004616 A1 WO 2018004616A1
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Prior art keywords
region
mtj
crystal texture
texture region
forming
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PCT/US2016/040479
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English (en)
Inventor
Charles C. Kuo
Anurag Chaudhry
Kaan OGUZ
Mark L. Doczy
Brian S. Doyle
Kevin P. O'brien
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Intel Corporation
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Priority to PCT/US2016/040479 priority Critical patent/WO2018004616A1/fr
Publication of WO2018004616A1 publication Critical patent/WO2018004616A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices

Definitions

  • Magnetic tunnel junction (MTJ) devices leverage quantum mechanical effects of placing a thin electrically insulating material between two ferromagnets. Specifically, in MTJ devices, electrons tunnel from one ferromagnet to the other through the electrically insulating material. A direction of polarization of at least one of the two
  • ferromagnets can be independently controlled. When the directions of polarization of the two ferromagnets are the same, an electrical resistance across the MTJ device is relatively low. When the directions of polarization of the two ferromagnets are different (e.g., opposite), the electrical resistance across the MTJ device is relatively high.
  • STT-RAM spin-transfer torque
  • STT-RAM STT random access memory
  • STT-MRAM STT random access memory
  • different states including a parallel state (in which the two ferromagnets are polarized in the same direction) and an antiparallel state (in which the two ferromagnets are polarized in opposite directions) can be set by applying different electrical currents.
  • the state can then be read by measuring the electrical resistance (e.g., by applying an electrical read current and measuring a resulting voltage drop) of the MTJ device.
  • the measured electrical resistance is relatively high, it can be determined that the MTJ device is in the antiparallel state. If the measured electrical resistance is relatively low, it can be determined that the MTJ device is in the parallel state.
  • Different logic levels e.g., logic levels "1" and "0" can be assigned to each of the parallel and antiparallel states, enabling digital information to be stored in arrays of MTJ devices.
  • FIG. 1 is a simplified cross-sectional view of an example MTJ device.
  • FIG. 2 is a simplified cross-sectional view of an MTJ device, according to some embodiments.
  • FIG. 3 is a simplified cross-sectional view of another MTJ device, according to some embodiments.
  • FIG. 4 is a simplified cross-sectional view of yet another MTJ device, according to some embodiments.
  • FIG. 5 is a simplified block diagram of a memory device, according to some embodiments.
  • FIG. 6 is a simplified flowchart illustrating a method of forming an MTJ device, according to some embodiments.
  • FIG. 7 illustrates an interposer that includes one or more embodiments discussed herein.
  • FIG. 8 illustrates a computing device, according to some embodiments.
  • MTJ devices Disclosed herein are MTJ devices, computing systems, and related methods that use crystal texture regions in the MTJ stack to mitigate crystal lattice mismatch within and avoid degraded device performance of MTJ devices.
  • various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. It will be apparent to one skilled in the art, however, that the disclosure may be practiced without the specific details. In other instances, well- known features are omitted or simplified in order not to obscure the illustrative implementations.
  • the terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate.
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure (e.g., silicon-on-glass (SOG), silicon-on- sapphire (SOS), etc.).
  • SOI silicon-on-insulator
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials.
  • One or more MTJ devices may be fabricated on or in a substrate.
  • the MTJ devices may be described as a stack of different functional regions. This geometric structure should not, however, be interpreted as limiting. As will be apparent to those skilled in the art, MTJ devices may be formed horizontally, radially, or otherwise, as well as vertically.
  • FIG. 1 is a simplified cross-sectional view of an example MTJ device 100.
  • the MTJ device 100 includes a stack 180 including an MTJ body 190 operably coupled between electrodes 110, 170.
  • the MTJ body 190 includes an oxide region 140 including an oxide material (e.g., magnesium oxide (MgO)) between a reference region 150 and a free region 130.
  • the reference region 150 and the free region 130 each include ferromagnets.
  • the free region 130 may include a cobalt iron barium (CoFeB) stack including a metallic insert between two CoFeB regions.
  • the reference region 150 may include CoFeB.
  • the electrodes 110, 170 include electrically conductive material (e.g., titanium, aluminum, copper, tungsten, polysilicon, alloys, etc.).
  • the electrodes 110, 170 are configured to conduct control currents l c through the MTJ body 190.
  • a direction of a magnetic polarization of the free region 130 may be controllable through application of the control currents l c through the MTJ body 190.
  • a read of a current state (e.g., a parallel state, an antiparallel state) of the MTJ body 190 may be determined through application of the control currents l c through the MTJ body 190.
  • the stack 180 includes a cap region 120 including a metal (e.g., MgO).
  • the cap region 120 is configured to improve operational stability of the MTJ device 100.
  • the stack 180 includes a synthetic antiferromagnet (SAF) region 160 including a magnet (e.g., layers of cobalt platinum).
  • SAF region 160 is also configured to improve operational stability of the MTJ device 100 by stabilizing a direction of polarization of the reference region 150.
  • Some of the various regions of the MTJ device 100 may include different crystal characteristics (e.g., crystallinity) from others of the regions of the MTJ device 100.
  • the SAF region 160 and the reference region 150 may have different crystallinities from each other (e.g., the SAF region 160 may have a crystal orientation of 1-1-1 and the reference region 150 may have a crystal orientation of 1-0-0).
  • a crystallinity mismatch may exist between the electrode 170 and the SAF region 160.
  • crystallinity mismatches may exist between the CAP region 120 and the free region 130, between the cap region 120 and the electrode 110, or a combination thereof. Such mismatches in crystallinity may result in degradation of performance of the MTJ device 100.
  • mismatches in crystallinity may cause some recrystallization in one or more of the regions of the MTJ device 100.
  • recrystallization of the reference region 150 may result in the reference region being physically weak, less stable, or a combination thereof. Instability of the reference region 150 may result in switching prematurely between operational states (e.g., the parallel and antiparallel states).
  • mismatch in crystallinity may result in recrystallization of the oxide region 140 (e.g., away from a 1-0-0 crystal orientation).
  • a tunnel magnetoresistance (TMR), switching currents, or combinations thereof may be affected adversely. Any crystallinity mismatch within the MTJ device 100 may cause a ripple effect through the MTJ device 100, potentially effecting crystallinity of regions that are displaced from the mismatched crystallinity interface.
  • MTJ devices including crystal texture regions configured to mitigate crystal lattice mismatches, decreasing device degradation due to the crystal lattice mismatches.
  • an MTJ device including an MTJ body.
  • the MTJ body includes a free region, a reference region, and an oxide region.
  • the free region includes a ferromagnetic material
  • the reference region includes a ferromagnetic material
  • the oxide region includes an oxide material between the free region and the reference region.
  • the MTJ device also includes an electrode including electrically conductive material and a crystal texture region between regions of different crystallinity within the MTJ device.
  • a method of forming an MTJ device includes forming an MTJ body including a free region, a reference region, and an oxide region between the free region and the reference region.
  • the method also includes forming at least one electrode including conductive material configured to conduct electrical current at least one of to or from the MTJ body.
  • the method further includes forming at least one crystal texture region between regions of the MTJ device having different crystal properties.
  • a computing device including a memory device configured to electrically store data.
  • the memory device includes at least one MTJ device including a pair of electrodes, an MTJ body including an oxide region between a reference region and a free region, the MTJ body between the pair of electrodes.
  • the MTJ device also includes at least one crystal texture region including a conductive amorphous material between regions of the MTJ device having different crystallinities.
  • FIG. 2 is a simplified cross-sectional view of an MTJ device 200, according to some embodiments.
  • the MTJ device 200 includes an MTJ stack 280 similar to the MTJ stack 180 of FIG. 1 except that the MTJ stack 280 includes a crystal texture region 202 including an inert, electrically conductive, amorphous material (e.g., amorphous carbon).
  • amorphous material e.g., amorphous carbon
  • electrically conductive refers to materials that have low electrical resistance.
  • the term "low electrical resistance" of a crystal texture region 202 refers to electrical resistances below about 100 ⁇ .
  • the amorphous material functions as a barrier for recrystallization between other regions of the MTJ device 200 that have different crystal properties (e.g., crystallinity) from each other during an annealing operation.
  • amorphous carbon may serve as a good crystal texture region 202 because amorphous carbon is relatively stable at annealing temperatures (e.g., around 400° C), and is inert and has low electrical resistance.
  • the crystal texture region 202 is at least about 1 Angstrom thick. In some embodiments, the crystal texture region 202 is less than or equal to about 10 Angstroms thick.
  • the MTJ device 200 includes the MTJ body 290 including a reference region 250, a free region 230, and an oxide region 240 between the reference region 250 and the free region 230, similar to the reference region 150, the oxide region 140, and the free region 130 discussed above with reference to FIG. 1.
  • the MTJ device 200 also includes electrodes 210, 270, similar to the electrodes 110, 170 of FIG. 1.
  • the MTJ device 200 further includes one or more of a cap region 220 and a SAF region 260, similar to the cap region 120 and the SAF region 160 of FIG. 1.
  • a crystal texture region or regions may be included between components of the MTJ stack 280 other than, or in addition to, between the SAF region 260 and the electrode 270 (as illustrated in FIG. 2). Such crystal regions may be included between any of the components shown in the MTJ stack 280 (e.g., between the electrode 210 and the CAP region 220, between the CAP region 220 and the free region 230, between reference region 250 and the SAF region 260, between the SAF region 260 and the electrode 270, etc., or combinations thereof).
  • FIGS. 3 and 4 illustrate two different examples. Other examples will be apparent to those of ordinary skill in the art in view of the disclosure.
  • a conductive amorphous material prevents recrystallization between regions of the MTJ device 200.
  • physical strength and stability of the reference region 2 may be improved.
  • recrystallization of the oxide region 240 may be avoided. Accordingly, stability and proper operation of the MTJ device 200 may be improved, as compared to the MTJ device 100 of FIG. 1.
  • FIG. 3 is a simplified cross-sectional view of another MTJ device 300, according to some embodiments.
  • the MTJ device 300 includes an MTJ stack 380 that is similar to the MTJ stack 280 of FIG. 2 except that the MTJ stack 380 includes a crystal texture region 302 between the SAF region 260 and the electrode 270 instead of the crystal texture region 202 between the cap region 220 and the electrode 210.
  • FIG. 4 is a simplified cross-sectional view of yet another MTJ device 400, according to some embodiments.
  • the MTJ device 400 includes an MTJ stack 480 that is similar to the MTJ stack 280 of FIG. 2 except that the MTJ stack 480 includes crystal texture regions 402 between the electrode 210 and the CAP region 220, between the free region 230 and the CAP region 220, between the reference region 250 and the SAF region 260, and between the SAF region 260 and the electrode 270.
  • FIG. 5 is a simplified block diagram of a memory device 500, according to some embodiments.
  • the memory device 500 includes memory control circuitry 510 operably coupled to an array of cells 520. At least one of the cells in the array of cells 520 includes an MTJ device 200, 300, 400 (FIGS. 2, 3, and 4) including at least one crystal texture region 202, 302, 402 (FIGS. 2, 3, and 4), as discussed above.
  • the memory control circuitry 510 is configured to provide control currents l c (e.g., read currents, write currents, etc.) to the array of cells 520.
  • FIG. 6 is a simplified flowchart illustrating a method 600 of forming an MTJ device 200, 300, 400, according to some embodiments.
  • the method 600 includes forming 610 an MTJ body 290 including a free region 230, a reference region 250, and an oxide region 240 between the free region 230 and the reference region 250.
  • the method 600 also includes forming 620 at least one electrode 210, 270 including conductive material configured to conduct electrical current at least one of to or from the MTJ body 290.
  • the method 600 further includes forming 630 at least one crystal texture region 202, 302, 402 between regions of the MTJ device 200, 300, 400 having different crystal properties.
  • forming 630 the at least one crystal texture region 202, 302, 402 includes forming at least one inert, conductive, and amorphous material.
  • forming 630 the at least one crystal texture region 202, 302, 402 includes forming at least one crystal texture region of amorphous carbon.
  • FIG. 7 illustrates an interposer 1000 that includes one or more embodiments discussed herein.
  • the interposer 1000 is an intervening substrate used to bridge a first substrate 1002 to a second substrate 1004.
  • the first substrate 1002 may be, for instance, an integrated circuit die.
  • the second substrate 1004 may be, for instance, a memory module (e.g., the memory device 500 of FIG. 5), a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 1000 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that can subsequently be coupled to the second substrate 1004.
  • BGA ball grid array
  • first and second substrates 1002/1004 are attached to opposing sides of the interposer 1000. In other embodiments, the first and second substrates 1002/1004 are attached to the same side of the interposer 1000. And in further embodiments, three or more substrates are interconnected by way of the interposer 1000.
  • the interposer 1000 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer 1000 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer 1000 may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012.
  • TSVs through-silicon vias
  • the interposer 1000 may further include embedded devices 1014, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and
  • ESD electrostatic discharge
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1000.
  • RF radio-frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 1000.
  • FIG. 8 illustrates a computing device 1200, according to some embodiments.
  • the computing device 1200 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices.
  • SoC system-on-a-chip
  • components in the computing device 1200 include, but are not limited to, an integrated circuit die 1202 and at least one communications logic unit 1208.
  • the communications logic unit 1208 is fabricated within the integrated circuit die 1202 while in other implementations the communications logic unit 1208 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1202.
  • the integrated circuit die 1202 may include a CPU 1204 as well as on-die memory 1206, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM) (e.g., such as the memory device 500 of FIG. 5).
  • eDRAM embedded DRAM
  • SRAM spin-transfer torque memory
  • STT-MRAM spin-transfer torque memory
  • Computing device 1200 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1210 (e.g., DRAM), non-volatile memory 1212 (e.g., ROM or flash memory, the memory device 500 of FIG.
  • volatile memory 1210 e.g., DRAM
  • non-volatile memory 1212 e.g., ROM or flash memory, the memory device 500 of FIG.
  • a graphics processing unit 1214 GPU
  • a digital signal processor 1216 e.g., a digital signal processor 1216
  • a crypto processor 1242 e.g., a specialized processor that executes cryptographic algorithms within hardware
  • a chipset 1220 at least one antenna 1222 (in some implementations two or more antenna may be used), a display or a touchscreen display 1224, a touchscreen controller 1226, a battery 1229 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1228, a compass (not shown), a motion coprocessor or sensors 1232 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 1234, a camera 1236, user input devices 1238 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1240 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so
  • the computing device 1200 may incorporate further transmission, telecommunication, or radio functionality not already described herein.
  • the computing device 1200 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the computing device 1200 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the communications logic unit 1208 enables wireless communications for the transfer of data to and from the computing device 1200.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communications logic unit 1208 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 1200 may include a plurality of communications logic units 1208.
  • a first communications logic unit 1208 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 1208 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1204 of the computing device 1200 includes one or more devices, such as MTJ devices 200, 300, 400, that are formed in accordance with embodiments disclosed herein.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communications logic unit 1208 may also include one or more devices, such as MTJ device 200, 300, 400, that are formed in accordance with embodiments disclosed herein.
  • another component housed within the computing device 1200 may contain one or more devices, such as MTJ device 200, 300, 400, that are formed in accordance with implementations disclosed herein.
  • the computing device 1200 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • PDA personal digital assistant
  • the computing device 1200 may be any other electronic device that processes data.
  • Example 1 A magnetic tunnel junction (MTJ) device, including: an MTJ body, including: a free region including a ferromagnetic material; a reference region including a ferromagnetic material; and an oxide region including an oxide material between the free region and the reference region; an electrode including electrically conductive material; and a crystal texture region between regions of different crystallinity within the MTJ device.
  • MTJ magnetic tunnel junction
  • Example 2 The MTJ device of Example 1, wherein the crystal texture region includes an amorphous material.
  • Example 3 The MTJ device of Example 2, wherein the crystal texture region includes carbon.
  • Example 4 The MTJ device according to any one of Examples 1-3, further including a synthetic antiferromagnet (SAF) operably coupled between the reference region of the MTJ body and the crystal texture region.
  • SAF synthetic antiferromagnet
  • Example 5 The MTJ device according to any one of Examples 1-4, further including a synthetic antiferromagnet (SAF) operably coupled between the crystal texture region and the electrode.
  • SAF synthetic antiferromagnet
  • Example 6 The MTJ device according to any one of Examples 1-5, further including a cap region including an electrically conductive material operably coupled between the free region of the MTJ body and the crystal texture region.
  • Example 7 The MTJ device according to any one of Examples 1-6, further including a cap region including an electrically conductive material operably coupled between the crystal texture region and the electrode.
  • Example 8 The MTJ device according to any one of Examples 1-7, further including: another electrode including electrically conductive material and located opposite the electrode across the MTJ body; and another crystal texture region operably coupled between the MTJ body and the other electrode.
  • Example 9 The MTJ device according to any one of Examples 1-8, wherein at least one of the free region and the reference region includes a metallic insert region between two CoFeB regions.
  • Example 10 The MTJ device according to any one of Examples 1-9, wherein the oxide region includes magnesium oxide (MgO).
  • MgO magnesium oxide
  • Example 11 The MTJ device according to any one of Examples 1-10, further including at least one other crystal texture region.
  • Example 12 A method of forming a magnetic tunnel junction (MTJ) device, the method including: forming an MTJ body including a free region, a reference region, and an oxide region between the free region and the reference region; forming at least one electrode including conductive material configured to conduct electrical current at least one of to or from the MTJ body; and forming at least one crystal texture region between regions of the MTJ device having different crystal properties.
  • MTJ magnetic tunnel junction
  • Example 13 The method of Example 12, wherein forming the at least one crystal texture region includes forming the at least one crystal texture region of an amorphous material.
  • Example 14 The method of Example 13, wherein forming the at least one crystal texture region of an amorphous material includes forming the at least one crystal texture region of an amorphous carbon.
  • Example 15 The method according to any one of Examples 12-14, wherein forming at least one crystal texture region includes forming a plurality of crystal texture regions.
  • Example 17 The computing device of Example 16, further including at least one device selected from the group consisting of: a processor mounted to a substrate, a graphics processing unit, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor.
  • a processor mounted to a substrate a graphics processing unit, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor.
  • Example 18 The computing device according to any one of Examples 16 and 17, wherein the at least one crystal texture region is less than or equal to about 10 Angstroms thick.
  • Example 19 The computing device according to any one of Examples 16-18, wherein the at least one crystal texture region is at least about one (1) Angstrom thick.
  • Example 20 The computing device according to any one of Examples 16-19, wherein the memory device includes a spin-transfer torque (STT) random access memory device.
  • STT spin-transfer torque
  • Example 21 A method of operating a magnetic tunnel junction (MTJ) device, the method including: applying an electrical control current to an electrode of the MTJ device, the electrode including electrically conductive material, the electrical control current configured to at least one of control and detect an operational state of an MTJ body of the MTJ device; and conducting the electrical control current through a crystal texture region between regions of different crystallinity within the MTJ device.
  • MTJ magnetic tunnel junction
  • Example 22 The method of Example 21, wherein conducting the electrical control current through a crystal texture region includes conducting the electrical control current with a conductive amorphous material.
  • Example 23 The method of Example 22, wherein conducting the electrical control current with a conductive amorphous material includes conducting the electrical control current with amorphous carbon.
  • Example 24 The method according to any one of Examples 21-23, wherein conducting the electrical control current through a crystal texture region includes conducting the electrical control current with a crystal texture region separated from the MTJ body by a synthetic antiferromagnet (SAF).
  • SAF synthetic antiferromagnet
  • Example 25 The method according to any one of Examples 21-24, wherein conducting the electrical control current through a crystal texture region includes conducting the electrical control current with a crystal texture region separated from the electrode by a synthetic antiferromagnet (SAF).
  • SAF synthetic antiferromagnet
  • Example 26 The method according to any one of Examples 21-25, wherein conducting the electrical control current with a crystal texture region includes wherein conducting the electrical control current with a crystal texture region separated from the MTJ body by a cap region including an electrically conductive material.
  • Example 27 The method according to any one of Examples 21-26, wherein conducting the electrical control current with a crystal texture region includes conducting the electrical control current with a crystal texture region separated from the electrode by a cap region including an electrically conductive material.
  • Example 28 The method according to any one of Examples 21-27, further including: conducting the electrical control current with another electrode including electrically conductive material and located opposite the electrode across the MTJ body; and conducting the electrical control current with another crystal texture region operably coupled between the MTJ body and the other electrode.
  • Example 29 The method according to any one of Examples 21-28, further including conducting the electrical control current to the MTJ device including a free region, a reference region, and an insulating region between the free region and the reference region, at least one of the free region and the reference region including a metallic insert region between two CoFeB regions.
  • Example 30 The method of Example 29, wherein the insulating region includes magnesium oxide (MgO).
  • Example 31 The method according to any one of Examples 21-29, further including conducting the electrical control current with at least one other crystal texture region of the MTJ device.
  • Example 32 A magnetic tunnel junction (MTJ) device, including: an MTJ body including a free region, a reference region, and an oxide region between the free region and the reference region; at least one electrode including conductive material configured to conduct electrical current at least one of to or from the MTJ body; and at least one crystal texture region between regions of the MTJ device having different crystal properties.
  • MTJ magnetic tunnel junction
  • Example 33 The MTJ device of Example 32, wherein the at least one crystal texture region includes an amorphous material.
  • Example 34 The MTJ device of Example 33, wherein the amorphous material includes amorphous carbon.
  • Example 35 The MTJ device according to any one of Examples 32-35, wherein the at least one crystal texture region includes a plurality of crystal texture regions.
  • Example 36 A method of assembling a computing device, the method including: providing a memory device configured to electrically store data, the memory device including: at least one magnetic tunnel junction (MTJ) device including: a pair of electrodes; an MTJ body including an oxide region between a reference region and a free region, the MTJ body between the pair of electrodes; and at least one crystal texture region including a conductive amorphous material between regions of the MTJ device having different crystallinities.
  • MTJ magnetic tunnel junction
  • Example 37 The method of Example 36, further including adding at least one device selected from the group consisting of: a processor mounted to a substrate, a graphics processing unit, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor.
  • a processor mounted to a substrate a graphics processing unit, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor.
  • Example 38 The method according to any one of Examples 36 and 37, wherein providing a memory device including at least one crystal texture region includes providing the memory device including at least one crystal texture region that is less than or equal to about ten (10) Angstroms thick.
  • Example 39 The method according to any one of Examples 36-38, wherein providing a memory device including at least one crystal texture region includes providing the memory device including at least one crystal texture region that is at least about 100 Angstroms thick.
  • Example 40 The method according to any one of Examples 36-39, wherein providing a memory device includes providing a spin-transfer torque (STT) random access memory device.
  • STT spin-transfer torque
  • Example 41 A non-transitory computer-readable storage medium including computer-readable instructions stored thereon, the computer-readable instructions configured to instruct a processor to perform at least a portion of the method according to any one of Examples 12-15, 21-31, and 37-40.
  • Example 42 A means for performing the method according to any one of Examples 12-15, 21-31, and 37-40.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

L'invention concerne des dispositifs à jonction tunnel magnétique (MTJ), des dispositifs de calcul et des procédés associés. Un dispositif MTJ comprend un corps MTJ, une électrode et une région de texture cristalline. La région de texture cristalline est accouplée fonctionnellement entre des régions de cristallinité différente à l'intérieur du dispositif MTJ. Un dispositif de calcul comprend un dispositif de mémoire comprenant au moins un dispositif MTJ, qui comprend à son tour au moins une région de texture cristalline. Un procédé de formation d'un dispositif MTJ comprend la formation d'un corps MTJ, la formation d'au moins une électrode, et la formation d'au moins une région de texture cristalline électriquement entre des régions du dispositif MTJ possédant des propriétés cristallines différentes.
PCT/US2016/040479 2016-06-30 2016-06-30 Barrière de texture cristalline dans la conception d'un empilement formant jonction tunnel magnétique perpendiculaire (pmtj) WO2018004616A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060291105A1 (en) * 2005-06-28 2006-12-28 Chang Y A Fabrication of magnetic tunnel junctions with epitaxial and textured ferromagnetic layers
US20080182015A1 (en) * 2004-11-10 2008-07-31 International Business Machines Corporation Magnetic Tunnel Junctions Using Amorphous Materials as Reference and Free Layers
US20150035095A1 (en) * 2013-08-02 2015-02-05 Woojin Kim Magnetic memory devices having a perpendicular magnetic tunnel junction
US20150061058A1 (en) * 2011-05-10 2015-03-05 Headway Technologies, Inc. Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications
US20150194596A1 (en) * 2012-09-26 2015-07-09 Lntel Corporation Perpendicular mtj stacks with magnetic anisotrophy enhancing layer and crystallization barrier layer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080182015A1 (en) * 2004-11-10 2008-07-31 International Business Machines Corporation Magnetic Tunnel Junctions Using Amorphous Materials as Reference and Free Layers
US20060291105A1 (en) * 2005-06-28 2006-12-28 Chang Y A Fabrication of magnetic tunnel junctions with epitaxial and textured ferromagnetic layers
US20150061058A1 (en) * 2011-05-10 2015-03-05 Headway Technologies, Inc. Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications
US20150194596A1 (en) * 2012-09-26 2015-07-09 Lntel Corporation Perpendicular mtj stacks with magnetic anisotrophy enhancing layer and crystallization barrier layer
US20150035095A1 (en) * 2013-08-02 2015-02-05 Woojin Kim Magnetic memory devices having a perpendicular magnetic tunnel junction

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