WO2018004568A1 - Diodes à faible capacité utilisant la technologie des transistors à effet de champ à ailettes - Google Patents

Diodes à faible capacité utilisant la technologie des transistors à effet de champ à ailettes Download PDF

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Publication number
WO2018004568A1
WO2018004568A1 PCT/US2016/040074 US2016040074W WO2018004568A1 WO 2018004568 A1 WO2018004568 A1 WO 2018004568A1 US 2016040074 W US2016040074 W US 2016040074W WO 2018004568 A1 WO2018004568 A1 WO 2018004568A1
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Prior art keywords
fin
cathode
anode
diffusion regions
diode
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PCT/US2016/040074
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English (en)
Inventor
Nathan D. Jack
Steven S. Poon
Jae B. LIMB
Chinmay P. JOSHI
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Intel Corporation
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Priority to PCT/US2016/040074 priority Critical patent/WO2018004568A1/fr
Publication of WO2018004568A1 publication Critical patent/WO2018004568A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body

Definitions

  • This disclosure relates generally to diodes, and, more particularly, to low capacitance diodes using fin field effect transistor technology.
  • MOSFETs Metal oxide semiconductor field effect transistors
  • Fin field effect transistor (FinFET) technology has enabled the production of ICs with increased performance and smaller footprints than traditional MOSFET ICs.
  • Blocks of transistors manufactured using FinFET technology have been used to create diodes offering electrostatic discharge (ESD) protection for ICs. Using transistor blocks to create diodes is often employed in this manner because no additional masks are needed beyond those already used for the individual transistors.
  • ESD electrostatic discharge
  • FIG. 1 is a schematic illustration of an example circuit in an IC that provides dual diode ESD protection.
  • FIG. 2 is a plan view of a layout of a first example transistor block to implement first example diode units to implement either of the diodes of FIG. 1.
  • FIG. 3 is a three-dimensional view of the first example diode unit of FIG. 2.
  • FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. 2 that also illustrates interleaving of back-end metal.
  • FIG. 5 is a plan view of a layout of a second example transistor block to implement second example diode units to implement either of the diodes of FIG. 1.
  • FIG. 6 is a plan view of a layout of a third example transistor block to implement third example diode units to implement either of the diodes of FIG. 1.
  • FIG. 7 is a plan view of a layout of a fourth example transistor block to implement fourth example diode units to implement either of the diodes of FIG. 1.
  • FIG. 8 is a three-dimensional view of the fourth example diode unit of FIG. 7.
  • FIG. 9 is a cross-sectional view of a fifth example transistor block similar to the fourth example transistor block of FIGS. 7 and 8 but with a different number of diffusion regions corresponding to the number shown in FIG. 4.
  • FIG. 10 is a flow chart of an example method to manufacture either of the diodes 102, 104 of FIG. 1 using the layout shown in FIG. 7.
  • FIG. 11 is a plan view of a layout of a sixth example transistor block to implement sixth example diode units to implement either of the diodes of FIG. 1.
  • FIG. 1 is a schematic illustration of an example circuit 100 in an IC that provides dual diode ESD protection. As shown in the illustrated example, an upper diode 102 and a lower diode 104 are positioned on either side of ajunction 106 between a transmitter/receiver 110 and an I/O pad 108.
  • the diodes 102, 104 direct the current through the upper diode 102 to a power supply 112 or positive voltage supply to then be directed around to a negative voltage supply 114 or ground, thereby preventing the transmitter/receiver 110 from experiencing the electrical surge.
  • the voltage at the junction 106 needs to be as low as possible, which corresponds to the lower diode 104 having a low resistance.
  • the resistance of the lower diode 104 can be decreased by increasing the size of the diode 104.
  • the diode 104 size increases so does the overall size of the IC.
  • a larger diode has a higher capacitance, which is undesirable. Accordingly, there is a desire to fabricate diodes as small as possible while maintaining both low resistance and low capacitance.
  • the diodes 102, 104 are fabricated from a block of transistors including a number of individual diode units to achieve the desired level of current handling capabilities.
  • FIG. 2 is a plan view of a portion of layout of an example transistor array or block 200 to implement either the upper or lower diode 102, 104 of FIG. 1. In many applications, the array of transistors may be larger but follow the partem shown in FIG. 2.
  • the transistor block 200 includes a plurality of diode units (four of which are demarcated with boxes labelled with reference numerals 202, 204, 206, 208). A three-dimensional view of the example diode unit 202 is shown in FIG. 3.
  • the diode unit 202 is shown in isolation in FIG. 3, the entire transistor block 200 is formed on a single silicon block or substrate 302. That is, the diode units 204, 206, 208 are omitted in FIG. 3 for the sake of clarity, but would all be formed on the same silicon substrate 302. [0018]
  • the transistor block 200 is fabricated using FinFET technology.
  • the transistor block 200 includes a plurality of fins 210. During fabrication, the fins 210 may be formed of silicon on the silicon substrate 302 extending continuously from one side of the transistor block 200 (e.g., left side of FIG. 2) to the other side of the transistor block 200 (e.g., the right side of FIG. 2).
  • the fins 210 may originally extend across an entire diode unit and continue extending across other adjacent diode units.
  • these single continuous fins 210 are divided into separate fin segments 212 with a length 213 shorter than the full length of the single continuous fins 210 as shown in FIGS. 2 and 3.
  • the continuous fins 210 are divided into the separate fin segments 212 during subsequent manufacturing processes to isolate individual multi-fin transistors each having a separate gate 214. More particularly, as shown in the illustrated example, there are anode multi-fin transistors 216 and cathode multi-fin transistors 218.
  • the anode multi-fin transistors 216 correspond to the anode of a diode and are characterized by fin segments 212 each having two anode diffusion regions 220 (represented with gray shading in FIG. 2) separated by a transistor gate 214.
  • the cathode multi-fin transistors 218 correspond to the cathode of a diode and are characterized by fin segments 212 each having two cathode diffusion regions 222 (represented in black in FIG. 2) separated by a transistor gate 214.
  • the diffusion regions 220, 222 are portions of the silicon-based fins that have been doped with impurities to form n-type or p-type regions as shown and described in greater detail below in connection with FIG. 4.
  • the impurities may be any suitable acceptor to form p-type regions (e.g. boron, aluminium, gallium, indium, etc.) or any suitable donor to form n-type regions (e.g., phosphorus, arsenic, antimony, bismuth, etc.).
  • the gates 214 may be formed with an electrical insulator (e.g., silicon dioxide) using any suitable technique.
  • each isolated grouping of fin segments 212 (e.g., each individual multi-fin transistor) is referred to herein as a separate or isolated anode 216 or cathode 218.
  • the individual anodes 216 are electrically coupled to form the overall anode for a diode.
  • metal wiring electrically couples the individual cathodes 218 to form the overall cathode for the diode.
  • each diode unit 202, 204, 206, 208 includes three separate multi-fin transistors in which at least one is an anode 216 and at least one is a cathode 218.
  • each multi-fin transistor e.g., each separate anode 216 and each separate cathode 2128
  • a shallow trench isolation (STI) material 224 e.g., glass
  • the STI 224 serves to cut the originally continuous fins 210 into the separate fin segments 212 to isolate each anode 216 and cathode 218 within the transistor block 200.
  • the STI 224 is disposed between each of the adjacent fins 210 to fill a portion of the valley between the fins as shown in FIG. 3. The portion of the fins 210 that is below the top surface of the STI 224 is referred to as the sub-fin.
  • diodes implemented according to the layout shown in FIG. 2 are referred to as STI-defined diodes because the STI 224 separates the individual anodes 216 and cathodes 218.
  • diodes can be implemented as gate-blocked diodes in which the separate anodes 216 and cathodes 218 of each diode unit are isolated by an additional gate that crosses the fins 210.
  • the fin segments 212 are not cut but remain connected as a continuous fin 210 with a gate between the anode 216 and cathode 218 (e.g., the gate 214 at the junction between an anode 216 and a cathode 218 would define an anode diffusion region 220 on one side and a cathode diffusion region 222 on the other side).
  • each multi-fin transistor is four-fin transistor because it includes four fin segments that are crossed by a single gate 214.
  • more or fewer fin segments 212 may be associated with a particular transistor (e.g., 1, 2, 5, 6, 10, 25, etc.).
  • the space (of STI 224) between the different diode units 202, 204, 206 is primarily to facilitate the patterning used to manufacture the transistor block 200.
  • the separate diode unit 202, 204, 206 could be fabricated as a single unit by adding a fin 210 between the diode units 202, 204, 206 and forming the gates 214 to cross all of the fins 210.
  • the gate 214 serves to define and separates the diffusion regions 220, 222 corresponding to the source and drain of individual transistors constructed on each fin segment 212 of each fin 210.
  • a cross-sectional view (taken along line 4-4 of FIG. 2) of one of the fins 210 of the transistor block 200 is illustrated in FIG. 4.
  • the anode 216 and cathodes 218 of the diode unit 202 are formed in an N-well 402 that spans the entire diode unit 202. More particularly, the anode 216 includes p-type anode diffusion regions 220 within the N-well 402 (corresponding to a P+ source and a P+ drain of a PMOS transistor).
  • the cathodes 218 include n-type cathode diffusion regions 222 (e.g., N+ N-well taps) within the N-well 402
  • FIG. 4 illustrates a P+/N-well diode
  • the inverse may also be implemented (to create an N+/P-well diode) by forming a P-well within an n-type silicon substrate 302.
  • the well 402 may be excluded such that the doped N+ and P+ source and drain regions are formed directly within the p-type (or n-type) silicon substrate 302.
  • the gates 214 are "dummy" gates in that they are not used to generate a conductive channel between the source and gain of each transistor.
  • the gates 214 are included in the transistor block 200 because the gates 214 serve to block the formation of the STI 224 and to define the different diffusion regions 220, 222 (i.e., the source and drain) for each of the anodes 216 and cathode 218 of each diode unit 202, 204, 206, 208.
  • the illustrated example uses a single-gate transistor design.
  • the anode and cathode 216, 218 of a single diode unit 202, 204, 206, 208 are positioned such that the fin segments 212 of the anode 216 are longitudinally aligned or collinear with the fin segments 212 of the cathode 218. That is, adjacent fin segments 212 in adj acent ones of the anode 216 and cathode 218 are positioned end to end with their lengths extending along a common line.
  • the collinear fin segments 212 of each of the anode 216 and cathode 218 of each diode unit were originally part of the same continuous fin 210 before the fin 210 was cut by the STI 224 into separate segments.
  • the anode and cathode 216, 218 are arranged in this manner, current between the anode and the cathode travels in a direction parallel to the fins 210.
  • a diode unit 502 may be arranged such that an outer fin segment 503 of the anode 506 is positioned adj acent and alongside an outer fin segment 504 of the cathode 508 with both ends of both fin segments 503, 504 align in a direction perpendicular to the longitudinal length of the fin segments.
  • current between the anode 506 and the cathode 508 travels in a direction perpendicular to the fins.
  • FIG. 4 shows metal towers or stacks 412 representative of the back-end metal used to form the anode and cathode terminals of the diode. As can be seen, significant interleaving of anode and cathode metal wiring connections is required to access the diffusions regions 220, 222 of the anode 216 and cathode 218.
  • the close proximity of the metal stacks 412 in the repeating anode-cathode-anode- cathode pattern results in significant parasitic capacitance (represented by the symbols labelled with reference numeral 414) that can, in some scenarios, exceed junction capacitance associated with an I/O pin of an IC.
  • the tight interleaving of anode and cathode metal stacks 412 may also create problems for high voltage applications where the tight metal to metal spacing can result in dielectric breakdown. This problem becomes a larger concern as semiconductor technology advances to smaller scaled devices because the metal pitches decrease while the voltage requirements remain unchanged.
  • each diode unit 602, 604, 606 includes one or more gaps 608 to space out the anode and cathode portions of the diode units. While this approach successfully reduces the parasitic capacitance created from the back-end metal and at least partially alleviates high voltage concerns, it significantly increases the overall footprint of the diode array. Accordingly, a better diode layout is needed that reduces capacitance without requiring a larger footprint.
  • FIG. 7 is a plan view of a layout of an example transistor array or block 700 to implement either of the diodes 102, 104 of FIG. 1.
  • the transistor block 700 includes multiple diode units (one of which is demarcated by the box labelled with the reference numeral 702).
  • a three-dimensional view of the example diode unit 702 is shown in FIG. 8.
  • the example diode unit 702 includes an anode 704 and a cathode 706 (including two individual portions) formed on a silicon substrate 708.
  • the anode 704 and cathode 706 each include a plurality of fins 712 that have been cut into separate fin segments 714 by STI 710.
  • the fins 712 and fin segments 714 may be constructed similarly to the fins 210 and fin segments 212 described above in connection with FIGS. 2-4. In some examples, ones of the fin segments 714 along each continuous fin 712 may have different lengths than other ones of the fin segments 714. As shown in the illustrated example, a length 715 of each fin segment 714 associated with the anode 704 is longer than a length 716 of each fin segment 714 associated with the cathode 706. Further, as shown in the illustrated example, a plurality of gates 717 extend across the fins 712 in the same manner as the gates 214 cross over the fins 210 as shown in FIG. 2. However, unlike the diode unit 202 of FIG.
  • the diode unit 702 of FIG. 7 includes multiple gates 717 that cross each discrete fin segment 714 to define more than two diffusion regions 719, 720 associated with each anode 704 and cathode 706. As illustrated in FIG. 7, the multiple gates 717 (and corresponding diffusion regions 719, 720) disposed along the single continuous length 715, 716 of a particular fin segment 714 result in fin segments 714 that are much longer than the fin segments 212 of FIG. 2. In some examples, an individual fin segment 714 has a length 715, 716 that is at least five times a width 718 of the fin segment.
  • the gates 717 of FIG. 7 may be similar in construction to the gates 214 described above in connection with FIG. 2. Thus, in some examples, the gates 717 shown in FIG. 7 are "dummy" gates that are not electrically coupled to any metal wiring. Rather, the gates 717 serve to block STI from forming and to define the different diffusion regions 719, 720 along each of the fin segments 714 (e.g., corresponding to the source and drain of separate transistors). In the illustrated example, there are nine gates 717 crossing the fin segments 714 of the anode 704 resulting in ten separate anode diffusion regions 719 along each fin segment.
  • each of the cathodes 706 includes four gates 717, thereby defining five cathode diffusion regions 720 along each fin segment in each portion of the cathode 706.
  • the number of anode diffusion regions 719 with the diode unit 702 is the same as the total number of cathode diffusion regions 720. In other examples, the number of anode diffusion regions may be greater than or less than the number of cathode diffusion regions.
  • the cathode 7 is symmetric with the same number of gates 717 (and corresponding number of diffusion regions) in each portion of the cathode 706 on either side of the anode 704, in other examples, one portion of the cathode 706 may be larger than the other portion (e.g., include more gates 717). Further still, in some examples, there may be only one cathode 706 that is paired with one or more anode 704.
  • the anode and cathode 704, 706 of the diode unit 702 are positioned such that the fins segments 714 of the anode 216 longitudinally align with or are collinear with the fin segments 714 of the cathode 218.
  • current between the anode and the cathode travels in a direction parallel to the fins 712.
  • the anode and cathode may be arranged similar to the example shown in FIG. 5 such that the current between the anode and cathode flows in a direction perpendicular to the fins.
  • the fin segments 714 of the anode and cathode 704, 706 may have originally been formed as part of single continuous fins 712 that extend across the entire transistor block 700. In the illustrated examples, such fins have been cut into the shorter fin segments 714 specific to each of the anode 704 or cathode 706. In some examples, the fin segments 714 may remain as part of continuous fins spanning the transistor block 700. In such examples, rather than the STI 710 cutting the fins 712 to define the individual fin segments 714, additional gates may be placed over the continuous fins 712 at the junctions between the anodes and cathodes 704, 706. That is, in some examples, the transistor block 700 may implement a gate-blocked diode rather than an STI-defined diode.
  • FIG. 9 is a cross-sectional view of an example transistor block 900 constructed in accordance with the teachings disclosed herein illustrating the interleaving of the back-end metal to implement either of the diodes 102, 104 of FIG. 1.
  • the transistor block 900 includes an anode 902 and a cathode 904 (formed out of two separate portions).
  • Each of the anode 902 and the cathode 904 include multiple gates 906 similar to the examples shown in FIGS 7 and 8 except that there are fewer gates 906 in FIG. 9. More particularly, the anode 902 in the example shown in FIG.
  • FIG. 9 includes five gates 906 to define six anode diffusion regions 908, while each portion of the cathode 904 includes three gates 906 defining four cathode diffusion regions 910.
  • the cross-sectional view of FIG. 9 shows the same number of anode diffusion regions and the same number of cathode diffusion regions as is shown in the cross-sectional view of FIG. 4.
  • the transistor blocks in each of FIGS. 4 and 9 will have a similar front-end conductance.
  • FIG. 4 shows six locations in which STI 224 separates adjacent anodes and cathodes 216, 218,
  • FIG. 9 includes only two locations in which STI 912 separates the anode 902 from each portion of the adjacent cathode 904.
  • the fewer locations for the STI 912 is the result of the diffusion regions 908, 910 being grouped together along a single continuous fin segment with a corresponding group of gates 906. This reduction in the need for STI 912 results in a smaller overall footprint for the transistor block 900 when compared against the example shown in FIG. 4.
  • the grouping of the gates 906 and associated diffusion regions 908, 910 for each of the anode 902 and cathode 904 results in less interleaving of anode and cathode metal wiring. More particularly, as shown in the illustrated example, the anode 902 and each portion of the cathode 904 of FIG. 9 are each associated with a single metal stack 914 for a total of three stacks rather than the seven separate stacks 412 of FIG. 4. This reduction in anode and cathode interleaving results in a reduction in parasitic capacitance generated between the back-end metal stacks 914 of FIG. 9 (represented by the symbols identified with reference numeral 916) as compared with the capacitance 414 of FIG. 4.
  • the footprint of each individual metal stack 914 is greater than for the metal stacks 412 of FIG. 4.
  • the larger base for the metal stacks 914 enables the stacks to be tapered in some examples as shown in FIG. 9. Such tapering increases the spacing between the metal stacks 914 near the top, thereby decreasing the concern for dielectric breakdown in high voltage applications.
  • testing reveals that the twelve anode diffusion region diode of the same size results in approximately a 73% reduction in back-end capacitance, a 21% decrease in back-end resistance, and a 94% reduction in the back-end capacitance per conductance (Rx C). Further, when compared against a diode implemented using the layout shown in FIG. 7, testing reveals that the twelve anode diffusion region diode of only half the size results in approximately a 59% reduction in capacitance, a 25% increase in back-end resistance, and a 34% reduction in the back-end capacitance per conductance (Rx C).
  • the advantages realized in the example diode layout of FIG. 7 is partially based on the fact that a primary source of diode front-end resistance comes from the diffusion regions (e.g., the diffusion regions 908, 910 of FIG. 9) and first-level contacts rather than the well (e.g., the N-well 918 of FIG. 9) and sub-fins. That is, if current from the anode 902 was confined to within the protruding portion of the fins (where the diffusion regions and first-level contacts are located), the current density within each fin could lead to increased resistance from self-heating. Furthermore, such resistance is increased as the fin is lengthened to include more diffusion regions.
  • anode 902 is expanded to include more anode diffusion regions 908 separated by additional gates 906, at some point the diffusion regions 908 near the center of the anode 902 will contribute less to the overall conductance than the diffusion regions 908 closer to the cathodes 904.
  • diodes using at least 12 anode diffusion strips grouped on a single continuous fin segment provide comparable conductance under ESD-like conditions to diodes using the layout illustrated in FIG. 2.
  • Another potentially limited factor to the width of the anode is delayed tum-on speed of the diode.
  • Charged device model ESD events have a sharp slew rate (e.g., approximately 5A / 300ps).
  • on-chip ESD protection elements need to respond and clamp very quickly.
  • the high injection of charge results in conductivity modulation of the diode.
  • the well e.g., the N-well 918 of FIG. 9
  • the background doping becomes relatively insignificant when compared to the injected carriers resulting in an effective decrease in the diode conductance.
  • FIG. 10 is a flow chart illustrated an example method to manufacture either of the diodes 102, 104 of FIG. 1 based on the layout shown in FIG. 7.
  • the method begins at block 1000 where fins 712 are formed on a silicon substrate 708.
  • the method involves forming a first plurality of gates 717 that cross over the fins 712 to define a plurality of anode diffusion regions 719 in the fins 712.
  • the number of anode diffusion regions 719 is one greater than the number gates 717 on the anode 704 such that multiple gates 717 (at least two) results in at least three anode diffusion regions 719.
  • the method involves forming a second plurality of gates 717 that cross over the fins 712 to define a plurality of cathode diffusion regions 720 in the fins 712.
  • the anode diffusion regions 719 are located along segments of the fins 28 different than the cathode diffusion regions 720 (and corresponding gates 717).
  • the number of cathode diffusion regions 720 may be one greater than the number gates 717 on the cathode 706.
  • the method involves applying shallow trench isolation (e.g., the STI 710) to separate the anode 704 and cathode 706 portions of a diode. That is, in some examples, the STI 710 is used to divide the fins 712 into separate fin segments 714 associated with each of the anode 704 and cathode 706.
  • the method involves doping the diffusion regions 719, 720 with impurities for the anode 704 and cathode 706 portions.
  • the method involves adding metal wiring to connect diffusion regions 719, 720 of the anode 704 and cathode 706 portions.
  • the example method of FIG. 10 ends.
  • the example method is described with reference to the flowchart illustrated in FIG. 10, many other methods of manufacturing the example diodes in accordance with the teachings disclosed herein may alternatively be used.
  • the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined.
  • the example method of FIG. 10 describes the formation of gates 717 (block 1002) prior to the doping of the diffusion regions 719, 720 (block 1008), in other examples, the diffusion regions 719, 720 may be formed before the gates 717.
  • FIG. 11 is a plan view of a layout of another example transistor array or block 1100 to implement either of the diodes 102, 104 of FIG. 1.
  • the transistor block 1100 is similar to the transistor block 700 of FIG. 7. That is, as shown in FIG. 11, each diode unit of the transistor block 1100 (one of which is demarcated by the box labelled with the reference numeral 1102) is formed from a plurality of fins 1104 divided into fin segments 1106 corresponding to separate portions associated with either an anode 1108 or a cathode 1110.
  • each diode unit of the transistor block 1100 is formed from a plurality of fins 1104 divided into fin segments 1106 corresponding to separate portions associated with either an anode 1108 or a cathode 1110.
  • the transistor block 1100 of FIG. 11 does not include any gates. Rather, as shown in FIG. 11, the multiple anode diffusion regions 1112 and cathode diffusion regions 1114 are separated or spaced apart by non-diffused regions 1116.
  • the non-diffused regions 1116 are formed from a mask that is subsequently etched away or otherwise removed after the doping procedure to form the diffusion regions 1112, 1114.
  • only some of the gates 719717 shown in FIG. 7 may be formed across the fins 1104 such that at least two diffusion regions (separated by a non-diffusion region) are formed between adjacent gates crossing the same continuous fin segment.
  • the diffusion regions 1112, 1114 of FIG. 11 are shown to be a similar size to the diffusion regions 719, 720 of FIG. 7, in other examples, the diffusion regions 1112, 1114 may be larger (e.g., extend along a longer portion of each fin segment 1106).
  • the length of each diffusion region 1112, 1114 extending in a direction along the length of each fin segment 1106 is approximately equal to the width of each fin segment 1106.
  • the length of each diffusion region 1112, 1114 extending in a direction along the length of each fin segment 1106 is larger than the width of the fin segment (e.g., 2, 3, 5, 10, etc. times longer).
  • each diffusion region 1112, 1114 extending in a direction along the length of each fin segment 1106 may be less than the width of the fin segment.
  • the length of each non-diffusion region 1116 extending in a direction along the length of each fin segment 1106 may be less than, equal to, or greater than the width of the fin segment.
  • each individual fin segment 1106 may not include any non- diffusion regions 1116 such that each anode or cathode diffusion region 1112, 1114 is connected with other adjacent diffusion regions on each fin segment 1106.
  • the fin segment 1106 corresponds to a single diffusion region 1112, 1114 extending approximately the entire length between each end of the fin segment 1106 (e.g., defined by STI material or gate at the junction between adjacent anode and cathode fin segments).
  • the length and/or spacing of the diffusion regions 719, 720 and/or the width of each gate 717 in the example of FIG. 7 may be similarly varied based on the placement, spacing, and/or size of the gates 717.
  • Example 1 includes is a diode that includes an anode including a first fin segment coupled with a silicon substrate.
  • the anode includes at least three anode diffusion regions spaced apart along a length of the first fin segment.
  • the diode includes a cathode including a second fin segment coupled with the silicon substrate.
  • the cathode includes at least three cathode diffusion regions spaced apart along the second fin segment. Current between the anode and the cathode is to flow in a direction parallel to the length of the first fin segment.
  • Example 2 includes the subj ect matter of Example 1, wherein the first fin segment is longitudinally aligned with the second fin segment.
  • Example 3 includes the subj ect matter of any one of Examples 1 or 2, wherein the first fin segment is separated from the second fin segment, and a shallow trench isolation material is disposed between the first fin segment and the second fin segment.
  • Example 4 includes the subj ect matter of any one of Examples 1 or 2, wherein the first fin segment and second fin segment correspond to different portions of a single continuous fin, and a gate is disposed at a junction of the first fin segment and the second fin segment.
  • Example 5 includes the subj ect matter of any one of Examples 1-4, wherein the first fin segment is one of a first plurality of fin segments extending across the anode in parallel to one another and the second fin segment is one of a second plurality of fin segments extending across the cathode in parallel to one another.
  • Example 6 includes the subj ect matter of Example 5, wherein ones of the first plurality of fin segments are collinear with respective ones of the second plurality of fin segments.
  • Example 7 includes the subj ect matter of any one of Examples 1-6, and further includes a first metal stack electrically connecting the at least three anode diffusion regions.
  • the apparatus includes a second metal stack electrically connecting the at least three cathode diffusion regions.
  • Example 8 includes the subj ect matter of Example 7, wherein at least one of the first or second metal stacks is tapered.
  • Example 9 includes the subj ect matter of any one of Examples 1-8, and further includes a second cathode including a third fin segment coupled with the silicon substrate. The anode is positioned between the cathode and the second cathode. A total number of cathode diffusion regions along the second and third fin segments is equal to or greater than a total number of anode diffusion regions along the first fin segment.
  • Example 10 includes the subject matter of Example 9, wherein a first number of the cathode diffusion regions along the second fin segment is different than a second number of the cathode diffusion regions along the third fin segment.
  • Example 11 includes the subject matter of any one of Examples 1-10, wherein the at least three anode diffusion regions are defined by a first plurality of gates crossing the first fin segment.
  • the at least three cathode diffusion regions are defined by a second plurality of gates crossing the second fin segment.
  • Example 12 is an apparatus to protect against electrostatic discharge that includes a silicon substrate.
  • the apparatus includes a plurality of fins disposed on the substrate. A first portion of the fins correspond to an anode. A second portion of the fins correspond to a cathode.
  • the apparatus includes a plurality of gates crossing the fins to define at least three diffusion regions positioned sequentially along a segment of one of the fins
  • Example 13 includes the subject matter of Example 12, wherein ones of the first portion of the fins are longitudinally aligned with respective ones of the second portion of the fins.
  • Example 14 includes the subject matter of any one of Examples 12 or 13, and further includes a shallow trench isolation material separating the first portion of the fins from the second portion of the fins.
  • Example 15 includes the subject matter of any one of Examples 12-14, and further includes a tapered metal stack electrically coupling the at least three diffusion regions.
  • Example 16 includes the subject matter of any one of Examples 12-15, wherein at least two of the at least three diffusion regions are located between adjacent ones of the plurality of gates crossing the segment of one of the fins.
  • Example 17 includes the subject matter of any one of Examples 12-16, wherein a third portion of the fins corresponds to a second cathode. The first portion of the fins is positioned between the second and third portions of the fins.
  • Example 18 includes the subject matter of Example 17, wherein a first number of cathode diffusion regions along the second portion of the fins being different than a second number of cathode diffusion regions along the third portion of the fins.
  • Example 19 includes the subject matter of any one of Examples 17 or 18, wherein a total number of cathode diffusion regions along the second and third portions of the fins is equal to or greater than a total number of anode diffusion regions along the first portion of the fins.
  • Example 20 is a method to manufacture a diode that includes forming a first fin on a silicon substrate.
  • the first fin is associated with an anode of the diode.
  • the first fin has a length at least five times a width of the first fin.
  • the method includes forming a second fin on the silicon substrate.
  • the second fin is associated with a cathode of the diode.
  • the second fin longitudinally aligns with the first fin.
  • the method includes forming at least three anode diffusion regions along the first fin.
  • Example 21 includes the subject matter of Example 20, and further includes applying a shallow trench isolation material to separate the first fin from the second fin.
  • Example 22 includes the subject matter of any one of Examples 20 or 21, and further includes forming a first metal stack to electrically connect the at least three anode diffusion regions.
  • the method includes forming a second metal stack to electrically connect cathode diffusion regions along the second fin. At least one of the first or second metal stacks is tapered.
  • Example 23 includes the subject matter of any one of Examples 20-22, wherein the at least three anode diffusion regions are interconnected to form portions of a single diffusion region substantially extending the length of the first fin.
  • Example 24 includes the subject matter of any one of Examples 20-23, wherein the at least three anode diffusion regions are separated by non- diffusion regions.
  • Example 25 includes the subject matter of any one of Examples 20-24, wherein the at least three anode diffusion regions are separated by gates crossing the first fin.
  • Example 26 includes the subject matter of Example 25, wherein the first fin and the second fin correspond to different portions of a single continuous fin. A junction of the first fin and the second fin is defined by another gate.
  • Example 27 includes the subject matter of any one of Examples 20-26, wherein the first fin is one of a first plurality of fins extending across the anode in parallel to one another and the second fin is one of a second plurality of fins extending across the cathode in parallel to one another.
  • Example 28 includes the subject matter of any one of Examples 20-27, wherein ones of the first plurality of fins are collinear with respective ones of the second plurality of fins. Current between the anode and cathode to flow in a direction parallel to the first fin.
  • Example 29 includes the subject matter of any one of Examples 20-28, and further includes forming a third fin on the silicon substrate. The third fin is associated with a second cathode of the diode. The anode is positioned between the cathode and the second cathode. The method includes forming a plurality of cathode diffusion regions along the second and third fins. A total number of the cathode diffusion regions along the second and third fins is equal to or greater than a total number of the anode diffusion regions along the first fin.
  • Example 30 includes the subject matter of Example 29, wherein a first number of the cathode diffusion regions along the second fin is different than a second number of the cathode diffusion regions along the third fin.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne des diodes à faible capacité utilisant la technologie des transistors à effet de champ à ailettes. Une diode donnée à titre d'exemple comprend une anode comprenant un premier segment d'ailette accouplé à un substrat en silicium. L'anode comprend au moins trois régions de diffusion d'anode espacées le long d'une longueur du premier segment d'ailette. La diode donnée à titre d'exemple comprend en outre une cathode comprenant un second segment d'ailette accouplé au substrat en silicium. La cathode comprend au moins trois régions de diffusion de cathode espacées le long du second segment d'ailette. Un courant circule entre l'anode et la cathode dans une direction parallèle à la longueur du premier segment d'ailette. D'autres modes de réalisation peuvent être décrits et/ou revendiqués.
PCT/US2016/040074 2016-06-29 2016-06-29 Diodes à faible capacité utilisant la technologie des transistors à effet de champ à ailettes WO2018004568A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2016/040074 WO2018004568A1 (fr) 2016-06-29 2016-06-29 Diodes à faible capacité utilisant la technologie des transistors à effet de champ à ailettes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2016/040074 WO2018004568A1 (fr) 2016-06-29 2016-06-29 Diodes à faible capacité utilisant la technologie des transistors à effet de champ à ailettes

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060063334A1 (en) * 2004-09-17 2006-03-23 International Business Machines Corporation Fin FET diode structures and methods for building
US20060273372A1 (en) * 2002-12-03 2006-12-07 International Business Machines Corporation Lateral lubistor structure and method
US20130292745A1 (en) * 2012-05-03 2013-11-07 Globalfoundries Inc. Finfet compatible pc-bounded esd diode
US20140191319A1 (en) * 2013-01-04 2014-07-10 GlobalFoundries, Inc. Finfet compatible diode for esd protection
US20140252476A1 (en) * 2013-03-08 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Rotated STI Diode on FinFET Technology

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060273372A1 (en) * 2002-12-03 2006-12-07 International Business Machines Corporation Lateral lubistor structure and method
US20060063334A1 (en) * 2004-09-17 2006-03-23 International Business Machines Corporation Fin FET diode structures and methods for building
US20130292745A1 (en) * 2012-05-03 2013-11-07 Globalfoundries Inc. Finfet compatible pc-bounded esd diode
US20140191319A1 (en) * 2013-01-04 2014-07-10 GlobalFoundries, Inc. Finfet compatible diode for esd protection
US20140252476A1 (en) * 2013-03-08 2014-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Rotated STI Diode on FinFET Technology

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