WO2018004496A1

WO2018004496A1 - A configurable latch circuit with low leakage current and instant trigger input

Info

Publication number: WO2018004496A1
Application number: PCT/TR2017/050233
Authority: WO
Inventors: Alper YAZAR
Original assignee: Aselsan Elektronik Sanayi Ve Ticaret Anonim Sirketi
Priority date: 2016-06-28
Filing date: 2017-06-01
Publication date: 2018-01-04
Also published as: TR201609051A2

Abstract

The present invention relates to latch circuit (1) which is connected between a power source and a load, which can be adjusted such that it will be latched/not latched depending on the configuration of the switches during application of the power for the first time, which can be closed again in a certain time after it is latched, and which essentially comprises three MOSFETs, four switches, four capacitors, a power input, a power output, a trigger output, and a suspension input.

Description

A CONFIGURABLE LATCH CIRCUIT WITH LOW LEAKAGE CURRENT AND INSTANT TRIGGER INPUT

Field of the Invention

The present invention is a latch circuit design which is especially designed for products operating with batteries, which can be adjusted to various forms of operations, which has low leakage current and instant trigger input and which is comprised of discrete components. The circuit can be considered as an on/off switch which is connected in series between the power source and the load. When a short pulse is given through the trigger input, the circuit latches itself; it continues to transfer power to the load even if the trigger pulse is removed. After a while, it enters to open circuit state again. If desired, it can be enabled to stay in continuous closed circuit state via a control signal. The circuit can latch itself for one time as if a trigger signal has been driven when power is applied from the power supply for the first time depending on the chosen configuration. According to this choice, the current to be drawn by the circuit (the leakage current) from the power supply when it becomes open circuit can be adjusted, and it can be kept at μΑ or nA level. The designed circuit is suitable for systems which will wait for a trigger for a long time and which requires low stand-by current. Background of the Invention

Latch topologies enable circuits to remain in open or closed state in accordance with an input signal, and circuits continue to maintain their last states even if the input signal is removed. United States Patent Document no US5790961, an application known in the state of the art, discloses a circuit requiring a switch which comprises a microcontroller and latches itself mechanically. United States Patent Document no US6255875 Bl, an application known in the state of the art, discloses a latch circuit which comprises four switches and for FET transistors.

In several embodiments known in the state of the art, on/off operations are performed in turn by using the same trigger input. The circuit which is applied for is opened from the trigger input, and if desired, it is closed back after a certain time or it can always be kept open with a control signal run from outside.

The Problems Solved with the Invention

The present invention particularly provides a latch circuit which enables to reduce the power consumptions of systems operating with battery in stand-by situations. For this purpose, depending on the selected configuration, a latch circuit with instant trigger input designed with discrete components is provided which can be adjusted such that it will be latched/not latched during the first time application of power, and which can be closed back in a certain time if desired after it is latched.

Detailed Description of the Invention

A latch circuit developed to fulfill the objectives of the present invention is illustrated in the accompanying figures, in which:

Figure 1 is the schematic of the latch circuit.

Figure 2 is the flow diagram showing the operating principle of the latch circuit.

The components shown in the figures are each given reference numbers as follows:

1. Latch circuit Ri. First resistor 2. Input port R₂. Second resistor

3. Output port R₃. Third resistor

4. Trigger port R4. Fourth resistor

5. Suspension port R5. Fifth resistor

Ql. First MOSFET R6. Sixth resistor

Q2. Second MOSFET R₇. Seventh resistor

Q₃. Third MOSFET Re. Eighth resistor

SWi. First switch R9. Ninth resistor

SW₂. Second switch Rio. Tenth resistor

SW₃. Third switch Ci. First capacitor

SW₄. Fourth switch C₂. Second capacitor

Vi„. Input voltage C₃. Third capacitor

Vout. Output voltage C4. Fourth capacitor

D. Drain terminal

S. Source terminal

G. Gate terminal

The inventive latch circuit (1), which is connected between a power source and the load, essentially comprises

- at least one input port (2) to which the power source to be switched is connected,

at least one output port (3) to which the loads to switched on and off are connected,

a first MOSFET (Qi) which is connected between the input port (2) connected to the source terminal (S) and the output port (3) connected to the drain terminal (D),

a fourth switch (SW₄) which is connected between the input port (2) and the source terminal (S) of the first MOSFET (Qi),

a first switch (SWi) one terminal of which is between the fourth switch (SW₄) and the source terminal (S) of the first MOSFET (Qi), and the other terminal of which is connected to the gate terminal (G) of the first MOSFET (QO through a first capacitor (CO,

a trigger port (4) which is connected to the gate terminal (G) of the first MOSFET (QO through a second resistor (R₂), and to which the instantaneous trigger input is driven,

a second MOSFET (Q₂) the drain terminal (D) of which is connected to the gate terminal (G) of the first MOSFET (QO through a third resistor (R₃), and the source terminal (S) of which is connected to the ground,

a second capacitor (C₂) which is connected between the drain terminal (D) of the second MOSFET (Q₂) and the ground through a third switch (SW₃), a second switch (SW₂) which is connected in series with a fourth resistor (R₄) on a branch which is parallel to a branch on which the third switch (SW₃) is present,

a third capacitor (C₃) which is connected between the gate terminal (G) and the source terminal (S) of the second MOSFET (Q₂),

a third MOSFET (Q₃) the drain terminal (D) of which is connected to the gate terminal (G) of the second MOSFET (Q₂) through a sixth resistor (R₆), and the source terminal (S) of which is connected to the ground,

a fourth capacitor (C₄) which is connected between the gate terminal (G) of the third MOSFET (Q₃) and the ground,

a suspension port (5) which is connected to the gate terminal (G) of the third MOSFET (Q₃) through a ninth resistor (R9), and wherein the control signal is driven in order to prevent the latched circuit from entering to the closed state again.

The inventive latch circuit (1) the schematic of which is given in Figure 1 is designed with components comprised of MOSFET, transistors, resistors and capacitors that can easily be found in the market. Ten resistors are used in the latch circuit (1). The arrangement of the said resistors is as follows: the first resistor (R0 is connected between the source terminal (S) and the gate terminal (G) of the first MOSFET (Qi). The second resistor (R₂) is connected between the trigger port (4) and the gate terminal (G) of the first MOSFET (Qi) The third resistor (R₃) is connected between the gate terminal (G) of the first MOSFET (Qi) and the drain terminal (D) of the second MOSFET (Q₂). The fourth resistor (R₄) is connected between the second switch (SW₂) and the ground. One terminal of the fifth resistor (R₅) is connected between the output port (3) and the drain terminal (D) of the first MOSFET (Qi), and its other end is connected to the gate terminal (G) of the second MOSFET (Q₂). The sixth resistor (R₆) is connected between the gate terminal (G) of the second MOSFET (Q₂) and the drain terminal (D) of the third MOSFET (Q₃). One terminal of the seventh resistor (R₇) is connected to the gate terminal (G) of the second MOSFET (Q₂) and its other terminal is connected to the ground. The eighth resistor (R₈) is connected between the output port (3) and the gate terminal (G) of the third MOSFET (Q₃)_. The ninth resistor (R9) is connected between the suspension port (5) and the gate terminal (G) of the third MOSFET (Q₃)_. The tenth resistor (Ri₀) is connected between the gate terminal (G) of the third MOSFET (Q₃) and the ground.

The working principle of the said latch circuit (1) is given as flow diagram in Figure 2. The names of the states shown in Figure 2 are written as italic in the explanations below. Furthermore, in the flow diagram a switch being closed indicates that it is in conduction, that is it is in closed circuit state; and a switch being open indicates that it is not in conduction, that is it is in open circuit state. The input port (2) shown in Figure 1 shows the power input of the circuit. The power source to be switched is connected to the said port. The output port (3) is the power output of the circuit. The loads to be switched on and off are connected to the said output. The designed switching circuit (1) can be considered as a serial switch connected to the positive line. Within this context, the input of the switch is the input port (2), and its output is the output port (3). The trigger port (4) is an active low port from which the circuit receives instantaneous trigger. The suspension port (5) is an active low control port which controls the operation of the timer part which causes the circuit to enter to open circuit state after a certain time from the closed circuit state. Other switches (the first switch (SWi), the second switch (SW₂) and the third switch (SW₃)) except from the fourth switch (SW₄) located in the latch circuit (1) are put in order to show that the latch circuit (1) can be adjusted in different configurations. After the operation configuration is determined, there is no situation which requires the use of the said switches. By considering the positions of the switches in the desired configuration, the circuit can be fixed and the switches can be removed. The fourth switch (SW₄) is included in order to emulate application of the input power. When the fourth switch (SW₄) is open, the circuit will enter to the Closed state whatever the state shown in Figure 2 is. The latch circuit (1) can be adjusted such that it will be Closed Circuit or Open Circuit independent from the trigger input with the help of the first switch (SWi), the second switch (SW₂) and the third switch (SW₃) after the fourth switch (SW₄) is closed. This selection is essentially performed with adjusting the C_GSQI/C_DSQ2 ratio. The said capacitances show the capacitances between the gate terminal (G) - source terminal (S) of the first MOSFET (Qi) and the drain terminal (D) - source terminal (S) of the second MOSFET (Q₂), respectively. The said capacitances are essentially comprised of parasitic capacitances of the MOSFETs when the first switch (SWi) and the third switch (SW₃) are open. When the first switch (SWi) is closed, C_GSQI is comprised of the first capacitor (Ci) and the parasitic capacitance of the gate terminal (G) - source terminal (S) of the first MOSFET (Qi). Similarly, when the third switch (SW₃) is closed, C_DSQ2 is comprised of the second capacitor (C₂) and the drain terminal (D) - source terminal (S) parasitic capacitance of the second MOSFET (Q₂). Although the parasitic capacitances of the MOSFETs are not under the control of the user, capacitors such as the first capacitor (Ci) and the second capacitor (C₂) can be connected and disconnected so that the C_GSQI/C_DSQ2 ratio can be changed. When the fourth switch (SW₄) is closed, if the condition that the voltage between the source terminal (S) - gate terminal (G) of the first MOSFET (Qj) is higher than the threshold voltage of the first MOSFET (Qi) (VSGQI > I thQi l) is provided for a sufficient time period, the output voltage (V_out) will start increasing to the input voltage (Vi_n) value. At the same time the voltage on third capacitor (C₃) will increase in a level the value of which is determined by the seventh resistor (R₇), the fifth resistor (R5) and the output voltage (V_out) through the fifth resistor (R5). If the conduction time of the first MOSFET (Qi) is long enough, the condition that the voltage between the gate terminal (G) - source terminal (S) of the second MOSFET (Q₂) is higher than the threshold voltage of the second MOSFET (Q₂) (VGSQ2 > thQ₂) can be obtained. In this case, the second MOSFET (Q₂) will start to conduct. When the ratio of the resistance value of first resistor (Ri) to the resistance value of third resistor (R₃) (Ri/R₃) is selected high enough, the voltage dropped on the first resistor (Ri) due to the current that will pass through the second MOSFET (Q₂) will keep the first MOSFET (Qi) in conduction. Under these conditions as long as the first MOSFET (Qi) is in conduction, the second MOSFET (Q₂) will also be in conduction; and thus the output voltage (V_out) will almost be equal to the input voltage (Vi_n) (V_out ~ Vi_n) since both transistors will keep themselves in conduction. At this point, the latch circuit (1) latches itself. In the meantime, the fourth capacitor (C₄) continues to charge just as the third capacitor (C₃). For proper operation, upon voltage increase on the fourth capacitor (C₄), the condition that the voltage between the gate terminal (G) - source terminal (S) of the third MOSFET (Q₃) is higher than the threshold voltage of the third MOSFET (Q₃) (VGSQ3 > thQ₃) should be satisfied in much later time that the condition of VGSQ₂ >

upon the voltage increase on the third capacitor (C₃). Therefore, the values of the components should be selected in this way. While the second MOSFET (Q₂) being in conduction latches the circuit, the third MOSFET (Q₃) will force the second MOSFET (Q₂) to cut-off conduction when it starts conducting. When the second MOSFET (Q₂) stops conduction, the first MOSFET (Qi) will also stop the conduction and output voltage (V_out) will approximately be 0V (V_out ~ 0V). In order that the circuit will close itself back after a certain time; the values of the fifth resistor (R₅) and the seventh resistor (R₇) should be selected such that the value of the parallel equivalent resistance they form will be much higher (R₆«R5//R₇) than the value of the sixth resistor (R₆). After a certain time the latch circuit (1) latches itself, it can close itself. However, the said closing can be stopped if desired. The closing feature is controlled via the suspension port (5). When the condition that the parallel equivalent resistance value formed by the eighth resistor (R₈) and the tenth resistor (Rio) is much higher (R9«R₈//Rio) than the value of the ninth resistor (R9) is met, if the suspension port (5) is kept at low level from the outside (if low level voltage is applied), the fourth capacitor (C₄) will not be charged and the third MOSFET (Q₃) cannot conduct in this time period. This enables the circuit to remain latched. If it is considered that there is an intelligent component on the part which is powered by the circuit, this component can keep the suspension port (5) in low level as long as power is required. When the power is desired to be cut off, the suspension port (5) is left at floating level. After this point, when the fourth capacitor (C₄) is charged sufficiently, the third MOSFET (Q₃) will start conduction and inhibit the latch structure. At this point, the circuit will remain in Open Circuit state shown in Figure 2.

The trigger port (4) of the circuit is used for entering to Closed Circuit state from the Open Circuit state. When signal in a sufficient length is applied from there, the first MOSFET (Qi) will start conduction, and the circuit will start operating as described above. The second resistor (R₂) is used to limit the current that will flow into the trigger source (trigger port (4)) at a safe value. The trigger signal should remain in low level long enough to allow the formation of latch structure. Since the circuit can latch itself after this point, the trigger signal can be removed. Applying a high level trigger signal can cause the circuit to close before time out (before the third MOSFET (Q₃) starts conduction). If this is desired, the voltage level of the closing signal to be applied from the trigger input should be selected considering the input voltage (Vi_n), the first resistor (Ri), the second resistor (R₂) and the third resistor (R₃). Even if the circuit topology will allow this usage, in the design objective of the invention the trigger input is only for enabling transition from Open Circuit state to Closed Circuit state. Consider that the circuit is configured to latch itself when power is applied (that is in case the fourth switch (SW₄) is closed). In order to realize this situation, as stated before, C_GSQI/C_DSQ2 ratio should be adjusted properly. When this ratio is much smaller than one («1), it can be thought that the circuit will steadily show this characteristic. The value of parasitic capacitances of other circuit elements and MOSFETs has great importance in determining the suitable ratio. In order to provide this condition, the third switch (SW₃) is closed and C_DSQ2 is increased (by connecting the second capacitor (C₂)) and the C_GSQI capacitance is kept at a lower value by leaving the first switch (SWi) open. Let's consider that the circuit can latch itself when power is given in this way. Think that the circuit will bring itself to Open Circuit state with time out feature after a certain time after power is applied. While waiting in this way, the circuit will enter to Closed state when the input power of the circuit is removed. Then, when the power is applied immediately, the circuit may not latch itself even though the First Power Option is Closed Circuit. The reason for this is that the second capacitor (C₂) is charged nearly to output voltage (Vi_n) level after the second MOSFET (Q₂) stops conduction when the circuit enters to Open Circuit state. However, V_GSQI and D_SQ2 voltages should nearly be 0V so that the circuit can latch itself when the power is applied. The second capacitor (C₂) can only be discharged by its internal leakage current and the through the second MOSFET (Q₂). This discharge rate may not be suitable for the purpose for which the circuit will be used. If the discharge is not realized, the circuit cannot latch itself when the power is applied again.

For this, a discharge resistor which is a fourth resistor (R₄) that can be selected with the second switch (SW₂) is added. This resistor discharges the second capacitor (C₂) after entering to Closed state. The discharge rate will increase as the resistance value of the fourth resistor (R₄) decreases and the recovery time required for the circuit to enter to the Closed Circuit state by latching itself when power is applied after entering to the Closed state decreases. However, the value of the said fourth resistor (R₄) increases the current (leakage current) drawn by the circuit from the input in Open Circuit state. A current will flow through the first resistor (Ri), third resistor (R₃) and fourth resistor (R₄) in the Open Circuit state. The resistance values should be selected considering a balance between the recovery time of the circuit and the leakage current. If the circuit is configured such that it will be in the Open Circuit state when power is applied, there will be no use of using the said resistance as well as there will be a disadvantage of increasing the leakage current.

If it is wanted to configure the circuit such that it will not latch itself when power is applied (that is when the fourth switch (SW₄) is closed), C_GSQI/C_DSQ2 » 1 condition should be provided for stable operation. In order to provide this, the first switch (SWi) is closed, and C_GSQI capacitance is increased by means of the first capacitor (Ci). At the same time, the third switch (SW₃) is kept open, and thus the C_DSQ2 capacitance is kept at a lower value. As it is stated before, in this case it is not required to connect the fourth resistor (R₄), and leaving the second switch (SW₂) open will enable the leakage current to remain low.

The operation principle of the circuit expressed in Figure 2 can be explained as below by using the schematic in Figure 1: The Closed state indicates that the fourth switch (SW₄) is open circuit, no power is applied to the circuit. When the fourth switch (SW₄) is closed, Power is applied event takes place. When the fourth switch (SW₄) is opened in any state, that is when the power of the circuit is cut off, the Power off event takes place and the circuit enters to Closed state. When the first switch (SWi) is open and the third switch (SW₃) is closed, "First Power Option" will be Closed Circuit and the circuit will enter to Closed Circuit State as soon as the power is applied if the component values are selected suitably. When the switches are adjusted in exact opposite way, "First Power Option" will be Open circuit and the circuit will enter to Open Circuit State as soon as the power is applied. Closed Circuit corresponds to the state where the first MOSFET (Qi) is in conduction. In this case, the output voltage (V_out) at the output port (3) will nearly be equal to the input voltage (Vi_n) at the input port (2) (V_out ~ i_n). If the suspension port (5) will be kept at low level from outside in this state, the Time Out will be Disabled and the circuit will remain in Closed Circuit state. When the suspension port (5) is left at floating level, the Time Out will be Enabled and the circuit will enter to Countdown state. In this case, the first MOSFET (Qi) will remain in conduction. However, in the meantime the fourth capacitor (C₄) will be charged. If the suspension port (5) is driven with low level signal before the voltage on this capacitor put the third MOSFET (Q₃) in conduction and reaches a level that will inhibit the latch structure, Time Out Disabled event takes places and it enters from Countdown state to Closed Circuit state. However, if the fourth capacitor (C₄) is charged enough so that the third MOSFET (Q₃) will start conduction in Countdown state, Time is up event takes place, and the circuit closes itself and enters to Open Circuit state. The first MOSFET (Qi) will not be in conduction in Open Circuit state. In this case, it can be entered to Closed Circuit state with a low level trigger signal to be applied to the trigger port (4). If the circuit is configured such that the First Power Option will be Closed Circuit, it can be entered to Closed Circuit state again by alternatively realizing the Power off and then Power is applied events. In order to realize this transitions, as previously stated, it should be V_DSQ2 ~ 0V. Otherwise, First Power Option will not operate properly. The fourth resistor (R₄) (discharge load) can be activated for discharge acceleration.

The circuit is built with the values and components given in Table 1, and the leakage currents are measured according to several circumstances. Table 1. Exemplary values to be used for the components in the latch circuit

Table 2. Different configurations of circuit depending on the positions of the switches

resistor deactivated

For the configurations given in Table 2, the leakage currents of the circuit built with materials given in Table 1 in Open Circuit state with measurements performed at ambient temperature of 25 °C are given in Table 3 for different operation voltages.

Table 3. The leakage currents of Latch Circuit (1) measured for different input voltages (V_in)

Claims

A latch circuit (1), which is connected between a power source and a load, which can be adjusted such that it will be latched/not latched depending on the configuration of the switches during application of the power for the first time, which can be closed again in a certain time after it is latched, essentially characterized by

a first MOSFET (Qi) which is connected between an input port (2) to which the power source to be switched to the source terminal (S) is connected and an output port (3) to which the loads to be switched on and off by being switched to the drain terminal (D),

- a fourth switch (SW₄) which is connected between the input port (2) and the source terminal (S) of the first MOSFET (Qj),

- a first switch (SWi) one terminal of which is between the fourth switch (SW₄) and the source terminal (S) of the first MOSFET (Qi), and the other terminal of which is connected to the gate terminal (G) of the first MOSFET (Qi) through a first capacitor (Ci),

- a trigger port (4) which is connected to the gate terminal (G) of the first MOSFET (Qi) through a second resistor (R₂), and to which the instantaneous trigger input is given,

- a second MOSFET (Q₂) the drain terminal (D) of which is connected to the gate terminal (G) of the first MOSFET (Qi) through a third resistor (R₃), and the source terminal (S) of which is connected to the ground,

- a second capacitor (C2) which is connected between the drain terminal (D) of the second MOSFET (Q₂) and the ground through a third switch (SW₃),

- a second switch (SW₂) which is connected in series to a fourth resistor (R₄) on a branch parallel to a branch on which the third switch (SW₃) is present,

- a third capacitor (C₃) which is connected between the gate terminal (G) and the source terminal (S) of the second MOSFET (Q₂), - a third MOSFET (Q₃) the drain terminal (D) of which is connected to the gate terminal (G) of the second MOSFET (Q₂) through a sixth resistance (R₆), and the source terminal (S) of which is connected to the ground,

- a fourth capacitor (C₄) which is connected between the gate terminal (G) of the third MOSFET (Q₃) and the ground,

- a suspension port (5) which is connected to the gate terminal (G) of the third MOSFET (Q₃) through a ninth resistor (R9), and wherein the control signal is given in order to prevent the latched circuit from entering to the closed state again.

A latch circuit (1) according to claim 1, characterized by first resistor (Ri) which is connected between the source terminal (S) and gate terminal (G) of the first MOSFET (Ql), and third resistor (R₃) which is connected between the gate terminal (G) of the first MOSFET (Qi) and the drain terminal (D) of the second MOSFET (Q₂).

A latch circuit (1) according to claim 1, characterized by second resistor (R₂) which is connected between the trigger port (4) and the gate terminal (G) of the first MOSFET (Qi)_, and which enables to limit the current to flow into the trigger port (4).

A latch circuit (1) according to claim 1, characterized by fourth resistor (R₄) which is connected between the second switch (SW₂) and the ground, and which enables the second capacitor (C₂) to discharge.

A latch circuit (1) according to claim 1, characterized by fifth resistor (R₅) one terminal of which is connected between the output port (3) and the drain terminal (D) of the first MOSFET (Qi), and the other terminal of which is connected to the gate terminal (G) of the second MOSFET (Q₂), and a seventh resistor (R₇) one terminal of which is connected to the gate terminal (G) of the second MOSFET (Q₂) and the other terminal of which is connected to the ground.

6. A latch circuit (1) according to claim 5, characterized by sixth resistor (R₆) which is connected between the gate terminal (G) of the second MOSFET

(Q₂) and the drain terminal (D) of the third MOSFET (Q₃), and the value of which is smaller than the value of the parallel equivalent resistance formed by the fifth resistor (R₅) and the seventh resistor (R₇).

7. A latch circuit (1) according to claim 1, characterized by eighth resistor (R₈) which is connected between the output port (3) and the gate terminal (G) of the third MOSFET (Q₃), and a tenth resistor (Rio) which is connected between the gate terminal (G) of the third MOSFET (Q₃) and the ground.

8. A latch circuit (1) according to claim 7, characterized by ninth resistor (R9) which is connected between the suspension port (5) and the gate terminal (G) of the third MOSFET (Q₃), and the value of which is smaller than the parallel equivalent resistance value formed by the eighth resistor (R₈) and the tenth resistor (Rio).

9. A latch circuit (1) according to claim 1, characterized by fourth switch (SW₄) which enables the input power to be applied/cut off.

10. A latch circuit (1) according to claim 9, characterized by first MOSFET (Qi) which can start conduction when the fourth switch (SW₄) is closed.

11. A latch circuit (1) according to claim 10, characterized by second MOSFET (Q₂) which starts conduction after the first MOSFET (Qi) starts conduction.

12. A latch circuit (1) according to claim 5, characterized by third capacitor (C₃) the value of which increases to a level determined by the fifth resistor (R₅), seventh resistor (R₇) and output voltage (V_out) through the fifth resistor (R₅) upon the second MOSFET (Q₂) passing to the conduction.

13. A latch circuit (1) according to claim 1 or 2, characterized by first resistor (Ri) which keeps the first MOSFET (Qj) with the voltage dropped thereon by means of the current passing through the second MOSFET (Q₂).

14. A latch circuit (1) according to claim 12, characterized by third MOSFET (Q₃) which stops the conduction of the second MOSFET (Q₂), when it is in conduction.

15. A latch circuit (1) according to claim 14, characterized by second MOSFET (Q₂) which stops the conduction of the first MOSFET (Qi), when it stops its conduction.

16. A latch circuit (1) according to claim 1, characterized by suspension port (5) wherein low level voltage is applied enabling that the fourth capacitor (C₄) cannot be charged through the eighth resistor (R₈) in order to prevent the third MOSFET (Q₃) from starting conduction.

17. A latch circuit (1) according to claim 1 or 16, characterized by suspension port (5) which can be left at floating level in order to enable the third MOSFET (Q₃) to conduct and therefore inhibit the latch structure by charging the fourth capacitor (C₄).

18. A latch circuit (1) according to claim 15, characterized by trigger port (4) to which the signal to activate the first MOSFET (Qi) for conduction for entering from Open Circuit state to Closed Circuit state.

19. A latch circuit (1) according to claim 15, characterized by trigger port (4) to which a high level trigger signal is given for closing the circuit before the third MOSFET (Q₃) starts conduction.