WO2017215710A1 - Composant semi-conducteur doté d'électrodes en faces avant et arrière et son procédé de fabrication - Google Patents

Composant semi-conducteur doté d'électrodes en faces avant et arrière et son procédé de fabrication Download PDF

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Publication number
WO2017215710A1
WO2017215710A1 PCT/DE2017/100498 DE2017100498W WO2017215710A1 WO 2017215710 A1 WO2017215710 A1 WO 2017215710A1 DE 2017100498 W DE2017100498 W DE 2017100498W WO 2017215710 A1 WO2017215710 A1 WO 2017215710A1
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WO
WIPO (PCT)
Prior art keywords
layer
semiconductor component
electrically insulating
component according
semiconductor
Prior art date
Application number
PCT/DE2017/100498
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German (de)
English (en)
Inventor
Bernd Stannowski
Onno GABRIEL
Natalie PREISSLER
Rutger Schlatmann
Original Assignee
Helmholtz-Zentrum Berlin Für Materialien Und Energie Gmbh
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Filing date
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Application filed by Helmholtz-Zentrum Berlin Für Materialien Und Energie Gmbh filed Critical Helmholtz-Zentrum Berlin Für Materialien Und Energie Gmbh
Publication of WO2017215710A1 publication Critical patent/WO2017215710A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1872—Recrystallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a semiconductor device with front and rear electrode and a method for its preparation.
  • Semiconductor devices are electronic components that consist of
  • Semiconductor materials i. Materials of different conductivity type, as well as metals and insulators exist. Their mode of action or function is based on the behavior, in particular the movement, of charge carriers. According to the prior art, there are a variety of semiconductor devices with different functions and thus with
  • different layer arrangements having on a substrate at least one contact layer for carriers of a conductivity type, on which one or more active semiconductor layers and another
  • the person skilled in the art will arrange contacts on the front and rear sides of the semiconductor component or contact the semiconductor component on one side, ie position both contacts on the front or rear side.
  • the contacts applied during the further processing of the semiconductor component should not entail undesired diffusion of impurities from the contact material or from the substrate.
  • the contacts should meet further requirements, for example, they should ensure a good optical reflection and the survive in the further processing of the semiconductor device possibly necessary high temperatures.
  • semiconductor devices are also known as functional layers adjacent to the contact layers.
  • Both sides contacted semiconductor devices can be made of p-type or n-type conductive silicon. Often, they are realized as a semiconductor diode which, when at least one of the contacts is translucent, as a photodiode (light detector) or as a solar cell (for energy conversion) is used.
  • the silicon is usually contacted on both sides in the form of a crystalline wafer, but can also, as in this invention, be applied as a silicon layer on a substrate.
  • the generated backside contact is selective and passivates the silicon layer.
  • the whole-area passivation layer is very thin (1 to 2 nm), so that the charge carriers can tunnel through it.
  • a thin layer of highly doped silicon also applied over the entire surface of the passivation layer, in combination with the underlying layers, enables a lossless outflow of the current from the solar cell.
  • most of the prior art publications follow the path of structuring one or more superimposed layers for improved contacting of the respective semiconductor device.
  • WO 2013/067 998 A1 describes a semiconductor wafer solar cell with a surface-passivated reverse side contacted on both sides, wherein a front-side electrode structure is provided and the rear side of the
  • Semiconductor wafer is surface-passivated with a layer.
  • Passivation layer is applied a backside metal electrode structure containing sintered metal particles.
  • a backside metal electrode structure containing sintered metal particles.
  • Contact areas which are realized through openings of the passivation layer, which may also be formed as a thin-film stack, contacts the back-side metal electrode structure, which is not applied over the entire area, the semiconductor wafer.
  • the openings occupy an area of less than 5% of the rear surface.
  • a first dielectric layer of silicon dioxide (S1O2) and a second dielectric layer of silicon nitride (SiNx) are arranged on the wafer back side.
  • the wafer has opposing conductivities produced on its front and back surfaces by doping.
  • a sacrificial layer is applied and thereon a metal layer which forms the backside contact. Via openings in the contact layer and the two dielectric layers, contact is made with the back surface of defined conductivity of the wafer.
  • Metal electrode layer and is shared with the sacrificial layer
  • DE 38 15 512 A1 describes a solar cell contacted on both sides with a reduced recombination speed of the charge carriers. For this purpose, at the back of the positive-conducting (p-type) semiconductor body and the
  • a passivation film is disposed on the back surface of the p-type Si substrate having a plurality of openings.
  • the passivation film is formed of alumina (Al 2 O 3) or niobium dioxide (NbO 2).
  • alumina Al 2 O 3
  • niobium dioxide NbO 2
  • between the passivation film and the back surface of the Si substrate is optionally one having a group III element,
  • the rear electrode is connected to the back surface of the Si substrate through the plurality of punctiform or line-shaped openings.
  • non-passivated back surface of the semiconductor layer can be improved.
  • Thin-film solar cell in superstrate configuration described.
  • the one-sided contacted layer arrangement is indeed produced with methods known from thin-film technology, but yet relatively complicated, since the
  • Structuring methods must be separated, nested, and manufactured.
  • contacted thin-film solar cell assembly also includes a
  • the p + layer of a pp + junction is provided with holes.
  • Aluminum is deposited on this layer to form electrical contacts with the p + layer.
  • the object of the invention is now to provide a further solution for a semiconductor device contacted on both sides with a layer arrangement which is improved in comparison with the prior art for the back contact, whereby the surfaces of the active layers of the semiconductor device are passivated and at the same time ensures good optical properties become.
  • a semiconductor device comprising on a substrate at least one contact layer for
  • Such a layer system prevents the diffusion of impurities from, for example, the back electrode into the at least one active semiconductor layer and passivates the back surface of the at least one active semiconductor layer and at the same time ensures good optical properties through its properties as a Bragg reflector.
  • the formation of a rear side field in the layer arrangement also improves the electrical back contact.
  • the use of such a layer system is possible for semiconductor components of various functions, in particular in those in which the properties mentioned are to be ensured.
  • the following embodiments of the invention relate to the individual layers in the semiconductor device.
  • the at least one active semiconductor layer is formed from crystalline silicon.
  • Preferred for this purpose is an Si layer applied, for example, by means of PECVD or electrode beam evaporation and subsequently produced by liquid-phase crystallization.
  • the thickness of the at least one active semiconductor layer is between 5 pm and 40 m.
  • the substrate is made of glass and the back electrode is formed of a refractory metal or the substrate and the back electrode are replaced by a metal foil.
  • the rear electrode is provided, this from a
  • refractory metal preferably molybdenum
  • Layer thickness should be between 100 nm and 1 pm.
  • inventions relate to the at least two dielectric layers which are formed from SiOx or SiN x or silicon oxynitride (SiOxNy) or Al 2 O 3 or silicon carbide (SiCx).
  • the layer thickness of the at least two dielectric layers is in each case between 50 nm and 400 nm.
  • the electrically conductive layer arranged between the two dielectric layers provision is made for them to be formed from a semiconductor layer of higher doping than for the at least one active semiconductor layer, the doping being between 1 ⁇ 10 19 cm -3 and 1 ⁇ 10 21 cm -3 and the layer thickness of the conductive layer is between 50 nm and 100 nm.
  • the highly doped semiconductor layer contributes to the quality improvement of the back contact layer.
  • Contact openings in the at least two dielectric layers - is intended to form these point or Hnienförmig.
  • the contact openings have a typical distance from each other of 0.5 pm to 500 pm and correspondingly a diameter of 50 nm to 50 pm and a width of 50 nm to 50 pm.
  • the side facing away from the substrate is the side facing away from the substrate
  • This silicon thin-film solar cell may then comprise, for example, an active semiconductor layer liquid-phase crystallized silicon of a conductivity type which forms the absorber layer, and a second active semiconductor layer of silicon with a direction opposite to the absorber layer conductivity type which forms the emitter layer.
  • the back electrode is one
  • the high-temperature-resistant conductive layer and the front-side electrode formed of a transparent conductive material.
  • Absorber layer be textured.
  • the layer arrangement described can be made of all-over formed back electrode and two electrically insulating dielectric intermediate layers, between which at least one electrically conductive layer is arranged, wherein the electrically insulating dielectric layers have mutually staggered contact openings.
  • the bottom cell is a Si-based thin-film cell
  • the top cell can then, for example, again be a silicon solar cell, but also a perovskite solar cell.
  • the method for producing a semiconductor component according to the invention comprises the following method steps: application of a back-side all-over electrode layer to a substrate, then production of a first electrically insulating dielectric layer with contact openings to the underlying back-side electrode,
  • PECVD plasma-enhanced chemical vapor deposition
  • PVD plasma-enhanced chemical vapor deposition
  • a deposition temperature in the range of 200 ° C to 600 ° C.
  • the material for the first dielectric layer SiO x or SiN x or SiO x N y or SiC x or AI2O3 is used as the material for the first dielectric layer SiO x or SiN x or SiO x N y or SiC x or AI2O3 and applied in a thickness of between 50 nm and 400 nm.
  • the punctiform contact openings are produced with a diameter of 50 nm to 50 pm and a distance of 0.5 pm to 500 pm and the line-shaped contact openings with a width of 50 nm to 50 m and a distance from each other 0.5 pm to 500 pm. Then the
  • Deposition of the semiconductor layer first an Si layer with a thickness of 5 pm to 40 pm by PECVD or electron beam evaporation
  • an emitter layer with the first active semiconductor layer is applied and then crystallized.
  • the crystallization of Silicon layer is carried out by liquid phase crystallization by means of laser beam in air or in vacuum or in an inert gas or by electron beam in a vacuum. For this reason, therefore, high-temperature resistant layers between the substrate and the semiconductor layer are necessary.
  • an emitter layer with the first active semiconductor layer is applied and then crystallized.
  • a front electrode layer of a transparent conductive oxide such as indium tin oxide or zinc oxide, deposited by PVD or evaporation.
  • a grid structure can also be applied as a further component of the front-side electrode.
  • it is provided to expose the back-side electrode after the application of the front-side electrode.
  • Semiconductor device based on liquid-phase crystallized silicon as an active semiconductor layer also two-sided contact, making the process easier to handle and cheaper.
  • the staggered positioning of the openings in the two dielectric layers requires less accuracy in introducing the openings, the materials used also allow process steps at high temperatures.
  • FIG. 1 shows a schematic representation of a silicon thin-film solar cell according to the invention in substrate configuration
  • Fig. 2 is a plan view of a possible distribution of point contacts in the two dielectric layers
  • Fig. 3 is a plan view of a possible distribution of linear
  • FIG. 1 schematically shows a silicon thin-film solar cell in FIG.
  • the back electrode 2 so arranged on a
  • Glass substrate 1 is a high-temperature resistant conductive layer and formed of molybdenum in a thickness of 400 nm. Between the back electrode 2 and absorber layer 7 are two electrically insulating dielectric
  • the intermediate layer 3 adjacent to the molybdenum layer 2 is formed from S 10 O 2, the intermediate layer 5 adjacent to the liquid-phase-crystallized silicon absorber layer 7 also consisting of S 10 O 2.
  • the highly doped semiconductor layer 4 is in this embodiment, an n ++ - doped crystalline 50 nm thick silicon layer, which also by
  • Liquid phase crystallization - in the same crystallization step as the absorber layer - is generated.
  • Interlayers 3, 5 have mutually offset holes with a
  • a front electrode layer is also made of a transparent conductive oxide (TCO), also not shown.
  • TCO transparent conductive oxide
  • ITO indium tin oxide
  • a metallic electrode grid may additionally be arranged on the ITO layer (not shown).
  • the surface of the absorber layer 7 facing away from the glass substrate 1 may have a texture for improving light trapping (also not shown).
  • the described silicon thin-film solar cell arrangement is produced by the following method steps: On a glass substrate 1, the backside electrode 2 made of molybdenum is first applied by means of PVD. Subsequently, the first dielectric layer 3 of S1O2 is deposited at a deposition temperature of 200 to 600 ° C. In this layer 3 now point-shaped openings. 6
  • a conductive layer 4 is deposited by means of PVD, which in this exemplary embodiment is a highly doped n ++ silicon layer.
  • the second dielectric layer 5 is applied from S 1O2, in which also punctiform openings 6 are introduced by laser. This is done analogously to the method steps as have already been described for the first dielectric layer 3. It should be noted here that the openings 6 in the first dielectric layer 3 and the openings 6 in the second dielectric layer 5 are offset from each other, so that a transverse conduction of the charge carriers in the
  • Electrode layer 2 with the absorber layer 7 of the silicon thin-film solar cell assembly is electrically connected.
  • a silicon layer is first applied by means of PECVD and then subjected to liquid phase crystallization by means of a laser.
  • the intermediate layers 3, 5 reduce the diffusion of impurities from the
  • the hetero emitter layer comprising an intrinsic and a p-type amorphous hydrogen-containing silicon layer, applied by means of PECVD (with thicknesses of 5 and 10 nm, respectively).
  • PECVD PECVD
  • the front-side electrode may have an additional electrode grid.
  • the thickness of the ITO layer in this embodiment is 80 nm. Is a textured surface of the
  • the absorber layer 7 is first patterned by anisotropic etching (eg, wet-chemical or dry by means of plasma) and the following Layers are deposited in accordance with the structure.
  • anisotropic etching eg, wet-chemical or dry by means of plasma
  • the exposure of the rear electrode is carried out by laser ablation or back etching (eg by means of reactive ion etching with O2 and SF6) through the layers to the Mo layer.
  • Figures 2 and 3 are each a possible arrangement of point and line-shaped arrangements of the contact openings in the two
  • liquid phase crystallized silicon known.
  • the layer system described comprises at least two dielectric layers with an intermediate highly conductive layer and in the dielectric layers offset from one another
  • the arrangement according to the invention enables series connection, as is usual in thin-film components, and does not require interlaced structures.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Manufacturing & Machinery (AREA)
  • Sustainable Development (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne un composant semi-conducteur doté d'électrodes en faces avant et arrière, comprenant sur un substrat au moins une couche de contact, pour des porteurs de charge d'un type de conductivité, en tant qu'électrode en face arrière, sur laquelle sont disposées au moins une couche semi-conductrice active et une électrode en face avant et entre l'électrode en face arrière et la ou les couches semi-conductrices actives est disposée au moins une couche intermédiaire. Selon l'invention, il est prévu au moins deux couches intermédiaires diélectriques électriquement isolantes et entre celles-ci au moins une couche électroconductrice, les deux couches diélectriques électriquement isolantes ou plus comprenant des ouvertures de contact disposées décalées les unes par rapport aux autres de sorte que l'électrode en face arrière, qui est formée sur toute la surface, et la ou les couches semi-conductrices actives sont reliées de manière électroconductrice. L'invention concerne en outre un procédé de fabrication.
PCT/DE2017/100498 2016-06-15 2017-06-14 Composant semi-conducteur doté d'électrodes en faces avant et arrière et son procédé de fabrication WO2017215710A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102016110965.7A DE102016110965B4 (de) 2016-06-15 2016-06-15 Halbleiter-Bauelement mit vorder- und rückseitiger Elektrode und Verfahren zu dessen Herstellung
DE102016110965.7 2016-06-15

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Publication Number Publication Date
WO2017215710A1 true WO2017215710A1 (fr) 2017-12-21

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DE (1) DE102016110965B4 (fr)
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Citations (8)

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Publication number Priority date Publication date Assignee Title
US4395583A (en) 1980-04-30 1983-07-26 Communications Satellite Corporation Optimized back contact for solar cells
DE3815512A1 (de) 1988-05-06 1989-11-16 Telefunken Electronic Gmbh Solarzelle mit verminderter effektiver rekombinationsgeschwindigkeit der ladungstraeger
US20090301543A1 (en) * 2008-06-04 2009-12-10 Solexant Corp. Thin film solar cells with monolithic integration and backside contact
GB2471732A (en) 2009-06-22 2011-01-12 Rec Solar As Back surface passivation solar cell
WO2013067998A1 (fr) 2011-11-08 2013-05-16 Q-Cells Se Cellule solaire à plaque de semi-conducteur, mise en contact des deux côtés, sa face arrière ayant subi une passivation de surface
WO2013102181A1 (fr) * 2011-12-30 2013-07-04 Solexel, Inc. Métallisation de cellules solaires à plusieurs niveaux
US20140102509A1 (en) * 2012-10-12 2014-04-17 International Business Machines Corporation Solar cell with reduced absorber thickness and reduced back surface recombination
US20150021439A1 (en) 2012-02-01 2015-01-22 Herakles Space vehicle with electric propulsion and solid propellant chemical propulsion

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US20070295399A1 (en) 2005-12-16 2007-12-27 Bp Corporation North America Inc. Back-Contact Photovoltaic Cells
CN104882513A (zh) 2009-04-22 2015-09-02 泰特拉桑有限公司 通过局部激光辅助转变太阳能电池中的功能膜得到的局部金属接触
CN104471716B (zh) 2012-07-19 2017-08-29 日立化成株式会社 钝化膜、涂布型材料、太阳能电池元件及带钝化膜的硅基板

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4395583A (en) 1980-04-30 1983-07-26 Communications Satellite Corporation Optimized back contact for solar cells
DE3815512A1 (de) 1988-05-06 1989-11-16 Telefunken Electronic Gmbh Solarzelle mit verminderter effektiver rekombinationsgeschwindigkeit der ladungstraeger
US20090301543A1 (en) * 2008-06-04 2009-12-10 Solexant Corp. Thin film solar cells with monolithic integration and backside contact
GB2471732A (en) 2009-06-22 2011-01-12 Rec Solar As Back surface passivation solar cell
WO2013067998A1 (fr) 2011-11-08 2013-05-16 Q-Cells Se Cellule solaire à plaque de semi-conducteur, mise en contact des deux côtés, sa face arrière ayant subi une passivation de surface
WO2013102181A1 (fr) * 2011-12-30 2013-07-04 Solexel, Inc. Métallisation de cellules solaires à plusieurs niveaux
US20150021439A1 (en) 2012-02-01 2015-01-22 Herakles Space vehicle with electric propulsion and solid propellant chemical propulsion
US20140102509A1 (en) * 2012-10-12 2014-04-17 International Business Machines Corporation Solar cell with reduced absorber thickness and reduced back surface recombination

Non-Patent Citations (3)

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Title
IN SOLAR ENERGY MATERIALS & SOLAR CELLS, vol. 117, 2013, pages 505 - 511
M.A. GREEN, IN SOLAR ENERGY, vol. 77, 2004, pages 857 - 863
SOLAR ENERGY MATERIALS & SOLAR CELLS, vol. 131, 2014, pages 100 - 104, Retrieved from the Internet <URL:http://www.bine.info/themen/erneuerbareenergien/photovoltaik/news/weltrekord-fuer-beidseitig-kontaktierte-siliciumsolarzellen>

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DE102016110965B4 (de) 2019-03-14

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