WO2017215030A1 - Storage device having search function, and search method thereof - Google Patents

Abstract

Provided are a storage device having a search function, and a search method thereof; the storage device comprises an instruction decoder, a controller, an address generator and decoder, a storage-device set, and a search analyzer set, wherein: the instruction decoder is used for instruction-decoding a received instruction and producing a control signal; the controller is used for controlling the generation of a first address, and the increment, decrement, reset, and hold of the address; the address generator and decoder is used for producing an initial address used for searching, and decoding the address to obtain an address signal; the search analyzer set comprises search analyzers in a one-to-one correspondence with the storage device; according to the address signal and the control signal, label, search, categorize, and read operations are performed on the data in the corresponding storage device, and a search result is outputted. The time of usage of the described storage device and search method thereof does not increase with an increase in the amount of data; the data search speed is significantly increased in big-data situations, and search speed is not affected by hardware or system read/write bottlenecks.

Description

Memory with query function and query method thereof Technical field

The present invention relates to the field of integrated circuit technologies, and in particular, to a memory with a query function and a query method thereof.

Background technique

In the prior art, the memory chip is a single storage function, and a read command is issued to the memory through a computer. After the computer receives the returned data, the processor processes the data accordingly. For large-scale data storage, a plurality of memories are generally used. The form of the array expands the storage size, but the disadvantage is that the query speed cannot keep up with the expansion speed of the storage scale.

Data query technology: The hardware mainly consists of a storage system and a computing system, and relies on database software or a distributed system infrastructure such as hadoop to implement data query. This kind of system has a very slow query speed under the PB level big data condition, and it is difficult to meet the requirements of real-time query. And as the amount of data grows, it will be difficult to cope with the future EB-level data volume and even higher levels of data.

A high-speed memory is disclosed in Chinese Patent No. 201310591511.0, which includes: a charging circuit, a lithium battery, a low leakage storage circuit and a read/write control circuit; the charging circuit is connected between the power source and the lithium battery, For charging the lithium battery; when the power is turned off, cutting off a leakage path of the battery; the read/write control circuit is connected to a power source and a low leakage storage circuit, when the power is turned on, a read or write operation of the low leakage storage circuit; the lithium battery, when the power is turned off, is used to supply power to the low leakage storage circuit, the low leakage storage circuit maintaining stored information. Although the scheme in this reference can reduce the write operation time of the memory and increase the reading speed. However, for large-scale data, in order to realize the query of the data, the data in the memory can still be read one by one, and then the processor judges whether the data satisfies the query condition, and the query speed of the whole system is very slow.

Summary of the invention

The technical problem to be solved by the present invention is to provide a memory with query function for fast and real-time querying of data and an inquiry method thereof by using an embedded data query analyzer for the defect of slow query speed in the prior art.

The technical solution adopted by the present invention to solve the technical problem thereof is:

The invention provides a memory with query function, including an instruction decoder, a controller, and an address

Health and decoder, memory bank and Query Analyzer group, where:

The instruction decoder is configured to decode the received instruction and generate a control signal;

The controller is configured to control the generation of the first address, the incrementing, decrementing, resetting, and maintaining of the address according to the result of the instruction decoding;

The address generation and decoder is configured to generate a start address used by the query, and perform address decoding to obtain an address signal;

The memory group includes a plurality of memories connected in parallel with each other;

The query analyzer group includes a query analyzer corresponding to the memory one by one, each query analyzer obtains a control signal from the instruction decoder through the instruction bus, and obtains an address signal from the address generation and the decoder through the address bus, according to The address signal and the control signal mark, query, classify and read the data in the corresponding memory, and output the query result through the data output bus.

Further, the query analyzer of the present invention includes a relationship analyzer, a type analyzer, and a plurality of registers;

The type analyzer is configured to analyze the type of data output from the memory, output the data to a register or a relationship analyzer, and output the type analysis result to the relationship analyzer;

The relationship analyzer is configured to perform data relationship analysis with the data outputted from the memory according to the immediate value in the instruction, and determine whether to output the data.

Further, the query analyzer of the present invention further includes a first memory for storing a result of analyzing the data by the relationship analyzer according to the control instruction.

Further, the register of the present invention includes a first register, a second register, and a register file;

a first register is disposed between the first memory and the relationship analyzer for registering data output from the first memory;

The second register is connected to the relationship analyzer for registering whether data in the first memory has valid data;

The register file is placed between the type analyzer and the relational analyzer to store the collection data.

The invention provides a query method for a memory with query function, comprising the following steps:

S1, the instruction decoder performs instruction decoding on the instruction to obtain a control signal;

S2, the controller controls the address generation according to the control signal, and the decoder generates the first address and performs address decoding to obtain an address signal, and the memory outputs the data at the address;

S3. The query analyzer performs a label scan, a query scan, a classification scan, and a read operation on the data output from the memory according to the control signal;

S4, outputting the query result through the data output bus.

Further, the specific method for marking scanning in step S2 of the present invention includes:

Step 1, the controller controls the address generator to generate a starting address, reads the data in the address in the memory DataA={A1, A2}, and outputs an output DataA to the type analyzer;

Step 2. If the data type is data, output A2 to the relationship analyzer;

If the data type is an address, input A2 as an address to the address input end of the register file, and the register file outputs the data C corresponding to the address to the relationship analyzer;

Step 3: The relationship analyzer analyzes the relationship between A2 or C and the immediate value B1 in the instruction, and determines whether the relationship between the two is consistent with the relationship specified by the relationship code OP in the instruction;

Step 4: If the data type is a set address and the relationship is consistent, setting the second register to be valid, and writing a valid signal to the first memory at the current address;

Step 5. If the data type is data, and the second register is valid, write a valid signal to the first memory at the current address;

Step 6, the controller increments the address by 1, and continues to perform the marking process of steps 1-5;

Step 7. The address continues to increase by one until it increases to the address maximum; for each increment of the address, the Query Analyzer performs a marking process.

Further, the specific method for querying scanning in step S2 of the present invention includes:

Step 1, the controller controls the address generator to generate an address, reads the data in the address of the memory DataA={A1, A2}, and outputs the data to the type analyzer at an output end of the memory; The data of the address in a memory is output to the input end of the second register, and the second register records the data on the next clock edge, and the second register remains the original value before the clock edge arrives;

Step 2. If the data type is data, output A2 directly to the relationship analyzer;

If the data type is a collection address, the register file outputs data C corresponding to the address to the relationship analyzer;

Step 3: The relationship analyzer analyzes the relationship between A2 or C and the immediate value B1 in the instruction, and determines whether the relationship between the two is consistent with the relationship specified by the relationship code OP in the instruction;

Step 4: If the data type is data and the relationship is consistent, and the second register is valid, the valid signal is written to the first memory at the current address;

Step 5: The controller increments the address by 1, and the query analyzer performs a query process.

Step 6. The address continues to increase by one until it increases to the address maximum; for each increment, the Query Analyzer performs a query process.

Further, the specific method for classifying scanning in step S2 of the present invention includes:

Step 1, setting the second register to be invalid, the controller controls the address generator to generate the address maximum value, and reads the data of the address in the first memory;

Step 2. If the data type is data, and if the second register is invalid, write the memory Ra value to the second register, and if the second register is valid, keep the second register original value;

Step 3. If the data type is an address, the second register is invalid, and A2 is read out to the address input end of the register file, and A2 is the data value of the data DataA={A1, A2} in the memory. Passing the register group corresponding to the address, setting the value of the register file to B2, and B2 is the immediate number passed in the instruction;

Step 4: The controller reduces the address by 1, and the query analyzer performs a classification process.

Step 5. The address continues to decrease by 1 until it decreases to the address minimum; for every 1 minus, the Query Analyzer performs a classification process.

Further, the specific method for performing reading in step S2 of the present invention includes:

Step 1. The controller acquires a control instruction and performs a label scanning process;

Step 2: The controller controls the address generator to generate an address and a chip select signal;

Step 3: The query analyzer reads the data of the memory in the address, and if the register outputs the flag bit If it is valid, the data is output.

The invention has the beneficial effects that the inquiry function memory of the invention divides the memory into a plurality of groups within the integrated circuit, and each memory is provided with a query analyzer, and the data inside the memory is queried, which is greatly improved. The data query speed; the memory increases the data query function module inside the memory, the query time does not increase with the increase of the data amount, and the data query speed can be significantly increased in the case of big data, and is not subject to the hardware system read and write bottleneck The impact on query speed.

DRAWINGS

The present invention will be further described below in conjunction with the accompanying drawings and embodiments, in which:

1 is a schematic structural diagram of a memory with a query function according to an embodiment of the present invention;

2 is a schematic structural diagram of a query analyzer of a memory having a query function according to an embodiment of the present invention;

3 is a flowchart of a method for querying a memory with a query function according to an embodiment of the present invention;

4 is a schematic structural diagram of a query analyzer for removing a register file of a memory having a query function according to an embodiment of the present invention.

detailed description

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in FIG. 1, the query function memory of the embodiment of the present invention includes an instruction decoder, a controller, an address generation and decoder, a memory group and a query analyzer group, wherein:

An instruction decoder for decoding the received instruction and generating a control signal;

a controller, configured to control the generation of the first address, the increment, decrement, reset, and hold of the address according to the result of the instruction decoding;

An address generation and decoder for generating a start address used by the query, and performing address decoding to obtain an address signal;

a memory bank comprising a plurality of memories connected in parallel with each other;

Query analyzer group, including a query analyzer corresponding to the memory one by one, each query analyzer through The instruction bus obtains the control signal from the instruction decoder, obtains the address signal from the address generation and the decoder through the address bus, and marks, queries, classifies, and reads the data in the corresponding memory according to the address signal and the control signal. Operate and output the query results through the data output bus.

As shown in FIG. 2, the Query Analyzer includes a relationship analyzer, a type analyzer, and a plurality of registers;

The type analyzer is used to analyze the type of data output from the memory, output the data to a register or a relational analyzer, and output the type analysis result to the relational analyzer; the relational analyzer is used to output the data with the memory according to the immediate value in the instruction. Perform data relationship analysis and determine whether to output data.

The Query Analyzer also includes a first memory for storing results of the analysis of the data by the relationship analyzer based on the control instructions.

The register includes a first register, a second register, and a register file; the first register is disposed between the first memory and the relationship analyzer for registering data output from the first memory; and the second register is coupled to the relationship analyzer for The data in the first memory is registered to have valid data; the register file is disposed between the type analyzer and the relationship analyzer for storing the aggregate data.

In another embodiment of the invention, the memory S is a memory in the memory bank, the register file is the register file Rc, the first memory is the memory Ra, the first register is the register Rr, and the second register is the register Rin.

The instructions include: an opcode OC, a relationship code OP, an immediate B1, and an immediate B2. The opcode OC is decoded to obtain a control signal CMD. The control signal CMD represents a different operation, the relationship code OP represents eight comparison relationships of the relationship analyzer, and B1 and B2 are values for comparing data in the memory.

The functions of each module are:

First, the memory S:

Function: Used to store data and data types.

Supplementary note: The storage capacity of one memory S is not limited. The capacity is n*m bits (n is the number of bytes in the memory S, and m is the word length.)

Example: One byte stored DataA={A1 data type, A2 data}. A1, A2 word length is not limited. For example, the A1 word length can be 2 bits, 3 bits, and the like. The A2 word length can be 8 bits, 16 bits, and so on. The word length of DataA is equal to the A1 word length plus the A2 word length.

Example: In DataA={10100111100}, A1=101 words are 3 bits long. A2=00111100 word length It is 8 digits. DataA word length is 11 digits;

In DataA={01010000000000111100}, A1=0101 word length is 4;

A2=0000000000111100 word length is 16 bits. The DataA word is 20 bits long.

Second, the memory Ra:

Function: Used to store the results of the analysis of the data by the relationship analyzer based on the current instruction. The result is recorded in a memory location corresponding to the byte pointed to by the current address of the memory S.

Third, the register Rr:

Function: Registers the data output from the memory Ra. The update of the Rr value is the clock edge at the end of a query analysis. This means that the value in Rr is always the value of Ra in the previous address. When the address is the starting address. Rr is the default value of 0.

For example: the following table. The current address is 00101. The output of Ra is data 0 in Ra pointed to by address 00101. The data in Rr at this time is data 1 in Ra pointed to by address 00100.

address	Ra	A1	A2
00100	110	1	t
00101	0	101	i
00110	0	101	t

Fourth, the register Rin:

Function: Record whether Ra is valid.

For example, in the demo example, when the classification instruction is executed, the address is decremented from the maximum value. When Ra=1 at an address and Rin=0, Rin=1 is set. The value of Rin is then unchanged until Rin=0 is found when the data type is a byte of the set address.

Five, type analyzer:

Function: Analyze what type of A1 is in DataA, and control whether A2 output to register file Rc or relational analyzer according to type. At the same time, the type analysis result is output to the relationship analyzer.

There are 8 types of A1: null, data start address, set address, data end address, number, character, outreach, and nothing.

The five types of which are null, data start address, data end address, outreach, and irrelevant are used in the external device regardless of the circuit.

Sixth, the register file Rc

Function: Store collection data. That is, data indicating which classification the data record belongs to is stored.

For example: in the following record

<B title=”CPU”author=”John”/>

There is a byte (address 00000) in front of the character < to store the collection address as shown in the following table:

The record <B title=”CPU”author=”John”/> belongs to the last two bits of the set address of 00000000 (the number of bits depends on the number of bits of the Rc set address), that is, the set 0001 pointed to by 00.

That is, the record <B title="CPU"author="John"/> belongs to the set 0001.

If 00000000 is changed to 00000010 then: record <B title="CPU"author="John"/> belongs to set 0101.

Seven, relationship analyzer;

Features:

1. According to the instruction CMD, analyze whether the relationship between the immediate numbers B1 and C or B1 and A2 is the relationship described by op. 2. According to the command CMD and the current values of Ra, Rr, Rin, and the relationship between B1 and C or A2, control the value of writing Ra, Rin.

3. Control whether B2 is written to the register file Rc.

4. Determine whether to output data according to the value of Ra in the data read command.

There are eight types of relationships described by op:

1. No comparison; 2, A>B; 3, A==B; 4, A>B or A==B; 5, A<B; 6, A<B or A>B; 7, A<B Or A==B; 8, A<B or A==B or A>B.

As shown in FIG. 3, the query method of the query function memory according to the embodiment of the present invention includes the following steps:

S1, the instruction decoder performs instruction decoding on the instruction to obtain a control signal;

S2, the controller controls the address generation according to the control signal, and the decoder generates the first address and performs address translation. Code, get the address signal, and the memory outputs the data at the address;

S3. The query analyzer performs a label scan, a query scan, a classification scan, and a read operation on the data output from the memory according to the control signal;

S4, outputting the query result through the data output bus.

The specific method of marking scanning in step S2 includes:

Step 1, the controller controls the address generator to generate a starting address, reads the data in the address in the memory DataA={A1, A2}, and outputs an output DataA to the type analyzer;

Step 2. If the data type is data, output A2 to the relationship analyzer;

If the data type is an address, input A2 as an address to the address input end of the register file, and the register file outputs the data C corresponding to the address to the relationship analyzer;

Step 3: The relationship analyzer analyzes the relationship between A2 or C and the immediate value B1 in the instruction, and determines whether the relationship between the two is consistent with the relationship specified by the relationship code OP in the instruction;

Step 4: If the data type is a set address and the relationship is consistent, setting the second register to be valid, and writing a valid signal to the first memory at the current address;

Step 5. If the data type is data, and the second register is valid, write a valid signal to the first memory at the current address;

Step 6, the controller increments the address by 1, and continues to perform the marking process of steps 1-5;

Step 7. The address continues to increase by one until it increases to the address maximum; for each increment of the address, the Query Analyzer performs a marking process.

The specific method for querying scanning in step S2 includes:

Step 1, the controller controls the address generator to generate an address, reads the data in the address of the memory DataA={A1, A2}, outputs the data to the type analyzer at one output of the memory; and simultaneously reads the first memory. The address data is output to the input of the second register, and the second register records the data on the next clock edge, and the second register remains at the original value before the clock edge arrives;

Step 2. If the data type is data, output A2 directly to the relationship analyzer;

If the data type is a collection address, the register file outputs data C corresponding to the address to the relationship analyzer;

Step 3. The relationship analyzer analyzes the relationship between A2 or C and the immediate B1 in the instruction, and determines the two. Whether the relationship is consistent with the relationship specified by the relationship code OP in the instruction;

Step 4: If the data type is data and the relationship is consistent, and the second register is valid, the valid signal is written to the first memory at the current address;

Step 5: The controller increments the address by 1, and the query analyzer performs a query process.

Step 6. The address continues to increase by one until it increases to the address maximum; for each increment, the Query Analyzer performs a query process.

The specific method of the classification scan in step S2 includes:

Step 1, setting the second register to be invalid, the controller controls the address generator to generate the address maximum value, and reads the data of the address in the first memory;

Step 2. If the data type is data, and if the second register is invalid, write the memory Ra value to the second register, and if the second register is valid, keep the second register original value;

Step 3. If the data type is an address, the second register is invalid, and A2 is read out to the address input end of the register file, and A2 is the data value of the data DataA={A1, A2} in the memory. Passing the register group corresponding to the address, setting the value of the register file to B2, and B2 is the immediate number passed in the instruction;

Step 4: The controller reduces the address by 1, and the query analyzer performs a classification process.

Step 5. The address continues to decrease by 1 until it decreases to the address minimum; for every 1 minus, the Query Analyzer performs a classification process.

The specific method for reading in step S2 includes:

Step 1. The controller acquires a control instruction and performs a label scanning process;

Step 2: The controller controls the address generator to generate an address and a chip select signal;

Step 3. The Query Analyzer reads the data of the memory in the address, and if the register output flag bit is valid, the data is output.

In another embodiment of the method of the present invention, the memory S is a memory in the memory bank, the register file is the register file Rc, the first memory is the memory Ra, the first register is the register Rr, and the second register is the register Rin.

1. It consists of a controller, an address generator, an address decoder, three memories (A0, A1, A2) and three query analyzers (E0, E1, E2).

2. Logic 1 indicates valid, and logic 0 indicates invalid.

3. Each memory has a storage capacity of 16*11 bits and a memory address range of 0000 to 1111.

4. DataA={A1, A2}. Among them, A1 is 3 bits, A2 is 8 bits, and DataA is 11 bits. Record the data type with A1 and record the data value with A2.

5. Data type coding, as shown in the following table:

coding	significance
010	Collection address
101	data

6, relationship code:

7. The meaning and sample data of each data bit of a single byte of memory are as follows:

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S0_A2
00000	0	010	00	0	010	00	0	010	00
00001	0	101	<	0	101	<	0	101	<
00010	0	101	B	0	101	B	0	101	C
00011	0	101	Space	0	101	Space	0	101	Space
00100	0	101	t	0	101	t	0	101	t
00101	0	101	i	0	101	i	0	101	i
00110	0	101	t	0	101	t	0	101	t
00111	0	101	l	0	101	l	0	101	l
01000	0	101	e	0	101	e	0	101	e
01001	0	101	=	0	101	=	0	101	=
01010	0	101	"	0	101	"	0	101	"
01011	0	101	C	0	101	F	0	101	R

01100	0	101	P	0	101	a	0	101	E
01101	0	101	U	0	101	c	0	101	D
01110	0	101	"	0	101	e	0	101	"
01111	0	101	Space	0	101	"	0	101	Space
10000	0	101	a	0	101	Space	0	101	a
10001	0	101	u	0	101	a	0	101	u
10010	0	101	t	0	101	u	0	101	t
10011	0	101	h	0	101	t	0	101	h
10100	0	101	o	0	101	h	0	101	o
10101	0	101	r	0	101	o	0	101	r
10110	0	101	=	0	101	r	0	101	=
10111	0	101	"	0	101	=	0	101	"
11000	0	101	j	0	101	"	0	101	L
11001	0	101	o	0	101	L	0	101	e
11010	0	101	h	0	101	P	0	101	e
11011	0	101	n	0	101	"	0	101	"
11100	0	101	"	0	101	Space	0	101	Space
11101	0	101	Space	0	101	/	0	101	/
11110	0	101	/	0	101	>	0	101	>
11111	0	101	>	0	101		0	101

Query example:

In the following three records

<B title=”CPU”author=”John”/>

<B title=”Face”author=”LP”/>

<C title=”RED”owner=”Lee”/>

Find the record of title=”CPU” and output it.

Circuit working process:

[1] Marking instructions:

Execute the mark instruction 01000 010 00000001;

The starting address is 00000.

If the type analyzer determines that S0_A1 is the set address, the register file Rc outputs the data of the address and outputs it to the relational analyzer. The relationship analyzer determines the relationship between this value and B. If it is consistent with the pending relationship in the instruction, Rin=1, and the write Ra is 1 at the address; otherwise, the write Ra is 0 at the address.

If the type analyzer determines that S0_A1 is data and Rin=1, the write Ra at this address is 1; otherwise, the write Ra at this address is 0.

The address is incremented by 1, and the above process is performed. Until the address increases to the maximum.

Each memory and register changes are as follows:

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00000	1	010	00	1	010	00	0	010	00
00001	1	101	<	1	101	<	0	101	<
00010	1	101	B	1	101	B	0	101	C
00011	1	101	Space	1	101	Space	0	101	Space
00100	1	101	t	1	101	t	0	101	t
00101	1	101	i	1	101	i	0	101	i
00110	1	101	t	1	101	t	0	101	t
00111	1	101	l	1	101	l	0	101	l
01000	1	101	e	1	101	e	0	101	e
01001	1	101	=	1	101	=	0	101	=
01010	1	101	"	1	101	"	0	101	"
01011	1	101	C	1	101	F	0	101	R
01100	1	101	P	1	101	a	0	101	E
01101	1	101	U	1	101	c	0	101	D
01110	1	101	"	1	101	e	0	101	"
01111	1	101	Space	1	101	"	0	101	Space
10000	1	101	a	1	101	Space	0	101	a
10001	1	101	u	1	101	a	0	101	u
10010	1	101	t	1	101	u	0	101	t
10011	1	101	h	1	101	t	0	101	h
10100	1	101	o	1	101	h	0	101	o
10101	1	101	r	1	101	o	0	101	r
10110	1	101	=	1	101	r	0	101	=
10111	1	101	"	1	101	=	0	101	"
11000	1	101	j	1	101	"	0	101	L
11001	1	101	o	1	101	L	0	101	e
11010	1	101	h	1	101	P	0	101	e
11011	1	101	n	1	101	"	0	101	"
11100	1	101	"	1	101	Space	0	101	Space
11101	1	101	Space	1	101	/	0	101	/
11110	1	101	/	1	101	>	0	101	>
11111	1	101	>	1	101		0	101

[2] Query instructions:

Execute the query command: 00100 010 00111100

1. The address generator generates the address n=00000.

2. The output data type is 010, which is the aggregate address. Rr records the output of Ra, where Rr=1. Set Ra[0]=0.

3. The relationship between Rr=1, S0_A2[1]=00111100 and the immediate number 00111100 (representing the character "<") is 010. Set Ra[1]=1.

4. The relationship between Rr=1, S0_A2[1]=01000010 and the immediate number 00111100 is not 010. Set Ra[2]=0.

5. Similar to the fourth step, from Ra[2] to Ra[31] are set to zero.

(00111100 is the ASCii code of the character "<") where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00001	1	101	<	1	101	<	0	101	<

According to the [2] procedure, the query command is executed: 00100 010 01000010 (01000010 is the ASCii code of the character "B"), wherein Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00010	1	101	B	1	101	B	0	101	C

According to the [2] procedure, the query instruction is executed: 00100 010 00100000 (00100000 is a space for the ASCii code) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00011	1	101	Space	1	101	Space	0	101	Space

[3] Classification instructions:

Execution classification instruction 00010 010 00000001 00000011

1, the address generator generates the maximum address 11111

2. From address 11111 to address 00100, neither Ra=1 nor Rin=0, then Rin No change, Rin=0;

3. When the address is 00011, Ra=1 is satisfied, and Rin=0 condition, then Rin=1;

4, the address is self-decreasing, from address 00010 to address 00001 does not satisfy Ra = 1, and Rin = 0 condition, so Rin does not change, Rin = 1;

When the address is 00000, the type is the aggregate address, and the relationship analyzer analyzes the second two values of A2 as the address and outputs it to the Rc address input. S0_Rc output data is 0001, S1_Rc output data is 0001, relationship analyzer E0, E1 compares 0001 with immediate B2 (B2=00000001), whether the relationship between the last four digits is 010, where the result is YES, then Rc[00 ]=0011.

[4] Marking instructions:

Execute the mark instruction 01000 010 00000011;

The instruction execution process is the same as [1], but the immediate value is 00000011.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00000	1	010	00	1	010	00	0	010	00
00001	1	101	<	1	101	<	0	101	<
00010	1	101	B	1	101	B	0	101	C
00011	1	101	Space	1	101	Space	0	101	Space
00100	1	101	t	1	101	t	0	101	t
00101	1	101	i	1	101	i	0	101	i
00110	1	101	t	1	101	t	0	101	t
00111	1	101	l	1	101	l	0	101	l
01000	1	101	e	1	101	e	0	101	e
01001	1	101	=	1	101	=	0	101	=
01010	1	101	"	1	101	"	0	101	"
01011	1	101	C	1	101	F	0	101	R
01100	1	101	P	1	101	a	0	101	E
01101	1	101	U	1	101	c	0	101	D
01110	1	101	"	1	101	e	0	101	"
01111	1	101	Space	1	101	"	0	101	Space
10000	1	101	a	1	101	Space	0	101	a
10001	1	101	u	1	101	a	0	101	u
10010	1	101	t	1	101	u	0	101	t
10011	1	101	h	1	101	t	0	101	h
10100	1	101	o	1	101	h	0	101	o
10101	1	101	r	1	101	o	0	101	r

10110	1	101	=	1	101	r	0	101	=
10111	1	101	"	1	101	=	0	101	"
11000	1	101	j	1	101	"	0	101	L
11001	1	101	o	1	101	L	0	101	e
11010	1	101	h	1	101	P	0	101	e
11011	1	101	n	1	101	"	0	101	"
11100	1	101	"	1	101	Space	0	101	Space
11101	1	101	Space	1	101	/	0	101	/
11110	1	101	/	1	101	>	0	101	>
11111	1	101	>	1	101		0	101

[5] query instruction

Execute the query instruction 00100 010 01110100 (01110100 is the ASCii code of the character t) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00100	1	101	t	1	101	t	0	101	t

Execute the query instruction 00100 010 01101001 (01101001 is the ASCii code of the character i) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00101	1	101	i	1	101	i	0	101	i

Execute the query instruction 00100 010 01110100 (01110100 is the ASCii code of the character t) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00110	1	101	t	1	101	t	0	101	t

Execute the query instruction 00100 010 01101100 (01101100 is the ASCii code of the character l) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00111	1	101	l	1	101	l	0	101	l

Execute the query instruction 00100 010 01100101 (01100101 is the ASCii code of the character e) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01000	1	101	e	1	101	E	0	101	e

Execute the query instruction 00100 010 00111101 (00111101 is the character = ASCii code) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01001	1	101	=	1	101	=	0	101	=

Execute the query command 00100 010 00100010 (00100010 is the character "ASCii code") where Ra changes as shown in the following table. Ra is not listed as 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
010010	1	101	"	1	101	"	0	101	"

Execute the query instruction 00100 010 01000011 (01000011 is the ASCii code of character C) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01011	1	101	C	0	101	F	0	101	R

Execute the query instruction 00100 010 01010000 (01010000 is the ASCii code of the character P) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01100	1	101	P	0	101	a	0	101	R

Execute the query instruction 00100 010 01010101 (01010101 is the ASCii code of the character U) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01101	1	101	U	0	101	c	0	101	R

Execute the query instruction 00100 010 00100010 (00100010 is the character "ASCii code") where Ra changes as shown in the following table. Ra is not listed as 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01110	1	101	"	0	101	E	0	101	R

[6] Classification instructions:

Execute the classification instruction 00010 010 00000011 00000100;

The instruction execution process is the same as [3], but the immediate value is 00000011 00000100.

[7] read

1. Execute the marking instruction 01000 010 00000100 first. The execution process is the same as [1], but the implementation The number is 00000100.

2, execute the read command 00001 010 00000100

A start address 00000 and a chip select signal are generated. When Ra of S0 is 1, the data S0_A1, S0_A2 is output to the output bus. Ra = 0 makes the output high impedance. As the address is incremented, the data is read out in sequence.

As shown in FIG. 4, in another embodiment of the present invention, the register file Rc is removed from the Query Analyzer.

The specific method of marking scanning in step S2 includes:

Step 1. The controller controls the address generator to generate a start address, and the read memory is in the address. Data Data==A1, A2}, A1 is output to the type analyzer, and A2 is output to the relationship analyzer;

Step 2: The relationship analyzer analyzes the relationship between A2 and the immediate value B1 in the instruction, and determines whether the relationship between the two is consistent with the relationship specified by the relationship code OP in the instruction;

Step 3: If the data type is a set and the relationship is consistent, setting the second register to be valid, and writing a valid signal to the first memory at the current address;

Step 4. If the data type is data, and the second register is valid, write a valid signal to the first memory at the current address;

Step 5: The controller increments the address by 1, and continues to perform the marking process of steps 1-4;

Step 6. The address continues to increase by one until it increases to the address maximum; for each increment of the address, the Query Analyzer performs a marking process.

The specific method for querying scanning in step S2 includes:

Step 1, the controller controls the address generator to generate an address, reads the data of the memory in the address DataA={A1, A2}, A1 outputs to the type analyzer, A2 outputs to the relationship analyzer; and simultaneously reads the first memory The data of the address is output to the input of the second register, and the second register records the data on the next clock edge, and the second register remains the original value before the clock edge arrives;

Step 2: The relationship analyzer analyzes the relationship between A2 and the immediate value B1 in the instruction, and determines whether the relationship between the two is consistent with the relationship specified by the relationship code OP in the instruction;

Step 3. If the data type is data and the relationship is consistent, and the second register is valid, the valid signal is written to the first memory at the current address;

Step 4: The controller increments the address by 1, and the query analyzer performs a query process.

Step 5. The address continues to increase by one until it increases to the address maximum; for each increment, the Query Analyzer performs a query process.

The specific method of the classification scan in step S2 includes:

Step 1, setting the second register to be invalid, the controller controls the address generator to generate the address maximum value, and reads the data of the address in the first memory;

Step 2. If the data type is data, and if the second register is invalid, write the memory Ra value to the second register, and if the second register is valid, keep the second register original value;

Step 3. If the data type is a set, set the second register to be invalid, and set the memory to be The value at the previous address is B2, which is the immediate number passed in the instruction;

Step 4: The controller reduces the address by 1, and the query analyzer performs a classification process.

Step 5. The address continues to decrease by 1 until it decreases to the address minimum; for every 1 minus, the Query Analyzer performs a classification process.

The specific method for reading in step S2 includes:

Step 1. The controller acquires a control instruction and performs a label scanning process;

Step 2: The controller controls the address generator to generate an address and a chip select signal;

Step 3. The Query Analyzer reads the data of the memory in the address, and if the register output flag bit is valid, the data is output.

In this embodiment, a corresponding process is:

The memory S is a memory in the memory group, the first memory is the memory Ra, the first register is the register Rr, and the second register is the register Rin.

1. It consists of a controller, an address generator, an address decoder, three memories (A0, A1, A2) and three query analyzers (E0, E1, E2).

2. Logic 1 indicates valid, and logic 0 indicates invalid.

3. Each memory has a storage capacity of 16*11 bits and a memory address range of 0000 to 1111.

4. DataA={A1, A2}. Among them, A1 is 3 bits, A2 is 8 bits, and DataA is 11 bits. Record the data type with A1 and record the data value with A2.

5. Data type coding, as shown in the following table:

coding	significance
010	set
101	data

6, relationship code:

7. The meaning and sample data of each data bit of a single byte of memory are as follows:

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S0_A2
00000	0	010	00	0	010	00	0	010	00
00001	0	101	<	0	101	<	0	101	<
00010	0	101	B	0	101	B	0	101	C
00011	0	101	Space	0	101	Space	0	101	Space
00100	0	101	t	0	101	t	0	101	t
00101	0	101	i	0	101	i	0	101	i
00110	0	101	t	0	101	t	0	101	t
00111	0	101	l	0	101	l	0	101	l
01000	0	101	e	0	101	e	0	101	e
01001	0	101	=	0	101	=	0	101	=
01010	0	101	"	0	101	"	0	101	"
01011	0	101	C	0	101	F	0	101	R
01100	0	101	P	0	101	a	0	101	E
01101	0	101	U	0	101	c	0	101	D
01110	0	101	"	0	101	e	0	101	"
01111	0	101	Space	0	101	"	0	101	Space
10000	0	101	a	0	101	Space	0	101	a
10001	0	101	u	0	101	a	0	101	u
10010	0	101	t	0	101	u	0	101	t
10011	0	101	h	0	101	t	0	101	h
10100	0	101	o	0	101	h	0	101	o
10101	0	101	r	0	101	o	0	101	r
10110	0	101	=	0	101	r	0	101	=
10111	0	101	"	0	101	=	0	101	"
11000	0	101	j	0	101	"	0	101	L
11001	0	101	o	0	101	L	0	101	e
11010	0	101	h	0	101	P	0	101	e
11011	0	101	n	0	101	"	0	101	"
11100	0	101	"	0	101	Space	0	101	Space
11101	0	101	Space	0	101	/	0	101	/
11110	0	101	/	0	101	>	0	101	>
11111	0	101	>	0	101		0	101

Query example:

In the following three records

<B title=”CPU”author=”John”/>

<B title=”Face”author=”LP”/>

<C title=”RED”owner=”Lee”/>

Find the record of title=”CPU” and output it.

Circuit working process:

[1] Marking instructions:

Execute the mark instruction 01000 010 00000001;

The starting address is 00000.

If the type analyzer determines that S0_A1 is a set, the relationship analyzer determines the relationship between this value and B. If it is consistent with the pending relationship in the instruction, Rin=1, and write Ra at the address is 1; otherwise, write Ra The data is 0 at this address.

If the type analyzer determines that S0_A1 is data and Rin=1, the write Ra at this address is 1; otherwise, the write Ra at this address is 0.

The address is incremented by 1, and the above process is performed. Until the address increases to the maximum.

Each memory and register changes are as follows:

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00000	1	010	00	1	010	00	0	010	00
00001	1	101	<	1	101	<	0	101	<
00010	1	101	B	1	101	B	0	101	C
00011	1	101	Space	1	101	Space	0	101	Space
00100	1	101	t	1	101	t	0	101	t
00101	1	101	i	1	101	i	0	101	i
00110	1	101	t	1	101	t	0	101	t
00111	1	101	l	1	101	l	0	101	l
01000	1	101	e	1	101	e	0	101	e
01001	1	101	=	1	101	=	0	101	=
01010	1	101	"	1	101	"	0	101	"
01011	1	101	C	1	101	F	0	101	R
01100	1	101	P	1	101	a	0	101	E
01101	1	101	U	1	101	c	0	101	D

01110	1	101	"	1	101	e	0	101	"
01111	1	101	Space	1	101	"	0	101	Space
10000	1	101	a	1	101	Space	0	101	a
10001	1	101	u	1	101	a	0	101	u
10010	1	101	t	1	101	u	0	101	t
10011	1	101	h	1	101	t	0	101	h
10100	1	101	o	1	101	h	0	101	o
10101	1	101	r	1	101	o	0	101	r
10110	1	101	=	1	101	r	0	101	=
10111	1	101	"	1	101	=	0	101	"
11000	1	101	j	1	101	"	0	101	L
11001	1	101	o	1	101	L	0	101	e
11010	1	101	h	1	101	P	0	101	e
11011	1	101	n	1	101	"	0	101	"
11100	1	101	"	1	101	Space	0	101	Space
11101	1	101	Space	1	101	/	0	101	/
11110	1	101	/	1	101	>	0	101	>
11111	1	101	>	1	101		0	101

[2] Query instructions:

Execute the query command: 00100 010 00111100

1. The address generator generates the address n=00000.

2. The output data type is 010 is a collection. Rr records the output of Ra, where Rr=1. Set Ra[0]=0.

3. The relationship between Rr=1, S0_A2[1]=00111100 and the immediate number 00111100 (representing the character "<") is 010. Set Ra[1]=1.

4. The relationship between Rr=1, S0_A2[1]=01000010 and the immediate number 00111100 is not 010. Set Ra[2]=0.

5. Similar to the fourth step, from Ra[2] to Ra[31] are set to zero.

(00111100 is the ASCii code of the character "<") where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00001	1	101	<	1	101	<	0	101	<

According to the [2] procedure, the query command is executed: 00100 010 01000010 (01000010 is the ASCii code of the character "B"), wherein Ra changes as shown in the following table. Ra that is not listed is 0.

address

S0_Ra

S0_A1

S0_A2

S1_Ra

S1_A1

S1_A2

S2_Ra

S2_A1

S2_A2

00010

1

101

B

1

101

B

0

101

C

According to the [2] procedure, the query instruction is executed: 00100 010 00100000 (00100000 is a space for the ASCii code) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00011	1	101	Space	1	101	Space	0	101	Space

[3] Classification instructions:

Execution classification instruction 00010 010 00000001 00000011

1, the address generator generates the maximum address 11111

2, from address 11111 to address 00100 do not satisfy Ra = 1, and Rin = 0 condition, then Rin does not change, Rin = 0;

3. When the address is 00011, Ra=1 is satisfied, and Rin=0 condition, then Rin=1;

4, the address is self-decreasing, from address 00010 to address 00001 does not satisfy Ra = 1, and Rin = 0 condition, so Rin does not change, Rin = 1;

When the address is 00000, the type is a set. The relationship analyzer analyzes whether the relationship between the last two digits of A2 and the last two digits of the immediate B2 (B2=00000001) is 010. If the result is YES, then A2=11.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00000	1	010	11	1	010	11	0	010	00

[4] Marking instructions:

Execute the mark instruction 01000 010 00000011;

The instruction execution process is the same as [1], but the immediate value is 00000011.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00000	1	010	11	1	010	11	0	010	00
00001	1	101	<	1	101	<	0	101	<
00010	1	101	B	1	101	B	0	101	C
00011	1	101	Space	1	101	Space	0	101	Space
00100	1	101	t	1	101	t	0	101	t
00101	1	101	i	1	101	i	0	101	i
00110	1	101	t	1	101	t	0	101	t
00111	1	101	l	1	101	l	0	101	l
01000	1	101	e	1	101	e	0	101	e
01001	1	101	=	1	101	=	0	101	=
01010	1	101	"	1	101	"	0	101	"
01011	1	101	C	1	101	F	0	101	R
01100	1	101	P	1	101	a	0	101	E
01101	1	101	U	1	101	c	0	101	D
01110	1	101	"	1	101	e	0	101	"

01111	1	101	Space	1	101	"	0	101	Space
10000	1	101	a	1	101	Space	0	101	a
10001	1	101	u	1	101	a	0	101	u
10010	1	101	t	1	101	u	0	101	t
10011	1	101	h	1	101	t	0	101	h
10100	1	101	o	1	101	h	0	101	o
10101	1	101	r	1	101	o	0	101	r
10110	1	101	=	1	101	r	0	101	=
10111	1	101	"	1	101	=	0	101	"
11000	1	101	j	1	101	"	0	101	L
11001	1	101	o	1	101	L	0	101	e
11010	1	101	h	1	101	P	0	101	e
11011	1	101	n	1	101	"	0	101	"
11100	1	101	"	1	101	Space	0	101	Space
11101	1	101	Space	1	101	/	0	101	/
11110	1	101	/	1	101	>	0	101	>
11111	1	101	>	1	101		0	101

[5] query instruction

Execute the query instruction 00100 010 01110100 (01110100 is the ASCii code of the character t) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00100	1	101	t	1	101	t	0	101	t

Execute the query instruction 00100 010 01101001 (01101001 is the ASCii code of the character i) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00101	1	101	i	1	101	i	0	101	i

Execute the query instruction 00100 010 01110100 (01110100 is the ASCii code of the character t) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00110	1	101	t	1	101	t	0	101	t

Execute the query instruction 00100 010 01101100 (01101100 is the ASCii code of the character l) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
00111	1	101	l	1	101	l	0	101	l

Execute the query instruction 00100 010 01100101 (01100101 is the ASCii code of the character e) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01000	1	101	e	1	101	E	0	101	e

Execute the query instruction 00100 010 00111101 (00111101 is the character = ASCii code) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01001	1	101	=	1	101	=	0	101	=

Execute the query command 00100 010 00100010 (00100010 is the character "ASCii code") where Ra changes as shown in the following table. Ra is not listed as 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
010010	1	101	"	1	101	"	0	101	"

Execute the query instruction 00100 010 01000011 (01000011 is the ASCii code of character C) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01011	1	101	C	0	101	F	0	101	R

Execute the query instruction 00100 010 01010000 (01010000 is the ASCii code of the character P) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01100	1	101	P	0	101	a	0	101	R

Execute the query instruction 00100 010 01010101 (01010101 is the ASCii code of the character U) where Ra changes as shown in the following table. Ra that is not listed is 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01101	1	101	U	0	101	c	0	101	R

Execute the query instruction 00100 010 00100010 (00100010 is the character "ASCii code") where Ra changes as shown in the following table. Ra is not listed as 0.

address	S0_Ra	S0_A1	S0_A2	S1_Ra	S1_A1	S1_A2	S2_Ra	S2_A1	S2_A2
01110	1	101	"	0	101	E	0	101	R

[6] Classification instructions:

Execute the classification instruction 00010 010 00000011 00000001;

The instruction execution process is the same as [3], but the immediate value is 00000011 00000001.

[7] read

1. Execute the marking instruction 01000 010 00000100 first. The execution process is the same as [1], but the immediate value is 00000100.

2, execute the read command 00001 010 00000001

A start address 00000 and a chip select signal are generated. When Ra of S0 is 1, the data S0_A1, S0_A2 is output to the output bus. Ra = 0 makes the output high impedance. As the address is incremented, the data is read out in sequence.

It is to be understood that those skilled in the art will be able to make modifications and changes in accordance with the above description, and all such modifications and variations are intended to be included within the scope of the appended claims.

Claims (9)

1. A memory with query function, comprising: an instruction decoder, a controller, an address generation and decoder, a memory group and a query analyzer group, wherein:

   The instruction decoder is configured to decode the received instruction and generate a control signal;

   The controller is configured to control the generation of the first address, the incrementing, decrementing, resetting, and maintaining of the address according to the result of the instruction decoding;

   The address generation and decoder is configured to generate a start address used by the query, and perform address decoding to obtain an address signal;

   The memory group includes a plurality of memories connected in parallel with each other;

   The query analyzer group includes a query analyzer corresponding to the memory one by one, each query analyzer obtains a control signal from the instruction decoder through the instruction bus, and obtains an address signal from the address generation and the decoder through the address bus, according to The address signal and the control signal mark, query, classify and read the data in the corresponding memory, and output the query result through the data output bus.
2. The query function memory according to claim 1, wherein the query analyzer comprises a relationship analyzer, a type analyzer and a plurality of registers;

   The type analyzer is configured to analyze the type of data output from the memory, output the data to a register or a relationship analyzer, and output the type analysis result to the relationship analyzer;

   The relationship analyzer is configured to perform data relationship analysis with the data outputted from the memory according to the immediate value in the instruction, and determine whether to output the data.
3. The query function memory according to claim 2, wherein the query analyzer further comprises a first memory for storing a result of analyzing the data by the relationship analyzer according to the control instruction.
4. The Query-enabled memory of claim 3, wherein the register comprises a first register, a second register, and a register file;

   a first register is disposed between the first memory and the relationship analyzer for registering data output from the first memory;

   The second register is coupled to the relationship analyzer for registering whether data in the first memory exists valid data;

   The register file is placed between the type analyzer and the relational analyzer to store the collection data.
5. A method for querying a query-enabled memory according to claim 1, comprising the steps of:

   S1, the instruction decoder performs instruction decoding on the instruction to obtain a control signal;

   S2, the controller controls the address generation according to the control signal, and the decoder generates the first address and performs address decoding to obtain an address signal, and the memory outputs the data at the address;

   S3. The query analyzer performs a label scan, a query scan, a classification scan, and a read operation on the data output from the memory according to the control signal;

   S4, outputting the query result through the data output bus.
6. The method for querying a query-enabled memory according to claim 5, wherein the specific method of marking scanning in step S2 comprises:

   Step 1, the controller controls the address generator to generate a starting address, reads the data in the address in the memory DataA={A1, A2}, and outputs an output DataA to the type analyzer;

   Step 2. If the data type is data, output A2 to the relationship analyzer;

   If the data type is an address, input A2 as an address to the address input end of the register file, and the register file outputs the data C corresponding to the address to the relationship analyzer;

   Step 3: The relationship analyzer analyzes the relationship between A2 or C and the immediate value B1 in the instruction, and determines whether the relationship between the two is consistent with the relationship specified by the relationship code OP in the instruction;

   Step 4: If the data type is a set address and the relationship is consistent, setting the second register to be valid, and writing a valid signal to the first memory at the current address;

   Step 5. If the data type is data, and the second register is valid, write a valid signal to the first memory at the current address;

   Step 6, the controller increments the address by 1, and continues to perform the marking process of steps 1-5;

   Step 7. The address continues to increase by one until it increases to the address maximum; for each increment of the address, the Query Analyzer performs a marking process.
7. The method for querying a query-enabled memory according to claim 5, wherein the specific method for querying scanning in step S2 comprises:

   Step 1, the controller controls the address generator to generate an address, reads the data in the address of the memory DataA={A1, A2}, outputs the data to the type analyzer at one output of the memory; and simultaneously reads the first memory. The address data is output to the input of the second register, and the second register records the data on the next clock edge, and the second register remains at the original value before the clock edge arrives;

   Step 2. If the data type is data, output A2 directly to the relationship analyzer;

   If the data type is a collection address, the register file outputs data C corresponding to the address to the relationship analyzer;

   Step 3: The relationship analyzer analyzes the relationship between A2 or C and the immediate value B1 in the instruction, and determines whether the relationship between the two is consistent with the relationship specified by the relationship code OP in the instruction;

   Step 4: If the data type is data and the relationship is consistent, and the second register is valid, the valid signal is written to the first memory at the current address;

   Step 5: The controller increments the address by 1, and the query analyzer performs a query process.

   Step 6. The address continues to increase by one until it increases to the address maximum; for each increment, the Query Analyzer performs a query process.
8. The method for querying a query-enabled memory according to claim 5, wherein the specific method of the classification scan in step S2 comprises:

   Step 1, setting the second register to be invalid, the controller controls the address generator to generate the address maximum value, and reads the data of the address in the first memory;

   Step 2. If the data type is data, and if the second register is invalid, write the memory Ra value to the second register, and if the second register is valid, keep the second register original value;

   Step 3. If the data type is an address, the second register is invalid, and A2 is read out to the address input end of the register file, and A2 is the data value of the data DataA={A1, A2} in the memory. Passing the register group corresponding to the address, setting the value of the register file to B2, and B2 is the immediate number passed in the instruction;

   Step 4: The controller reduces the address by 1, and the query analyzer performs a classification process.

   Step 5. The address continues to decrease by 1 until it decreases to the address minimum; for every 1 minus, the Query Analyzer performs a classification process.
9. The method for querying a query-enabled memory according to claim 5, characterized in that The specific method for reading in step S2 includes:

   Step 1. The controller acquires a control instruction and performs a label scanning process;

   Step 2: The controller controls the address generator to generate an address and a chip select signal;

   Step 3. The Query Analyzer reads the data of the memory in the address, and if the register output flag bit is valid, the data is output.

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