WO2017202501A1 - Data bus and method - Google Patents

Data bus and method Download PDF

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Publication number
WO2017202501A1
WO2017202501A1 PCT/EP2017/025130 EP2017025130W WO2017202501A1 WO 2017202501 A1 WO2017202501 A1 WO 2017202501A1 EP 2017025130 W EP2017025130 W EP 2017025130W WO 2017202501 A1 WO2017202501 A1 WO 2017202501A1
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WO
WIPO (PCT)
Prior art keywords
data
serial
significant bit
bus
data bus
Prior art date
Application number
PCT/EP2017/025130
Other languages
French (fr)
Inventor
Donald Forbes
Original Assignee
Donald Forbes
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Donald Forbes filed Critical Donald Forbes
Publication of WO2017202501A1 publication Critical patent/WO2017202501A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • G06F13/4256—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4273—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/80—Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups H04B10/03 - H04B10/70, e.g. optical power feeding or optical transmission through water
    • H04B10/801—Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups H04B10/03 - H04B10/70, e.g. optical power feeding or optical transmission through water using optical interconnects, e.g. light coupled isolators, circuit board interconnections

Definitions

  • the present disclosure relates to a data bus. Moreover, the present disclosure concerns a method of communicating data in the aforesaid data bus.
  • one or more data buses are employed to communicate data between processors and also with input/output devices and data memory.
  • a contemporary data bus comprises:
  • Serial data communication standards are known, for example MIDI standard for musical instruments, Ethernet and similar.
  • the present disclosure seeks to provide an improved data bus that is more robust to eavesdropping. Moreover, the present disclosure seeks to provide an improved data bus that is more flexible in accommodating variable data word size, as well as employing fewer data lines in comparison to conventional known data buses. Furthermore, the present disclosure seeks to provide an improved data bus that is less vulnerable to injection of computer viruses and similar types of malware.
  • a data bus for communicating data between a data processing arrangement, a data memory arrangement and an input/output device arrangement, characterized in that the data bus includes at least one serial data line for communicating in operation data in a serial manner, and one or more data control lines for providing additional data for coordinating and/or directing in operation data flowing via the at least one serial data line), characterized in that the at least one serial data line (20) is implemented using an optical communication link.
  • the invention is of advantage in that communicating the at least one serial data line of the data bus assists to transform the data bus into an arrangement that is more difficult to eavesdrop and corrupt.
  • the data bus is implemented using one or more wires, one or more conductive tracks, one or more optical communication links or one or more wireless communication links.
  • the data bus is implemented such that address data is communicated via the one or more data control lines. More optionally, the address data is communicated in a serial manner. Yet more optionally, in the data bus, the address data is communicated in a temporally changing manner, switching between serial and parallel communications of the address data.
  • the data bus is implemented such that the at least one serial data line has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last.
  • the data bus is implemented such that the at least one serial data line has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last.
  • the data bus is implemented such that the at least one serial data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order defined by data conveyed via the one or more data control lines.
  • the data bus is implemented such that the at least one serial data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order that varies temporally as defined by data conveyed via the one or more data control lines.
  • LSB least significant bit
  • MSB most significant bit
  • the data bus is implemented such that the data bus includes at least one parallel-to-serial interface including at least one latch arrangement with parallel data input/output at a first of its data ports, and serial data input/output at a second of its data ports.
  • a method of communicating data via a data bus between a data processing arrangement, a data memory arrangement and an input/output device arrangement characterized in that the method includes:
  • the method includes implementing the data bus using one or more wires, one or more conductive tracks, one or more optical communication links or one or more wireless communication links.
  • the method includes communicating the address data via the one or more data control lines.
  • the method includes communicating the address data in a serial manner.
  • the method includes communicating the address data in a temporally changing manner, switching between serial and parallel communications of the address data.
  • the at least one serial data line has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last.
  • LSB least significant bit
  • MSB most significant bit
  • the at least one serial data line has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last.
  • the at least one serial data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order defined by data conveyed via the one or more data control lines.
  • the at least one serial data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order that varies temporally as defined by data conveyed via the one or more data control lines.
  • the method includes arranging for the data bus to include at least one parallel-to-serial interface including at least one latch arrangement with parallel data input/output at a first of its data ports, and serial data input/output at a second of its data ports.
  • a data bus for communicating data between a data processing arrangement, a data memory arrangement and an input/output device arrangement, characterized in that the data bus includes at least one serial data line for communicating in operation data in a serial manner, and one or more data control lines for providing additional data for coordinating and/or directing in operation data flowing via the at least one serial data line.
  • the data bus is implemented such that the at least one serial data line (20) is implemented using an optical communication link.
  • a method of communicating data via a data bus between a data processing arrangement, a data memory arrangement and an input/output device arrangement characterized in that the method includes:
  • the method includes implementing the at least one serial data line using an optical communication link.
  • FIG. 1 is a schematic illustration of a data bus according to the present disclosure.
  • FIG. 2 is a schematic illustration of a serial-to-parallel data bus interface used for implementing embodiments of the present disclosure.
  • an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent.
  • a non-underlined number relates to an item identified by a line linking the non-underlined number to the item.
  • the non-underlined number is used to identify a general item at which the arrow is pointing.
  • the present disclosure relates to a data bus, indicated generally by 10, that includes a data line 20 (D) that communicates data in a serial manner, wherein the data Iine20 is provided in parallel with one or more data control Iines30.
  • one or more of the data control Iines30 are address control lines 40, for example one address control line for conveyingin operation addressdata.
  • one or more of the data control lines 30 are clock data lines for providing clock information for temporally coordinating data flows and data exchanges via the data bus 10.
  • the data line 20 and the data control lines 30 are implemented as waveguides for conveying electrical signals at a data bit rate of up to 3 GHz, more optionally up to 10 GHz, and yet more optionally up to 30 GHz.
  • the data bus 10 is implemented using electrical tracks or wires, for example formed on an integrated circuit chip or printed circuit board.
  • the data bus is implemented, at least in part, using optical communication links, for example optical waveguides, for example the data line 20 is optionally implemented using an optical waveguide, and the one or more data control lines 30 are implemented using wires or conductive tracks.
  • the parallel-to-serial data bus interface50 includes a data latch 70, wherein:
  • the data latch 70 is loaded with data in a parallel manner with data from data lines 80 of the parallel data bus 60 and reads out the data of the data latch 70 in a serial manner to generate serial data for the data line 20 of the data bus 10;
  • the data latch 70 is loaded with data in a serial manner with data from the data line 20 and reads out the data of the data latch 70 in a parallel manner to generate parallel data for the data lines 80 of the parallel data bus 60.
  • parallel address lines 90 of the data bus 60 are treated in a similar manner to the data lines 80, such that the data bus conveys address data in a serial manner also, instead of in a parallel manner.
  • the data bus 10 is operable to switch, by suitably controlling the parallel-to-serial data bus interface 50, between conveying address data in a serial manner and in a parallel manner within the data bus 10, so as to make it more difficult for unauthorized third parties to decipher data flows occurring within the data bus 10.
  • the parallel-to-serial data bus interface 50 is conveniently implemented by using standard logic integrated circuits, or by using an field programmable gate array (FPGA), or by using a high-speed reduced-instruction-set-computer (RISC), or by using a custom-designed integrated circuit.
  • FPGA field programmable gate array
  • RISC reduced-instruction-set-computer
  • the data line 20 is arranged to have data words communicated in a serial manner therethrough, temporally commencing for a given data word with a least significant bit (LSB) of the given data word and ending with a most significant data bit (MSB) of the given data word.
  • the data line 20 is arranged to have data words communicated in a serial manner therethrough, temporally commencing for a given data word with a most significant bit (MSB) of the given data word and ending with a least significant data bit (MSB) of the given data word.
  • the order of bits in the given data word in the data line 20 is dynamically varied, to make eavesdropping of the data bus 20 a more complex task for unauthorized third parties.
  • the parallel-to-serial data bus interface 50 is especially useful for financial transaction apparatus, for example in ATM's, when communicating within modules of the financial transaction apparatus, to avoid eavesdropping and hacking by unauthorized personnel.
  • the parallel-to-serial data bus interface 50 is also beneficial to use in military apparatus where it is important to render the military apparatus difficult to hack into, in a digital manner, when capture by enemy forces.
  • the parallel-to-serial data bus interface 50 is useful to employ in situations where invasion by computer viruses is likely to occur, as operation of the data latch 70 tends to "mince” virus code it passes through the parallel-to-serial data bus interface 50, therefore protecting the parallel data bus 60 from virus and malware attack.
  • the data bus 10 is operable to communicate data words have a data width in a range of 4 to 128 bits, for example 32 bits.

Abstract

A data bus (10) for communicating data between a data processing arrangement, a data memory arrangement and an input/output device arrangement, characterized in that the data bus (10) includes at least one serial data line (20) for communicating in operation data in a serial manner, and one or more data control lines (30) for providing additional data for coordinating and/or directing in operation data flowing via the at least one serial data line (20).

Description

DATA BUS AND METHOD
Technical Field
The present disclosure relates toa data bus. Moreover, the present disclosure concerns a method of communicating data in the aforesaid data bus.
Background
Within known contemporary digital apparatus including one or more data processors, one or more data buses are employed to communicate data between processors and also with input/output devices and data memory. Moreover, it is often desirable to design digital apparatus in such a manner that it is more difficult for unauthorized third parties to decipher data flows occurring within one or more data buses of the digital apparatus.
It has been known to employ encryption within data communication arrangements, to protect against unauthorized third party eavesdropping of data flows. However, such encryption imposes a considerable additional computing load on data processors of the data communication arrangements, causing data communication capacity of such data communication arrangements, when using encryption, to be impaired.
A contemporary data bus comprises:
(i) a plurality of parallel data lines, from least significant bit (LSB) to most significant bit (MSB);
(ii) a plurality of address data lines; and
(iii) one or more data control lines.
Serial data communication standards are known, for example MIDI standard for musical instruments, Ethernet and similar.
Summary
The present disclosure seeks to provide an improved data bus that is more robust to eavesdropping. Moreover, the present disclosure seeks to provide an improved data bus that is more flexible in accommodating variable data word size, as well as employing fewer data lines in comparison to conventional known data buses. Furthermore, the present disclosure seeks to provide an improved data bus that is less vulnerable to injection of computer viruses and similar types of malware.
According to a first aspect, there is provided a data bus for communicating data between a data processing arrangement, a data memory arrangement and an input/output device arrangement, characterized in that the data bus includes at least one serial data line for communicating in operation data in a serial manner, and one or more data control lines for providing additional data for coordinating and/or directing in operation data flowing via the at least one serial data line), characterized in that the at least one serial data line (20) is implemented using an optical communication link.
The invention is of advantage in that communicating the at least one serial data line of the data bus assists to transform the data bus into an arrangement that is more difficult to eavesdrop and corrupt.
Optionally, the data bus is implemented using one or more wires, one or more conductive tracks, one or more optical communication links or one or more wireless communication links. Optionally, the data bus is implemented such that address data is communicated via the one or more data control lines. More optionally, the address data is communicated in a serial manner. Yet more optionally, in the data bus, the address data is communicated in a temporally changing manner, switching between serial and parallel communications of the address data.
Optionally, the data bus is implemented such that the at least one serial data line has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last. Optionally, the data bus is implemented such that the at least one serial data line has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last. Optionally, the data bus is implemented such that the at least one serial data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order defined by data conveyed via the one or more data control lines. More optionally, the data bus is implemented such that the at least one serial data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order that varies temporally as defined by data conveyed via the one or more data control lines.
Optionally, the data bus is implemented such that the data bus includes at least one parallel-to-serial interface including at least one latch arrangement with parallel data input/output at a first of its data ports, and serial data input/output at a second of its data ports.
According to a second aspect, there is provided a method of communicating data via a data bus between a data processing arrangement, a data memory arrangement and an input/output device arrangement, characterized in that the method includes:
(i) arranging for the data bus to include at least one serial data line for communicating in operation data in a serial manner;
(ii) arranging for one or more data control lines to provide additional data for coordinating and/or directing in operation data flowing via the at least one serial data line, characterized in that the at least one serial data line (20) is implemented using an optical communication link.
Optionally, the method includes implementing the data bus using one or more wires, one or more conductive tracks, one or more optical communication links or one or more wireless communication links.
Optionally, the method includes communicating the address data via the one or more data control lines. Optionally, the method includes communicating the address data in a serial manner.
Optionally, the method includes communicating the address data in a temporally changing manner, switching between serial and parallel communications of the address data.
Optionally, in the method, the at least one serial data line has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last.
Optionally, in the method, the at least one serial data line has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last. Optionally, in the method, the at least one serial data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order defined by data conveyed via the one or more data control lines. More optionally, in the method, the at least one serial data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order that varies temporally as defined by data conveyed via the one or more data control lines.
Optionally, the method includes arranging for the data bus to include at least one parallel-to-serial interface including at least one latch arrangement with parallel data input/output at a first of its data ports, and serial data input/output at a second of its data ports.
According to an additional aspect, there is provided a data bus for communicating data between a data processing arrangement, a data memory arrangement and an input/output device arrangement, characterized in that the data bus includes at least one serial data line for communicating in operation data in a serial manner, and one or more data control lines for providing additional data for coordinating and/or directing in operation data flowing via the at least one serial data line. Optionally, the data bus is implemented such that the at least one serial data line (20) is implemented using an optical communication link.
According to another additional aspect, there is provided a method of communicating data via a data bus between a data processing arrangement, a data memory arrangement and an input/output device arrangement, characterized in that the method includes:
(i) arranging for the data bus to include at least one serial data line for communicating in operation data in a serial manner;
(ii) arranging for one or more data control lines to provide additional data for coordinating and/or directing in operation data flowing via the at least one serial data line.
Optionally, the method includes implementing the at least one serial data line using an optical communication link.
It will be appreciated that features of the invention are susceptible to being combined in various combinations without departing from the scope of the invention as defined by the appended claims.
Description of the diagrams
Embodiments of the present invention will now be described, by way of example only, with reference to the following diagrams wherein:
FIG. 1 is a schematic illustration of a data bus according to the present disclosure; and
FIG. 2 is a schematic illustration of a serial-to-parallel data bus interface used for implementing embodiments of the present disclosure.
In the accompanying diagrams, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non- underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing. Description of embodiments
In overview, with reference to FIG. 1 , the present disclosure relates to a data bus, indicated generally by 10, that includes a data line 20 (D) that communicates data in a serial manner, wherein the data Iine20 is provided in parallel with one or more data control Iines30. Optionally, one or more of the data control Iines30 are address control lines 40, for example one address control line for conveyingin operation addressdata. Optionally, one or more of the data control lines 30 are clock data lines for providing clock information for temporally coordinating data flows and data exchanges via the data bus 10.
Optionally, the data line 20 and the data control lines 30 are implemented as waveguides for conveying electrical signals at a data bit rate of up to 3 GHz, more optionally up to 10 GHz, and yet more optionally up to 30 GHz. Optionally, the data bus 10 is implemented using electrical tracks or wires, for example formed on an integrated circuit chip or printed circuit board. Optionally, the data bus is implemented, at least in part, using optical communication links, for example optical waveguides, for example the data line 20 is optionally implemented using an optical waveguide, and the one or more data control lines 30 are implemented using wires or conductive tracks.
Referring next to FIG. 2, there is shown an arrangement of digital logic, indicated generally by 50 and referred to as a parallel-to-serial data bus interface, required for interface the data bus 10 to a parallel data bus 60, for example found internally within portions of a circuit board associated with data memory and/or data processors. The parallel-to-serial data bus interface50 includes a data latch 70, wherein:
(i) the data latch 70 is loaded with data in a parallel manner with data from data lines 80 of the parallel data bus 60 and reads out the data of the data latch 70 in a serial manner to generate serial data for the data line 20 of the data bus 10; and
(ii) the data latch 70 is loaded with data in a serial manner with data from the data line 20 and reads out the data of the data latch 70 in a parallel manner to generate parallel data for the data lines 80 of the parallel data bus 60. Optionally, parallel address lines 90 of the data bus 60 are treated in a similar manner to the data lines 80, such that the data bus conveys address data in a serial manner also, instead of in a parallel manner. Optionally, the data bus 10 is operable to switch, by suitably controlling the parallel-to-serial data bus interface 50, between conveying address data in a serial manner and in a parallel manner within the data bus 10, so as to make it more difficult for unauthorized third parties to decipher data flows occurring within the data bus 10.
The parallel-to-serial data bus interface 50 is conveniently implemented by using standard logic integrated circuits, or by using an field programmable gate array (FPGA), or by using a high-speed reduced-instruction-set-computer (RISC), or by using a custom-designed integrated circuit.
Optionally, the data line 20 is arranged to have data words communicated in a serial manner therethrough, temporally commencing for a given data word with a least significant bit (LSB) of the given data word and ending with a most significant data bit (MSB) of the given data word. Alternatively, optionally, the data line 20 is arranged to have data words communicated in a serial manner therethrough, temporally commencing for a given data word with a most significant bit (MSB) of the given data word and ending with a least significant data bit (MSB) of the given data word. Yet more optionally, depending upon data conveyed via the data control lines 30, the order of bits in the given data word in the data line 20 is dynamically varied, to make eavesdropping of the data bus 20 a more complex task for unauthorized third parties. The parallel-to-serial data bus interface 50 is especially useful for financial transaction apparatus, for example in ATM's, when communicating within modules of the financial transaction apparatus, to avoid eavesdropping and hacking by unauthorized personnel. Moreover, the parallel-to-serial data bus interface 50 is also beneficial to use in military apparatus where it is important to render the military apparatus difficult to hack into, in a digital manner, when capture by enemy forces. Furthermore, the parallel-to-serial data bus interface 50 is useful to employ in situations where invasion by computer viruses is likely to occur, as operation of the data latch 70 tends to "mince" virus code it passes through the parallel-to-serial data bus interface 50, therefore protecting the parallel data bus 60 from virus and malware attack.
Optionally, the data bus 10 is operable to communicate data words have a data width in a range of 4 to 128 bits, for example 32 bits.
Modifications to embodiments of the invention described in the foregoing are possible without departing from the scope of the invention as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "consisting of", "have", "is" used to describe and claim the present invention are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. Numerals included within parentheses in the accompanying claims are intended to assist understanding of the claims and should not be construed in any way to limit subject matter claimed by these claims.

Claims

We claim: 1 . A data bus (10) for communicating data between a data processing arrangement, a data memory arrangement and an input/output device arrangement, characterized in that the data bus (10) includes at least one serial data line (20) for communicating in operation data in a serial manner, and one or more data control lines (30) for providing additional data for coordinating and/or directing in operation data flowing via the at least one serial data line (20), characterized in that the at least one serial data line (20) is implemented using an optical communication link.
2. The data bus (10) as claimed in claim 1 , characterized in that the data bus (10) is implemented using one or more wires, one or more conductive tracks, one or more optical communication links or one or more wireless communication links.
3. The data bus (10) as claimed in claim 1 or 2, characterized in that address data is communicated via the one or more data control lines.
4. The data bus (10) as claimed in claim 3, characterized in that the address data is communicated in a serial manner.
5. The data bus (10) as claimed in claim 3, characterized in that the address data is communicated in a temporally changing manner, switching between serial and parallel communications of the address data.
6. The data bus (10) as claimed in any one of the preceding claims, characterized in that the at least one serial data line (20) has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last.
7. The data bus (10) as claimed in any one of the preceding claims, characterized in that the at least one serial data line (20) has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last.
8. The data bus (10) as claimed in any one of the preceding claims, characterized in that the at least one serial data line (20) has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order defined by data conveyed via the one or more data control lines (30).
9. The data bus (10) as claimed in Claim 89, characterized in that the at least one serial data line (20) has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order that varies temporally as defined by data conveyed via the one or more data control lines (30).
10. The data bus (10) as claimed in any one of the preceding claims, characterized in that the data bus (10) includes at least one parallel-to-serial interface (50) including at least one latch arrangement with parallel data input/output at a first of its data ports, and serial data input/output at a second of its data ports.
1 1 . A method of communicating data via a data bus (10) between a data processing arrangement, a data memory arrangement and an input/output device arrangement, characterized in that the method includes:
(i) arranging for the data bus (10) to include at least one serial data line (20) for communicating in operation data in a serial manner;
(ii) arranging for one or more data control lines (30) to provide additional data for coordinating and/or directing in operation data flowing via the at least one serial data line (20), characterized in that the at least one serial data line (20) is implemented using an optical communication link.
12. The method as claimed in claim 1 1 , characterized in that the method includes implementing the data bus (10) using one or more wires, one or more conductive tracks, one or more optical communication links or one or more wireless communication links.
13. The method as claimed in claim 1 1 or 12, characterized in that the method includes communicating the address data via the one or more data control lines.
14. The method as claimed in claim 13, characterized in that the method includes communicating the address data in a serial manner.
15. The method as claimed in claim 13, characterized in that the method includes communicating the address data in a temporally changing manner, switching between serial and parallel communications of the address data.
16. The method as claimed in any one of claims 1 1 to 15, characterized in that the at least one serial data line (20) has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last.
17. The method as claimed in any one of claims 1 1 to 1 6, characterized in that the at least one serial data line (20) has its data words occurring with their least significant bit (LSB) first and their most significant bit (MSB) last.
18. The method as claimed in any one of claims 1 1 to 17, characterized in that the at least one serial data line (20) has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order defined by data conveyed via the one or more data control lines (30).
19. The method as claimed in Claim 18, characterized in that the at least one serial data line (20) has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order that varies temporally as defined by data conveyed via the one or more data control lines (30).
20. The method as claimed in any one of claims 1 1 to 19, characterized in that the method includes arranging for the data bus (10) to include at least one parallel-to- serial interface (50) including at least one latch arrangement with parallel data input/output at a first of its data ports, and serial data input/output at a second of its data ports.
PCT/EP2017/025130 2016-05-23 2017-05-16 Data bus and method WO2017202501A1 (en)

Applications Claiming Priority (2)

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GB1609061.5 2016-05-23
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US20040126115A1 (en) * 2002-12-31 2004-07-01 Levy Paul S. System having multiple agents on optical and electrical bus
US20050066136A1 (en) * 2003-09-18 2005-03-24 Schnepper Randy L. Memory hub with integrated non-volatile memory

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