GB2550590A

GB2550590A - Data bus and method

Info

Publication number: GB2550590A
Application number: GB1609061.5A
Authority: GB
Inventors: Forbes Donald
Original assignee: Individual
Current assignee: Individual
Priority date: 2016-05-23
Filing date: 2016-05-23
Publication date: 2017-11-29
Anticipated expiration: 2036-05-23
Also published as: GB2550590B; GB201609061D0; WO2017202501A1

Abstract

A data bus 10 is provided for communicating data between a plurality of devices 90 that are mutually coupled via the data bus. The devices each include a digital logic arrangement 50 for interfacing to the data bus. The data bus is operable to employ a plurality of phase lines φ1, φ2, 44, 46 for signalling data communication via the data bus, wherein a first phase line φ1, 44 is employed for acknowledging receipt of data at a receiving device 90, and at least a second phase line φ2, 46 is employed for signalling other information than acknowledging receipt of the data at the receiving device 90. The data bus may further include at least one data line D, 20 and one or more clock lines CLK, 40, relative to which the phase lines are asynchronous. In operation the first phase line φ1, 44 may be triggered prior to the second phase line φ2, 46. The data lines and the clock lines can be level-triggered and the phase lines edge-triggered.

Description

DATA BUS AND METHOD Technical Field

The present disclosure relates to data buses. Moreover, the present disclosure concerns a method of communicating data via the aforesaid data buses.

Background

Digital output apparatus providing binary-valued outputs are known, for example when implemented as digital logic systems and components thereof. Often, the output devices conventionally employ a parallel architecture internally therein.

Within known contemporary digital apparatus including one or more data processors, one or more data buses are employed to communicate data between the one or more data processors and also with input/output devices and data memory. Moreover, it is often desirable to design digital apparatus in such a manner that it is more difficult for unauthorized third parties to decipher data flows occurring within one or more data buses of the digital apparatus. Moreover, it is often desirable to be able to debug problems arising when data transmissions occur via one or more data buses of the digital apparatus.

It has been known to employ encryption within data communication arrangements, thereby protecting against unauthorized third party eavesdropping of data flows. However, such encryption imposes a considerable additional computing load on one or more data processors of the data communication arrangements. Moreover, employing encryption within the data communication arrangements is ineffective if the data communication arrangements have been compromised in other ways, for example as a result of undetected malware providing unencrypted routes for data to be disseminated. Moreover, in an event of digital communication bugs arising, for example data transmission errors occurring or statis in the data communication arrangements arising, debugging when heavily encrypted data is being communicated is especially complex to perform. A contemporary data bus comprises: (i) a plurality of parallel data lines, from a least significant bit (LSB) to a most significant bit (MSB); (ii) a plurality of address data lines; and (iii) one or more data control lines.

Serial data communication standards are also known, for example MIDI standard for musical instruments, Ethernet and similar.

In a Chinese patent CN104486111, there is described a 1553B data bus system network management method. According to the method, there is provided in respect of a 1553B data bus a method of "sending a real time clock (RTC) and judging an online state and an offline state according to a responder", and "sending a vector character by a remote terminal and reporting a data state". The method is concerned with addressing a requirement to operate, in a collaborative manner, a bus command and node state in a 1553B data bus with dynamic bus control. In order to address the requirement, the online state and the data update state of the remote terminal are obtained by uniformly coordinating a bus controller in order to obtain an effect of "only sending a command for the online state", and "only sending a command for data update", thereby reducing bus occupation by ineffective commands. However, such a minimalistic approach does not necessarily provide for enhanced data bus security against third party attack, and are potentially complex to debug in an event of data transmission errors occurring in operation.

Summary

The present disclosure seeks to provide an improved data bus that is more robust to unauthorized eavesdropping, whilst providing for efficient and coordinated data communication.

Moreover, the present disclosure seeks to provide an improved data bus that is more effective at enabling debugging of transmission errors, unwanted statis (i.e. "hanging up") of the data bus.

Furthermore, the present disclosure seeks to provide an Improved data bus that Is less vulnerable to injection of computer viruses and similar types of malware.

According to a first aspect, there is provided a data bus for communicating data between a plurality of devices that are mutually coupled via the data bus, wherein the devices each include a digital logic arrangement for interfacing to the data bus, characterized in that the data bus is operable to employ a plurality of phase lines {φί, ψι) for signalling data communication via the data bus, wherein a first phase line {¢{) is employed for acknowledging receipt of data at a receiving device, and at least a second phase line {φι) is employed for signalling other information than acknowledging receipt of the data at the receiving device.

The invention is of advantage in that communicating data via the at least one data line of the data bus in combination with employing a plurality of phase lines {φί, φι) assists to render the data bus more difficult to eavesdrop and corrupt.

Optionally, the data bus (10) further includes at least one data line (D) for communicating data packets, and one or more clock lines (CLK), wherein the at least one data line (D) is mutually synchronous with the one or more clock lines (CLK).

More optionally, in the data bus, the plurality of phase lines {φ\, φη) are asynchronous relative to the at least one data line (D) and the one or more clock lines (CLK).

More optionally, in the data bus, the at least one data lines (D) and the one or more clock lines (CLK) are level-triggered lines, and the plurality of phase lines {φί, φι) are edge-triggered lines.

Optionally, in the data bus, in operation, the first phase line {φ{) is triggered prior to the second phase line {φι) being triggered.

Optionally, in the data bus, the phase lines {φι, φι) are non-mandatory for a data sending device to act upon.

Optionally, the data bus is arranged to provide transmission of data between a processing arrangement, a data memory arrangement and an input/output device arrangement via at least one data line (D), and one or more control lines of the data bus are employed for providing additional data for coordinating and/or directing in operation data flowing via the at least one data line.

More optionally, in the data bus, the at least one data line is implemented using an optical communication link.

Optionally, the data bus is implemented using one or more wires, one or more conductive tracks, one or more optical communication links or one or more wireless communication links.

Optionally, in the data bus, the at least one data line has its data words occurring with their least significant bit (LSB) temporally first and their most significant bit (MSB) temporally last.

Optionally, in the data bus, the at least one data line has its data words occurring with their most significant bit (MSB) temporally first and their least significant bit (LSB) temporally last.

Optionally, in the data bus, the at least one data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in a temporal order defined by data conveyed via the one or more control lines.

More optionally, in the data bus, the at least one data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order that varies temporally as defined by data conveyed via the one or more control lines.

Optionally, in the data bus the interfacing arrangement includes at least one latch arrangement with parallel data input/output at a first of its data ports, and serial data input/output at a second of its data ports.

According to a second aspect, there is provided a method of using a data bus for communicating data between a plurality of devices that are mutually coupled via the data bus, wherein the devices each include a digital logic arrangement for interfacing to the data bus, characterized in that the method includes arranging for the data bus to employ a plurality of phase lines {φί, φι) for signalling data communication via the data bus, wherein a first phase line {¢{) is employed for acknowledging receipt of data at a receiving device, and at least a second phase line {φι) is employed for signalling other information than acknowledging receipt of the data at the receiving device.

Optionally, the method includes arranging for the data bus to include at least one data line (D) for communicating data packets, and one or more clock lines (CLK) that are synchronous with the at least one data lines (D).

Optionally, the method includes arranging for the plurality of phase lines {φί, φι) to be asynchronous relative to the at least one data line (D) and the one or more clock lines (CLK).

Optionally, the method includes arranging for at least one data lines (D) and the one or more clock lines (CLK) to be level-triggered lines, and the plurality of phase lines {φι, φι) to be edge-triggered lines.

Optionally, in the method, in operation, the first phase line {φι) is triggered prior to the second phase line {Φ2) being triggered.

Optionally, in the method, the phase lines {φι, φι) are non-mandatory for a data sending device to act upon.

Optionally, the method includes arranging for the data bus to provide transmission of data between a processing arrangement, a data memory arrangement and an input/output device arrangement via at least one data line (D), and one or more control lines of the data bus to be employed for providing additional data for coordinating and/or directing in operation data flowing via the at least one data line.

More optionally, in the method, the at least one data line is implemented using an optical communication link.

Optionally, in the method, the data bus is implemented using one or more wires, one or more conductive tracks, one or more optical communication links or one or more wireless communication links.

Optionally, in the method, the at least one data line has its data words occurring with their least significant bit (LSB) temporally first and their most significant bit (MSB) temporally last.

Optionally, in the method, the at least one data line has its data words occurring with their most significant bit (MSB) temporally first and their least significant bit (LSB) temporally last.

Optionally, in the method, the at least one data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in a temporal order defined by data conveyed via the one or more control lines.

More optionally, in the method, the at least one data line has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order that varies temporally as defined by data conveyed via the one or more control lines.

Optionally, in the method, the interfacing arrangement includes at least one latch arrangement with parallel data input/output at a first of its data ports, and serial data input/output at a second of its data ports.

It will be appreciated that features of the invention are susceptible to being combined in various combinations without departing from the scope of the invention as defined by the appended claims.

Description of the diagrams

Embodiments of the present invention will now be described, by way of example only, with reference to the following diagrams wherein: FIG. 1 is a schematic illustration of a data bus according to the present disclosure; FIG. 2 is a schematic iiiustration of a data bus interface used for impiementing embodiments of the present disciosure; FIG. 3 is a schematic iiiustration of a configuration of a piuraiity of data bus interfaces of FIG. 2 that are operabie to provide for bi-direction data communication between two systems coupied via the data bus of FIG. 1; and FIG. 4 is a schematic iiiustration of various data controi iines of the data bus of FIG. 1.

In the accompanying diagrams, an underiined number is empioyed to represent an item over which the underiined number is positioned or an item to which the underiined number is adjacent. A non-underiined number reiates to an item identified by a iine iinking the non-underiined number to the item. When a number is non-underiined and accompanied by an associated arrow, the non-underiined number is used to identify a generai item at which the arrow is pointing.

Description of embodiments

According to a first aspect, there is provided a data bus for communicating data between a plurality of devices that are mutually coupled via the data bus, wherein the devices each include a digital logic arrangement for interfacing to the data bus, characterized in that the data bus is operable to employ a plurality of phase lines {φί, ψι) for signalling data communication via the data bus, wherein a first phase line {¢{) is employed for acknowledging receipt of data at a receiving device, and at least a second phase line {φζ) is employed for signalling other information than acknowledging receipt of the data at the receiving device.

Optionally, the data bus (10) further includes at least one data line (D) for communicating data packets, and one or more clock lines (CLK) that are synchronous with the at least one data lines (D).

More optionaliy, in the data bus, the piuraiity of phase iines {φι, φι) are asynchronous reiative to the at ieast one data iine (D) and the one or more dock iines (CLK).

Optionally, in the data bus, in operation, the first phase line {¢{) is triggered prior to the second phase line {φι) being triggered.

According to a second aspect, there is provided a method of using a data bus for communicating data between a plurality of devices that are mutually coupled via the data bus, wherein the devices each include a digital logic arrangement for interfacing to the data bus, characterized in that the method includes arranging for the data bus to employ a plurality of phase lines {φι, φζ) for signalling data communication via the data bus, wherein a first phase line {¢{) is employed for acknowledging receipt of data at a receiving device, and at least a second phase line {ψζ) is employed for signalling other information than acknowledging receipt of the data at the receiving device.

Optionally, the method includes arranging for the plurality of phase lines {ψι, ψζ) to be asynchronous relative to the at least one data line (D) and the one or more clock lines (CLK).

Optionally, the method includes arranging for at least one data lines (D) and the one or more clock lines (CLK) to be level-triggered lines, and the plurality of phase lines {ψί, ψζ) to be edge-triggered lines.

Optionally, in the method, in operation, the first phase line {¢{) is triggered prior to the second phase line {ψζ) being triggered.

Optionally, in the method, the phase lines {φι, φ£) are non-mandatory for a data sending device to act upon.

In overview, with reference to FIG. 1, the present disclosure relates to a data bus, indicated generally by 10, that includes at least one data line 20 (D) that communicates data, wherein the at least one data line 20 is provided together with one or more control lines 30. Optionally, for the data bus 10, there is included a plurality of data lines 20 (D). Optionally, the at least one data line (D) 20 is operable to communicate a serial data flow.

Optionally, one or more of the data control lines 30 include: (ii) one or more clock lines (CLK) 40 for providing clock information for temporally coordinating data flows and data exchanges via the data bus 10; and (iv) a plurality of phase lines, for example two phase lines {ψί, φι) 44, 46.

The at least one data line 20, and the one or more control lines 30 are interfaced in operation via a digital logic arrangement logic 50, for example providing an interface for a specific device (not shown) coupled to the data bus 10. The control lines 30 will be described in greater detail later, with reference to FIG. 3. Thus, a plurality of the of digital logic arrangements 50 can be coupled onto the data bus 10, if required.

Referring again to FIG. 1, optionally, the at least one data line (D) 20 and the control lines 30 are implemented as waveguides for conveying electrical signals at a data bit rate of up to 3 GHz, more optionally up to 10 GHz, and yet more optionally up to 30 GHz. Optionally, the data bus 10 is implemented using electrical tracks or wires, for example formed onto an integrated circuit chip by microfabrication, onto a hybrid chip header (as in a customer hybrid integrated circuit module), or onto a printed circuit board. Optionally, the data bus 10 is implemented, at least in part, using optical communication links, for example optical waveguides, for example the at least one data line 20 is optionally implemented using an optical waveguide, and the one or more control lines 30 are implemented using optical waveguides, wires or conductive tracks, for example as aforementioned.

Referring next to FIG. 2, there is shown an implementation of the digital logic arrangement 50, and referred to here as a parallel-to-serial data bus interface, required for interfacing the data bus 10 to a parallel data bus 60. Thus, the digital logic arrangement 50 is conveniently implemented to operate to provide for uni-direction data flow therethrough. Optionally, when bi-directional data flow is required in operation between two systems 90 via the data bus 10, a pair of digital logic arrangements 50 is employed in forward and reverse directions, as depicted in FIG. 3. The digital logic arrangement 50 optionally includes a data latch 70, wherein: (i) the data latch 70 is loaded with data in a parallel manner with data from data lines 80 of the parallel data bus 60 and reads out the data of the data latch 70 in a serial manner to generate serial data for the at least one data line 20 of the data bus 10; or (ii) the data latch 70 is loaded with data in a serial manner with data from the at least one data line 20 and reads out the data of the data latch 70 in a parallel manner to generate parallel data for the data lines 80 of the parallel data bus 60.

Thus, the digital logic arrangement 50 is optionally implemented in a unidirectional manner, such that bi-directional communication between the data bus 10 and the data bus 60 is provided by using a configuration of two digital logic arrangements 50 arranged in opposite directions in respect of their data buses 10, 60, namely as illustrated in FIG. 3.

The control lines 30 are included for synchronizing and coordinating data exchanges via the data bus 10.

The digital logic arrangement 50 is conveniently implemented by using standard logic integrated circuits, or by using a field-programmable gate array (FPGA), or by using a high-speed reduced-instruction-set-computer (RISC), or by using a custom-designed integrated circuit.

Optionally, the at least one data line (D) 20 is operable to have data words communicated in a serial manner therethrough, temporally commencing for a given data word with a least significant bit (LSB) of the given data word and ending with a most significant data bit (MSB) of the given data word. Aiternativeiy, optionaiiy, the at ieast one data iine 20 is arranged to have data words communicated in a seriai manner therethrough, temporally commencing for a given data word with a most significant bit (MSB) of the given data word and ending with a ieast significant data bit (MSB) of the given data word. Yet more optionaiiy, depending upon data conveyed via the control lines 30, the order of bits in the given data word communicated via the at ieast one data line 20 is dynamicaiiy varied, to make eavesdropping of the data bus 10 a more compiex task for unauthorized third parties.

The digitai iogic arrangement 50, nameiy paraiiei-to-seriai data bus interface, is especiaiiy usefui when performing financiai transactions, namely using financial transaction apparatus, for exampie in ATM's, when communicating within moduies of the financiai transaction apparatus, to avoid eavesdropping and hacking by unauthorized personnei. Moreover, the digital logic arrangement 50, nameiy paraiiei-to-seriai data bus interface, is also beneficial to use in military apparatus where it is important to render the military apparatus difficult to hack into, in a digitai manner, when captured by enemy forces. Furthermore, the digitai iogic arrangement 50 is useful to employ in situations where invasion by computer viruses is likely to occur, as operation of the data latch 70 tends to "mince" virus code as it passes through the digital logic arrangement 50, therefore protecting the parallel data bus 60 from virus and malware attack. Such virus code is devised by third parties to interface directly to the data bus 60, so data manipulation executed by the digital logic arrangement 50 tends to disorganize such virus code and render it impotent.

Optionally, the data bus 10 is operable to communicate data words have a data width in a range of 4 to 128 bits, for example 32 bits.

Referring next to FIG. 4, the data control lines 30 include, for example, as aforementioned: (i) one or more clock lines (CLK) 40 for providing for synchronizing to individual data bits communicated via the data line (D) 20; (ii) a plurality of phase lines, for example two phase lines {φι, φι) 44, 46, for providing control information for temporally coordinating data flows and data exchanges via the data bus 10 (via use of the phase data line {φί, 44)), for example to indicate that the data bus 10 is clear, or that the data bus 10 has reached statis (namely has become inactive because it has ''hung up" in an unwanted (disallowed)stalled state) (via use of the phase data line {ψζ, 46)).

The plurality of phase lines {φί, φι, 44, 46) are logically edge-triggered signals, and are asynchronous relative to the one or more clock lines (CLK) 40 and the at least one data line (D) 20. A first phase line (^, 44) is employed by a receiver of data via the digital logic arrangement 50 to provide an acknowledgement that data has been successfully received. Moreover, a second phase line (^, 46) is employed by a receiver of data via the digital logic arrangement 50 to provide an acknowledgement for a different reason than successful receipt of data, for example that: (i) statis has occurred of that the receiver of data is unable to receive further new data; or (ii) an encryption algorithm employed to encrypt data to be communicated via the data bus 10 should be modified, for example to an alternative encryption and/or obfuscation algorithm, for example to frustrate third party eavesdropping of the data bus 10; or (iii) that a form of data corruption has occurred in data transmitted via the data bus 10, and so forth.

Beneficially, the first phase line (^, 44) is conceived to be a simple and normal hardware acknowledgement of given transfer. However, in contradistinction, the second phase line {φι, 46) is conceived to be for further acknowledging transfer of data, but programmable by a receiver of information from the data bus 10, such that a number of cycles of data transfer may have occurred before the second phase line {φι, 46), for example in respect of issues arising in data packet assembly. Thus, unlike the first phase line (¢)1, 44), the second phase line {φι, 46) is capable of providing the data bus 10 with a recovery mode to avoid the system falling into statis, thereby enabling recovery to be achieved from such stasis (namely, data bus "lockup" or "hang-up"). Optionally, more than two phase lines are employed to provide for more comprehensive debugging of the data bus 10, when statis or similar types of events occur.

The at least one data line (D) 20 and the one or more clock (CLK) lines 40 are level triggered, namely are regarded as having a binary state 0 or 1 depending upon a magnitude of the at least one data line (D) 20 and the one or more clock (CLK) lines 40, for example depending upon their voltage level. In contradistinction, optionally, the phase lines (^, φι, 44, 46) are edge-triggered such that a change in their levels indicates a data value, for example a rising edge indicates a value "1" and a falling edge indicates a value "0". The phase lines {φί, φι, 44, 46) superficially may appear similar to a hardware interrupt, but are not interrupts, in that they are not obligatory for a sender of data to respond to receipt of information sent via the phase data lines {φί, φι, 44, 46); in other words, the phase lines {φ\, φι, 44, 46) are not mandatory signals, but merely conveying information that is useful to operation of the data bus 10, for example for automatic reset purposes after statis has occurred and/or for debugging purposes. Moreover, optionally, only a single data line (D, 20) is provided in the data bus 10, for example data is sent serially via the data bus 10. In embodiments of the present disclosure, the phase lines {φί, φι, 44, 46) are not required to be configured in mutual anti-phase, but can be toggled mutually Independently. The phase lines {φι, φι, 44, 46) are switched in a manner to avoid temporal ambiguity, such the first phase line {φί, 44) is raised before the second phase line (Φ2, 46) is raised, in a normal manner of operation or data communication via the data bus 10.

Optionally, pre-processing and post-processing are optionally possible for the digital logic arrangement 50.

Data edges of the data line (D) 20 are temporally synchronous to the one or more clock lines (CLK) 40, as aforementioned.

When the data bus 10 is in operation, the one or more control lines 30 provide following functions: (i) the one or more clock lines (CLK) 40 are operable to establish synchronization of communication in the data bus 10; (iii) one or more phase lines {φί, φ£) 44, 46 are operable to provide signalling by edge triggering, for purpose of indicating that a system associated with the data bus 10 , for example a device "hung" (namely coupled) onto the data bus 10, is now clear to process more information or supply more information.

Embodiments of the present disclosure are susceptible to being implemented with various modifications. Optionally, the data bus 10 is operable to switch, by suitably controlling the parallel-to-serial data bus interface 50, dynamically between conveying data in a serial manner and in a parallel manner within the data bus 10, so as to make it more difficult for unauthorized third parties to decipher data flows occurring within the data bus 10.

The data bus 10 is capable of enabling a digital system coupled to the data bus 10 to output digital values with a particular view with regard to acknowledgement of output of the digital values. Clocked output is present in the data bus 10 at a phase of the one or more clock lines (CLK) 40 and is registered by receiving logic if it is present and operating correctly. In the data bus 10, such output data is presented against clock timing, as aforementioned. When implementing the data bus 10, there is conveniently employed open-collector or open-drain transistor configurations, for example as known for use in contemporary Ethernet-type data buses on which multiple devices can be directly coupled onto the data buses. The one or more phase lines {φι, φι) 44, 46 are employed for a higher layer or higher level of communication protocol on the data bus 10, as aforementioned; for example, the one or more phase lines {φί, φτ) 44, 46 are used to signal commencement and termination of a communication of a data packet comprising a plurality of bytes of data between several devices coupled to the data bus 10. In an event that a given byte of the data packet is not successfully received, such that an acknowledgement is not received in the data bus 10 via the first phase signal (¢51, 44), then the given byte can be retransmitted rather than having to retransmit the entire data packet again.

The data bus 10 conveniently employs a communication protocol, as follows: STEP 1: In respect of the clock line (CLK), the first phase line {φ\, 44) is raised for indicating that a data packet has now been transmitted, wherein the second phase line {φι, 46) is kept in abeyance. A second packet may optionally be Initiated, but will take, for example, 16 clock cycles to complete. During communication of the second data packet, the second phase line (jfc, 46) is raised, again as a level trigger, namely asynchronously in respect of the clock line (CLK) 40. STEP 2: to complete transfer of the second data packet, the second phase line {ψ2, 46) is raised. A key significant of the second phase line {φι, 46) is that it enables a staging of responses in the data bus 10 and associated devices coupled, thereto as a whole. There is thereby provided a second level of protocol that Is susceptible to being implemented with relatively minimal digital hardware. A very fine-grain control is thereby achievable, substantially unbreakable in the form employed.

As aforementioned, higher levels of protocol for data communication in the data bus 10, can be employed to obtain even more reliable and efficient data communication within the data bus 10. Moreover, such higher levels of protocol are useful when debugging the data bus 10 when developing new devices for use with the data bus 10.

Modifications to embodiments of the invention described in the foregoing are possible without departing from the scope of the invention as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "consisting of", "have", "is" used to describe and claim the present invention are intended to be construed in a non-exclusive manner, namely allowing for Items, components or elements not explicitly described also to be present. Reference to the singular Is also to be construed to relate to the plural. Numerals Included within parentheses in the accompanying claims are intended to assist understanding of the claims and should not be construed in any way to limit subject matter claimed by these claims.

Claims

CLAIMS We claim:

1. A data bus (10) for communicating data between a plurality of devices (90) that are mutually coupled via the data bus (10), wherein the devices each include a digital logic arrangement (50) for interfacing to the data bus (10), characterized in that the data bus (10) is operable to employ a plurality of phase lines {φί, φι, 44, 46) for signalling data communication via the data bus (10), wherein a first phase line {φ\, 44) is employed for acknowledging receipt of data at a receiving device (90), and at least a second phase line {ψι, 46) is employed for signalling other information than acknowledging receipt of the data at the receiving device (90).

2. A data bus (10) of claim 1, characterized in that the data bus (10) further includes at least one data line (D, 20) for communicating data packets, and one or more clock lines (CLK, 40) that are synchronous with the at least one data lines (D, 20).

3. A data bus (10) of claim 2, characterized in that the plurality of phase lines {φί, φι, 44, 46) are asynchronous relative to the at least one data line (D, 20) and the one or more clock lines (CLK, 40).

4. A data bus (10) of claim 2 or 3, characterized in that the at least one data lines (D, 20) and the one or more clock lines (CLK, 40) are level-triggered lines, and the plurality of phase lines {φ\, φι, 44, 46) are edge-triggered lines.

5. A data bus (10) of any one of claims 1 to 4, characterized in that, in operation, the first phase line {φί, 44) is triggered prior to the second phase line {φι, 46) being triggered.

6. A data bus (10) of any one of claims 1 to 5, characterized in that the phase lines {φί, φ2, 44, 46) are non-mandatory for a data sending device (90) to act upon.

7. A data bus (10) of any one of claims 1 to 6, characterized in that the data bus (10) is arranged to provide transmission of data between a processing arrangement, a data memory arrangement and an input/output device arrangement via at least one data line (D, 20), and one or more control lines (30) of the data bus (10) are employed for providing additional data for coordinating and/or directing in operation data flowing via the at least one data line (20).

8. A data bus (10) of claim 7, characterized in that the at least one data line (20) is implemented using an optical communication link.

9. A data bus (10) of any one of claims 1 to 8, characterized in that the data bus (10) is implemented using one or more wires, one or more conductive tracks, one or more optical communication links or one or more wireless communication links.

10. A data bus (10) of any one of the preceding claims, characterized in that the at least one data line (20) has its data words occurring with their least significant bit (LSB) temporally first and their most significant bit (MSB) temporally last.

11. A data bus (10) of any one of claims 1 to 9, characterized in that the at least one data line (20) has its data words occurring with their most significant bit (MSB) temporally first and their least significant bit (LSB) temporally last.

12. A data bus (10) of any one of claims 1 to 9, characterized in that the at least one data line (20) has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in a temporal order defined by data conveyed via the one or more control lines (30).

13. A data bus (10) of claim 12, characterized in that the at least one data line (20) has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order that varies temporally as defined by data conveyed via the one or more control lines (30).

14. A data bus (10) of any one of the preceding claims, characterized in that the interfacing arrangement (50) includes at least one latch arrangement with parailei data input/output at a first of its data ports, and serial data input/output at a second of its data ports.

15. A method of using a data bus (10) for communicating data between a piurality of devices (90) that are mutually coupled via the data bus (10), wherein the devices (90) each inciude a digital logic arrangement (50) for interfacing to the data bus (10), characterized in that the method includes arranging for the data bus (10) to empioy a plurality of phase lines {φι, ψι, 44, 46) for signailing data communication via the data bus (10), wherein a first phase line {ψι, 44) is empioyed for acknowiedging receipt of data at a receiving device (90), and at ieast a second phase iine (<fc, 46) is employed for signalling other information than acknowiedging receipt of the data at the receiving device (90).

16. A method of ciaim 15, characterized in that the method includes arranging for the data bus (10) to include at least one data line (D, 20) for communicating data packets, and one or more clock lines (CLK, 40) that are synchronous with the at ieast one data iines (D, 20).

17. A method of ciaim 16, characterized in that the method includes arranging for the piuraiity of phase iines {φι, ψι, 44, 46) to be asynchronous relative to the at ieast one data iine (D, 20) and the one or more clock lines (CLK, 40).

18. A method of ciaim 16 or 17, characterized in that the method includes arranging for at ieast one data lines (D, 20) and the one or more clock lines (CLK, 40) to be ievei-triggered lines, and the plurality of phase lines {φ\, φι, 44, 46) to be edge-triggered iines.

19. A method of any one of claims 15 to 18, characterized in that, in operation, the first phase line {φί, 44) is triggered prior to the second phase line {φ2, 46) being triggered.

20. A method of any one of claims 15 to 19, characterized in that the phase lines {φί, φι, 44, 46) are non-mandatory for a data sending device (90) to act upon.

21. A method of any one of claims 15 to 20, characterized in that the method includes arranging for the data bus (10) to provide transmission of data between a processing arrangement, a data memory arrangement and an input/output device arrangement via at least one data line (D, 20), and one or more control lines (30) of the data bus (10) to be employed for providing additional data for coordinating and/or directing in operation data flowing via the at least one data line (20).

22. A method of claim 21, characterized in that the at least one data line (20) is implemented using an optical communication link.

23. A method of any one of claims 15 to 22, characterized in that the data bus (10) is implemented using one or more wires, one or more conductive tracks, one or more optical communication links or one or more wireless communication links.

24. A method of any one of claims 15 to 23, characterized in that the at least one data line (20) has its data words occurring with their least significant bit (LSB) temporally first and their most significant bit (MSB) temporally last.

25. A method of any one of claims 15 to 23, characterized in that the at least one data line (20) has its data words occurring with their most significant bit (MSB) temporally first and their least significant bit (LSB) temporally last.

26. A method of any one of claims 15 to 23, characterized in that the at least one data line (20) has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in a temporal order defined by data conveyed via the one or more control lines (30).

27. A method of claim 26, characterized in that the at least one data line (20) has its data words occurring with their least significant bit (LSB) and their most significant bit (MSB) in an order that varies temporally as defined by data conveyed via the one or more control lines (30).

28. A method of any one of claims 15 to 27, characterized in that the interfacing arrangement (50) includes at least one latch arrangement with parallel data input/output at a first of its data ports, and serial data input/output at a second of its data ports.