WO2017193716A1 - 一种极化码的编码和速率匹配方法、装置及设备 - Google Patents

一种极化码的编码和速率匹配方法、装置及设备 Download PDF

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WO2017193716A1
WO2017193716A1 PCT/CN2017/078313 CN2017078313W WO2017193716A1 WO 2017193716 A1 WO2017193716 A1 WO 2017193716A1 CN 2017078313 W CN2017078313 W CN 2017078313W WO 2017193716 A1 WO2017193716 A1 WO 2017193716A1
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deleted
bits
column
matrix
coded
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PCT/CN2017/078313
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English (en)
French (fr)
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陈莹
罗禾佳
李榕
李斌
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华为技术有限公司
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Priority to EP17795334.6A priority Critical patent/EP3444980B1/en
Publication of WO2017193716A1 publication Critical patent/WO2017193716A1/zh
Priority to US16/186,437 priority patent/US10797826B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • Embodiments of the present invention relate to a wireless communication technology, and in particular, to a method, an apparatus, and a device for encoding and rate matching a polarization code.
  • the Internet of Things (English: Internet of Things: IoT) communication system presents some new features, such as high reliability, low complexity and wide coverage.
  • Polar Code (Polar Code) is the first and only known channel coding method that can be rigorously proven to "reach" the Shannon limit.
  • a brief description of the coded code of the polarization code is as follows:
  • the polarization code is a linear code. Let its generator matrix (or coding matrix) be G N and its encoding process is among them It is a bit to be encoded of length N, and N is a positive integer greater than 1. G N is an N ⁇ N matrix, and among them, B N is an N ⁇ N transposed matrix, such as a Bit Reversal matrix; It is the product of the log 2 N F 2 Kronecker; the addition and multiplication operations mentioned above are the addition and multiplication operations on the binary Galois field.
  • the most basic decoding method of the polarization code is continuous elimination (English: Successive Cancellation; abbreviation: SC) decoding, and the subsequent SC-List decoding algorithm is extended by horizontal path and cyclic redundancy check (English: Cyclic Redundancy Check) Abbreviation: CRC)
  • SC Successive Cancellation
  • CRC Cyclic Redundancy Check
  • One type of rate matching scheme for polarized codes is to concatenate the polarization code with another linear block code and to implement the encoding of the arbitrary code length as the inner code.
  • This type of scheme requires two different encoders and decoders when encoding the code to increase the complexity and cost of implementation.
  • Another type of rate matching scheme for polarization codes is to find the optimal or suboptimal puncturing method by exhaustive or greedy algorithms to reduce the effect of rate matching on the performance of the polarization code.
  • the exhaustive method needs to traverse every possible puncturing method, calculate the reliability of its corresponding information bits, and determine the puncturing bits according to the level of reliability.
  • the biggest drawback of this type of solution is the complexity. If a greedy algorithm is used, only the puncturing method that has the least influence on the information bit reliability can be selected. Although the greedy algorithm can reduce the amount of calculation, its complexity is still large.
  • the embodiments of the present invention provide a method, a device, and a device for encoding and rate matching a polarization code to implement joint coding and rate matching, thereby greatly reducing computational complexity.
  • an embodiment of the present invention provides a method for encoding and rate matching a polarization code, including:
  • Determining one or more rows to be deleted of the generation matrix wherein the generation matrix is determined by a preset mother code length, and the column of the one or more rows to be deleted includes at least one column weight of 1 Column
  • the coded bits are encoded and rate matched according to the final generator matrix.
  • the polarization code of different target code lengths under the same mother code does not need to perform reliability calculation to determine the position of the information bit and the fixed bit. This eliminates the need to repeatedly calculate reliability ordering, and therefore can greatly reduce computational complexity.
  • the reliability of the one or more rows to be deleted is obtained by querying a reliability ranking table, where the reliability ranking table indicates different mother code lengths and different positions of the to-be-transmitted vector under different transport block sizes.
  • the vector to be transmitted is a vector having a length equal to the length of the mother code.
  • Polarization codes of different target code lengths can be encoded according to the reliability order of the same mother code length.
  • the reliability order of different target code lengths under the same mother code length can be obtained by looking up the table or by calculating it once. This can greatly reduce the number of tables and the computational complexity.
  • the bit to be encoded is obtained by placing information bits and fixed bits in the to-be-coded vector according to reliability order, wherein a position corresponding to all the deleted columns of the initial generation matrix is A puncturing position, the final generation matrix placing a fixed bit at the puncturing position relative to a position corresponding to all deleted rows of the initial generation matrix.
  • the encoding and rate matching of the to-be-coded bits according to the final generation matrix includes: deleting the fixed bits corresponding to all the deleted lines in the to-be-coded bits;
  • the generation matrix determined by the code length is encoded according to the final generation matrix, and the bits to be coded after the punctured deletion are encoded to obtain the coded and rate matched bits.
  • the encoding and rate matching of the to-be-coded bits according to the final generation matrix includes: encoding, according to a generation matrix determined by the mother code length, a coded bit; The puncturing position punctifies the encoded bits to obtain coded and rate matched bits.
  • the method provided by the embodiment of the invention can implement coding and rate matching at the same time, which simplifies the calculation complexity and reduces the amount of the table.
  • an embodiment of the present invention provides a coding and rate matching apparatus for a polarization code, including:
  • a determining module configured to determine one or more rows to be deleted of the generating matrix, wherein the generating matrix is determined by a preset mother code length, and the column of the one or more rows to be deleted includes at least a column a column with a column weight of 1;
  • a deleting module configured to delete a row corresponding to the least reliable polarized channel of the one or more to-be-deleted rows, and delete a column in the column where the row 1 of the row is 1 to be deleted, and obtain the deleted column.
  • control module configured to send the deleted generation matrix to the determining module as a generation matrix until the order of the final generation matrix is equal to the target code length
  • a coding and rate matching module configured to perform coding and rate matching on the coded bits according to the final generation matrix.
  • the polarization code of different target code lengths under the same mother code does not need to perform reliability calculation to determine the position of the information bit and the fixed bit. This eliminates the need to repeatedly calculate reliability ordering, and therefore can greatly reduce computational complexity.
  • the reliability of the one or more rows to be deleted is obtained by querying a reliability ranking table, where the reliability ranking table indicates different mother code lengths and different positions of the to-be-transmitted vector under different transport block sizes.
  • the vector to be transmitted is a vector having a length equal to the length of the mother code.
  • Polarization codes of different target code lengths can be encoded according to the reliability order of the same mother code length.
  • the reliability order of different target code lengths under the same mother code length can be obtained by looking up the table or by calculating it once. From It can greatly reduce the number of tables and the computational complexity.
  • the bit to be encoded is obtained by placing information bits and fixed bits in the to-be-coded vector according to reliability order, wherein a position corresponding to all the deleted columns of the initial generation matrix is The puncturing position, the final generation matrix places fixed bits relative to the position corresponding to all deleted rows of the original generation matrix.
  • the coding and rate matching module includes an encoding submodule and a rate matching submodule, and the rate matching submodule is configured to delete the fixed bit corresponding to all the deleted rows in the to-be-coded bit. And encoding, according to the final generation matrix, the deleted bits to be encoded to obtain coded and rate matched bits.
  • the coding and rate matching module includes an encoding submodule and a rate matching submodule, and the encoding submodule is configured to be encoded according to a generation matrix determined by the mother code length. The bit is encoded; the rate matching sub-module is configured to perform puncturing on the encoded bit according to the puncturing position to obtain a coded and rate-matched bit.
  • the method provided by the embodiment of the invention can implement coding and rate matching at the same time, which simplifies the calculation complexity and reduces the amount of the table.
  • an embodiment of the present invention provides a coding and rate matching device for a polarization code, including: a processor, a memory, and a bus, wherein the processor and the memory perform data transmission by using the bus connection;
  • the processor is configured to determine one or more rows to be deleted of the generation matrix, wherein the generation matrix is determined by a preset mother code length, and the column of the one or more rows to be deleted includes at least a column a column having a column weight of 1; deleting a row corresponding to the least reliable polarization channel among the one or more rows to be deleted, and deleting a column having a column weight of 1 in the column of the row 1 of the row, Deleting the generator matrix; repeating the above steps after the deleted generator matrix is again used as the generator matrix until the order of the final generator matrix is equal to the target code length; according to the final generator matrix, the coded bits are encoded and Rate matching
  • the memory is configured to store a generator matrix in the processor processing.
  • the polarization code of different target code lengths under the same mother code does not need to perform reliability calculation to determine the position of the information bit and the fixed bit. This eliminates the need to repeatedly calculate reliability ordering, and therefore can greatly reduce computational complexity.
  • the reliability of the one or more rows to be deleted is obtained by querying a reliability ranking table, where the reliability ranking table indicates different mother code lengths and different positions of the to-be-transmitted vector under different transport block sizes.
  • the vector to be transmitted is a vector having a length equal to the length of the mother code.
  • Polarization codes of different target code lengths can be encoded according to the reliability order of the same mother code length.
  • the reliability order of different target code lengths under the same mother code length can be obtained by looking up the table or by calculating it once. This can greatly reduce the number of tables and the computational complexity.
  • the bit to be encoded is obtained by placing information bits and fixed bits in the to-be-coded vector according to reliability order, wherein a position corresponding to all the deleted columns of the initial generation matrix is The puncturing position, the final generation matrix places fixed bits relative to the position corresponding to all deleted rows of the original generation matrix.
  • the encoding and rate matching of the to-be-coded bits according to the final generation matrix includes:
  • the deleted bits to be coded are encoded to obtain coded and rate matched bits.
  • the encoding and rate matching of the to-be-coded bits according to the final generation matrix includes:
  • the coded bits are punctured according to the puncturing position to obtain coded and rate matched bits.
  • the polarization code of different target code lengths under the same mother code does not need to perform reliability calculation to determine the position of the information bit and the fixed bit. So there is no need to repeatedly calculate the reliability ranking, so Can greatly reduce the computational complexity.
  • 1 is a schematic flow chart of a communication system
  • FIG. 2 is a schematic diagram of a frame of a method for encoding and rate matching a polarization code according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a method for encoding and rate matching a polarization code according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of reliability ranking according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a process of deleting a generator matrix by taking G 8 as an example
  • FIG. 6 is a schematic diagram of another method for encoding and rate matching a polarization code according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a polarization code encoding and rate matching process according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a coding and rate matching apparatus for a polarization code according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a coding and rate matching device for a polarization code according to an embodiment of the present invention.
  • FIG. 1 is a schematic flow chart of a communication system. As shown in Figure 1, the information is transmitted through the source code, channel coding code, rate matching and de-rate matching, and modulation and demodulation. Channel coding and rate matching are used to transmit information throughout the communication system. Reliability plays a crucial role.
  • a rate matching scheme with a polarization code is called quasi-uniform puncturing (English: Qausi-Uniform Puncturing; referred to as QUP).
  • QUP quasi-uniform Puncturing
  • the punching method of the scheme is very simple, and only the mother code of the polarization code is punched sequentially from the back to the front or from the back to the front.
  • This scheme provides a relatively simple but better performance of the polarization code rate matching scheme, but it is necessary to recalculate the reliability of each polarization channel according to the puncturing method of the mother code, and use the new reliability order to determine the information bits and The position of the fixed bit.
  • FIG. 2 is a schematic diagram of a frame of a method for encoding and rate matching a polarization code according to an embodiment of the present invention.
  • the polarization code before the encoding, the polarization code first determines the reliability ranking of the polarized channel according to the transport block size (English: Transport Block size; TBs), the mother code length, and the channel information of the actual channel. Specifically, it can be obtained by looking up a table (such as the table shown in FIG. 4).
  • the transport block size indicates the number of information bits, and the mother code can be regarded as a code that is coded without rate matching, and the polarized channel is a channel whose reliability exhibits polarization.
  • the coded bits are subjected to polarization code encoding and rate matching according to the reliability of the polarized channel, the target code length, and the generation matrix determined by the mother code length. Specifically, according to the method provided by the embodiment of the present invention, all the columns to be deleted of the generated matrix are determined according to the reliability of the polarized channel; the fixed bits are placed in the positions of the to-be-coded vectors corresponding to 1 of the columns to be deleted, and the remaining bits are left. The location places information bits and fixed bits from high to low according to reliability, and obtains bits to be encoded.
  • the vector to be encoded is a vector of length N. The information bits and fixed bits are placed in the vector to be encoded to obtain the bits to be encoded.
  • FIG. 3 is a schematic diagram of a method for encoding and rate matching a polarization code according to an embodiment of the present invention. As shown in Figure 3:
  • Step 301 Determine one or more rows to be deleted of the generation matrix, where the generation matrix is determined by a preset mother code length, and the column of the one or more rows to be deleted includes at least one column weight 1 column;
  • the generation matrix Among them, N can be considered as the preset mother code length.
  • the method provided by the embodiment of the present invention may also be applied regardless of the impact of the B N .
  • the generation matrix is obtained by taking the preset mother code length of 8 as an example:
  • each row corresponds to each position of the vector to be encoded.
  • the first row of the generation matrix corresponds to the first position of the vector to be encoded
  • the second row of the generation matrix corresponds to the second position of the vector to be encoded
  • the last row of the matrix and the vector to be encoded are generated. The last position corresponds.
  • At least one column of the column in which the element 1 is located has a column weight of 1.
  • all the columns in the generation matrix whose column weight is 1 are determined, and then the rows of the columns 1 of the columns whose weights are 1 are determined, and the rows are the rows to be deleted of the generation matrix.
  • the column whose column weight is 1 has only the eighth column (that is, the last column), and the eighth row (that is, the last row) of the behavior to be deleted.
  • Step 302 Delete a row corresponding to the least-polarized polarized channel among the one or more to-be-deleted rows, and delete a column with a column weight of 1 in the column where the row 1 is located, and obtain a deleted generation matrix;
  • FIG. 4 is a schematic diagram of reliability ranking according to an embodiment of the present invention.
  • the I TBS is an index of a transport block size, and each index value corresponds to one transport block size, and N is a mother code length.
  • the value in the column corresponding to the code length of each mother code in FIG. 4 indicates the number of information bits in the mother code of the mother code length, and the specific value may be different from that shown in FIG. 4, and may be based on actual conditions or standards. The regulations are determined.
  • the number of information bits in the mother code is 56, and the reliability ranking is as shown in the lower part of Fig. 4.
  • the numerical value in the box indicates each position of the vector to be encoded having a length of 128, and the reliability of these positions is sequentially increased from left to right. That is to say, the reliability of the first position of the vector to be coded is the lowest, the reliability of the third position is increased, and so on, and the reliability of the first one hundred and twenty-seventh position is the highest.
  • the numerical values in these blocks are only schematic, and the specific values may be different from those shown in FIG. 4, and may be determined according to actual conditions or standard regulations.
  • Deleting the row corresponding to the least reliable polarized channel among the one or more to-be-deleted rows, and deleting one of the columns in which the row 1 is located has a column weight of 1.
  • G 8 the last column of the last row of G 8 is deleted, and the deleted G 8 is obtained .
  • Step 303 Repeat the above steps by re-creating the generated generator matrix as a generator matrix until the order of the final generator matrix is equal to the target code length;
  • FIG. 5 is a schematic diagram of an example procedure to remove the generator matrix G 8 in.
  • (1) of FIG. 5 when step 301 and step 302 are performed for the first time, since there is only one row to be deleted that satisfies the condition, and its reliability is F 1 , the last row and the last column are deleted.
  • (2) of FIG. 5 for the deleted G 8 , when step 301 and step 302 are performed for the second time, three rows to be deleted satisfying the condition can be obtained.
  • the fourth row corresponds to the lowest reliability.
  • the first row of 1 exists in the first, third, fifth, and seventh columns, and the fourth column in which the column weight is 1 is satisfied. Therefore, as shown in (3) of FIG. 5, the fourth row and the seventh column are deleted.
  • the repetition process described in step 303 may also be terminated when the number of columns in which the generation matrix is deleted in the entire process is equal to the number of holes required for rate matching.
  • the target code length is 6 or the number of punched holes is 2
  • the deleted G 8 shown in (3) of FIG. 5 is the finally obtained deleted generation matrix.
  • Step 304 Encode and rate match the coded bits according to the final generation matrix.
  • the generated matrix obtained in step 303 is compared with the initial generation matrix, and the positions of the to-be-coded vectors corresponding to all the deleted rows are placed in fixed bits, wherein the fixed bits are positions to be punctured when performing rate matching.
  • the remaining positions place information bits and fixed bits from high to low in accordance with reliability, thereby obtaining bits to be encoded, in which information bits are placed at a position where reliability is high.
  • the fixed bits corresponding to all the deleted lines in the bits to be encoded are deleted; and the deleted bits to be encoded are encoded according to the final generation matrix.
  • the coded and rate matched bits can be obtained.
  • the bit to be encoded is first encoded according to a generation matrix determined by the code length of the mother code.
  • the coded bits to be coded are rate matched according to the determined location of the puncturing.
  • FIG. 6 is a schematic diagram of another method for encoding and rate matching a polarization code according to an embodiment of the present invention. As shown in Figure 6:
  • Step 601 Determine one or more columns to be deleted of the generation matrix, wherein the generation matrix is determined by a preset mother code length, and the column weight of the one or more columns to be deleted is 1;
  • all columns with a column weight of 1 can be obtained by searching the generation matrix, and these columns are the columns to be deleted.
  • Step 602 Delete the row corresponding to the least-polarized channel with the lowest reliability of the row of the one or more columns to be deleted, and delete the column with the column weight of 1 in all the columns of the row in the row, and obtain the column after the deletion.
  • the rows of the generated matrix in steps 301 and 302 correspond to the position of the vector to be encoded and the polarized channel. Therefore, it is possible to determine a row corresponding to the least reliable polarization channel in which one of the one or more columns to be deleted is located. Delete the column and the row where the column 1 is located, and get the generated matrix after deletion.
  • Step 603 Repeat the above steps by re-creating the generated generator matrix as a generator matrix until the order of the final generator matrix is equal to the target code length;
  • Step 604 Encode and rate match the coded bits according to the final generation matrix.
  • Steps 603 and 604 are the same as those in the embodiment shown in FIG. 3, and details are not described herein again.
  • some technical features involved in steps 601 and 602, such as a generation matrix, a mother code length, a polarization channel, and a reliability, are the same as or similar to the embodiment shown in FIG. 3, and are not described herein.
  • the position in the corresponding vector to be encoded is determined as part or all of the fixed bits (and the puncturing position).
  • the intermediate variables can be introduced to record the columns (and rows) that need to be deleted, or some or all of the fixed bits (and the punched positions) corresponding to the columns (and rows) can be directly recorded. That is to say, in actual implementation, it is only necessary to determine the position of some or all of the fixed bits in the bits to be encoded and the position of the puncturing.
  • the coded bits are encoded and rate matched according to the determined information bits, fixed bits, puncturing positions, and generation matrix.
  • the bit to be encoded can be considered to be obtained by placing information bits and fixed bits by the vector to be encoded.
  • FIG. 7 is a schematic diagram of a polarization code encoding and rate matching process according to an embodiment of the present invention. As shown in Figure 7:
  • Step 701 Generate a construction matrix H whose initial value is the same as the generation matrix G, wherein the generation matrix G is uniquely determined by the mother code length N;
  • Step 702 Find a column with a column weight of 1 in the column of H, and record the row where 1 of the columns is located as a matrix r;
  • Step 703 Compare the reliability of the polarized channel corresponding to the row in r, determine the row and column of the corresponding one of the least reliable polarization channels, and record their positions in G as r and c, respectively.
  • the positions in H are denoted as r' and c';
  • Step 704 Add r and c to the indication vector R and the vector C, respectively, where the initial values of R and C are null;
  • Step 705 Determine the size of the vector R or C. If the size is equal to N-M, go to step 707. If the size is smaller than N-M, go to step 706, where M is the target code length.
  • Step 706 Delete the rows and columns of positions h' and c' in the matrix H to obtain a new construction matrix and set it to H, and then continue from step 702;
  • Step 707 placing fixed bits in the R position of the vector to be encoded, and remaining positions are placed into information bits and fixed bits according to their reliability from high to low, to obtain a vector U to be encoded;
  • Step 708 Delete the column of position C in the generation matrix G, and obtain a new generation matrix G' to encode the coded bit u to obtain the coded bit uG'.
  • N-M in step 705 can be considered as the number of punches.
  • the embodiment of the present invention provides an implementation manner, which includes: from the perspective of determining a puncturing position (or a fixed bit to be punctured), including:
  • the coded bits are coded and rate matched according to the puncturing position and the generator matrix.
  • polarization code encoding and rate matching method including:
  • the target matrix is obtained by deleting the generation matrix
  • the part or all of the fixed bits of the to-be-coded bits are in one-to-one correspondence with the row of the deleted column, wherein the deleted column is all deleted columns of the generation matrix relative to the target matrix.
  • the one-to-one correspondence between the fixed bit in the bit to be encoded and the row in the deleted column indicates that the bits to be encoded corresponding to all the rows in the deleted column are fixed bits.
  • the remaining bits in the bits to be encoded are placed with information bits and fixed bits from high to low in accordance with reliability.
  • information bits are placed in locations where reliability is high.
  • Parameter Type Typical value Coded modulation scheme 0-28 Number of resource blocks 1-110 Cell-specific reference channel port mode 1,2,4 Demodulation reference channel port mode 0,4,8 Number of physical downlink control channel symbols 1,2,3,4*
  • the polarization code of different target code lengths under the same mother code does not need to perform reliability calculation to determine the position of the information bit and the fixed bit. That is to say, polarization codes of different target code lengths can be encoded according to the reliability order of the same mother code length. In this case, the reliability order of different target code lengths under the same mother code length can be obtained by looking up the table or by calculating it once. In other words, the punching method does not affect the reliability ranking. This eliminates the need to repeatedly calculate reliability ordering, and therefore can greatly reduce computational complexity.
  • FIG. 8 is a schematic diagram of a coding and rate matching apparatus for a polarization code according to an embodiment of the present invention. As shown in FIG. 8, the apparatus includes:
  • a determining module 801 configured to determine one or more rows to be deleted of the generating matrix, wherein the generating matrix is determined by a preset mother code length, and the column of the one or more rows to be deleted is included in the column At least one column with a column weight of 1;
  • the deleting module 802 is configured to delete a row corresponding to the least reliable polarized channel among the one or more to-be-deleted rows, and delete a column with a column weight of 1 in the column where the row 1 is located, and obtain the deleted column.
  • the control module 803 is configured to send the deleted generation matrix as a generation matrix to the determining module until the order of the final generation matrix is equal to the target code length;
  • the coding and rate matching module 804 is configured to perform coding and rate matching on the coded bits according to the final generation matrix.
  • the coding and rate matching apparatus of the polarization code in the above embodiment wherein some technical features are involved, such as a polarized channel, a fixed bit, a column weight, a reliability, a puncturing position, etc., and other further descriptions (such as The reliability ranking table, etc., is similar or corresponding to some of the technical features involved in the foregoing method embodiments, and the repeated description is not repeated here.
  • FIG. 9 is a schematic diagram of a coding and rate matching device for a polarization code according to an embodiment of the present invention.
  • the bus 903 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Etc., here is not limited.
  • the bus 903 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 9, but it does not mean that there is only one bus or one type of bus. among them:
  • the memory 902 is used to store data or executable program code, where the program code includes computer operating instructions, which may specifically be: an operating system, an application, or the like.
  • Memory 902 may include high speed RAM memory and may also include non-volatile memory, such as at least one disk memory.
  • the processor 901 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more configured to implement the embodiments of the present invention. integrated circuit.
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • the processor 901 is configured to implement the encoding and rate matching method of the polarization code in the foregoing embodiment by executing the program code in the memory 902, and some technical features involved, such as a polarized channel, a fixed bit, a column weight, and a reliable Degrees, puncturing positions, and the like, and other further descriptions (such as the reliability ranking table, etc.) are similar or corresponding to some of the technical features involved in the above method embodiments, and will not be repeatedly described herein.
  • the present invention also provides a non-transitory computer readable storage medium, which enables a network device to perform encoding and rate matching of any of the above-described polarization codes when the instructions in the storage medium are executed by a processor of the network device
  • Method including some technical features, such as: polarized channel, fixed bit, column weight, reliability, and puncturing position, and other further descriptions (such as reliability ranking table, etc.), and in the above method embodiments Some of the technical features involved are similar or corresponding, and will not be repeated here.
  • Computer readable The medium includes computer storage media and communication media including any medium that facilitates transfer of the computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure.
  • any connection may suitably be a computer readable medium.
  • the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
  • the coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixing of the associated media.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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Abstract

本发明实施例提供了一种一种极化码的编码和速率匹配方法，包括：确定生成矩阵的一个或多个待删除行，其中，所述生成矩阵由预设的母码码长确定，所述一个或多个待删除行的1所在的列中包含至少一个列重为1的列；删除所述一个或多个待删除行中可靠度最低的极化信道对应的行，以及删除该行的1所在的列中的一个列重为1的列，得到删除后的生成矩阵；将所述删除后的生成矩阵重新作为生成矩阵重复上述步骤，直到最终的生成矩阵的阶数等于目标码长为止；根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配。从而无需重复计算可靠度排序，因此也可以大大降低计算复杂度。

Description

一种极化码的编码和速率匹配方法、装置及设备
本申请要求于2016年5月12日提交中国专利局、申请号为201610319645.0、发明名称为“一种极化码的编码和速率匹配方法、装置及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及无线通信技术，尤其涉及一种极化码的编码和速率匹配方法、装置及设备。
背景技术
随着无线通信的发展，物联网(英文：Internet of Things；简称：IoT)通信系统呈现出一些新的特点，例如：高可靠度、低复杂度以及广覆盖等。
而现有的主流编码，例如：Turbo码和低密度奇偶校验(英文：Low Density Parity Check；简称：LDPC)码不能够很好地满足IoT通信系统的要求。在性能方面，虽然Turbo码和LDPC码随着码长的变长能够逼近香农极限，但Turbo码和LDPC码由于自身编译码的特点，在有限码长下很难达到理想的性能。在实现方面，Turbo码和LDPC码在编译码实现过程中具有较高的复杂度。因此，IoT通信系统中，急需一种新的编码技术来解决现有技术在短包，可靠度以及复杂度上存在的问题。
最近，极化码(英文：Polar Code)是第一种、也是已知的唯一一种能够被严格证明“达到”香农极限的信道编码方法。极化码的编译码的简单描述如下：
极化码是一种线性码。设其生成矩阵(或编码矩阵)为GN,其编码过程为
Figure PCTCN2017078313-appb-000001
其中
Figure PCTCN2017078313-appb-000002
是长度为N的待编码比特，N大于1的正整数。GN是一个N×N的矩阵，且
Figure PCTCN2017078313-appb-000003
其中，
Figure PCTCN2017078313-appb-000004
BN是一个N×N的转置矩阵，例如比特翻转(英文：Bit Reversal)矩阵；
Figure PCTCN2017078313-appb-000005
是log2N个F2的克罗内克(英文：Kronecker)乘积；以上涉及的加法、乘法操作均为二进制伽罗华域(英文：Galois Field)上的加法、乘法操作。
极化码最基本的译码方法是连续消除(英文：Successive Cancellation；简称：SC)译码，后续提出的SC-List译码算法通过横向路径扩展以及循环冗余校验(英文：Cyclic Redundancy Check；简称：CRC)选择的方法提高了短码的译码性能。
从极化码的编码原理可以看出极化码的一个特点是其码长为2的整数次幂，而实际通信中要求码长可以根据实际要求(如调制编码方案的要求)灵活配置。因此，需要通过速率匹配技术实现码长的灵活可变。
极化码的一类速率匹配方案是将极化码与另外一种线性分组码进行级联，并将极化码作为内码实现任意码长的编码。该类方案在编译码的时候需要两种不同的编码器和译码器增加了实现的复杂度和成本。
极化码的另一类速率匹配方案是通过穷举或者贪婪算法找到最优或者次优的打孔方式，以减少速率匹配对极化码性能的影响。穷举法需要遍历每一种可能的打孔方式，计算其对应的信息比特的可靠度，根据可靠度的高低确定打孔比特。这类方案最大的缺点是复杂度太大。如果用贪婪算法，可以只选出对信息比特可靠度影响最小的打孔方式。用贪婪算法虽然可以减少一定的计算量但其复杂度仍然较大。
发明内容
有鉴于此，本发明实施例提供了一种极化码的编码和速率匹配方法、装置及设备，以实现联合的编码和速率匹配，从而可以大大降低计算复杂度。
第一方面，本发明实施例提供了一种极化码的编码和速率匹配方法，包括：
确定生成矩阵的一个或多个待删除行，其中，所述生成矩阵由预设的母码码长确定，所述一个或多个待删除行的1所在的列中包含至少一个列重为1的列；
删除所述一个或多个待删除行中可靠度最低的极化信道对应的行，以及删除该行的1所在的列中的一个列重为1的列，得到删除后的生成矩阵；
将所述删除后的生成矩阵重新作为生成矩阵重复上述步骤，直到最终的生成矩阵的阶数等于目标码长为止；
根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配。
在本发明实施例提供的极化码的编码和速率匹配方法中，同一母码下不同目标码长的极化码无需再进行可靠度计算来确定信息比特与固定比特的位置。从而无需重复计算可靠度排序，因此也可以大大降低计算复杂度。
具体地，所述一个或多个待删除行的可靠度通过查询可靠度排序表获得，其中，所述可靠度排序表指示不同母码码长和不同传输块大小下的待传输向量不同位置的可靠度顺序，所述待传输向量为长度等于所述母码码长的向量。
不同目标码长的极化码可以根据同一个母码码长的可靠度排序进行编码。在这种情况下，同一个母码码长下的不同目标码长的可靠度排序可以查表获得或只需计算一次即可获得。从而可以大大减少存表数量以及计算复杂度。
具体地，所述待编码比特由根据可靠度排序在所述待编码向量中放置信息比特和固定比特得到，其中，所述最终的生成矩阵相对于初始的生成矩阵的所有删除列对应的位置为打孔位置，所述最终的生成矩阵相对于初始的生成矩阵的所有删除行对应的位置所述打孔位置放置固定比特。
在一种可能的实现方式中，所述根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配包括：将待编码比特中所述所有删除行对应的固定比特删除；根据由所述母码码长确定的生成矩阵根据所述最终的生成矩阵，对打孔删除后的待编码比特进行编码，得到编码和速率匹配后的比特。
在另一种可能的实现方式中，所述根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配包括：根据由所述母码码长确定的生成矩阵，对待编码比特进行编码；根据所述打孔位置，对编码后的比特进行打孔，得到编码和速率匹配后的比特。
本发明实施例提供的方法可以同时实现编码和速率匹配，简化了计算复杂度，同时也减小了存表量。
第二方面，本发明实施例提供了一种极化码的编码和速率匹配装置，包括：
确定模块，用于确定生成矩阵的一个或多个待删除行，其中，所述生成矩阵由预设的母码码长确定，所述一个或多个待删除行的1所在的列中包含至少一个列重为1的列；
删除模块，用于删除所述一个或多个待删除行中可靠度最低的极化信道对应的行，以及删除该行的1所在的列中的一个列重为1的列，得到删除后的生成矩阵；
控制模块，用于将所述删除后的生成矩阵重新作为生成矩阵送入所述确定模块，直到最终的生成矩阵的阶数等于目标码长为止；
编码和速率匹配模块，用于根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配。
在本发明实施例提供的极化码的编码和速率匹配方法中，同一母码下不同目标码长的极化码无需再进行可靠度计算来确定信息比特与固定比特的位置。从而无需重复计算可靠度排序，因此也可以大大降低计算复杂度。
具体地，所述一个或多个待删除行的可靠度通过查询可靠度排序表获得，其中，所述可靠度排序表指示不同母码码长和不同传输块大小下的待传输向量不同位置的可靠度顺序，所述待传输向量为长度等于所述母码码长的向量。
不同目标码长的极化码可以根据同一个母码码长的可靠度排序进行编码。在这种情况下，同一个母码码长下的不同目标码长的可靠度排序可以查表获得或只需计算一次即可获得。从 而可以大大减少存表数量以及计算复杂度。
具体地，所述待编码比特由根据可靠度排序在所述待编码向量中放置信息比特和固定比特得到，其中，所述最终的生成矩阵相对于初始的生成矩阵的所有删除列对应的位置为打孔位置，所述最终的生成矩阵相对于初始的生成矩阵的所有删除行对应的位置放置固定比特。
在一种可能的实现方式中，所述编码和速率匹配模块包括编码子模块和速率匹配子模块；所述速率匹配子模块，用于将待编码比特中所述所有删除行对应的固定比特删除；根据所述最终的生成矩阵，对删除后的待编码比特进行编码，得到编码和速率匹配后的比特。
在另一种可能的实现方式中，所述编码和速率匹配模块包括编码子模块和速率匹配子模块；所述编码子模块，用于根据由所述母码码长确定的生成矩阵，对待编码比特进行编码；所述速率匹配子模块，用于根据所述打孔位置，对编码后的比特进行打孔，得到编码和速率匹配后的比特。
本发明实施例提供的方法可以同时实现编码和速率匹配，简化了计算复杂度，同时也减小了存表量。
第三方面，本发明实施例提供了一种极化码的编码和速率匹配设备，包括：处理器、存储器及总线，其中所述处理器及存储器通过所述总线连接进行数据传输；
所述处理器用于确定生成矩阵的一个或多个待删除行，其中，所述生成矩阵由预设的母码码长确定，所述一个或多个待删除行的1所在的列中包含至少一个列重为1的列；删除所述一个或多个待删除行中可靠度最低的极化信道对应的行，以及删除该行的1所在的列中的一个列重为1的列，得到删除后的生成矩阵；将所述删除后的生成矩阵重新作为生成矩阵重复上述步骤，直到最终的生成矩阵的阶数等于目标码长为止；根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配；
所述存储器用于存储所述处理器处理过程中的生成矩阵。
在本发明实施例提供的极化码的编码和速率匹配方法中，同一母码下不同目标码长的极化码无需再进行可靠度计算来确定信息比特与固定比特的位置。从而无需重复计算可靠度排序，因此也可以大大降低计算复杂度。
具体地，所述一个或多个待删除行的可靠度通过查询可靠度排序表获得，其中，所述可靠度排序表指示不同母码码长和不同传输块大小下的待传输向量不同位置的可靠度顺序，所述待传输向量为长度等于所述母码码长的向量。
不同目标码长的极化码可以根据同一个母码码长的可靠度排序进行编码。在这种情况下，同一个母码码长下的不同目标码长的可靠度排序可以查表获得或只需计算一次即可获得。从而可以大大减少存表数量以及计算复杂度。
具体地，所述待编码比特由根据可靠度排序在所述待编码向量中放置信息比特和固定比特得到，其中，所述最终的生成矩阵相对于初始的生成矩阵的所有删除列对应的位置为打孔位置，所述最终的生成矩阵相对于初始的生成矩阵的所有删除行对应的位置放置固定比特。
在一种可能的实现方式中，所述根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配包括：
将待编码比特中所述所有删除行对应的固定比特删除；
根据所述最终的生成矩阵，对删除后的待编码比特进行编码，得到编码和速率匹配后的比特。
在一种可能的实现方式中，所述根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配包括：
根据由所述母码码长确定的生成矩阵，对待编码比特进行编码；
根据所述打孔位置，对编码后的比特进行打孔，得到编码和速率匹配后的比特。
本发明实施例通过查找生成矩阵中列重为1的列以及该1所在的行，根据可靠度排序，确定部分或全部固定比特以及打孔位置，对待编码比特进行极化码编码和速率匹配。在本发明实施例提供的极化码的编码和速率匹配方法中，同一母码下不同目标码长的极化码无需再进行可靠度计算来确定信息比特与固定比特的位置。从而无需重复计算可靠度排序，因此也 可以大大降低计算复杂度。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种通信系统的流程示意图；
图2为本发明实施例提供的一种极化码的编码和速率匹配方法的框架示意图；
图3为本发明实施例提供的一种极化码的编码和速率匹配方法示意图；
图4为本发明实施例提供的一种可靠度排序示意表；
图5为以G8为例删除生成矩阵的过程示意图；
图6为本发明实施例提供的另一种极化码的编码和速率匹配方法示意图；
图7为本发明实施例提供的一种极化码编码和速率匹配流程示意图；
图8为本发明实施例提供的一种极化码的编码和速率匹配装置示意图；
图9为本发明实施例提供的一种极化码的编码和速率匹配设备示意图。
具体实施例
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。图1为一种通信系统的流程示意图。如图1所示，信息在进行传输的过程中，要经过信源编译码、信道编译码、速率匹配与解速率匹配、调制解调，其中信道编码及速率匹配在整个通信系统中对信息传输的可靠度起到至关重要的作用。有一种极化码的速率匹配方案称为准均匀打孔(英文：Qausi-Uniform Puncturing；简称：QUP)。该方案的打孔方式非常简单，只需对极化码的母码从前往后或者从后往前顺序进行打孔。该方案提供了一种相对简单但性能较好的极化码速率匹配方案，但是需要根据母码的打孔方式重新计算每个极化信道的可靠度，利用新的可靠度排序确定信息比特和固定比特的位置。
图2为本发明实施例提供的一种极化码的编码和速率匹配方法的框架示意图。如图2所示，极化码在编码前首先根据传输块大小(英文：Transport Block size；简称：TBs)、母码码长和实际信道的信道信息，确定极化信道的可靠度排序。具体地，可以通过查表得到(如图4所示的表)。其中，传输块大小指示信息比特的个数，母码可以认为是进行编码而未进行速率匹配的码，极化信道是可靠度呈现极化现象的信道。根据极化信道的可靠度、目标码长以及由母码码长确定的生成矩阵，对待编码比特进行极化码编码和速率匹配。具体地，利用本发明实施例提供的方法，根据极化信道的可靠度，确定生成矩阵的所有待删除列；待编码向量中与这些待删除列中的1对应的位置放置固定比特，剩下的位置按照可靠度从高到低放置信息比特和固定比特，得到待编码比特。其中，待编码向量是长度为N的向量。在待编码向量中放置信息比特和固定比特后得到待编码比特。
图3为本发明实施例提供的一种极化码的编码和速率匹配方法示意图。如图3所示：
步骤301：确定生成矩阵的一个或多个待删除行，其中，该生成矩阵由预设的母码码长确定，该一个或多个待删除行的1所在的列中包含至少一个列重为1的列；
具体地，由背景技术中描述可知，生成矩阵
Figure PCTCN2017078313-appb-000006
其中，N可以认为是预设的母码码长。在实际实现中，也可以不考虑BN的影响，同样可以应用本发明实施例提供的方法。为了简化说明，以预设的母码码长是8为例，可以得到生成矩阵：
Figure PCTCN2017078313-appb-000007
对于生成矩阵，其每一行与待编码向量的每一个位置对应。例如，生成矩阵的第一行与待编码向量的第一个位置对应，生成矩阵的第二行与待编码向量的第二个位置对应，以此类推，生成矩阵的最后一行与待编码向量的最后一个位置对应。
对于生成矩阵的待删除行，其元素1所在的列中至少有一列的列重为1。在另一种可能的实现方式中，确定生成矩阵中所有列重为1的列，然后确定这些列重为1的列的1所在的行，这些行即为该生成矩阵的待删除行。
以G8为例，其列重为1的列只有第八列(也就是最后一列)，则的待删除行为第八行(也就是最后一行)。
步骤302：删除该一个或多个待删除行中可靠度最低的极化信道对应的行，以及删除该行的1所在的列中的一个列重为1的列，得到删除后的生成矩阵；
根据步骤301确定出来的一个或多个待删除行以及该一个或多个待删除行与极化信道的对应关系，确定该一个或多个待删除行中可靠度最低的极化信道对应的行。其中，该一个或多个待删除行与待编码向量的一个或多个位置对应，而待编码向量的一个或多个位置又对应着极化信道的可靠度。在一种可能的实现方式中，可以通过查表的方式确定该一个或多个待删除行中可靠度最低的极化信道对应的行。举例来说，图4为本发明实施例提供的一种可靠度排序示意表。如图4所示，ITBS为传输块大小的索引，其每一个索引值对应一个传输块大小，N为母码码长。图4中每个母码码长对应的列中的数值表示该母码码长的母码中的信息比特的个数，其具体数值可能与图4中所示不同，可根据实际情况或标准规定确定。对于一个确定的N以及ITBS，当信道参数固定时，有一个确定的可靠度排序。该可靠度表示长度为N的待编码向量对应位置的可靠度。以图4中N＝128，ITBS＝6为例，在该中情况下，母码中信息比特的个数为56，其可靠度排序如图4下方所示。其中，方框内的数值表示长度为128的待编码向量的每一个位置，这些位置的可靠度从左到右依次增加。也就是说，待编码向量的第一个位置的可靠度最低，第三个位置的可靠度增加一些，以此类推，第一百二十七个位置的可靠度最高。当然，这些方框内的数值只是示意，其具体数值可能与图4中所示不同，可根据实际情况或标准规定确定。
删除该一个或多个待删除行中可靠度最低的极化信道对应的行，以及删除该行的1所在的列中的一个列重为1的列。以G8为例，则将G8的最后一行最后一列删除，得到删除后的G8。
步骤303：将删除后的生成矩阵重新作为生成矩阵重复上述步骤，直到最终的生成矩阵的阶数等于目标码长为止；
具体地，将步骤302得到的删除后的生成矩阵作为一个新的初始的生成矩阵，重复执行步骤301和步骤302，直到最终得到的生成矩阵的阶数等于目标码长为止。举例来说，图5为以G8为例删除生成矩阵的过程示意图。如图5中的(1)所示，在第一次执行步骤301和步骤302时，由于只有一个满足条件的待删除行，其可靠度为F1，则删除掉最后一行和最后一列。如图5中的(2)所示，针对删除后的G8，第二次执行步骤301和步骤302时，可以得到三个满足条件的待删除行。比较这三个待删除行的可靠度大小(具体可查找与图4类似的图表)，可知第四行对应的可靠度最低。第四行的1存在于第一、三、五、七列，其中这四 列中满足列重为1的只有第七列。因此，如图5中的(3)所示，删除第四行以及第七列。
在另一种实现方式中，当整个过程中生成矩阵被删除的列数等于速率匹配所需要打孔的个数时，也可以终止步骤303所述的重复过程。以G8为例，若目标码长为6或者打孔个数为2，则图5中(3)所示的删除后G8的就是最终得到的删除后的生成矩阵。
步骤304：根据该最终的生成矩阵，对待编码比特进行编码和速率匹配。
具体地，步骤303最终得到的生成矩阵与初始的生成矩阵相比，所有删除的行对应的待编码向量的位置放置固定比特，其中，这些固定比特是进行速率匹配时所要打孔的位置。剩下的位置按照可靠度从高到低放置信息比特和固定比特，从而得到待编码比特，其中可靠度高的位置放置信息比特。
在一种可能的实现方式中，将待编码比特中所有删除行对应的固定比特删除；根据最终的生成矩阵，对删除后的待编码比特进行编码。从而可以得到编码和速率匹配后的比特。
在另一种可能的实现方式中，根据由母码码长确定的生成矩阵，对待编码比特先进行编码。根据确定好的打孔的位置，对编码后的待编码比特进行速率匹配。
图6为本发明实施例提供的另一种极化码的编码和速率匹配方法示意图。如图6所示：
步骤601：确定生成矩阵的一个或多个待删除列，其中，该生成矩阵由预设的母码码长确定，该一个或多个待删除列的列重为1；
具体地，可以通过查找生成矩阵得到所有列重为1的列，这些列即为待删除列。
步骤602：删除该一个或多个待删除列的1所在的所有行可靠度最低的极化信道对应的行，以及删除该行中1所在的所有列中列重为1的列，得到删除后的生成矩阵；
在步骤301及302中生成矩阵的行与待编码向量的位置和极化信道对应。因此，可以确定该一个或多个待删除列中1所在的可靠度最低的极化信道对应的行。删除该列以及该列1所在的行，得到删除后的生成矩阵。
步骤603：将删除后的生成矩阵重新作为生成矩阵重复上述步骤，直到最终的生成矩阵的阶数等于目标码长为止；
步骤604：根据该最终的生成矩阵，对待编码比特进行编码和速率匹配。
步骤603及604与图3所示的实施例中的实现方式相同，在此不再赘述。另外，步骤601及602中涉及到的一些技术特征，例如：生成矩阵、母码码长、极化信道及可靠度等，与图3所示的实施例相同或类似，在此亦不赘述。
从图3及图6所示的实施例可以看出，不一定要对生成矩阵进行实质意义上的删除，可以通过记录对生成矩阵需要删除的列(以及行)，将这些列(以及行)对应的待编码向量中的位置确定为部分或全部固定比特(以及打孔位置)。具体可以通过引入中间变量来记录需要删除的列(以及行)，或直接记录这些列(以及行)对应的部分或全部固定比特(以及打孔位置)。也就是说，在实际实现时，只需确定待编码比特中部分或全部固定比特的位置以及打孔的位置即可。根据确定好的信息比特、固定比特、打孔位置以及生成矩阵，对待编码比特进行编码和速率匹配。其中，待编码比特可以认为由待编码向量放置信息比特和固定比特后得到。
图7为本发明实施例提供的一种极化码编码和速率匹配流程示意图。如图7所示：
步骤701：生成构造矩阵H，其初始值为与生成矩阵G相同，其中生成矩阵G由母码码长N唯一决定；
步骤702：找出H的列中列重为1的列，将这些列中1所在的行记为矩阵r；
步骤703：比较r中的行对应的极化信道的可靠度，确定可靠度最低的极化信道对应的1所在的行和列，将其在G中的位置分别记为r和c，将其在H中的位置记为r’和c’；
步骤704：将r和c分别添加至指示向量R和向量C中，其中，R和C的初始值为空；
步骤705：判断向量R或者C的大小，若其大小等于N-M，则执行步骤707，若其大小小于N-M，执行步骤706，其中，M为目标码长；
步骤706：删除矩阵H中位置为r’和c’的行和列得到新的构造矩阵并将其设为H，此后从步骤702继续执行；
步骤707：在待编码向量的R位置放置固定比特，剩下的位置按照其可靠度从高到低放入信息比特和固定比特，得到待编码向量U；
步骤708：将生成矩阵G中位置为C的列删除，得到新的生成矩阵G’对待编码比特u进行编码得到编码比特uG’。
因为步骤708中将生成矩阵G中位置为C的列删除，所以得到的编码比特uG’也是速率匹配后比特。另外，步骤705中的N-M可以认为是打孔个数。
进一步地，从确定打孔位置(或待打孔的固定比特)的角度出发，本发明实施例还提供了一种实现方式，包括：
将生成矩阵的可靠度最低的极化信道对应的行以及生成矩阵的列重最低的列记录在集合中，删除该行及该列，得到删除后的生成矩阵；
重复上一步骤，直到生成矩阵的大小等于目标码长为止；
根据该集合确定待编码比特中全部或部分固定比特以及打孔位置；
根据打孔位置和生成矩阵，对待编码比特进行编码和速率匹配。
进一步地，本发明实施例还提供的一种极化码编码和速率匹配方法，包括：
根据目标码长，通过删除生成矩阵得到目标矩阵；
根据目标矩阵，对待编码比特进行编码，得到编码和速率匹配后的比特；
其中，所述待编码比特中部分或全部固定比特与删除的列中1所在的行一一对应，其中，所述删除的列为所述生成矩阵相对于所述目标矩阵的所有删除列。
其中，所述待编码比特中部分或全部固定比特与删除的列中1所在的行一一对应表示：所述删除的列中1所在的所有行对应的待编码比特均为固定比特。可选地，待编码比特中剩下的位置按照可靠度从高到低放置信息比特和固定比特。从而其中可靠度高的位置放置信息比特。
在现有技术中，不同的目标码长都需要进行可靠度计算，且需要将各种情况/参数条件下指示信息比特的位置的序列进行存表。尤其是，每一种目标码长都需要对指示信息比特的位置的序列进行存表。而本发明只需存储一个母码码长下的可靠度排序表。因此，本发明实施例提供的方法与现有技术需要根据不同打孔模式/码长进行可靠度计算和排序相比，可以大大减少存表的序列。以LTE为列，表1为现有技术的参数表，相应需要存表的序列数为所有这些参数可能的组合，即29×110×3×3×4种组合。由于实际参数并未列举完全，因此，实际可能的组合个数会更多。表2为本发明实施例提供的方法的参数表，由于LTE的TBs有重复，所以可能的组合个数小于29×110×7种。
表1现有技术的参数表
参数类型 典型值
编码调制方案 0-28
资源块数 1-110
小区专有参考信道端口模式 1,2,4
解调参考信道端口模式 0,4,8
物理下行控制信道符号数 1,2,3,4*
表2本发明实施例提供的方法的参数表
Figure PCTCN2017078313-appb-000008
同时，在本发明实施例提供的极化码的编码和速率匹配方法中，同一母码下不同目标码长的极化码无需再进行可靠度计算来确定信息比特与固定比特的位置。也就是说，不同目标码长的极化码可以根据同一个母码码长的可靠度排序进行编码。在这种情况下，同一个母码码长下的不同目标码长的可靠度排序可以查表获得或只需计算一次即可获得。也就是说，打孔方式不影响可靠度排序。从而无需重复计算可靠度排序，因此也可以大大降低计算复杂度。
本发明实施例进一步给出实现上述方法实施例中各步骤及方法的装置实施例。图8为本发明实施例提供的一种极化码的编码和速率匹配装置示意图，如图8所示，该装置包括：
确定模块801，用于确定生成矩阵的一个或多个待删除行，其中，所述生成矩阵由预设的母码码长确定，所述一个或多个待删除行的1所在的列中包含至少一个列重为1的列；
删除模块802，用于删除所述一个或多个待删除行中可靠度最低的极化信道对应的行，以及删除该行的1所在的列中的一个列重为1的列，得到删除后的生成矩阵；
控制模块803，用于将所述删除后的生成矩阵重新作为生成矩阵送入所述确定模块，直到最终的生成矩阵的阶数等于目标码长为止；
编码和速率匹配模块804，用于根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配。
上述实施例中的极化码的编码和速率匹配装置，其中涉及到的一些技术特征，例如：极化信道、固定比特、列重、可靠度和打孔位置等，以及其他进一步的描述(如可靠度排序表等)，和上述方法实施例中涉及到的一些技术特征类似或对应，在此不再进行重复说明。
图9为本发明实施例提供的一种极化码的编码和速率匹配设备示意图。参照图9所示，包括：处理器901、存储器902及总线903，其中处理器901和存储器902通过总线903连接进行数据传输，存储器902用于存储处理器901处理的数据；
该总线903可以是工业标准体系结构(Industry Standard Architecture，简称为ISA)总线、外部设备互连(Peripheral Component，简称为PCI)总线或扩展工业标准体系结构(Extended Industry Standard Architecture，简称为EISA)总线等，此处并不限定。该总线903可以分为地址总线、数据总线、控制总线等。为便于表示，图9中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。其中：
存储器902用于存储数据或可执行程序代码，其中程序代码包括计算机操作指令，具体可以为：操作系统、应用程序等。存储器902可能包含高速RAM存储器，也可能还包括非易失性存储器(non-volatile memory)，例如至少一个磁盘存储器。
处理器901可能是一个中央处理器(Central Processing Unit，简称为CPU)，或者是特定集成电路(Application Specific Integrated Circuit，简称为ASIC)，或者是被配置成实施本发明实施例的一个或多个集成电路。
处理器901用于通过执行存储器902中的程序代码实现上述实施例中的极化码的编码和速率匹配方法，其中涉及到的一些技术特征，例如：极化信道、固定比特、列重、可靠度和打孔位置等，以及其他进一步的描述(如可靠度排序表等)，和上述方法实施例中涉及到的一些技术特征类似或对应，在此不再进行重复说明。
本发明还提供了一种非临时性计算机可读存储介质，当所述存储介质中的指令由网络设备的处理器执行时，使得网络设备能够执行上述任一种极化码的编码和速率匹配方法，其中涉及到的一些技术特征，例如：极化信道、固定比特、列重、可靠度和打孔位置等，以及其他进一步的描述(如可靠度排序表等)，和上述方法实施例中涉及到的一些技术特征类似或对应，在此不再进行重复说明。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。当使用软件实现时，可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读 介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如，如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的，那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定影中。如本发明所使用的，盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟，其中盘通常磁性的复制数据，而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。
总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

  1. 一种极化码的编码和速率匹配方法，其特征在于，包括：
    确定生成矩阵的一个或多个待删除行，其中，所述生成矩阵由预设的母码码长确定，所述一个或多个待删除行的1所在的列中包含至少一个列重为1的列；
    删除所述一个或多个待删除行中可靠度最低的极化信道对应的行，以及删除该行的1所在的列中的一个列重为1的列，得到删除后的生成矩阵；
    将所述删除后的生成矩阵重新作为生成矩阵重复上述步骤，直到最终的生成矩阵的阶数等于目标码长为止；
    根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配。
  2. 根据权利要求1所述的方法，其特征在于，
    所述一个或多个待删除行的可靠度通过查询可靠度排序表获得，其中，所述可靠度排序表指示不同母码码长和不同传输块大小下的待传输向量不同位置的可靠度顺序，所述待传输向量为长度等于所述母码码长的向量。
  3. 根据权利要求1所述的方法，其特征在于，
    所述待编码比特由根据可靠度排序在所述待编码向量中放置信息比特和固定比特得到，其中，所述最终的生成矩阵相对于初始的生成矩阵的所有删除列对应的位置为打孔位置，所述最终的生成矩阵相对于初始的生成矩阵的所有删除行对应的位置放置固定比特。
  4. 根据权利要求3所述的方法，其特征在于，所述根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配包括：
    将待编码比特中所述所有删除行对应的固定比特删除；
    根据所述最终的生成矩阵，对删除后的待编码比特进行编码，得到编码和速率匹配后的比特。
  5. 根据权利要求3所述的方法，其特征在于，所述根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配包括：
    根据由所述母码码长确定的生成矩阵，对待编码比特进行编码；
    根据所述打孔位置，对编码后的比特进行打孔，得到编码和速率匹配后的比特。
  6. 一种极化码的编码和速率匹配装置，其特征在于，包括：
    确定模块，用于确定生成矩阵的一个或多个待删除行，其中，所述生成矩阵由预设的母码码长确定，所述一个或多个待删除行的1所在的列中包含至少一个列重为1的列；
    删除模块，用于删除所述一个或多个待删除行中可靠度最低的极化信道对应的行，以及删除该行的1所在的列中的一个列重为1的列，得到删除后的生成矩阵；
    控制模块，用于将所述删除后的生成矩阵重新作为生成矩阵送入所述确定模块，直到最终的生成矩阵的阶数等于目标码长为止；
    编码和速率匹配模块，用于根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配。
  7. 根据权利要求6所述的装置，其特征在于，
    所述一个或多个待删除行的可靠度通过查询可靠度排序表获得，其中，所述可靠度排序表指示不同母码码长和不同传输块大小下的待传输向量不同位置的可靠度顺序，所述待传输向量为长度等于所述母码码长的向量。
  8. 根据权利要求6所述的装置，其特征在于，
    所述待编码比特由根据可靠度排序在所述待编码向量中放置信息比特和固定比特得到，其中，所述最终的生成矩阵相对于初始的生成矩阵的所有删除列对应的位置为打孔位置，所述最终的生成矩阵相对于初始的生成矩阵的所有删除行对应的位置放置固定比特。
  9. 根据权利要求8所述的装置，其特征在于，
    所述编码和速率匹配模块包括编码子模块和速率匹配子模块；
    所述速率匹配子模块，用于将待编码比特中所述所有删除行对应的固定比特删除；
    根据所述最终的生成矩阵，对删除后的待编码比特进行编码，得到编码和速率匹配后的比特。
  10. 根据权利要求8所述的装置，其特征在于，
    所述编码和速率匹配模块包括编码子模块和速率匹配子模块；
    所述编码子模块，用于根据由所述母码码长确定的生成矩阵，对待编码比特进行编码；
    所述速率匹配子模块，用于根据所述打孔位置，对编码后的比特进行打孔，得到编码和速率匹配后的比特。
  11. 一种极化码的编码和速率匹配设备，其特征在于，包括：处理器、存储器及总线，其中所述处理器及存储器通过所述总线连接进行数据传输；
    所述处理器用于确定生成矩阵的一个或多个待删除行，其中，所述生成矩阵由预设的母码码长确定，所述一个或多个待删除行的1所在的列中包含至少一个列重为1的列；删除所述一个或多个待删除行中可靠度最低的极化信道对应的行，以及删除该行的1所在的列中的一个列重为1的列，得到删除后的生成矩阵；将所述删除后的生成矩阵重新作为生成矩阵重复上述步骤，直到最终的生成矩阵的阶数等于目标码长为止；根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配；
    所述存储器用于存储所述处理器处理过程中的生成矩阵。
  12. 根据权利要求11所述的设备，其特征在于，
    所述一个或多个待删除行的可靠度通过查询可靠度排序表获得，其中，所述可靠度排序表指示不同母码码长和不同传输块大小下的待传输向量不同位置的可靠度顺序，所述待传输向量为长度等于所述母码码长的向量。
  13. 根据权利要求11所述的设备，其特征在于，
    所述待编码比特由根据可靠度排序在所述待编码向量中放置信息比特和固定比特得到，其中，所述最终的生成矩阵相对于初始的生成矩阵的所有删除列对应的位置为打孔位置，所述最终的生成矩阵相对于初始的生成矩阵的所有删除行对应的位置放置固定比特。
  14. 根据权利要求13所述的设备，其特征在于，所述根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配包括：
    将待编码比特中所述所有删除行对应的固定比特删除；
    根据所述最终的生成矩阵，对删除后的待编码比特进行编码，得到编码和速率匹配后的比特。
  15. 根据权利要求13所述的设备，其特征在于，所述根据所述最终的生成矩阵，对待编码比特进行编码和速率匹配包括：
    根据由所述母码码长确定的生成矩阵，对待编码比特进行编码；
    根据所述打孔位置，对编码后的比特进行打孔，得到编码和速率匹配后的比特。
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