WO2017185681A1 - 一种gel码字结构编码和译码的方法、装置及相关设备 - Google Patents

一种gel码字结构编码和译码的方法、装置及相关设备 Download PDF

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WO2017185681A1
WO2017185681A1 PCT/CN2016/102742 CN2016102742W WO2017185681A1 WO 2017185681 A1 WO2017185681 A1 WO 2017185681A1 CN 2016102742 W CN2016102742 W CN 2016102742W WO 2017185681 A1 WO2017185681 A1 WO 2017185681A1
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code
layer
check
bit
gel
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PCT/CN2016/102742
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English (en)
French (fr)
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马耶夫斯基阿列克谢
格里岑科弗拉基米尔
肖世尧
陈红
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华为技术有限公司
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Priority to EP16900189.8A priority Critical patent/EP3439186A4/en
Publication of WO2017185681A1 publication Critical patent/WO2017185681A1/zh
Priority to US16/169,212 priority patent/US10879937B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1525—Determination and particular use of error location polynomials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1545—Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/098—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit using single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2942—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes wherein a block of parity bits is computed only from combined information bits or only from parity bits, e.g. a second block of parity bits is computed from a first block of parity bits obtained by systematic encoding of a block of information bits, or a block of parity bits is obtained by an XOR combination of sub-blocks of information bits

Definitions

  • the present application relates to the field of communication coding, and in particular to a method, a device and a related device for encoding and decoding a codeword structure of a generalized error location (English name: Generalized Error-Locating, English abbreviation: GEL).
  • row code A and column code B are respectively defined on GF(q A ), GF(q B ), where GF is an abbreviation of Galois Field, which represents a Galois field, also called For a finite field, GF(q A ) represents a finite field containing q A elements, and GF(q B ) represents a finite field containing q B elements.
  • Row code A and column code B satisfy the following constraint relationship:
  • l 1 and l 2 are integers, and l 1 and l 2 represent bit widths of binary representations of elements in GF(2 l1 ) and GF(2 l2) , respectively, and l 1 can be divisible by l 2 because B
  • the syndrome required for decoding the code is the error value of the A code, so the bit width of the error value of the A code must be an integer multiple of the B code concomitant bit width. Due to the existing GEL codeword structure, there is a divisible constraint relationship between the row code and the GF field in which the column code is located, resulting in inflexible codeword construction, resulting in high implementation complexity and high codeword overhead.
  • the embodiments of the present invention provide a method, a device, and a related device for coding and decoding a GEL codeword structure, which are used to reduce decoding implementation complexity and reduce codeword overhead.
  • a first aspect of the present application provides a method for encoding a GEL codeword structure, including:
  • B code first original parity check matrix H C is obtained by elementary transformation target check matrix H B, H B then B information bits to obtain code check bits according to a first operation code B, then B correction code
  • the check digit is used as the information bit of the A code to encode the A code, and the check bit of the A code is obtained.
  • the check bit of the B code and the check bit of the A code are verified according to the second operation to obtain the check of the GEL code.
  • Code finally adding a single-bit parity SPC check bit, and the SPC check bit is used to verify the error location of the first layer in the A code during decoding;
  • the A code is a row code
  • the B code is a column code
  • the A code is defined on a finite field GF(2 l1 )
  • the B code is defined on a finite field GF(2 l2 )
  • l 1 and l 2 are positive integers.
  • the decoding process starts from the first layer, and the second layer to the last layer are sequentially decoded.
  • Each layer needs to obtain a priori information from the upper layer when decoding. Then according to the prior information for decoding, but the first layer can not get the prior information, so can only be decoded according to the row code and the column code check code, due to the decoding ability of the row code and column code check code May cause the first layer of decoding to fail.
  • an SPC check bit is added, and the SPC check bit is used to check the error position of the first layer in the A code (ie, the line code) during decoding;
  • the SPC check bit can be used as the a priori information of the first line A code, so that the first line A code can be decoded according to the SPC, and the decoding success rate of the first line A code is improved, thereby improving the entire translation. The efficiency of the code process.
  • the A code in the embodiment of the present application is defined on the finite field GF(2 l1 )
  • the B code is defined on the finite field GF(2 l2 )
  • l 1 and l 2 are positive integers.
  • the l 2 can be reduced as much as possible in the design process of the GEL code word structure, that is, the bit width of the B code symbol is reduced, that is, the decoding of the B code is reduced.
  • the complexity reduces the codeword overhead and effectively improves the performance of the GEL code. This not only satisfies the system's requirements for low power consumption of the product, but also improves the performance of the communication transmission system.
  • a second aspect of the present application provides a method for decoding a GEL codeword structure, including:
  • the a priori information of each layer A code is determined, wherein the a priori information of each layer A code is the wrong position when the B code is decoded by the upper layer, and the prior information of the first layer A code is SPC.
  • the check bit, the SPC check bit is the check bit added by the transmitting device when performing GEL encoding, and then the recovery of each layer A code by the same B code check matrix H B as the transmitting device, and then the restored
  • Each layer A code is decoded to obtain an erroneous B code and a B code syndrome, and then the erroneous B code is decoded by the B code syndrome to correct the erroneous B code;
  • the A code is The row code, the B code is the column code, the A code is defined on the finite field GF(2 l1 ), the B code is defined on the finite field GF(2 l2 ), and l 1 and l 2 are positive integers.
  • an SPC check bit is added, and the SPC check bit is used to check the error position of the first layer in the A code (ie, the line code) at the time of decoding; thus, the SPC check bit can be used as
  • the a priori information of the first line A code can decode the first line A code according to the SPC, and improve the decoding success rate of the first line A code, thereby improving the efficiency of the entire decoding process.
  • a third aspect of the present application provides a transmitting device having a function of implementing the method shown in the first aspect above.
  • This function can be implemented in hardware or in hardware by executing the corresponding software.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the sending device provided by the third aspect of the present application includes:
  • a transform unit configured to obtain a target check matrix H B by elementary transformation of the original check matrix H C of the B code
  • An operation unit configured to obtain, according to the first operation, the check bits of the B code according to the information bits of the target check matrix H B and the B code;
  • a coding unit configured to use the check bit of the B code as the information bit of the A code to perform RS coding on the A code;
  • the operation unit is further configured to: obtain a check code of the GEL code according to a second operation by performing a RS encoding of the check bit of the B code and the A code;
  • An adding unit configured to add a single-bit parity check SPC check bit, where the SPC check bit is used to verify an error location of the first layer in the A code during decoding;
  • the A code is a row code
  • the B code is a column code
  • the A code is defined on a finite field GF(2 l1 )
  • the B code is defined on a finite field GF(2 l2 )
  • l 1 and l 2 are positive integers.
  • a fourth aspect of the present application provides a receiving device having a function of implementing the method shown in the second aspect above.
  • This function can be implemented in hardware or in hardware by executing the corresponding software.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the receiving device provided by the fourth aspect of the present application includes:
  • a determining unit configured to determine a priori information of each layer A code, wherein the a priori information of each layer A code is an error location when the B code is decoded by the upper layer, and the first layer A code is a priori
  • the information is an SPC check bit, and the SPC check bit is a check bit added by the transmitting device when performing GEL encoding;
  • a recovery unit configured to recover each layer A code by using the same B code check matrix H B as the transmitting device
  • a decoding unit configured to decode each layer A code after recovery, to obtain an error B code and a B code syndrome
  • a correcting unit configured to decode the erroneous B code by the syndrome of the B code, and correct the erroneous B code
  • the A code is a row code
  • the B code is a column code
  • the A code is defined on a finite field GF(2 l1 )
  • the B code is defined on a finite field GF(2 l2 )
  • l 1 and l 2 are positive integers.
  • a fifth aspect of the present application provides a transmitting device having a function of implementing the method shown in the first aspect above.
  • This function can be implemented in hardware or in hardware by executing the corresponding software.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the transmitting device provided by the fifth aspect of the present application includes:
  • a memory a processor, and a transceiver, the memory, the processor, and the transceiver being interconnected by a bus, wherein the memory stores computer instructions, and the processor implements the computer instructions to implement the first aspect The method of encoding the GEL codeword structure.
  • a sixth aspect of the present application provides a receiving device having a function of implementing the method shown in the second aspect above.
  • This function can be implemented in hardware or in hardware by executing the corresponding software.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the receiving device provided by the sixth aspect of the present application includes:
  • a memory a processor, and a transceiver, wherein the memory, the processor, and the transceiver are interconnected by a bus, wherein the memory stores computer instructions, and the processor implements the computer instruction to implement the second A method of decoding a GEL codeword structure as described in the aspect.
  • a seventh aspect of the present application provides a storage medium for storing computer software instructions for use in the above-described transmitting device, including a program designed to execute the above aspects for a transmitting device.
  • An eighth aspect of the present application provides a storage medium for storing computer software instructions for use in the above-mentioned receiving device, comprising a program designed to perform the above aspects as a receiving device.
  • the names of the transmitting device and the receiving device are not limited to the device itself, and in actual implementation, these devices may appear under other names. As long as the functions of the respective devices are similar to the present application, they are within the scope of the claims and the equivalents thereof.
  • FIG. 1 is a schematic diagram of a transmitting device in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a method for encoding a GEL codeword structure in an embodiment of the present application
  • FIG. 3 is a schematic diagram of a GEL codeword structure in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a coding process of a GEL codeword structure in an embodiment of the present application.
  • FIG. 5 is another schematic diagram of a GEL codeword structure coding method according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a receiving device in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a method for decoding a GEL codeword structure in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a decoding process of a GEL codeword structure in an embodiment of the present application.
  • FIG. 9 is another schematic diagram of a sending device according to an embodiment of the present application.
  • FIG. 10 is another schematic diagram of a receiving device in an embodiment of the present application.
  • the embodiment of the present application provides a method, a device, and a related device for coding and decoding a GEL codeword structure, which are used to reduce implementation complexity, improve performance of a GEL code, and improve decoding efficiency.
  • Forward error correction is also called forward error correction code (English full name: Forward Error Correction, English abbreviation: FEC), which is a method to increase the reliability of data communication. It has the function of correcting data. In a one-way communication channel, once an error is found, its receiving device will not have the right to request a transmission. Therefore, when an error occurs in the transmission, the receiving device can correct the erroneous data through FEC.
  • FEC the GEL codeword structure is a commonly used coding structure and decoding structure. The GEL codeword structure includes a row code and a column code, and the check code of the column code is encoded by the row code to obtain the check of the GEL code. Code, thus completing the encoding of the data.
  • the transmitting device encodes the data by the GEL codeword structure before transmitting the data, and after receiving the data, the receiving device decodes the data through the GEL codeword structure and corrects the erroneous data.
  • the encoding mode of the GEL codeword structure is agreed, or the receiving device obtains the encoding mode of the GEL codeword structure of the transmitting device before receiving the data sent by the transmitting device.
  • FIG. 1 is a sending device 100 according to an embodiment of the present disclosure, where the sending device 100 includes a memory.
  • the processor 101 and the transceiver 103 are connected to each other by a bus 104.
  • the transmitting device 100 may further include a communication interface 105.
  • the processor 102, the memory 101, the transceiver 103, and the communication interface 105 can implement communication connection with each other through the bus 104, and can also implement communication by other means such as wireless transmission.
  • the memory 101 may include a volatile memory (English: volatile memory), such as random-access memory (English: random-access memory, abbreviation: RAM); the memory may also include non-volatile memory (English: non-volatile memory) For example, read-only memory (English: read-only memory, abbreviation: ROM), flash memory (English: flash memory), hard disk (English: hard disk drive, abbreviation: HDD) or solid state drive (English: solid state drive, Abbreviation: SSD); The memory 101 may also include a combination of the above types of memories.
  • the steps required to implement the method for encoding the GEL codeword structure provided in FIG. 2 of the present application are stored in the memory 101 and are processed by the processor 102. Execution, the receiving and transmitting functions of the transmitting device 100 are implemented by the processor 102 scheduling computer instructions in the memory 101 to control the transceiver 103.
  • the present application also provides a method for encoding a GEL codeword structure.
  • the transmitting device 100 in FIG. 1 executes the method at runtime, and the method is applied to a transmitting device, and a schematic flowchart thereof is shown in FIG. 2.
  • the original check matrix H C of the B code is obtained by elementary transformation to obtain a target check matrix H B ;
  • the B code is a column code.
  • the original check matrix H C of the B code needs to be obtained by elementary transformation to obtain a target check matrix H B for subsequent layering to obtain a check bit of the B code.
  • ⁇ is the primitive in the GF(2 ⁇ l2) domain.
  • the information bits of the target check matrix H B and the B code are obtained according to the first operation to obtain a check bit of the B code.
  • the first operation formula is:
  • R j represents the B code information bit
  • K A l represents the information bit of the 1st layer A code
  • the check bit of the B code is used as the information bit of the A code to perform RS coding on the A code.
  • the A code in the embodiment of the present application is a row code
  • the B code column code
  • the information bits are RS encoded for the A code.
  • the RS encoding formula is:
  • r(x) represents the parity of the A code
  • k(x) represents the information bit of the A code
  • g(x) represents the generator polynomial of the RS code.
  • Step 204 Perform a RS-coded check result of the check code of the B code and the A code to obtain a check code of the GEL code according to the second operation;
  • the second operation is:
  • Parity l represents the check code of the layer 1 GEL code.
  • the SPC check bit is added in the entire GEL codeword structure for the receiving device to verify the first layer A code according to the SPC check bit in the decoding process. Wrong location.
  • the A code is defined on the finite field GF(2 l1 )
  • the B code is defined on the finite field GF(2 l2 )
  • l1 and l2 are positive integers.
  • the values of both l1 and l2 can be similar or equal, so the finite field of the A code and the finite field of the B code can be similar or equal, thereby reducing the implementation complexity.
  • subcode constraint relationship of the A code and the subcode constraint relationship of the B code include:
  • n A represents the code length of the A code
  • n B represents the code length of the B code
  • k Ai represents the information bit of the ith row A code
  • k Bi represents the information bit of the ith row B code
  • d Ai represents the ith row
  • r Ai represents the check bit length of the A code of the i-th line
  • r Bi represents the check bit length of the B code of the i-th line
  • the information bits of each layer A code and B code are pre-designed.
  • the minimum code distance of each layer A code and B code is also pre-designed, and the minimum code distance of the first layer A code is greater than or equal to the minimum code distance of the second layer A code, and the minimum code of the second layer A code.
  • Each layer of the B code is a subordinate relationship, the first layer belongs to the second layer, the second layer belongs to the third layer, and so on.
  • FIG. 3 is a four-layer GEL codeword structure.
  • the coding method is not limited to the four-layer GEL codeword structure, and can be applied to two or more layers of GEL codeword structures.
  • Each row represents an A code
  • each column represents a B code
  • the B code is in a matrix form
  • the A code includes an information bit and a check bit
  • the check bit obtained by the B code operation is used as the information bit of the A code, and the A code information is passed.
  • the A code check bit obtained by performing RS coding on the bit is added to the check bit of the calculated B code to obtain a check code of the GEL.
  • the coding sequence of the method for encoding the GEL codeword structure in the embodiment of the present application starts from the last layer until the SPC check code is added.
  • Figure 4 shows the encoding of a three-layer GEL codeword structure. First, the third layer of coding is performed, and the second layer of coding is performed, and then the first layer of coding is performed. The coding order of each layer is to first calculate the B code check bit of the current layer, then check the B code check code, and then encode the current layer A code.
  • FIG. 5 is a flow chart showing the coding method of the GEL code word structure of FIG. 2 and the GEL code word structure shown in FIG.
  • I represents an information bit
  • P represents a parity bit
  • I11 and I12 represent the position of the information bit of the third layer
  • I21 represents the position of the information bit of the second layer
  • P21 represents the position of the parity bit of the second layer
  • K(x) represents the information bit of the A code
  • r(x) represents the check bit of the A code
  • the check bit of the B code is obtained by H B *R described in the above step 202.
  • FIG. 6 is a receiving device 600 according to an embodiment of the present disclosure.
  • the receiving device 600 includes a memory 601, a processor 602, and a transceiver 603.
  • the memory 601, the processor 602, and the transceiver 603 are connected to each other through a bus 604.
  • the receiving device 600 can also include a communication interface 605.
  • the processor 602, the memory 601, the transceiver 603, and the communication interface 605 can implement communication connection with each other through the bus 604, and can also implement communication by other means such as wireless transmission.
  • the memory 601 may include volatile memory such as random access memory; the memory may also include non-volatile memory such as read only memory, flash memory, hard disk or solid state hard disk; the memory 601 may also include a combination of the above types of memory. .
  • volatile memory such as random access memory
  • non-volatile memory such as read only memory, flash memory, hard disk or solid state hard disk
  • the memory 601 may also include a combination of the above types of memory.
  • the present application also provides a method for decoding a GEL codeword structure.
  • the receiving device 600 in FIG. 6 executes the method at runtime, and the method is applied to a receiving device, and a schematic flowchart thereof is shown in FIG. 7.
  • an SPC check bit is added in the GEL codeword structure, and the SPC check bit is used as the first layer A code for decoding.
  • Prior Information Prior Information.
  • decoding decoding is started from the first layer, and error correction is performed, and the second layer decoding and error correction are sequentially performed until the final decoding and error correction is completed, and each layer needs to be decoded.
  • the a priori information is generally the wrong position when the upper layer performs the B code decoding, but the first layer A code does not exist in the upper layer, so in the embodiment of the present application, the GEL codeword structure is The SPC check bit is added during encoding, so that the SCP check bit is used as the a priori code of the first layer A code during decoding. interest.
  • the A code with the prior information is decoded, and the error value obtained by the A decoding is the syndrome of the B code.
  • the original syndrome of the B code is calculated by the syndrome of the B code and the transformation matrix G.
  • the original corrector of the B code is to provide the corresponding error condition information for the decoding of the B code, and the B code is calculated by using the original syndrome. Wrong location.
  • the A code is a row code
  • the B code is a column code
  • the A code is defined on the finite field GF(2 l1 )
  • the B code is defined on the finite field GF(2 l2 )
  • l1 and l2 are positive integers.
  • the upper layer performs the B code decoding error
  • the B code error correction of the previous layer is first performed, and then the current layer B code is decoded.
  • FIG. 8 is a schematic diagram of a decoding performed by taking a GEL codeword structure as a three-layer codeword structure as an example.
  • the specific decoding method is:
  • the first layer of decoding process is as follows:
  • the first step calculating the SPC check bit (as the A code prior information), and simultaneously performing the first layer A code recovery;
  • the second step decoding the first layer A code, thereby obtaining the position (column position) of the wrong B code and the corresponding first layer B code syndrome;
  • the third step decoding the erroneous B code by the syndrome of the first layer B code, and correcting the erroneous B code;
  • the second layer decoding process is as follows:
  • the first step collecting the first layer B code decoding error position (as a priori information of the second layer A code), and performing the second layer A code recovery;
  • the second step decoding the second layer A code, thereby obtaining the position and corresponding of the wrong B code Second layer B code syndrome;
  • the third step when the first layer performs the B code decoding error, the error correction of the first layer B code is first performed, and then the erroneous B code is decoded by the second layer B code syndrome. Correcting the wrong B code;
  • the m-th layer decoding process is as follows:
  • the first step collecting the Bm-1 code decoding error location (as a priori information of the m-th layer A code), and performing the m-th layer A code recovery;
  • the second step decoding the mth layer Am code, thereby obtaining the position of the wrong B code and the corresponding syndrome of the mth layer B code;
  • the third step when the m-th layer performs the B-code decoding error, the error correction of the m-1 layer B code is first performed, and then the error B code is passed through the corrector of the m-th layer B code. Decoding to correct the erroneous B code;
  • the application further provides a sending device 900, which can be implemented by the sending device 100 shown in FIG. 1, or can be implemented by an application-specific integrated circuit (ASIC), or programmable logic.
  • Device (English: programmable logic device, abbreviation: PLD) implementation.
  • the above PLD can be a complex programmable logic device (English: complex programmable logic device, abbreviation: CPLD), a field programmable gate array (English full name: Field Programmable Gate Array, English abbreviation: FPGA), general array logic (English: generic Array logic, abbreviation: GAL) or any combination thereof.
  • the transmitting device 900 is configured to implement the method performed by the transmitting device shown in FIG. 2. When the method performed by the transmitting device shown in FIG. 2 is implemented by software, the transmitting device 900 may also be a software module.
  • the schematic diagram of the organization of the transmitting device 900 includes a transform unit 901 , an operation unit 902 , an encoding unit 903 , and an adding unit 904 .
  • the method performed by the transmitting device in the method of encoding the GEL codeword structure shown in FIG. 2 is performed.
  • the present application also provides a receiving device 1000, which can be implemented by the receiving device 600 shown in FIG. 6, and can also be implemented by an ASIC or a PLD.
  • the above PLD may be a CPLD, an FPGA, a GAL, or any combination thereof.
  • the receiving device 1000 is configured to implement the receiving device shown in FIG. The method that was performed.
  • the receiving device 1000 may also be a software module.
  • the organization structure of the receiving device 1000 includes a determining unit 1001, a restoring unit 1002, a decoding unit 1003, a correcting unit 1004, and a backing unit 1005.
  • the method performed by the receiving device in the method of decoding the GEL code word structure shown in FIG. 7 is performed.
  • the embodiment of the present application further provides a computer storage medium, wherein the computer storage medium may store a program, where the program includes some or all of the steps of the encoding and decoding method of the GEL codeword structure described in the foregoing method embodiment. .
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • a computer readable storage medium including instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the present application. All or part of the steps of the method described in the examples.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

本申请实施例公开了一种GEL码字结构编码的方法，本申请实施例方法包括：先将B码的HC变换得到HB，再将HB与B码的信息位运算得到B码的校验位，再将B码的校验位作为A码的信息位对A码进行RS编码，得到A码的校验位，再将B码的校验位与A码的校验位运算得到GEL码的校验码，最后增加单比特奇偶校验SPC校验位，其中，A码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。这样，SPC校验位则能够作为第一行A码的先验信息，提高了第一行A码的译码成功率，而且，在GEL码字结构设计过程中可以尽可能减小l2，即减少了B码符号的位宽，即降低B码译码实现复杂度，减少了码字开销，且有效提高GEL码的性能。

Description

一种GEL码字结构编码和译码的方法、装置及相关设备 技术领域
本申请涉及通信编码领域，尤其是一种广义错误定位(英文全称：Generalized Error-Locating，英文缩写：GEL)码字结构编码和译码的方法、装置及相关设备。
背景技术
随着数据中心建设的强劲增长，数据中心的建设快速增加，以及相应数据流量也快速增长，这对通信网络，尤其是对光网络市场产生了积极影响，为光网络设备市场注入了新的生命。而数据中心建设的持续增长，使得数据中心互联成为光网络的设备增长最快的应用，但同时也对数据中心互联也提出了新的要求。针对城域超大规模数据中心互联的新兴需求包括：在每比特成本上体积更小、功耗更低；
在现有的GEL码字结构中，行码A和列码B分别定义在GF(qA),GF(qB)上，其中，GF是Galois Field的缩写，表示伽罗华域，也称为有限域，GF(qA)表示包含qA个元素的有限域，GF(qB)表示包含qB个元素的有限域。行码A和列码B满足如下约束关系：
qA＝2l1,qB＝2l2,l1|l2
其中，l1与l2均为整数，l1和l2分别表示GF(2l1)和GF(2l2))中元素的二进制表示的位宽，且l1能被l2整除，因为B码进行译码所需的伴随式是A码的错误值，因此A码的错误值的位宽必须是B码伴随式位宽的整数倍。由于现有的GEL码字结构中，对行码与列码所在GF域存在整除约束关系，导致码字构造不灵活，造成了实现复杂度高以及较高的码字开销。
发明内容
本申请实施例提供了一种GEL码字结构编码和译码的方法、装置及相关设备，用于降低译码实现复杂度，减少了码字开销。
本申请第一方面提供一种GEL码字结构编码的方法，包括：
先将B码的原始校验矩阵HC通过初等变换得到目标校验矩阵HB，再将HB与B码的信息位按照第一运算得到B码的校验位，再将B码的校验位作为A码的信息位对A码进行里所RS编码，得到A码的校验位，再将B码的校验位与A码的校验位按照第二运算得到GEL码的校验码，最后增加单比特奇偶校验SPC校验位，SPC校验位用于在译码时校验A码中第一层的错误位置；
其中，A码为行码，B码为列码，A码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。
由于在GEL码字结构中，译码过程是从第一层开始译码，依次进行第二层到最后一层的译码，每一层在译码时需要从上一层获得先验信息，再根据先验信息进行译码，然而第一层无法得到先验信息，所以只能根据行码和列码的校验码进行译码，由于行码和列码的校验码的译码能力，可能导致第一层译码失败。而在本申请实施例中，在进行GEL编码时，增加了SPC校验位，所述SPC校验位用于在译码时校验A码(即行码)中第一层的错误位置；这样，SPC校验位则能够作为第一行A码的先验信息，从而能够根据SPC对第一行A码进行译码，提高了第一行A码的译码成功率，从而提升了整个译码过程的效率。
而且，在本申请实施例中的A码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。这样，l1与l2之间不存在整除的约束关系，因此在GEL码字结构设计过程中可以尽可能减小l2，即减少了B码符号的位宽，即降低B码译码实现复杂度，减少了码字开销，且有效提高GEL码的性能。这样既满足系统对产品低功耗的要求，同时提升通信传输系统的性能。
本申请第二方面提供一种GEL码字结构译码的方法，包括：
先确定每一层A码的先验信息，其中，每一层A码的先验信息是通过上一层进行B码译码时错误的位置，第一层A码的先验信息为SPC校验位，SPC校验位为发送设备在进行GEL编码时增加的校验位，再将通过与发送设备相同的B码校验矩阵HB对每一层A码进行恢复，再将恢复后的每一层A码进行译码，得到错误的B码以及B码的校正子，再通过B码的校正子对错误的B码进行译码，校正所述错误的B码；其中，A码为行码，B码为列码，A 码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。
在进行GEL编码时，增加了SPC校验位，所述SPC校验位用于在译码时校验A码(即行码)中第一层的错误位置；这样，SPC校验位则能够作为第一行A码的先验信息，从而能够根据SPC对第一行A码进行译码，提高了第一行A码的译码成功率，从而提升了整个译码过程的效率。
本申请第三方面提供一种发送设备，该发送设备具有实现上述第一方面所示的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块。
本申请第三方面提供的发送设备包括：
变换单元，用于将B码的原始校验矩阵HC通过初等变换得到目标校验矩阵HB；
运算单元，用于将所述目标校验矩阵HB与B码的信息位按照第一运算得到B码的校验位；
编码单元，用于将所述B码的校验位作为A码的信息位对A码进行里所RS编码；
所述运算单元还用于，将所述B码的校验位与所述A码进行RS编码后的结果按照第二运算得到GEL码的校验码；
增加单元，用于增加单比特奇偶校验SPC校验位，所述SPC校验位用于在译码时校验A码中第一层的错误位置；
其中，A码为行码，B码为列码，A码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。
本申请第四方面提供一种接收设备，该接收设备具有实现上述第二方面所示的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块。
本申请第四方面提供的接收设备包括：
确定单元，用于确定每一层A码的先验信息，其中，每一层A码的先验信息是通过上一层进行B码译码时错误的位置，第一层A码的先验信息为SPC校验位，所述SPC校验位为发送设备在进行GEL编码时增加的校验位；
恢复单元，用于将通过与发送设备相同的B码校验矩阵HB对每一层A码进行恢复；
译码单元，用于将恢复后的每一层A码进行译码，得到错误的B码以及B码的校正子；
校正单元，用于通过所述B码的校正子对错误的B码进行译码，校正所述错误的B码；
其中，A码为行码，B码为列码，A码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。
本申请第五方面提供一种发送设备，该发送设备具有实现上述第一方面所示的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块。
本申请第五方面提供的发送设备包括：
存储器、处理器以及收发器，所述存储器、处理器以及收发器之间通过总线互相连接，所述存储器中存储有计算机指令，所述处理器通过执行所述计算机指令，从而实现如第一方面所述的GEL码字结构编码的方法。
本申请第六方面提供一种接收设备，该接收设备具有实现上述第二方面所示的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块。
本申请第六方面提供的接收设备包括：
存储器、处理器以及收发器，所述存储器、处理器以及收发器之间通过总线互相连接，所述存储器中存储有计算机指令，所述处理器通过执行所述计算机指令，从而实现如上述第二方面所述的GEL码字结构译码的方法。
本申请第七方面提供一种存储介质，用于储存为上述发送设备所用的计算机软件指令，其包含用于执行上述方面为发送设备所设计的程序。
本申请第八方面提供一种存储介质，用于储存为上述接收设备所用的计算机软件指令，其包含用于执行上述方面为接收设备所设计的程序。
本申请中，发送设备以及接收设备的名字对设备本身不构成限定，在实际实现中，这些设备可以以其他名称出现。只要各个设备的功能和本申请类似，属于本发明权利要求及其等同技术的范围之内。
本发明的这些方面或其他方面在以下实施例的描述中会更加简明易懂。
附图说明
图1为本申请实施例中发送设备的一个示意图；
图2为本申请实施例中GEL码字结构编码的方法的一个示意图；
图3为本申请实施例中GEL码字结构的一个示意图；
图4为本申请实施例中GEL码字结构编码流程的一个示意图；
图5为本申请实施例中GEL码字结构编码方法的另一示意图；
图6为本申请实施例中接收设备的一个示意图；
图7为本申请实施例中GEL码字结构译码方法的一个示意图；
图8为本申请实施例中GEL码字结构译码流程的一个示意图；
图9为本申请实施例中发送设备的另一示意图；
图10为本申请实施例中接收设备的另一示意图。
具体实施方式
本申请实施例提供了一种GEL码字结构编码和译码的方法、装置及相关设备，用于降低实现的复杂度，提高GEL码的性能，且提升译码的效率。
前向纠错也叫前向纠错码(英文全称：Forward Error Correction，英文缩写：FEC)，是一种增加数据通讯可信度的方法，它具备对数据进行纠错的功能。在单向通讯信道中，一旦错误被发现，其接收设备将无权再请求传输。所以当传输中出现错误，接收设备则可以通过FEC对错误数据进行纠正。在FEC中，GEL码字结构是一种常用的编码结构以及译码结构，GEL码字结构包括行码和列码，通过行码对列码的校验位进行编码运算得到GEL码的校验码，从而完成对数据的编码。发送设备在发送数据之前，通过GEL码字结构对数据进行编码，接收设备在接收到数据后，通过GEL码字结构对数据进行译码，并纠正错误的数据。发送设备与接收设备在进行数据交互之前，先约定好GEL码字结构的编码方式，或者接收设备在接收到发送设备发送的数据之前，先获取发送设备的GEL码字结构的编码方式。
图1为本申请实施例提供的一种发送设备100，发送设备100包括存储器 101、处理器102以及收发器103，所述存储器101、处理器102以及收发器103之间通过总线104互相连接，所述发送设备100还可以包括通信接口105。
其中，处理器102、存储器101、收发器103和通信接口105可以通过总线104实现彼此之间的通信连接，也可以通过无线传输等其它手段实现通信。
存储器101可以包括易失性存储器(英文：volatile memory)，例如随机存取存储器(英文：random-access memory，缩写：RAM)；存储器也可以包括非易失性存储器(英文：non-volatile memory)，例如只读存储器(英文：read-only memory，缩写：ROM)，快闪存储器(英文：flash memory)，硬盘(英文：hard disk drive，缩写：HDD)或固态硬盘(英文：solid state drive，缩写：SSD)；存储器101还可以包括上述种类的存储器的组合。在通过软件来实现本申请提供的技术方案时，用于实现本申请图2提供的GEL码字结构编码的方法中所需要执行的步骤，计算机指令保存在存储器101中，并由处理器102来执行，发送设备100的接收和发送功能由处理器102调度存储器101中的计算机指令控制收发器103实现。
本申请还提供了一种GEL码字结构编码的方法，图1中发送设备100在运行时执行该方法，该方法应用于发送设备，其流程示意图如图2所示。
201、将B码的原始校验矩阵HC通过初等变换得到目标校验矩阵HB；
在本申请实施例中，B码为列码，首先则需要将B码的原始校验矩阵HC通过初等变换得到目标校验矩阵HB，用于后续分层获取B码的校验位。
HC的矩阵表达式为：
Figure PCTCN2016102742-appb-000001
其中α为GF(2^l2)域中的本原元。
HB的矩阵表达式为：HB＝G*HC其，中G为nB*nB的行初等变换矩阵。
202、将所述目标校验矩阵HB与B码的信息位按照第一运算得到B码的校验位；
可选的，第一运算公式为：
Figure PCTCN2016102742-appb-000002
其中，
Figure PCTCN2016102742-appb-000003
表示GEL码字结构中第l层的B码的编码矩阵，Rj表示B码信息位，KA l表示第l层A码的信息位。
203、将所述B码的校验位作为A码的信息位对A码进行里所RS编码；
在GEL码字结构中，A码(在本申请实施例中为行码)与B码(列码)进行交错编码以及交错译码，所以将计算得到后的B码的校验为作为A码的信息位对A码进行RS编码。
可选的，RS编码公式为：
Figure PCTCN2016102742-appb-000004
其中，r(x)表示A码的校验位，k(x)表示A码的信息位，g(x)表示RS编码的生成多项式。
204将所述B码的校验位与所述A码进行RS编码后的结果按照第二运算得到GEL码的校验码；
可选的，第二运算为：
Figure PCTCN2016102742-appb-000005
其中，Parityl表示第l层GEL码的校验码。
205、增加SPC校验位，所述单比特奇偶校验(英文全称：Single bit Parity Check，英文缩写：SPC)校验位用于在译码时校验A码中第一层的错误位置；
为了提高译码时第一层A码的效率，所以在整个GEL码字结构中增加SPC校验位，用于接收设备在译码过程中根据SPC校验位先校验第一层A码的错误位置。
需要说明的是，A码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。这样，l1与l2之间不存在整除的约束关系，l1与l2两者的值可以相近或者相等，那么A码的有限域与B码的有限域则可以相近或者相等，从而降低了实现复杂度，且有效提高GEL码的性能。这样既满足系统对产品低功耗的要求，同时提升通信传输系统的性能。
可选的，所述A码的子码约束关系以及B码的子码约束关系包括：
Figure PCTCN2016102742-appb-000006
Figure PCTCN2016102742-appb-000007
Figure PCTCN2016102742-appb-000008
Figure PCTCN2016102742-appb-000009
Figure PCTCN2016102742-appb-000010
其中，nA表示A码的码长，nB表示B码的码长，kAi表示第i行A码的信息位，kBi表示第i行B码的信息位，dAi表示第i行A码的最小码距，rAi表示第i行A码的校验位长度，rBi表示第i行B码的校验位长度；每一层A码以及B码的信息位都预先设计好，每一层A码以及B码的最小码距也都预先设计好，而且第一层A码的最小码距大于或等于第二层A码的最小码距，第二层A码的最小码距大于或等于第三层A码的最小码距，依次类推；而第一层B码的最小码距小于或等于第二层B码的最小码距，第二层B码的最小码距小于或等于第三层B码的最小码距，依次类推，使得在完成整个GEL编码后，使得GEL码字结构中每一层的校验能力都相当。B码的每一层都是从属关系，第一层属于第二层，第二层属于第三层，以此类推。
通过本申请实施例所述的GEL码字结构编码的方法所得到的GEL码字结构如图3所示，图3为一个四层GEL码字结构，本申请实施例所述的GEL码字结构编码的方法不限制在四层GEL码字结构，可以适用于两层或两层以上的GEL码字结构。其中，每一行代表A码，每一列代表B码，B码为矩阵形式，A码包括信息位与校验位，通过B码运算得到的校验位作为A码的信息位，通过A码信息位进行RS编码得到的A码校验位与计算得到的B码的校验位相加得到GEL的校验码。
参照图4所示，本申请实施例中GEL码字结构编码的方法的编码顺序是从最后一层开始编码，直到增加SPC校验码。图4所示为对一个三层GEL码字结构进行编码，则首先进行第三层编码，在进行第二层的编码，再进行第一层的编码。每一层的编码顺序是先进行当前层的B码校验位的计算，再进行B码校验码的检查，再进行当前层A码的编码。
图5为结合了图2的GEL码字结构的编码方法的流程以及图3所示的GEL码字结构示意图。其中，I代表信息位，P代表校验位，I11与I12表示第三层的信息位的位置，I21表示第二层的信息位的位置，P21表示第二层的校验位的位置，以此类推。K(x)表示A码的信息位，r(x)表示A码的校验位，B码的校验位由上述步骤202所述的HB*R得到。
图6为本申请实施例提供的一种接收设备600，接收设备600包括存储器601、处理器602以及收发器603，所述存储器601、处理器602以及收发器603之间通过总线604互相连接，所述接收设备600还可以包括通信接口605。
其中，处理器602、存储器601、收发器603和通信接口605可以通过总线604实现彼此之间的通信连接，也可以通过无线传输等其它手段实现通信。
存储器601可以包括易失性存储器，例如随机存取存储器；存储器也可以包括非易失性存储器，例如只读存储器，快闪存储器，硬盘或固态硬盘；存储器601还可以包括上述种类的存储器的组合。在通过软件来实现本申请提供的技术方案时，用于实现本申请图7提供的GEL码字结构译码的方法中所需要执行的步骤，计算机指令保存在存储器601中，并由处理器602来执行，接收设备600的接收和发送功能由处理器602调度存储器601中的计算机指令控制收发器603实现。
本申请还提供了一种GEL码字结构译码的方法，图6中接收设备600在运行时执行该方法，该方法应用于接收设备，其流程示意图如图7所示。
701、确定每一层A码的先验信息，其中，每一层A码的先验信息是通过上一层进行B码译码时错误的位置，第一层A码的先验信息为SPC校验位，所述SPC校验位为发送设备在进行GEL编码时增加的校验位；
在本申请的GEL码字结构中，在发送设备对数据进行编码时，在GEL码字结构中增加了SPC校验位，该SPC校验位是用于译码时作为第一层A码的先验信息。而在译码过程中，是从第一层开始译码，并进行纠错，依次进行第二层译码与纠错，直到最后一层译码纠错完成，而每一层译码时需要得到先验信息，该先验信息一般是上一层进行B码译码时错误的位置，然而第一层A码不存在上一层，所以在本申请实施例中，该GEL码字结构在编码时增加了SPC校验位，使得在译码时使用SCP校验位作为第一层A码的先验信 息。
702、将通过与发送设备相同的B码校验矩阵HB对每一层A码进行恢复；
703、将恢复后的每一层A码进行译码，得到错误的列以及B码的校正子；
在根据校验矩阵HB完成每一层A码的恢复后，再对带有先验信息的A码进行译码，A译码得到的错误值即是B码的校正子。最后由B码的校正子与变换矩阵G计算出B码的原始校正子，B码的原始校正子的作用是给B码译码提供相应的错误情况信息，B码利用原始校正子计算得出错误位置。其中B码的原始校验矩阵Hc、目标校验矩阵HB与变换矩阵G的关系为HC＝G*HB。
704、通过所述B码的校正子对错误的B码进行译码，校正所述错误的B码；
其中，A码为行码，B码为列码，A码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。
可选的，当上一层进行B码译码错误时，在当前层的B码译码过程中，先回退上一层的B码纠错，再进行当前层B码的译码。
译码过程具体举例如下说明。
图8为以GEL码字结构为三层码字结构为例进行的一个译码示意图，具体译码方式为：
第一层译码过程如下：
第一步：计算SPC校验位(作为A码先验信息)，同时进行第一层A码恢复；
第二步：对第一层A码进行译码，从而得到错误的B码的位置(列位置)以及对应的第一层B码校正子；
第三步：通过所述第一层B码的校正子对错误的B码进行译码，校正所述错误的B码；
第二层译码过程如下：
第一步：收集第一层B码译码错误位置(作为第二层A码的先验信息)，进行第二层A码恢复；
第二步：对第二层A码进行译码，从而得到错误的B码的位置以及对应 的第二层B码校正子；
第三步：当第一层进行B码译码错误时，先对第一层B码的纠错进行回退，然后通过所述第二层B码的校正子对错误的B码进行译码，校正所述错误的B码；
………
第m层译码过程如下：
第一步：收集Bm-1码译码错误位置(作为第m层A码的先验信息)，进行第m层A码恢复；
第二步：对第m层Am码进行译码，从而得到错误的B码的位置以及对应的第m层B码的校正子；
第三步：当第m-1层进行B码译码错误时，先对m-1层B码的纠错进行回退，然后通过所述第m层B码的校正子对错误的B码进行译码，校正所述错误的B码；
当完成所有层的GEL译码后，整个译码过程结束。
本申请还提供了一种发送设备900，该设备可以通过图1所示的发送设备100实现，还可以通过专用集成电路(英文：application-specific integrated circuit，缩写：ASIC)实现，或可编程逻辑器件(英文：programmable logic device，缩写：PLD)实现。上述PLD可以是复杂可编程逻辑器件(英文：complex programmable logic device，缩写：CPLD)，现场可编程逻辑门阵列(英文全称：Field Programmable Gate Array，英文缩写：FPGA)，通用阵列逻辑(英文：generic array logic,缩写：GAL)或其任意组合。该发送设备900用于实现图2所示的发送设备所执行的方法。通过软件实现图2所示的发送设备所执行的方法时，该发送设备900也可以为软件模块。
发送设备900的组织结构示意图如图9所示，包括：变换单元901、运算单元902、编码单元903以及增加单元904。其工作时，执行图2所示的GEL码字结构编码的方法中发送设备所执行的方法。
本申请还提供了一种接收设备1000，该设备可以通过图6所示的接收设备600实现，还可以通过ASIC实现，或PLD实现。上述PLD可以是CPLD，FPGA，GAL或其任意组合。该接收设备1000用于实现图7所示的接收设备 所执行的方法。通过软件实现图2所示的接收设备所执行的方法时，该接收设备1000也可以为软件模块。
接收设备1000的组织结构示意图如图10所示，包括：确定单元1001、恢复单元1002、译码单元1003、校正单元1004以及回退单元1005。其工作时，执行图7所示的GEL码字结构译码的方法中接收设备所执行的方法。
本申请实施例还提供一种计算机存储介质，其中，该计算机存储介质可存储有程序，该程序执行时包括上述方法实施例中记载的GEL码字结构的编码和译码方法的部分或全部步骤。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的 全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (16)

  1. 一种GEL码字结构编码的方法，其特征在于，所述方法包括：
    将B码的原始校验矩阵HC通过初等变换得到目标校验矩阵HB；
    将所述目标校验矩阵HB与B码的信息位按照第一运算得到B码的校验位；
    将所述B码的校验位作为A码的信息位对A码进行里所RS编码；
    将所述B码的校验位与所述A码进行RS编码后的结果按照第二运算得到GEL码的校验码；
    增加单比特奇偶校验SPC校验位，所述SPC校验位用于在译码时校验A码中第一层的错误位置；
    其中，A码为行码，B码为列码，A码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。
  2. 根据权利要求1所述的方法，其特征在于，所述将所述目标校验矩阵HB与B码的信息位按照第一运算得到B码的校验位的公式包括：
    Figure PCTCN2016102742-appb-100001
    其中，
    Figure PCTCN2016102742-appb-100002
    表示GEL码字结构中第l层的B码的目标校验矩阵HB，Rj表示B码信息位，KA l表示第l层A码的信息位。
  3. 根据权利要求1或2所述的方法，其特征在于，所述将所述B码的校验位作为A码的信息位对A码进行里所RS编码的公式包括：
    Figure PCTCN2016102742-appb-100003
    其中，r(x)表示A码的校验位，k(x)表示A码的信息位，g(x)表示RS编码的生成多项式。
  4. 根据权利要求1至3其中任意一项所述的方法，其特征在于，所述将所述B码的校验位于所述A码进行RS编码后的结果按照第二运算得到GEL码的校验码包括：
    Figure PCTCN2016102742-appb-100004
    其中，Parityl表示第l层GEL码的校验码。
  5. 根据权利要求1至4其中任意一项所述的方法，其特征在于，所述A码的子码约束关系以及B码的子码约束关系包括：
    Figure PCTCN2016102742-appb-100005
    Figure PCTCN2016102742-appb-100006
    Figure PCTCN2016102742-appb-100007
    Figure PCTCN2016102742-appb-100008
    Figure PCTCN2016102742-appb-100009
    其中，nA表示A码的码长，nB表示B码的码长，kAi表示第i行A码的信息位，kBi表示第i行B码的信息位，dAi表示第i行A码的最小码距，rAi表示第i行A码的校验位长度，rBi表示第i行B码的校验位长度。
  6. 一种GEL码字结构译码的方法，其特征在于，所述方法包括：
    确定每一层A码的先验信息，其中，每一层A码的先验信息是通过上一层进行B码译码时错误的位置，第一层A码的先验信息为SPC校验位，所述SPC校验位为发送设备在进行GEL编码时增加的校验位；
    将通过与发送设备相同的B码校验矩阵HB对每一层A码进行恢复；
    将恢复后的每一层A码进行译码，得到错误的B码以及B码的校正子；
    通过所述B码的校正子对错误的B码进行译码，校正所述错误的B码；
    其中，A码为行码，B码为列码，A码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。
  7. 根据权利要求6所述的方法，其特征在于，所述方法还包括：
    当上一层进行B码译码错误时，在当前层的B码译码过程中，先回退上一层的B码纠错。
  8. 一种发送设备，其特征在于，所述发送设备包括：
    变换单元，用于将B码的原始校验矩阵HC通过初等变换得到目标校验矩阵HB；
    运算单元，用于将所述目标校验矩阵HB与B码的信息位按照第一运算得到B码的校验位；
    编码单元，用于将所述B码的校验位作为A码的信息位对A码进行里所RS编码；
    所述运算单元还用于，将所述B码的校验位与所述A码进行RS编码后的结果按照第二运算得到GEL码的校验码；
    增加单元，用于增加单比特奇偶校验SPC校验位，所述SPC校验位用于在译码时校验A码中第一层的错误位置；
    其中，A码为行码，B码为列码，A码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。
  9. 根据权利要求8所述的发送设备，其特征在于，所述运算单元将所述目标校验矩阵HB与B码的信息位按照第一运算得到B码的校验位的公式包括：
    Figure PCTCN2016102742-appb-100010
    其中，
    Figure PCTCN2016102742-appb-100011
    表示GEL码字结构中第l层的B码的目标校验矩阵HB，Rj表示B码信息位，KA l表示第l层A码的信息位。
  10. 根据权利要求8或9所述的发送设备，其特征在于，所述编码单元将所述B码的校验位作为A码的信息位对A码进行里所RS编码的公式包括：
    Figure PCTCN2016102742-appb-100012
    其中，r(x)表示A码的校验位，k(x)表示A码的信息位，g(x)表示RS编码的生成多项式。
  11. 根据权利要求8至10其中任意一项所述的发送设备，其特征在于，所述运算单元将所述B码的校验位于所述A码进行RS编码后的结果按照第二运算得到GEL码的校验码包括：
    Figure PCTCN2016102742-appb-100013
    其中，Parityl表示第l层GEL码的校验码。
  12. 根据权利要求8至11其中任意一项所述的发送设备，其特征在于，所述A码的子码约束关系以及B码的子码约束关系包括：
    Figure PCTCN2016102742-appb-100014
    Figure PCTCN2016102742-appb-100015
    Figure PCTCN2016102742-appb-100016
    Figure PCTCN2016102742-appb-100017
    Figure PCTCN2016102742-appb-100018
    其中，nA表示A码的码长，nB表示B码的码长，kAi表示第i行A码的信息位，kBi表示第i行B码的信息位，dAi表示第i行A码的最小码距，rAi表示第i行A码的校验位长度，rBi表示第i行B码的校验位长度。
  13. 一种接收设备，其特征在于，所述接收设备包括：
    确定单元，用于确定每一层A码的先验信息，其中，每一层A码的先验信息是通过上一层进行B码译码时错误的位置，第一层A码的先验信息为SPC校验位，所述SPC校验位为发送设备在进行GEL编码时增加的校验位；
    恢复单元，用于将通过与发送设备相同的B码校验矩阵HB对每一层A码进行恢复；
    译码单元，用于将恢复后的每一层A码进行译码，得到错误的B码以及B码的校正子；
    校正单元，用于通过所述B码的校正子对错误的B码进行译码，校正所述错误的B码；
    其中，A码为行码，B码为列码，A码定义在有限域GF(2l1)上，B码定义在有限域GF(2l2)上，l1与l2为正整数。
  14. 根据权利要求13所述的接收设备，其特征在于，所述接收设备还包括：
    回退单元，用于当上一层进行B码译码错误时，在当前层的B码译码过程中，先回退上一层的B码纠错。
  15. 一种发送设备，其特征在于，包括存储器、处理器以及收发器，所述存储器、处理器以及收发器之间通过总线互相连接，所述存储器中存储有计算机指令，所述处理器通过执行所述计算机指令，从而实现如权利要求1至5其中任意一项所述的GEL码字结构编码的方法。
  16. 一种接收设备，其特征在于，包括存储器、处理器以及收发器，所述存储器、处理器以及收发器之间通过总线互相连接，所述存储器中存储有计算机指令，所述处理器通过执行所述计算机指令，从而实现如权利要求6至7其中任意一项所述的GEL码字结构译码的方法。
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