WO2017177758A1 - 数据信号的处理方法及装置 - Google Patents

数据信号的处理方法及装置 Download PDF

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Publication number
WO2017177758A1
WO2017177758A1 PCT/CN2017/073551 CN2017073551W WO2017177758A1 WO 2017177758 A1 WO2017177758 A1 WO 2017177758A1 CN 2017073551 W CN2017073551 W CN 2017073551W WO 2017177758 A1 WO2017177758 A1 WO 2017177758A1
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value
butterfly
binary tree
time
butterfly operation
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PCT/CN2017/073551
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English (en)
French (fr)
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吴昊
曹学鹏
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm

Definitions

  • the present disclosure relates to the field of communication computing, for example, to a method and apparatus for processing data signals.
  • FFT Fast Fourier Transform
  • IFFT Inverse Fast Fourier Transform
  • OFDM and OFDM can be used to implement OFDM (Orthogonal Frequency Division Multiplexing) modulation and demodulation
  • the transmitting end uses IFFT to modulate transmission data onto multiple orthogonal subcarriers, and transmits the channel through the channel.
  • the receiving end uses FFT to restore the original data from the orthogonal carrier vector, which greatly simplifies the complexity of the system implementation.
  • spectral analysis can be performed using FFT and IFFT to provide a closer look at the signal.
  • the accuracy of FFT and IFFT implementation has a great impact on the performance of these processes.
  • the input of each butterfly operation needs to be divided by the number of inputs, and the FFT or IFFT with a base number greater than 2, which will cause too many bits for each level of input data to be lost.
  • the accuracy error is large, which affects the performance of the communication system.
  • Embodiments of the present disclosure provide a data signal processing method and apparatus, which can improve the calculation precision of FFT and IFFT.
  • a data signal processing method includes:
  • each level of butterfly operations into multi-level cascade operations according to the input values of each level of butterfly operations;
  • the output value obtained by multi-level cascading operation of each level of the butterfly operation is used as an input value of the butterfly operation of the next stage;
  • an output sampling signal corresponding to the sampled input signal is obtained.
  • the step of decomposing each level of the butterfly operation into a multi-level cascading operation according to the input value of each level of the butterfly operation comprises:
  • each output operation of each stage of the butterfly operation is decomposed into a full binary tree operation structure for calculation
  • the number of layers of the full binary tree operation structure is log 2 m+1, and the number of leaf nodes in the full binary tree operation structure is m, where m is the cardinality of the fast transform algorithm between the time and frequency domains.
  • the step of decomposing each output operation of each stage of the butterfly operation into a full binary tree operation structure according to the input value of each level of the butterfly operation comprises:
  • the operation result of the value of each node in the full binary tree operation structure and its sibling node is used as the value of the parent node until the full binary tree operation is obtained.
  • the value of the root node in the structure
  • the value of the root node in the full binary tree operation structure is used as the value of the output operation corresponding to each butterfly operation.
  • the step of using the operation result of each node in the operation structure in the full binary tree operation structure and the value of the sibling node as the value of the parent node includes:
  • the calculated average value is taken as the value of the parent node.
  • the processing method before the step of determining an input value of each stage of the butterfly operation in the fast transform algorithm between the time-frequency domains, the processing method further includes:
  • the number of points is the number of sequence values after the input signal is sampled.
  • the determining, according to the number of points and the cardinality of the fast transform algorithm between the time-frequency domains, determining the number of stages of each stage of the butterfly operation in the fast transform algorithm between the time-frequency domains comprises:
  • k represents the number of stages of the butterfly operation of each stage in the fast transform algorithm between the time-frequency domains
  • m the cardinality of the fast transform algorithm between the time-frequency domains
  • N the time-frequency domain The number of points between the fast transform algorithms.
  • a data signal processing apparatus comprising:
  • the first determining module is configured to determine an input value of each butterfly operation in the fast transform algorithm between the time-frequency domains according to the sequence value sampled by the input signal; wherein, the number of input values of each butterfly operation a cardinality equal to a fast transform algorithm between the time-frequency domains;
  • the decomposition module is configured to decompose each level of the butterfly operation into a multi-level cascade operation according to the input value of each level of the butterfly operation determined by the determining module;
  • the cascading module is configured to output an output value obtained by multi-level cascading operation of each butterfly operation as an input value of the butterfly operation of the next stage;
  • the processing module is configured to obtain an output sampling signal corresponding to the sampled input signal according to an output value of the last stage butterfly operation.
  • the decomposition module includes:
  • Decomposing the sub-module configured to decompose each output operation of each stage of the butterfly operation into a full binary tree operation structure according to the input value of each level of the butterfly operation;
  • the number of layers of the full binary tree operation structure is log 2 m+1, and the number of leaf nodes in the full binary tree operation structure is m, where m is the cardinality of the fast transform algorithm between the time and frequency domains.
  • the decomposition submodule includes:
  • mapping unit configured to sequentially map an input value of each level of the butterfly operation to a value of a leaf node in the full binary tree operation structure
  • the arithmetic unit is configured to start from a leaf node in the full binary tree operation structure, and use the operation result of each node in the full binary tree operation structure and the value of the brother node as a value of the parent node until the a value of a root node in the full binary tree operation structure;
  • the cascading unit is configured to set the value of the root node in the full binary tree operation structure as the value of the output operation corresponding to each butterfly operation.
  • the operation unit includes:
  • Calculating a subunit configured to calculate an average value of each node in the full binary tree operation structure and its sibling node multiplied by a respective twiddle factor
  • the processing subunit is set to use the calculated average value as the value of the parent node.
  • the processing device further includes:
  • a second determining module configured to determine a number of points and a base according to a fast transform algorithm between the time-frequency domains, Determining a number of stages of the butterfly operation of each stage in the fast transform algorithm between the time-frequency domains, wherein the number of points of the fast transform algorithm between the time-frequency domains is a sequence value of the time-domain signal sampled Number.
  • k represents the number of stages of the butterfly operation of each stage in the fast transform algorithm between the time-frequency domains
  • m the cardinality of the fast transform algorithm between the time-frequency domains
  • N the time-frequency domain The number of points between the fast transform algorithms.
  • Yet another embodiment of the present disclosure provides a non-transitory storage medium storing computer executable instructions arranged to perform the processing of the data signals described above.
  • Yet another embodiment of the present disclosure provides a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions when the program instructions are When the computer is executed, the computer is caused to execute the above-described processing method of the data signal.
  • Yet another embodiment of the present disclosure provides an electronic device including at least one processor and a memory communicatively coupled to the at least one processor, the memory for storing instructions executable by the at least one processor, The instructions, when executed by the at least one processor, cause the at least one processor to perform the processing method of the data signal described above.
  • the data signal processing method and apparatus of the present disclosure refines the butterfly operation by decomposing each level of the butterfly operation in the fast transform algorithm between the time-frequency domain into a multi-level cascade operation, thereby eliminating the need for each level of butterfly operation.
  • the input is divided by the number of inputs to reduce the bit loss of each level of input data, improve the calculation accuracy of the fast transform algorithm between the time-frequency domain, and then can be processed by the fast transform algorithm between the time-frequency domains. Improve the performance of the communication system when communicating system data.
  • FIG. 1 is a flowchart showing a method of processing a data signal according to a first embodiment of the present disclosure
  • FIG. 2 is a flowchart showing a full binary tree operation provided by the first embodiment of the present disclosure
  • FIG. 3 is a schematic diagram showing a full binary tree operation structure provided by the first embodiment of the present disclosure
  • FIG. 4 is a schematic diagram showing another full binary tree operation structure provided by the first embodiment of the present disclosure.
  • FIG. 5 is a block diagram showing a processing apparatus of a data signal according to a second embodiment of the present disclosure
  • FIG. 6 is a structural block diagram of an electronic device according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a method for processing a data signal. As shown in FIG. 1, the processing method includes: steps S101 to S140.
  • step S110 an input value of each stage of the butterfly operation in the fast transform algorithm between the time-frequency domains is determined according to the sequence value sampled by the input signal.
  • the "fast transform algorithm between time and frequency domains” described herein is an FFT algorithm or an IFFT algorithm.
  • the "input signal” described here is a time domain signal, and the processing of the corresponding data signal is to complete the time domain to frequency domain transformation;
  • the "input signal” described herein is the frequency.
  • the processing of the corresponding data signal is to complete the frequency domain to time domain transformation.
  • the input value of each stage of the butterfly operation in the fast transform algorithm between the time and frequency domains is two or more values in the sequence value after the input signal is sampled.
  • the input value of each level of butterfly operation is the sequence value after sampling the time domain signal;
  • IFFT the input value of each level of butterfly operation is the sequence value after sampling of the frequency domain signal.
  • the number of input values of each stage of the butterfly operation is equal to the cardinality of the fast transform algorithm between the time-frequency domains.
  • FFT the number of input values for each level of butterfly operation is equal to the base of the FFT
  • IFFT the number of input values for each level of butterfly operation is equal to the base of IFFT.
  • step S120 each stage butterfly operation is decomposed into a multi-level cascade operation according to the input value of each level of the butterfly operation.
  • the multi-level cascade operation is to decompose the output operation of the original one-time operation in the butterfly operation into multiple operations, and to refine the output operation, which can prevent overflow and reduce the bit loss of the input data of each butterfly input operation. Improve the computational accuracy of the fast transform algorithm between time-frequency domains.
  • step S130 the output value obtained after the multi-stage cascade operation of each stage butterfly operation is used as the input value of the butterfly operation of the next stage.
  • the output value of each level of the butterfly operation is the input value of the butterfly operation of the next stage.
  • step S140 an output sampling signal corresponding to the sampled input signal is obtained according to the output value of the last stage butterfly operation.
  • the result of the current transformation is obtained, and the result of the current transformation is the output sampling signal corresponding to the sampled input signal.
  • the "output sampled signal” described herein is a frequency domain sampled signal, that is, an FFT transform is used to transform a time domain sampled signal into a frequency domain sampled signal.
  • the "output sampled signal” described herein is a time domain sampled signal, that is, an IFFT transform is used to transform a frequency domain sampled signal into a time domain sampled signal.
  • Embodiments of the present disclosure decompose each level of butterfly operations in a fast transform algorithm between time and frequency domains into Multi-level cascade operation, so that the input of each butterfly operation is not required to be divided by the number of inputs, so as to reduce the bit loss of input data of each stage of the butterfly operation, and improve the calculation of the fast transform algorithm between time and frequency domains.
  • Accuracy in turn, can improve the performance of the communication system when processing communication system data using fast transform algorithms between the time and frequency domains.
  • step S120 may be: according to the input value of each level of the butterfly operation, each output operation of each level of the butterfly operation is decomposed into a full binary tree operation structure for calculation.
  • the number of layers of the full binary tree operation structure is log 2 m+1, and the number of leaf nodes in the full binary tree operation structure is m, and m is the cardinality of the fast transformation algorithm between time and frequency domains.
  • m is the cardinality of the FFT
  • IFFT m is the cardinality of the IFFT.
  • the number of layers is a full binary tree structure calculation of log 2 4 + 1, 3 layer, i.e., a full binary tree leaf node number calculation structure 4.
  • the full binary tree operation structure is used to refine each output operation, and the calculation precision is high, and the calculation is relatively simple, and the calculation amount is low.
  • the implementation method of decomposing each output operation of each stage of the butterfly operation into a full binary tree operation structure may include:
  • Step S201 The input values of the butterfly operations of each stage are sequentially mapped to the values of the leaf nodes in the full binary tree operation structure.
  • the number of input values of each level of the butterfly operation is the same as the number of leaf nodes in the corresponding full binary tree operation structure, and each stage of the butterfly operation is calculated when calculating each output operation of each level of the butterfly operation
  • the input values are in turn mapped to the values of the leaf nodes in the full binary tree operation structure.
  • Step S202 Starting from a leaf node in the full binary tree operation structure, using the operation result of each node in the full binary tree operation structure and the value of the sibling node as the value of the parent node until the full binary tree operation structure is obtained. The value of the root node.
  • the calculation is started from the leaf node.
  • the value of a leaf node The value of the sibling node is subjected to a preset operation, and the result of the operation is used as the value of the parent node, and so on, until the value of the root node is obtained.
  • the "pre-defined operation” described here can be designed according to actual needs.
  • the preset operation between each node and the value of its sibling node may be: calculating the value of each node in the full binary tree operation structure and its sibling node multiplied by the respective twiddle factors. After the average value, the calculated average value is taken as the value of the parent node.
  • Step S203 The value of the root node in the full binary tree operation structure is used as the value of the output operation corresponding to each butterfly operation.
  • the value corresponding to the root node obtained by the operation between the nodes in the full binary tree operation structure is the value of the output operation corresponding to each butterfly operation.
  • each stage of the butterfly operation contains 2 output operations
  • each The output operation can decompose a structure in a full binary tree operation structure with 2 layers and 2 leaf nodes.
  • the two inputs of a butterfly operation are Xin(k1) and Xin(k2), and the two outputs are Xout(k1) and Xout(k2), respectively.
  • Xin(k1), Xin(k2) is the value of the leaf node in each full binary tree operation structure of the butterfly operation;
  • Xout(k1), Xout(k2) are respectively corresponding to each output operation of the butterfly operation
  • the value of the root node in the full binary tree operation structure is calculated as follows, and the operation result is used as the value of the parent node:
  • the two nodes corresponding to Xin(k1) and Xin(k2) are sibling nodes, and the node corresponding to Xout(k1) is Xin(k1).
  • each stage of the butterfly operation contains 4 output operations
  • each The output operation can decompose a full binary tree operation structure with a layer number of 3 and a number of leaf nodes of 4.
  • Xin(k1), Xin(k2), Xin(k3), and Xin(k4) are the four inputs of a butterfly operation.
  • the four outputs are Xout(k1), Xout(k2), Xout(k3), and Xout(k4).
  • Xin(k1), Xin(k2), Xin(k3), and Xin(k4) are the values of the leaf nodes in the full binary tree operation structure corresponding to the output operation of the butterfly operation;
  • Xout(k1), Xout(k2) Xout(k3) and Xout(k4) are the values of the root node in the full binary tree operation structure corresponding to the output operation of the butterfly operation, respectively.
  • the value of each node in the full binary tree operation structure and its sibling node is calculated as follows, and the operation result is used as the value of the parent node:
  • the first output operation is:
  • Xout(k1) (X'(k1)+X"(k2))/2.
  • the second output operation is:
  • Xout(k2) (X'(k1)-X"(k2))/2.
  • the third output operation is:
  • Xout(k3) (X'(k1)+X"(k2))/2.
  • the fourth output operation is:
  • X′′(k4) (Xin(k3) ⁇ jXin(k4))W 0 /2;
  • Xout(k4) (X'(k1)-X"(k2))/2.
  • the full binary tree operation structure is used to refine each output operation, and the calculation precision is high, and the calculation is relatively simple, and the calculation amount is low.
  • the base 2IFFT algorithm is similar to the base 2 FFT algorithm, the base 4 IFFT algorithm and the base 4 FFT algorithm, and will not be described here.
  • the embodiment of the present disclosure decomposes each output operation by using a full binary tree operation structure by decomposing the FFT or IFFT butterfly operation of each stage into a multi-level cascade operation, so that the input of each stage butterfly operation is not required to be divided by the input.
  • the number of bits to reduce the amount of bit loss per input data improve the computational accuracy of FFT or IFFT, and thus improve the performance of the communication system when processing communication system data using FFT or IFFT.
  • the processing method further includes: determining a number of stages of the butterfly operation in each of the fast transform algorithms between the time-frequency domains according to the number of points and the base of the fast transform algorithm between the time-frequency domains.
  • the number of points of the fast transform algorithm between the time and frequency domains is the number of sequence values after the input signal is sampled.
  • the number of points of the FFT is the number of sequence values after sampling the time domain signal;
  • IFFT the number of points of the IFFT is the number of sequence values after sampling the frequency domain signal.
  • k is the number of stages of the butterfly operation in each of the fast transform algorithms between the time and frequency domains
  • m is the cardinality of the fast transform algorithm between the time and frequency domains
  • N is the fast transform algorithm between the time and frequency domains.
  • k represents the number of stages of the butterfly operation of each stage of the FFT
  • m represents the cardinality of the FFT
  • N represents the number of points of the FFT.
  • IFFT k denotes the number of stages of the butterfly operation of the IFFT
  • m denotes the cardinality of the IFFT
  • N denotes the number of points of the IFFT.
  • An embodiment of the present disclosure provides a data signal processing apparatus. As shown in FIG. 5, the processing apparatus includes:
  • the first determining module 501 is configured to determine an input value of each level of the butterfly operation in the fast transform algorithm between the time-frequency domains according to the sequence value sampled by the input signal.
  • the "fast transform algorithm between time and frequency domains” described herein is an FFT algorithm or an IFFT algorithm.
  • the "input signal” described here is a time domain signal, and the processing of the corresponding data signal is to complete the time domain to frequency domain transformation;
  • the "input signal” described herein is the frequency.
  • the processing of the corresponding data signal is to complete the frequency domain to time domain transformation.
  • the input value of each stage of the butterfly operation in the fast transform algorithm between the time and frequency domains is two or more values in the sequence value after the input signal is sampled.
  • the input value of the butterfly operation of each level can be determined according to the butterfly operation rule in the prior art, and the comparison of the embodiments of the present disclosure is not limited.
  • FFT the input value of each level of butterfly operation is the sequence value after sampling the time domain signal
  • IFFT the input value of each level of butterfly operation is the sequence value after sampling of the frequency domain signal.
  • the number of input values of each stage of the butterfly operation is equal to the cardinality of the fast transform algorithm between the time-frequency domains.
  • FFT the number of input values for each level of butterfly operation is equal to the base of the FFT
  • IFFT the number of input values for each level of butterfly operation is equal to the base of IFFT.
  • the decomposition module 502 is configured to decompose each level of the butterfly operation into a multi-level cascade operation according to the input value of the butterfly operation of each level determined by the determination module 501.
  • the multi-level cascade operation is to decompose the output operation of the original one-time operation in the butterfly operation into multiple Sub-operation, refine the output operation, can prevent overflow, reduce the bit loss of the input data of each stage of the butterfly operation, and improve the calculation accuracy of the fast transform algorithm between the time-frequency domain.
  • the cascading module 503 is configured to set an output value obtained by multi-level cascading operation of each level of the butterfly operation as an input value of the butterfly operation of the next stage.
  • the output value of each level of the butterfly operation is the input value of the butterfly operation of the next stage.
  • the processing module 504 is configured to obtain a frequency domain sampling signal corresponding to the sampled time domain signal according to an output value of the last stage butterfly operation.
  • the result of the current transformation can be obtained, and the result of the current transformation is the frequency domain sampling signal corresponding to the sampled time domain signal.
  • the "output sampled signal” described herein is a frequency domain sampled signal, that is, an FFT transform is used to transform a time domain sampled signal into a frequency domain sampled signal.
  • the "output sampled signal” described herein is a time domain sampled signal, that is, an IFFT transform is used to transform a frequency domain sampled signal into a time domain sampled signal.
  • the processing device for the data signal provided by the embodiment of the present disclosure decomposes the butterfly operation of each stage in the fast transform algorithm between the time-frequency domain into a multi-level cascade operation, so that the input of each butterfly operation is not required to be deleted.
  • the number of inputs is used to reduce the bit loss of the input data of each stage of the butterfly operation, and the calculation precision of the fast transform algorithm between the time and frequency domains is improved, and the communication system can be processed by the fast transform algorithm between the time and frequency domains. Data improves the performance of the communication system.
  • the decomposition module 502 includes:
  • the decomposing sub-module is configured to decompose each output operation of each butterfly operation into a full binary tree operation structure according to the input value of each level of the butterfly operation.
  • the number of layers of the full binary tree operation structure is log 2 m+1, and the number of leaf nodes in the full binary tree operation structure is m, and m is the cardinality of the fast transformation algorithm between time and frequency domains.
  • m is the cardinality of the FFT
  • IFFT m is the cardinality of the IFFT.
  • the number of layers of the full binary tree operation structure is log 2 4+1, that is, 3 layers, and the number of leaf nodes in the full binary tree operation structure is 4.
  • the full binary tree operation structure is used to refine each output operation, and the calculation precision is high, and the calculation is relatively simple, and the calculation amount is low.
  • the decomposition submodule includes:
  • the mapping unit is arranged to sequentially map the input values of the butterfly operations of each level to the values of the leaf nodes in the full binary tree operation structure.
  • the number of input values of each level of the butterfly operation is the same as the number of leaf nodes in the corresponding full binary tree operation structure, and each stage of the butterfly operation is calculated when calculating each output operation of each level of the butterfly operation
  • the input values are in turn mapped to the values of the leaf nodes in the full binary tree operation structure.
  • the full binary tree operation structure is used to refine each output operation, and the calculation precision is high, and the calculation is relatively simple, and the calculation amount is low.
  • the operation unit is set to start from the leaf node in the full binary tree operation structure, and the operation result of each node in the full binary tree operation structure and the value of the sibling node is used as the value of the parent node until the full binary tree operation structure is obtained.
  • the calculation is started from the leaf node. Predetermine the value of a leaf node and the value of its sibling node, and use the result of the operation as the value of the parent node, and so on, until the value of the root node is obtained.
  • the "pre-defined operation” described here can be designed according to actual needs.
  • the cascading unit is set to use the value of the root node in the full binary tree operation structure as the value of the output operation corresponding to each butterfly operation.
  • the value corresponding to the root node obtained by the operation between the nodes in the full binary tree operation structure is the value of the output operation corresponding to each butterfly operation.
  • the embodiment of the present disclosure decomposes each output operation by using a full binary tree operation structure by decomposing each level of the butterfly operation in the fast transform algorithm between the time-frequency domains into a multi-level cascade operation, so that it is not necessary to
  • the input of the butterfly operation needs to be divided by the number of inputs to reduce the bit loss of each level of input data, improve the calculation accuracy of the fast transform algorithm between the time-frequency domains, and thus can be used between the frequency domains.
  • the fast transform algorithm improves the performance of the communication system when processing communication system data.
  • the arithmetic unit includes:
  • the calculation subunit is set to calculate the average value of each node in the full binary tree operation structure and its sibling node multiplied by the respective rotation factor.
  • the processing subunit is set to use the calculated average value as the value of the parent node.
  • the preset operation between the value of each node and its sibling node is preferably: the value of each node in the full binary tree operation structure and the value of its sibling node multiplied by the respective twiddle factors. Average calculation.
  • the processing device further includes:
  • the second determining module is configured to determine the number of stages of the butterfly operation of the fast transform algorithm between the time-frequency domains according to the number of points and the base of the fast transform algorithm between the time-frequency domains.
  • the number of points of the fast transform algorithm between the time and frequency domains is the number of sequence values after the time domain signal is sampled.
  • the number of points of the FFT is the number of sequence values after sampling the time domain signal;
  • IFFT the number of points of the IFFT is the number of sequence values after sampling the frequency domain signal.
  • k is the number of stages of the butterfly operation in each of the fast transform algorithms between the time and frequency domains
  • m is the cardinality of the fast transform algorithm between the time and frequency domains
  • N is the fast transform algorithm between the time and frequency domains.
  • k represents the number of stages of the butterfly operation of each stage of the FFT
  • m represents the cardinality of the FFT
  • N represents the number of points of the FFT.
  • IFFT k denotes the number of stages of the butterfly operation of the IFFT
  • m denotes the cardinality of the IFFT
  • N denotes the number of points of the IFFT.
  • the device is a device corresponding to the processing method of the data signal, and all the implementation manners in the foregoing method embodiments are applicable to the embodiment of the device, and the same technical effects can be achieved.
  • the present disclosure also provides a non-transitory storage medium storing computer executable instructions arranged to perform the processing of the data signals of the above-described embodiments.
  • the present disclosure also provides a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions, when the program instructions are executed by a computer, The computer is caused to execute the processing method of the data signal of the above embodiment.
  • FIG. 6 is a structural block diagram of an electronic device according to an embodiment of the present disclosure.
  • the electronic device may include a processor 61 and a memory 63, and may further include a communication interface 62 and a bus 64.
  • the processor 61, the communication interface 62, and the memory 63 can complete communication with each other through the bus 64.
  • Communication interface 62 can be used for information transfer.
  • the processor 61 can call the logic instructions in the memory 63 to perform the processing method of the data signals of the above embodiments.
  • the logic instructions in the memory 63 described above may be implemented in the form of a software functional unit and sold or used as a stand-alone product, and may be stored in a computer readable storage medium.
  • the technical solution of the present disclosure may be embodied in the form of a software product stored in a storage medium, including a plurality of instructions for causing a computer device (which may be a personal computer, a server, or a network) The device or the like) performs all or part of the steps of the method described in various embodiments of the present disclosure.
  • the foregoing storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk. a medium that can store program code, or It is a transient storage medium.
  • the butterfly operation is refined by decomposing each level of the butterfly operation in the fast transform algorithm between the time-frequency domains into a multi-level cascade operation, thereby eliminating the need for each level of butterfly
  • the input of the operation needs to be divided by the number of inputs to reduce the bit loss of each level of input data, improve the calculation accuracy of the fast transform algorithm between the time-frequency domain, and then enable a fast transform algorithm between the time-frequency domains. Improve the performance of the communication system when processing communication system data.

Abstract

本公开提供了一种数据信号的处理方法及装置，所述处理方法包括：根据输入信号采样后的序列值，确定时频域之间的快速变换算法中的每级蝶形运算的输入值；其中，每级蝶形运算的输入值的个数等于所述时频域之间的快速变换算法的基数；根据每级蝶形运算的输入值，将每级蝶形运算分解为多级级联运算；将每级蝶形运算经过多级级联运算后得到的输出值，作为下一级蝶形运算的输入值；根据最后一级蝶形运算的输出值，得到与采样后的所述输入信号对应的输出采样信号。

Description

数据信号的处理方法及装置 技术领域
本公开涉及通信计算领域，例如涉及一种数据信号的处理方法及装置。
背景技术
随着数字信号处理技术的发展，FFT(Fast Fourier Transform，快速傅里叶变换)和IFFT(Inverse Fast Fourier Transform，FFT逆变换)已广泛的应用到通信系统的各种运算中。例如，可以利用FFT和IFFT实现OFDM(Orthogonal Frequency Division Multiplexing，正交频分复用)的调制和解调，发射端使用IFFT将发送数据调制到多个正交子载波上，经过信道传输，在接收端使用FFT，从正交载波矢量中还原出原始数据，从而大大简化系统实现的复杂度。再例如，可以利用FFT和IFFT进行频谱分析，以便对信号具有更近进一步的了解。其中，FFT和IFFT实现的精度对这些过程的性能有着较大影响。相关技术中的定点FFT和IFFT为了防止溢出，每级蝶形运算的输入需除以输入的个数，对基数大于2的FFT或IFFT，这样会造成每级输入数据丢失的比特过多，计算精度误差较大，影响了通信系统的性能。
发明内容
本公开的实施例提供了一种数据信号的处理方法及装置，可以提高FFT和IFFT的计算精度。
依据本公开实施例的一个方面，提供了一种数据信号的处理方法，所述数据信号的处理方法包括：
根据输入信号采样后的序列值，确定时频域之间的快速变换算法中的每级蝶形运算的输入值；其中，每级蝶形运算的输入值的个数等于所述时频域之间的快速变换算法的基数；
根据每级蝶形运算的输入值，将每级蝶形运算分解为多级级联运算；
将每级蝶形运算经过多级级联运算后得到的输出值，作为下一级蝶形运算的输入值；以及
根据最后一级蝶形运算的输出值，得到与采样后的所述输入信号对应的输出采样信号。
可选地，所述根据每级蝶形运算的输入值，将每级蝶形运算分解为多级级联运算的步骤包括：
根据每级蝶形运算的输入值，将每级蝶形运算的每个输出运算分解为一满二叉树运算结构进行计算；
其中，所述满二叉树运算结构的层数为log2m+1，所述满二叉树运算结构中的叶结点数为m，m为所述时频域之间的快速变换算法的基数。
可选地，所述根据每级蝶形运算的输入值，将每级蝶形运算的每个输出运算分解为一满二叉树运算结构进行计算的步骤包括：
将每级蝶形运算的输入值依次映射为所述满二叉树运算结构中的叶结点的数值；
从所述满二叉树运算结构中的叶结点开始，将所述满二叉树运算结构中的每一结点与其兄弟结点的数值的运算结果作为双亲结点的数值，直到得到所述满二叉树运算结构中的根结点的数值；
将所述满二叉树运算结构中的根结点的数值作为每级蝶形运算对应的输出运算的数值。
可选地，所述将所述满二叉树运算结构中运算结构中的每一结点与其兄弟结点的数值的运算结果作为双亲结点的数值的步骤包括：
计算所述满二叉树运算结构中运算结构中的每一结点与其兄弟结点的数值乘以各自旋转因子后的平均值；
将计算得到的平均值作为双亲结点的数值。
可选地，所述确定时频域之间的快速变换算法中的每级蝶形运算的输入值的步骤之前，所述处理方法还包括：
根据所述时频域之间的快速变换算法的点数和基数，确定所述时频域之间的快速变换算法蝶形运算的级数，其中，所述时频域之间的快速变换算法的点数为所述输入信号采样后的序列值的个数。
可选地，所述根据所述时频域之间的快速变换算法的点数和基数，确定所述时频域之间的快速变换算法中的每级蝶形运算的级数的步骤包括：
根据预设公式：k＝logmN，确定蝶形运算的级数；
其中，k表示所述时频域之间的快速变换算法中的每级蝶形运算的级数，m表示所述时频域之间的快速变换算法的基数，N表示所述时频域之间的快速变换算法的点数。
依据本公开实施例的另一个方面，提供了一种数据信号的处理装置，所述数据信号的处理装置包括：
第一确定模块，设置为根据输入信号采样后的序列值，确定时频域之间的快速变换算法中的每级蝶形运算的输入值；其中，每级蝶形运算的输入值的个数等于所述时频域之间的快速变换算法的基数；
分解模块，设置为根据确定模块确定的每级蝶形运算的输入值，将每级蝶形运算分解为多级级联运算；
级联模块，设置为将每级蝶形运算经过多级级联运算后得到的输出值，作为下一级蝶形运算的输入值；以及
处理模块，设置为根据最后一级蝶形运算的输出值，得到与采样后的所述输入信号对应的输出采样信号。
可选地，所述分解模块包括：
分解子模块，设置为根据每级蝶形运算的输入值，将每级蝶形运算的每个输出运算分解为一满二叉树运算结构；
其中，所述满二叉树运算结构的层数为log2m+1，所述满二叉树运算结构中的叶结点数为m，m为所述时频域之间的快速变换算法的基数。
可选地，所述分解子模块包括：
映射单元，设置为将每级蝶形运算的输入值依次映射为所述满二叉树运算结构中的叶结点的数值；
运算单元，设置为从所述满二叉树运算结构中的叶结点开始，将所述满二叉树运算结构中的每一结点与其兄弟结点的数值的运算结果作为双亲结点的数值，直到得到所述满二叉树运算结构中的根结点的数值；
级联单元，设置为将所述满二叉树运算结构中的根结点的数值作为每级蝶形运算对应的输出运算的数值。
可选地，所述运算单元包括：
计算子单元，设置为计算所述满二叉树运算结构中的每一结点与其兄弟结点的数值乘以各自旋转因子后的平均值；
处理子单元，设置为将计算得到的平均值作为双亲结点的数值。
可选地，所述处理装置还包括：
第二确定模块，设置为根据所述时频域之间的快速变换算法的点数和基数， 确定所述时频域之间的快速变换算法中的每级蝶形运算的级数，其中，所述时频域之间的快速变换算法的点数为所述时域信号采样后的序列值的个数。
可选地，所述第二确定模块设置为：根据预设公式：k＝logmN，确定每级蝶形运算的级数；
其中，k表示所述时频域之间的快速变换算法中的每级蝶形运算的级数，m表示所述时频域之间的快速变换算法的基数，N表示所述时频域之间的快速变换算法的点数。
本公开的又一个实施例提供了一种非暂态存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述的数据信号的处理方法。
本公开的又一个实施例提供了一种计算机程序产品，所述计算机程序产品包括存储在非暂态计算机可读存储介质上的计算机程序，所述计算机程序包括程序指令，当所述程序指令被计算机执行时，使所述计算机执行上述的数据信号的处理方法。
本公开的又一个实施例提供了一种电子设备，包括至少一个处理器和与所述至少一个处理器通信连接的存储器，所述存储器用于存储可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行时，使所述至少一个处理器执行上述的数据信号的处理方法。
本公开的数据信号的处理方法和装置，通过将时频域之间的快速变换算法中的每级蝶形运算分解为多级级联操作，细化蝶形运算，从而不必每级蝶形运算的输入均需除以输入的个数，以减少每级输入数据的比特丢失量，提高时频域之间的快速变换算法的计算精度，进而能够在使用时频域之间的快速变换算法处理通信系统数据时提高通信系统的性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1表示本公开第一实施例提供的数据信号的处理方法的流程图；
图2表示本公开第一实施例提供的满二叉树运算的流程图；
图3表示本公开第一实施例提供的满二叉树运算结构的示意图；
图4表示本公开第一实施例提供的另一满二叉树运算结构的示意图；
图5表示本公开第二实施例提供的数据信号的处理装置的框图；
图6是本公开的实施例提供的电子设备的结构框图。
具体实施方式
以下结合附图对本公开的实施例进行详细说明，在不冲突的情况下，以下实施例和实施例中的特征可以相互组合。
第一实施例
本公开实施例提供了一种数据信号的处理方法，如图1所示，该处理方法包括：步骤S101至S140。
在步骤S110、根据输入信号采样后的序列值，确定时频域之间的快速变换算法中的每级蝶形运算的输入值。
其中，这里所述的“时频域之间的快速变换算法”为FFT算法或IFFT算法。对于FFT来说，这里所述的“输入信号”为时域信号，对应的数据信号的处理过程是完成时域到频域的变换；对于IFFT来说，这里所述的“输入信号”为频域信号，对应的数据信号的处理过程是完成频域到时域的变换。
其中，时频域之间的快速变换算法中的每级蝶形运算的输入值为输入信号采样后的序列值中的两个或多个数值。对于FFT来说，每级蝶形运算的输入值为时域信号采样后的序列值；对于IFFT来说，每级蝶形运算的输入值为频域信号采样后的序列值。
其中，每级蝶形运算的输入值的个数等于时频域之间的快速变换算法的基数。对于FFT来说，每级蝶形运算的输入值的个数等于FFT的基数；对于IFFT来说，每级蝶形运算的输入值的个数等于IFFT的基数。
在步骤S120、根据每级蝶形运算的输入值，将每级蝶形运算分解为多级级联运算。
其中，多级级联运算是将蝶形运算中原本一次性运算的输出运算分解为多次运算，细化输出运算，既能防止溢出，又能减少每级蝶形运算输入数据的比特丢失量，提高时频域之间的快速变换算法的计算精度。
在步骤S130、将每级蝶形运算经过多级级联运算后得到的输出值，作为下一级蝶形运算的输入值。
根据蝶形运算的规则，每级蝶形运算的输出值为下一级蝶形运算的输入值。
在步骤S140、根据最后一级蝶形运算的输出值，得到与采样后的输入信号对应的输出采样信号。
其中，在完成最后一级的蝶形运算后，即可得到本次变换的结果，而本次变换的结果即为与采样后的输入信号对应的输出采样信号。对于FFT来说，这里所述的“输出采样信号”为频域采样信号，也就是通过FFT变换，将时域采样信号变换为频域采样信号。对于IFFT来说，这里所述的“输出采样信号”为时域采样信号，也就是经过IFFT变换，将频域采样信号变换为时域采样信号。
本公开实施例通过将时频域之间的快速变换算法中的每级蝶形运算分解为 多级级联操作，从而不必每级蝶形运算的输入都需除以输入的个数，以减少每级蝶形运算输入数据的比特丢失量，提高时频域之间的快速变换算法的计算精度，进而能够在使用时频域之间的快速变换算法处理通信系统数据时提高通信系统的性能。
可选地，步骤S120可为：根据每级蝶形运算的输入值，将每级蝶形运算的每个输出运算分解为一满二叉树运算结构进行计算。
其中，满二叉树运算结构的层数为log2m+1，满二叉树运算结构中的叶结点数为m，m为时频域之间的快速变换算法的基数。对于FFT来说，m为FFT的基数；对于IFFT来说，m为IFFT的基数。
例如，若FFT的基数为4，则满二叉树运算结构的层数为log24+1，即3层，满二叉树运算结构中的叶结点数为4。采用满二叉树运算结构来细化每个输出运算，计算精度较高，且计算比较简单，运算量较低。
可选地，如图2所示，根据每级蝶形运算的输入值，将每级蝶形运算的每个输出运算分解为一满二叉树运算结构进行计算的实现方法可包括：
步骤S201、将每级蝶形运算的输入值依次映射为满二叉树运算结构中的叶结点的数值。
其中，每级蝶形运算的输入值的个数与对应的满二叉树运算结构中的叶节点的个数相同，在计算每级蝶形运算的每个输出运算时，将每级蝶形运算的输入值依次映射为满二叉树运算结构中的叶结点的数值。
步骤S202、从满二叉树运算结构中的叶结点开始，将满二叉树运算结构中的每一结点与其兄弟结点的数值的运算结果作为双亲结点的数值，直到得到满二叉树运算结构中的根结点的数值。
在进行满二叉树运算时，从叶结点开始进行计算。将一个叶结点的数值与 其兄弟结点的数值进行预设的运算，将运算结果作为双亲结点的数值，依次类推，直到得到根结点的数值。这里所述的“预设的运算”可根据实际需求设计。
在本公开实施例中，每一结点与其兄弟结点的数值之间的预设的运算，可为：计算满二叉树运算结构中的每一结点与其兄弟结点的数值乘以各自旋转因子后的平均值，将计算得到的平均值作为双亲结点的数值。
步骤S203、将满二叉树运算结构中的根结点的数值作为每级蝶形运算对应的输出运算的数值。
经过满二叉树运算结构中各结点之间的运算所得到的根结点对应的数值，即为每级蝶形运算对应的输出运算的数值。
为进一步理解上述S201～S203，下面分别以基2FFT算法和基4FFT算法对此进行进一步的解释说明。
(1)假设FFT点数为1024，FFT基数为2，那么蝶形运算的级数k＝10，每级蝶形运算的输入个数为2，每级蝶形运算包含2个输出运算，每个输出运算可分解一个层数为2、叶结点数为2的满二叉树运算结构中结构。
例如，一个蝶形运算的二个输入分别为Xin(k1)，Xin(k2)，二个输出分别为Xout(k1)，Xout(k2)。Xin(k1)，Xin(k2)是该蝶形运算每个满二叉树运算结构中的叶结点的数值；Xout(k1)，Xout(k2)分别是该蝶形运算的每一输出运算对应的满二叉树运算结构中的根结点的数值。将满二叉树运算结构中的每一结点与其兄弟结点的数值的进行如下运算，并将运算结果作为双亲结点的数值：
其中，如图3所示的满二叉树运算结构中，Xin(k1)和Xin(k2)所对应的两个结点互为兄弟结点，Xout(k1)所对应的结点为Xin(k1)和Xin(k2)所对应的两个结点的双亲结点，在此，同时也是满二叉树运算结构中的根结点。其中第一个输出运算为：Xout(k1)＝(Xin(k1)+Xin(k2)W0)/2。
由于第二个输出运算与第一输出运算类似，本公开实施例对此便不再以附图示意，运算过程如下所示：
第二个输出运算为：Xout(k2)＝(Xin(k1)+Xin(k2)W1)/2。
(2)假设FFT点数为1024，FFT基数为4，那么蝶形运算的级数k＝5，每级蝶形运算的输入个数为4，每级蝶形运算包含4个输出运算，每个输出运算可分解一个层数为3、叶结点数为4的满二叉树运算结构。
假设一个蝶形运算的四个输入分别为Xin(k1)，Xin(k2)，Xin(k3)，Xin(k4)。四个输出分别为Xout(k1)，Xout(k2)，Xout(k3)，Xout(k4)。Xin(k1)，Xin(k2)，Xin(k3)，Xin(k4)是该蝶形运算的输出运算对应的满二叉树运算结构中的叶结点的数值；Xout(k1)，Xout(k2)，Xout(k3)，Xout(k4)分别是该蝶形运算的输出运算对应的满二叉树运算结构中的根节点的数值。将满二叉树运算结构中的每一结点与其兄弟结点的数值的进行如下运算，并将运算结果作为双亲结点的数值：
其中，如图4所示的满二叉树运算结构，第一个输出运算为：
X′(k1)＝(Xin(k1)+Xin(k2))/2；
X″(k1)＝(Xin(k3)+Xin(k4))W0/2；
Xout(k1)＝(X′(k1)+X″(k2))/2。
由于，第二、三、四个输出运算与第一输出运算类似，本公开实施例对此便不再以附图示意，具体运算过程如下所示：
第二个输出运算为：
X′(k2)＝(Xin(k1)-jXin(k2))/2；
X″(k2)＝(Xin(k3)+jXin(k4))W1/2；
Xout(k2)＝(X′(k1)-X″(k2))/2。
第三个输出运算为：
X′(k3)＝(Xin(k1)-Xin(k2))/2；
X″(k3)＝(Xin(k3)-Xin(k4))W2/2；
Xout(k3)＝(X′(k1)+X″(k2))/2。
第四个输出运算为：
X′(k4)＝(Xin(k1)+jXin(k2))/2；
X″(k4)＝(Xin(k3)-jXin(k4))W0/2；
Xout(k4)＝(X′(k1)-X″(k2))/2。
其中，j表示虚数单位，W为旋转因子。
采用满二叉树运算结构来细化每个输出运算，计算精度较高，且计算比较简单，运算量较低。其中，基2IFFT算法与基2FFT算法、基4IFFT算法和基4FFT算法类似，这里便不再进行赘述。
本公开实施例通过将FFT或IFFT每级蝶形运算分解为多级级联操作，优选采用满二叉树运算结构来细化每个输出运算，从而不必每级蝶形运算的输入都需除以输入的个数，以减少每级输入数据的比特丢失量，提高FFT或IFFT的计算精度，进而能够在使用FFT或IFFT处理通信系统数据时提高通信系统的性能。
可选地，在S110之前，该处理方法还包括：根据时频域之间的快速变换算法的点数和基数，确定时频域之间的快速变换算法中的每级蝶形运算的级数。
其中，时频域之间的快速变换算法的点数为输入信号采样后的序列值的个数。对于FFT来说，FFT的点数为时域信号采样后的序列值的个数；对于IFFT来说，IFFT的点数为频域信号采样后的序列值的个数。
可选，可根据预设公式：k＝logmN，确定蝶形运算的级数。其中，k表示时频域之间的快速变换算法中的每级蝶形运算的级数，m表示时频域之间的快速 变换算法的基数，N表示时频域之间的快速变换算法的点数。对于FFT来说，k表示FFT每级蝶形运算的级数，m表示FFT的基数，N表示FFT的点数。对于IFFT来说，k表示IFFT每级蝶形运算的级数，m表示IFFT的基数，N表示IFFT的点数。
第二实施例
本公开实施例提供了一种数据信号的处理装置，如图5所示，所述处理装置包括：
第一确定模块501，设置为根据输入信号采样后的序列值，确定时频域之间的快速变换算法中的每级蝶形运算的输入值。
其中，这里所述的“时频域之间的快速变换算法”为FFT算法或IFFT算法。对于FFT来说，这里所述的“输入信号”为时域信号，对应的数据信号的处理过程是完成时域到频域的变换；对于IFFT来说，这里所述的“输入信号”为频域信号，对应的数据信号的处理过程是完成频域到时域的变换。
其中，时频域之间的快速变换算法中的每级蝶形运算的输入值为输入信号采样后的序列值中的两个或多个数值。具体每级蝶形运算的输入值可根据现有技术中的蝶形运算规则来确定，本公开实施例对比不进行限制。对于FFT来说，每级蝶形运算的输入值为时域信号采样后的序列值；对于IFFT来说，每级蝶形运算的输入值为频域信号采样后的序列值。
其中，每级蝶形运算的输入值的个数等于时频域之间的快速变换算法的基数。对于FFT来说，每级蝶形运算的输入值的个数等于FFT的基数；对于IFFT来说，每级蝶形运算的输入值的个数等于IFFT的基数。
分解模块502，设置为根据确定模块501确定的每级蝶形运算的输入值，将每级蝶形运算分解为多级级联运算。
其中，多级级联运算是将蝶形运算中原本一次性运算的输出运算分解为多 次运算，细化输出运算，既能防止溢出，又能减少每级蝶形运算输入数据的比特丢失量，提高时频域之间的快速变换算法的计算精度。
级联模块503，设置为将每级蝶形运算经过多级级联运算后得到的输出值，作为下一级蝶形运算的输入值。
根据蝶形运算的规则，每级蝶形运算的输出值为下一级蝶形运算的输入值。
处理模块504，设置为根据最后一级蝶形运算的输出值，得到与采样后的时域信号对应的频域采样信号。
其中，在完成最后一级的蝶形运算后，即可得到本次变换的结果，而本次变换的结果即为与采样后的时域信号对应的频域采样信号。对于FFT来说，这里所述的“输出采样信号”为频域采样信号，也就是通过FFT变换，将时域采样信号变换为频域采样信号。对于IFFT来说，这里所述的“输出采样信号”为时域采样信号，也就是经过IFFT变换，将频域采样信号变换为时域采样信号。
本公开实施例提供的数据信号的处理装置，通过将时频域之间的快速变换算法中的每级蝶形运算分解为多级级联操作，从而不必每级蝶形运算的输入都需除以输入的个数，以减少每级蝶形运算输入数据的比特丢失量，提高时频域之间的快速变换算法的计算精度，进而能够在使用时频域之间的快速变换算法处理通信系统数据时提高通信系统的性能。
可选地，分解模块502包括：
分解子模块，设置为根据每级蝶形运算的输入值，将每级蝶形运算的每个输出运算分解为一满二叉树运算结构进行运算。
其中，满二叉树运算结构的层数为log2m+1，满二叉树运算结构中的叶结点数为m，m为时频域之间的快速变换算法的基数。对于FFT来说，m为FFT的基数；对于IFFT来说，m为IFFT的基数。
例如，若FFT的基数为4，则满二叉树运算结构的层数为log24+1，即3层，满二叉树运算结构中的叶结点数为4。采用满二叉树运算结构来细化每个输出运算，计算精度较高，且计算比较简单，运算量较低。
可选地，分解子模块包括：
映射单元，设置为将每级蝶形运算的输入值依次映射为满二叉树运算结构中的叶结点的数值。
其中，每级蝶形运算的输入值的个数与对应的满二叉树运算结构中的叶节点的个数相同，在计算每级蝶形运算的每个输出运算时，将每级蝶形运算的输入值依次映射为满二叉树运算结构中的叶结点的数值。
采用满二叉树运算结构来细化每个输出运算，计算精度较高，且计算比较简单，运算量较低。
运算单元，设置为从满二叉树运算结构中的叶结点开始，将满二叉树运算结构中的每一结点与其兄弟结点的数值的运算结果作为双亲结点的数值，直到得到满二叉树运算结构中的根结点的数值。
在进行满二叉树运算时，从叶结点开始进行计算。将一个叶结点的数值与其兄弟结点的数值进行预设的运算，将运算结果作为双亲结点的数值，依次类推，直到得到根结点的数值。这里所述的“预设的运算”可根据实际需求设计。
级联单元，设置为将满二叉树运算结构中的根结点的数值作为每级蝶形运算对应的输出运算的数值。
经过满二叉树运算结构中各结点之间的运算所得到的根结点对应的数值，即为每级蝶形运算对应的输出运算的数值。
本公开实施例通过将时频域之间的快速变换算法中的每级蝶形运算分解为多级级联操作，优选采用满二叉树运算结构来细化每个输出运算，从而不必每 级蝶形运算的输入都需除以输入的个数，以减少每级输入数据的比特丢失量，提高时频域之间的快速变换算法的计算精度，进而能够在使用时频域之间的快速变换算法处理通信系统数据时提高通信系统的性能。
可选地，运算单元包括：
计算子单元，设置为计算满二叉树运算结构中的每一结点与其兄弟结点的数值乘以各自旋转因子后的平均值。
处理子单元，设置为将计算得到的平均值作为双亲结点的数值。
在本公开实施例中，每一结点与其兄弟结点的数值之间的预设的运算优选为：满二叉树运算结构中的每一结点与其兄弟结点的数值乘以各自旋转因子后的平均值计算。
可选地，该处理装置还包括：
第二确定模块，设置为根据时频域之间的快速变换算法的点数和基数，确定时频域之间的快速变换算法蝶形运算的级数。
其中，时频域之间的快速变换算法的点数为时域信号采样后的序列值的个数。对于FFT来说，FFT的点数为时域信号采样后的序列值的个数；对于IFFT来说，IFFT的点数为频域信号采样后的序列值的个数。
可选地，第二确定模块设置为：根据预设公式：k＝logmN，确定每级蝶形运算的级数。
其中，k表示时频域之间的快速变换算法中的每级蝶形运算的级数，m表示时频域之间的快速变换算法的基数，N表示时频域之间的快速变换算法的点数。对于FFT来说，k表示FFT每级蝶形运算的级数，m表示FFT的基数，N表示FFT的点数。对于IFFT来说，k表示IFFT每级蝶形运算的级数，m表示IFFT的基数，N表示IFFT的点数。
需要说明的是，该装置是与上述数据信号的处理方法对应的装置，上述方法实施例中所有实现方式均适用于该装置的实施例中，也能达到相同的技术效果。
本公开还提供了一种非暂态存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述实施例的数据信号的处理方法。
本公开还提供了一种计算机程序产品，所述计算机程序产品包括存储在非暂态计算机可读存储介质上的计算机程序，所述计算机程序包括程序指令，当所述程序指令被计算机执行时，使所述计算机执行上述实施例的数据信号的处理方法。
本公开还提供了一种电子设备。图6是本公开实施例提供的电子设备的结构框图。该电子设备可以包括：处理器(processor)61和存储器(memory)63，还可以包括通信接口(Communications Interface)62和总线64。其中，处理器61、通信接口62、存储器63可以通过总线64完成相互间的通信。通信接口62可以用于信息传输。处理器61可以调用存储器63中的逻辑指令，以执行上述实施例的数据信号的处理方法。
此外，上述的存储器63中的逻辑指令可以通过软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本公开的技术方案可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质可以是非暂态存储介质，包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质，也可 以是暂态存储介质。
工业实用性
根据本公开的数据信号的处理方法和装置，通过将时频域之间的快速变换算法中的每级蝶形运算分解为多级级联操作，细化蝶形运算，从而不必每级蝶形运算的输入均需除以输入的个数，以减少每级输入数据的比特丢失量，提高时频域之间的快速变换算法的计算精度，进而能够在使用时频域之间的快速变换算法处理通信系统数据时提高通信系统的性能。

Claims (15)

  1. 一种数据信号的处理方法，包括：
    根据输入信号采样后的序列值，确定时频域之间的快速变换算法中的每级蝶形运算的输入值；其中，每级蝶形运算的输入值的个数等于所述时频域之间的快速变换算法的基数；
    根据每级蝶形运算的输入值，将每级蝶形运算分解为多级级联运算；
    将每级蝶形运算经过多级级联运算后得到的输出值，作为下一级蝶形运算的输入值；以及
    根据最后一级蝶形运算的输出值，得到与采样后的所述输入信号对应的输出采样信号。
  2. 根据权利要求1所述的处理方法，其中，所述根据每级蝶形运算的输入值，将每级蝶形运算分解为多级级联运算的步骤包括：
    根据每级蝶形运算的输入值，将每级蝶形运算的每个输出运算分解为一满二叉树运算结构进行计算；
    其中，所述满二叉树运算结构的层数为log2m+1，所述满二叉树运算结构中的叶结点数为m，m为所述时频域之间的快速变换算法的基数。
  3. 根据权利要求2所述的处理方法，其中，所述根据每级蝶形运算的输入值，将每级蝶形运算的每个输出运算分解为一满二叉树运算结构进行计算的步骤包括：
    将每级蝶形运算的输入值依次映射为所述满二叉树运算结构中的叶结点的数值；
    从所述满二叉树运算结构中的叶结点开始，将所述满二叉树运算结构中的每一结点与其兄弟结点的数值的运算结果作为双亲结点的数值，直到得到所述满二叉树运算结构中的根结点的数值；
    将所述满二叉树运算结构中的根结点的数值作为每级蝶形运算对应的输出运算的数值。
  4. 根据权利要求3所述的处理方法，其中，所述将所述满二叉树运算结构中的每一结点与其兄弟结点的数值的运算结果作为双亲结点的数值的步骤包括：
    计算所述满二叉树运算结构中的每一结点与其兄弟结点的数值乘以各自旋转因子后的平均值；
    将计算得到的平均值作为双亲结点的数值。
  5. 根据权利要求1所述的处理方法，其中，所述确定时频域之间的快速变换算法中的每级蝶形运算的输入值的步骤之前，所述处理方法还包括：
    根据所述时频域之间的快速变换算法的点数和基数，确定所述时频域之间的快速变换算法中的蝶形运算的级数，其中，所述时频域之间的快速变换算法的点数为所述输入信号采样后的序列值的个数。
  6. 根据权利要求5所述的处理方法，其中，所述根据所述时频域之间的快速变换算法的点数和基数，确定所述时频域之间的快速变换算法中的蝶形运算的级数的步骤包括：
    根据预设公式：k＝logmN，确定蝶形运算的级数；
    其中，k表示所述时频域之间的快速变换算法中的蝶形运算的级数，m表示所述时频域之间的快速变换算法的基数，N表示所述时频域之间的快速变换算法的点数。
  7. 一种数据信号的处理装置，包括：
    第一确定模块，设置为根据输入信号采样后的序列值，确定时频域之间的快速变换算法的每级蝶形运算的输入值；其中，每级蝶形运算的输入值的个数 等于所述时频域之间的快速变换算法的基数；
    分解模块，设置为根据确定模块确定的每级蝶形运算的输入值，将每级蝶形运算分解为多级级联运算；
    级联模块，设置为将每级蝶形运算经过多级级联运算后得到的输出值，作为下一级蝶形运算的输入值；以及
    处理模块，设置为根据最后一级蝶形运算的输出值，得到与采样后的所述输入信号对应的输出采样信号。
  8. 根据权利要求7所述的处理装置，其中，所述分解模块包括：
    分解子模块，设置为根据每级蝶形运算的输入值，将每级蝶形运算的每个输出运算分解为一满二叉树运算结构进行计算；
    其中，所述满二叉树运算结构的层数为log2m+1，所述满二叉树运算结构中的叶结点数为m，m为所述时频域之间的快速变换算法的基数。
  9. 根据权利要求8所述的处理装置，其中，所述分解子模块包括：
    映射单元，设置为将每级蝶形运算的输入值依次映射为所述满二叉树运算结构中的叶结点的数值；
    运算单元，设置为从所述满二叉树运算结构中的叶结点开始，将所述满二叉树运算结构中的每一结点与其兄弟结点的数值的运算结果作为双亲结点的数值，直到得到所述满二叉树运算结构中的根结点的数值；
    级联单元，设置为将所述满二叉树运算结构中的根结点的数值作为每级蝶形运算对应的输出运算的数值。
  10. 根据权利要求9所述的处理装置，其中，所述运算单元包括：
    计算子单元，设置为计算所述满二叉树运算结构中的每一结点与其兄弟结点的数值乘以各自旋转因子后的平均值；
    处理子单元，设置为将计算得到的平均值作为双亲结点的数值。
  11. 根据权利要求7所述的处理装置，其中，所述处理装置还包括：
    第二确定模块，设置为根据所述时频域之间的快速变换算法的点数和基数，确定所述时频域之间的快速变换算法中的蝶形运算的级数，其中，所述时频域之间的快速变换算法的点数为所述输入信号采样后的序列值的个数。
  12. 根据权利要求11所述的处理装置，其中，所述第二确定模块具体用于：根据预设公式：k＝logmN，确定每级蝶形运算的级数；
    其中，k表示所述时频域之间的快速变换算法中的每级蝶形运算的级数，m表示所述时频域之间的快速变换算法的基数，N表示所述时频域之间的快速变换算法的点数。
  13. 一种非暂态存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行权利要求1-6任一项所述的数据信号的处理方法。
  14. 一种计算机程序产品，所述计算机程序产品包括存储在非暂态计算机可读存储介质上的计算机程序，所述计算机程序包括程序指令，当所述程序指令被计算机执行时，使所述计算机执行权利要求1-6任一项所述的数据信号的处理方法。
  15. 一种电子设备，包括至少一个处理器和与所述至少一个处理器通信连接的存储器，所述存储器用于存储可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行时，使所述至少一个处理器执行权利要求1-6任一项所述的数据信号的处理方法。
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