WO2017175645A1 - Dc/dc converter module and dc/dc converter circuit - Google Patents

Dc/dc converter module and dc/dc converter circuit Download PDF

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Publication number
WO2017175645A1
WO2017175645A1 PCT/JP2017/013006 JP2017013006W WO2017175645A1 WO 2017175645 A1 WO2017175645 A1 WO 2017175645A1 JP 2017013006 W JP2017013006 W JP 2017013006W WO 2017175645 A1 WO2017175645 A1 WO 2017175645A1
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Prior art keywords
coil
inductance value
dcdc converter
superimposed current
inductor
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PCT/JP2017/013006
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French (fr)
Japanese (ja)
Inventor
啓人 米森
浩和 矢▲崎▼
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株式会社村田製作所
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Priority to JP2018510557A priority Critical patent/JP6365805B2/en
Publication of WO2017175645A1 publication Critical patent/WO2017175645A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the present invention relates to a DCDC converter module and a DCDC converter circuit, and more particularly to a DCDC converter using a multilayer substrate with a built-in coil.
  • Patent Document 1 discloses a DCDC converter module in which a choke coil (inductor) is provided in a multilayer substrate and a switching IC (Integrated Circuit) chip is mounted on the multilayer substrate.
  • the conventional DCDC converter module adopts such a configuration to reduce the mounting area occupied on the mother board.
  • the DCDC converter module is required to be further reduced in height and size.
  • it is necessary to reduce the height and size of the inductor that occupies most of the area and volume of the module.
  • the inductance value of the choke coil in order to improve the characteristics of the DCDC converter (especially efficiency at heavy load), it is necessary to increase the inductance value of the choke coil (inductor) and suppress the DC resistance. If the number of turns of the inductor is increased and the line width is increased, the inductance value of the inductor can be increased and the direct current resistance can be suppressed. However, this increases the height and size of the DCDC converter module.
  • an object of the present invention is to provide a DCDC converter module and a DCDC converter circuit that are less likely to hinder a reduction in the height and size of the module and that have excellent characteristics.
  • a DCDC converter module includes a substrate, a switching IC element mounted on the substrate, and a choke coil connected to the switching IC element,
  • the choke coil includes a first coil formed by a coiled conductor pattern built in the substrate, and a chip-like second coil connected in series to the first coil and mounted on the substrate.
  • the first coil that is a substrate built-in coil is used as the main inductor
  • the second coil that is a surface-mounted chip inductor is used as the sub-inductor.
  • the choke coil is configured by connecting the first coil and the second coil in series.
  • the DC superimposition characteristics of the choke coil can be improved, and particularly when the DCDC converter is under heavy load, the ripple voltage can be suppressed.
  • unstable operation due to insufficient inductance value at the time of heavy load of the DCDC converter can be suppressed.
  • the second coil is a laminated chip coil in which a coil pattern is incorporated in an element body formed by laminating a plurality of magnetic layers, or a metal composite chip in which a coil conductor is incorporated in a compacted body of metal magnetic powder.
  • a coil or the like is suitable.
  • the second coil preferably has an inductance value and a DC resistance value smaller than the inductance value of the first coil.
  • the first coil has a first initial inductance value when the DC superimposed current is not applied, and the inductance value decreases at a first reduction rate with respect to the increase of the applied DC superimposed current.
  • the second coil has an inductance value when the DC superimposed current is not applied, a second initial inductance value, and a second reduction rate with respect to an increase of the applied DC superimposed current. It may have a second direct current superposition characteristic in which an inductance value decreases, the first initial inductance value may be greater than the second initial inductance value, and the first decrease rate may be greater than the second decrease rate.
  • the inductance value required for the choke coil is set to be the first coil having a large initial inductance value. Can be secured. Further, when the DCDC converter with a large DC superimposed current is heavily loaded, a decrease in the inductance value of the first coil can be compensated by the second coil having a small inductance value decrease rate. In this way, by combining the first coil and the second coil having different direct current superposition characteristics, an inductance value necessary for the choke coil can be secured in a wide range of the load of the DCDC converter.
  • the second coil may be constituted by a winding coil formed by winding a metal wire in a coil shape.
  • the substrate may be a magnetic substrate made of a ferrite sintered body
  • the first coil may be constituted by a metal sintered body incorporated in the ferrite sintered body.
  • the first coil is a coil with a built-in substrate using the ferrite sintered body as a core, and can have a large initial inductance value with a relatively small volume. Therefore, the DCDC converter module Useful for low profile and small size.
  • a DCDC converter circuit includes a choke coil including a first coil and a second coil connected in series to the first coil, and a DC superimposed current is applied to the first coil.
  • the second coil has a first DC superposition characteristic in which the inductance value decreases at a first decrease rate with respect to an increase in the applied DC superposition current.
  • the inductance value when the DC superimposed current is not applied is the second initial inductance value, and the second DC superimposed characteristic is such that the inductance value decreases at a second reduction rate with respect to the increase of the applied DC superimposed current.
  • the first initial inductance value is greater than the second initial inductance value, and the first decrease rate is greater than the second decrease rate.
  • the inductance value required for the choke coil is set to be the first coil having a large initial inductance value. Can be secured. Further, when the DCDC converter with a large DC superimposed current is heavily loaded, a decrease in the inductance value of the first coil can be compensated by the second coil having a small inductance value decrease rate. In this way, by combining the first coil and the second coil having different direct current superposition characteristics, an inductance value necessary for the choke coil can be secured in a wide range of the load of the DCDC converter.
  • the choke coil in a reference load state where a DC superimposed current of a reference current value is applied to the choke coil, the choke coil needs to have an inductance greater than a reference inductance value in order to generate a target output voltage.
  • the inductance value of the first coil is smaller than the reference inductance value in a state where the DC superimposed current of the reference current value is applied, and the inductance value of the second coil is a DC current of the reference current value. It may be larger than an inductance value obtained by subtracting the inductance value of the first coil from the reference inductance value in a state where the superimposed current is applied.
  • the first coil may have a core made of a ferrite magnetic material
  • the second coil may have a core made of a metal magnetic material
  • the first DC superposition characteristic of the first coil having both a large initial inductance value and a decrease rate, and the second DC of the second coil having both a small initial inductance value and a decrease rate can be realized using a material suitable for each characteristic.
  • the first coil which is a substrate built-in type coil
  • the second inductor which is a surface-mounted chip inductor having a good DC superposition characteristic and a small inductance value, as the sub-inductor.
  • the choke coil is configured by connecting the first coil and the second coil in series.
  • FIG. 1 is a perspective view showing an example of the appearance of a DCDC converter module according to an embodiment.
  • FIG. 2 is a cross-sectional view illustrating an example of the structure of the DCDC converter module according to the embodiment.
  • FIG. 3 is a circuit diagram illustrating an example of the DCDC converter circuit according to the embodiment.
  • FIG. 4 is a graph illustrating an example of the DC superposition characteristics of the first inductor and the second inductor according to the embodiment.
  • FIG. 5 is a graph illustrating an example of ripple characteristics of the DCDC converter according to the embodiment.
  • the DCDC converter module and the DCDC converter circuit according to the embodiment include a choke coil configured by connecting in series a first coil and a second coil having different direct current superposition characteristics.
  • the DC superimposition characteristic is a coil characteristic defined by an initial value of an inductance value when a DC superimposition current is not applied to the coil and a decrease rate of the inductance value with respect to an increase of the DC superimposition current.
  • the first coil has a first DC superimposition characteristic with both a large initial value and a decrease rate of the inductance value
  • the second coil has a second DC superimposition characteristic with a small initial value and a decrease rate of the inductance value. is doing.
  • the decrease in the inductance value of the first coil can be compensated by the second coil having a small decrease rate of the inductance value.
  • FIG. 1 is a perspective view showing an example of the appearance of a DCDC converter module according to an embodiment.
  • the DCDC converter module 1 is configured by mounting a switching IC chip 32, a chip capacitor 33, and a chip inductor 34, which are surface-mounted components, on a multilayer substrate 10 that incorporates a coil 31.
  • the multilayer substrate 10 is an example of a substrate
  • the switching IC chip 32 is an example of a switching element.
  • the coil 31 built in the multilayer substrate 10 is an example of a first coil
  • the chip inductor 34 surface-mounted on the multilayer substrate 10 is an example of a second coil.
  • the coil 31 and the chip inductor 34 are connected in series. When the height dimension of the chip inductor 34 is equal to or smaller than the height dimension of the chip capacitor 33, the height of the DCDC converter module is not increased.
  • FIG. 2 is a cross-sectional view showing an example of the structure of the DCDC converter module 1, and corresponds to a view of the II-II cross section of FIG. 1 viewed in the direction of the arrow.
  • the same type of components are shown in the same pattern, the reference numerals are omitted as appropriate, and strictly speaking, components in different cross sections may be shown in the same drawing and described.
  • the multilayer substrate 10 includes a core magnetic layer 11, a first nonmagnetic layer 12 and a second nonmagnetic layer formed on one main surface and the other main surface of the core magnetic layer 11, respectively. And a body layer 13.
  • the first nonmagnetic layer 12 and the second nonmagnetic layer 13 are formed as a surface layer on the one main surface and a surface layer on the other main surface of the multilayer substrate 10, respectively, and are exposed on the multilayer substrate 10.
  • a switching IC chip 32, a chip capacitor 33 (see FIG. 1), and a chip inductor 34 are mounted on the first nonmagnetic layer 12.
  • the second nonmagnetic layer 13 is formed by stacking nonmagnetic layers 131 and 132, and the core magnetic layer 11 is formed by stacking magnetic layers 111 to 119.
  • the magnetic layer 12 is formed by laminating nonmagnetic layers 121 and 122.
  • the multilayer substrate 10 is provided with various conductors for forming a DCDC converter circuit including the coil 31.
  • the conductors include surface electrodes 17 and 18, in-plane conductors 19, and interlayer conductors 20.
  • the surface electrode 17 is a conductor for mounting the DCDC converter module 1 on a mother board such as a printed wiring board.
  • the surface electrode 18 is a conductor for mounting the switching IC chip 32, the chip capacitor 33, and the chip inductor 34 on the multilayer substrate 10.
  • the in-plane conductor 19 is a conductor formed along the main surface of each magnetic layer or each non-magnetic layer.
  • the interlayer conductor 20 is a conductor formed so as to penetrate in the thickness direction of each magnetic layer or each nonmagnetic layer.
  • the in-plane conductor 19 and the interlayer conductor 20 may be referred to as a pattern and a via, respectively.
  • Each magnetic layer of the core magnetic layer 11 is made of magnetic ceramics having a larger magnetic permeability than the nonmagnetic layers of the first nonmagnetic layer 12 and the second nonmagnetic layer 13.
  • Each nonmagnetic material layer of the first nonmagnetic material layer 12 and the second nonmagnetic material layer 13 is made of low magnetic permeability or nonmagnetic ceramics.
  • magnetic ferrite ceramics are used as the magnetic ceramics.
  • ferrite containing iron oxide as a main component and containing at least one of zinc, nickel, and copper is used.
  • non-magnetic ferrite ceramics or alumina ceramics mainly composed of alumina are used as the low magnetic permeability or non-magnetic ceramics.
  • Each of the magnetic layers 112 to 119 is provided with a loop-shaped in-plane conductor 19 in plan view.
  • a coil 31 is configured by connecting in-plane conductors 19 adjacent to each other in the stacking direction with an interlayer conductor (not shown) penetrating the magnetic layer.
  • the in-plane conductor 19 for example, a metal or alloy mainly composed of copper is used.
  • the surface electrodes 17 and 18 may be plated with, for example, nickel, palladium, or gold.
  • the interlayer conductor 20 for example, a metal or alloy containing tin as a main component is used.
  • the multilayer substrate 10 is formed by stacking a plurality of non-magnetic or magnetic ceramic green sheets in which a conductor paste is disposed at a position where various conductors shown in FIG. It is produced by firing the blocks all at once.
  • the multilayer substrate 10 is a magnetic substrate made of a ferrite sintered body, and the coil 31 is composed of a metal sintered body incorporated in the ferrite sintered body.
  • LTCC ceramics (Low ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ Temperature Co-fired Ceramics) whose firing temperature is not higher than the melting point of silver may be used for the magnetic or nonmagnetic ferrite ceramics constituting each layer of the multilayer substrate 10.
  • the in-plane conductor 19 and the interlayer conductor 20 can be configured using silver.
  • the in-plane conductor 19 and the interlayer conductor 20 By forming the in-plane conductor 19 and the interlayer conductor 20 using silver having a low resistivity, a DCDC converter with low loss and excellent circuit characteristics such as power efficiency can be obtained.
  • the multilayer substrate 10 can be fired in an oxidizing atmosphere such as air.
  • FIG. 3 is a circuit diagram showing an example of a DCDC converter circuit using the DCDC converter module 1.
  • the DCDC converter circuit 100 shown in FIG. 3 includes a switching IC, a choke coil L0, and capacitors C1 and C2.
  • the switching IC, the choke coil L0, and the capacitor C1 are integrated into the DCDC converter module 1.
  • the switching IC is composed of a switching IC chip 32
  • the capacitor C1 is composed of a chip capacitor 33.
  • the choke coil L0 is formed by connecting a first inductor L1 and a second inductor L2 in series.
  • the first inductor L1 is composed of a substrate-embedded coil 31, and the second inductor L2 is composed of a chip inductor.
  • the capacitor C2 may be further integrated into the DCDC converter module 1.
  • the switching IC is an IC for controlling the switching operation of the DCDC converter circuit 100, and has a switching element such as a MOS type FET inside.
  • DCDC converter circuit 100 to the terminal V in the switching IC input voltage is applied from the terminal Lx of the switching IC, the output voltage via a choke coil L0 is output.
  • One end of the capacitor C1 is connected to the input voltage supply line between the terminal P in and the terminal V in, the other end of the capacitor C1 is connected to the ground terminal P GND.
  • One end of the capacitor C2 is connected to the output voltage power supply line between the terminal P out and the terminal P1, the other end of the capacitor C2 is connected to the ground terminal P GND.
  • Feedback terminal FB of the switching IC is connected to the output voltage power supply line between the choke coil L0 and the terminal P out, a ground terminal GND of the switching IC is connected to the ground terminal P GND, the enable terminal EN of the switching IC is It is connected to the enable terminal PEN .
  • DCDC converter circuit 100 an input voltage supplied to the terminal P in, switched at a predetermined frequency in the switching elements incorporated in the switching IC, by smoothed by the choke coil L0 and a capacitor C2, a desired Adjust to output voltage and output.
  • the switching IC performs, for example, PWM (Pulse Width Modulation) control that varies the pulse width while keeping the switching frequency constant based on the output voltage input to the feedback terminal FB, and stabilizes the output voltage at the set voltage.
  • PWM Pulse Width Modulation
  • the step-down DCDC converter circuit 100 using the switching IC chip 32 that performs the step-down operation is shown as an example.
  • the DCDC converter circuit is not limited to this example.
  • a step-up or step-up / step-down DCDC converter circuit may be configured using a DCDC converter module in which a switching IC that performs step-up or step-up / step-down operations is mounted.
  • FIG. 4 is a graph showing an example of the DC superposition characteristics of the first inductor L1 and the second inductor L2.
  • the inductance of the choke coil L0 is indicated by the sum of the inductance of the first inductor L1 and the inductance of the second inductor L2.
  • the reference current value Iref shown in FIG. 4 indicates the magnitude of the DC superimposed current applied to the choke coil L0 (that is, the first inductor L1 and the second inductor L2) in the reference load state.
  • the reference load state is a load state that is set under a rating of the DCDC converter circuit 100 or under a condition lower than the rating.
  • the DCDC converter circuit 100 is connected to a user application circuit by the application circuit.
  • the reference load state may be the maximum load state of the DCDC converter circuit 100 assumed in actual use.
  • the first inductor L1 has a first initial inductance value L1init when the DC superimposed current is not applied, and the inductance value decreases at a first reduction rate ⁇ L1 with respect to the increase of the applied DC superimposed current. 1 It has direct current superposition characteristics.
  • the inductance value of the second inductor L2 when the DC superimposed current is not applied is the second initial inductance value L2init, and the inductance value decreases at a second reduction rate ⁇ L2 with respect to the increase of the applied DC superimposed current. 2 Has direct current superposition characteristics.
  • the first initial inductance value L1init is larger than the second initial inductance value L2init (L1init> L2init), and the first decrease rate ⁇ L1 is larger than the second decrease rate ⁇ L2 ( ⁇ L1> ⁇ L2).
  • the first decrease rate ⁇ L1 and the second decrease rate ⁇ L2 are shown by the amount of decrease from the initial inductance value of the inductance value in the reference load state, but are not limited to this example.
  • an appropriate index that reflects the reduction rate of the inductance value with respect to the increase of the applied DC superimposed current such as the maximum value of the slope of the inductance value graph, can be used.
  • the first inductor L1 (the coil 31 of the DCDC converter module 1) may be constituted by a coil having a core made of a ferrite magnetic material.
  • a coil having a ferrite magnetic core has a large inductance reduction rate in the DC superposition characteristic, but has a large initial inductance value, and is therefore suitable for obtaining the first DC superposition characteristic.
  • the second inductor L2 (chip inductor 34 of the DCDC converter module 1) is a metal composite type coil having a core (magnetic core) made of a metal composite material (metal magnetic material). It may be configured.
  • the metal composite material is a material obtained by compacting metal magnetic particles containing a main component such as iron and subcomponents such as nickel and chromium and a binder resin.
  • the metal composite type coil means a coil whose core is made of a metal composite material, and specifically includes a coil in which a coil-shaped conductor is embedded in a metal composite material.
  • the metal composite type coil has a higher saturation magnetic flux density than a coil (first inductor L1) having a ferrite ceramic core, the direct current superimposition characteristic due to magnetic saturation is not easily deteriorated, and the second direct current superimposition characteristic is obtained.
  • the second inductor L2 may be formed of a wound type chip inductor formed by winding a metal wire in a coil shape.
  • a wound-type chip inductor has a small direct current resistance and is suitable for suppressing deterioration in efficiency of a DCDC converter.
  • FIG. 5 is a graph showing an example of the ripple characteristic of the DCDC converter.
  • FIG. 5 shows an example of a ripple voltage generated in the output voltage of the DCDC converter circuit 100 in accordance with the DC superimposed current applied to the choke coil L0.
  • an upper limit for proper operation of the DCDC converter is defined for the ripple voltage under heavy load.
  • the upper limit value Rlim of the ripple voltage is defined in the above-described reference load state (a state in which the DC superimposed current having the reference current value Iref is applied to the choke coil L0).
  • the choke coil L0 In the reference load state, the choke coil L0 needs to have an inductance value equal to or greater than a certain reference value in order to keep the ripple voltage below the upper limit value Rlim.
  • a reference value is represented by a reference inductance value Lref as an example. That is, FIG. 4 illustrates an example in which the choke coil L0 requires an inductance greater than the reference inductance value Lref in order for the DCDC converter circuit 100 to properly generate the target output voltage in the reference load state. Yes.
  • the target output voltage is a voltage in which the ripple voltage is suppressed to the upper limit value Rlim or less.
  • the inductance value L1ref of the first inductor L1 is smaller than the reference inductance value Lref (L1ref ⁇ Lref), and the inductance value L2ref of the second inductor L2 is calculated from the reference inductance value Lref. It may be larger than the value obtained by subtracting the inductance value L1ref of the first inductor L1 (L2ref> Lref ⁇ L1ref).
  • the choke coil L0 can have an inductance value L0ref that is greater than or equal to the reference inductance value Lref.
  • the first inductor L1 whose inductance value in the reference load state is less than the reference inductance value Lref necessary for the choke coil L0 may be intentionally used, and the shortage may be compensated by the second inductor L2.
  • the first inductor L1 has a large decrease rate ⁇ L1 of the inductance value, so that the first initial inductance value L1init is considerably increased. It needs to be bigger. For this reason, the shape of the first inductor L1 is increased, and there is a concern that the module is reduced in size and height.
  • the second inductor L2 in which the second initial inductance value L2init and the inductance value decrease rate ⁇ L2 are smaller than the first inductor L1 can be formed smaller than the first inductor L1 in its shape. Therefore, a DCDC converter circuit is employed in which a choke coil L0 is configured by connecting a first inductor L1 and a second inductor L2 having different DC superimposing characteristics in series. As a result, it is possible to configure a DCDC converter module that is unlikely to hinder a reduction in the height and size of the module and that has excellent characteristics.
  • the first coil which is a substrate built-in type coil
  • the DC superposition characteristics are good as the sub-inductor
  • the inductance value is small.
  • a second coil which is a surface mount type chip inductor is used. And the said 1st coil and the said 2nd coil are connected in series, the said choke coil is comprised, and the direct current superimposition characteristic of the said choke coil is improved.
  • the present invention can be widely used in electronic devices such as portable information terminals and digital cameras as a ceramic multilayer substrate with a built-in coil and an ultra-small DCDC converter using the ceramic multilayer substrate.
  • DCDC converter module 10 Multilayer substrate (substrate) 11 Core magnetic layer 111 to 119 Magnetic layer 12 First nonmagnetic layer 121, 122 Nonmagnetic layer 13 Second nonmagnetic layer 131, 132 Nonmagnetic layer 17, 18 Surface electrode 19 In-plane conductor 20 Interlayer Conductor 31 coil (first coil) 32 Switching IC chip (Switching IC element) 33 Chip capacitor 34 Chip inductor (second coil) 100 DCDC converter circuit

Abstract

This DC/DC converter module (1) is provided with: a multilayer substrate (10); a switching IC chip (32) that is mounted on the multilayer substrate (10); and a choke coil that is connected to the switching IC chip (32). The choke coil is configured of: a first coil (31) that is formed of a coil-like conductor pattern built in the multilayer substrate (10); and a chip-like second coil (34) that is connected in series to the first coil (31) and is mounted on the multilayer substrate (10).

Description

ＤＣＤＣコンバータモジュールおよびＤＣＤＣコンバータ回路DCDC converter module and DCDC converter circuit
　本発明は、ＤＣＤＣコンバータモジュールおよびＤＣＤＣコンバータ回路に関し、特には、コイルを内蔵した多層基板を用いたＤＣＤＣコンバータに関する。 The present invention relates to a DCDC converter module and a DCDC converter circuit, and more particularly to a DCDC converter using a multilayer substrate with a built-in coil.
　従来、コイルを内蔵した多層基板を用いたＤＣＤＣコンバータが周知である。例えば、特許文献１は、チョークコイル（インダクタ）を多層基板内に設け、スイッチングＩＣ（Integrated Circuit）チップを当該多層基板に実装してなるＤＣＤＣコンバータモジュールを開示している。従来のＤＣＤＣコンバータモジュールは、このような構成を採用することで、マザー基板に占める実装面積を小さくしている。 Conventionally, a DCDC converter using a multilayer substrate with a built-in coil is well known. For example, Patent Document 1 discloses a DCDC converter module in which a choke coil (inductor) is provided in a multilayer substrate and a switching IC (Integrated Circuit) chip is mounted on the multilayer substrate. The conventional DCDC converter module adopts such a configuration to reduce the mounting area occupied on the mother board.
特許第４３２５７４７号公報Japanese Patent No. 4325747
　しかしながら、昨今では、スマートフォンに代表される携帯端末の小型・薄型化により、ＤＣＤＣコンバータモジュールにも、さらなる低背化・小型化が求められている。ＤＣＤＣコンバータモジュールの低背化・小型化を実現させるには、モジュールの面積・体積の大部分を占めるインダクタの低背化・小型化が必要である。 However, in recent years, with the reduction in size and thickness of mobile terminals typified by smartphones, the DCDC converter module is required to be further reduced in height and size. In order to reduce the height and size of the DCDC converter module, it is necessary to reduce the height and size of the inductor that occupies most of the area and volume of the module.
　一方で、ＤＣＤＣコンバータの特性（特に重負荷時の効率）を向上させるためには、チョークコイル（インダクタ）のインダクタンス値を大きくするとともに直流抵抗を抑える必要がある。インダクタの巻き数を増やし、線幅を太くすれば、インダクタのインダクタンス値を大きくし、直流抵抗を抑えることができるが、ＤＣＤＣコンバータモジュールの高背化、大型化を招いてしまう。 On the other hand, in order to improve the characteristics of the DCDC converter (especially efficiency at heavy load), it is necessary to increase the inductance value of the choke coil (inductor) and suppress the DC resistance. If the number of turns of the inductor is increased and the line width is increased, the inductance value of the inductor can be increased and the direct current resistance can be suppressed. However, this increases the height and size of the DCDC converter module.
　そこで、本発明は、モジュールの低背化および小型化を阻害しにくく、かつ特性に優れたＤＣＤＣコンバータモジュールおよびＤＣＤＣコンバータ回路を提供することを目的とする。 Therefore, an object of the present invention is to provide a DCDC converter module and a DCDC converter circuit that are less likely to hinder a reduction in the height and size of the module and that have excellent characteristics.
　上記目的を達成するために、本発明の一態様に係るＤＣＤＣコンバータモジュールは、基板と、前記基板に実装されたスイッチングＩＣ素子と、前記スイッチングＩＣ素子に接続されたチョークコイルと、を備え、前記チョークコイルは、前記基板に内蔵されたコイル状導体パターンによって形成された第１コイルと、前記第１コイルに直列接続され、前記基板に実装されたチップ状の第２コイルと、で構成されている。 To achieve the above object, a DCDC converter module according to an aspect of the present invention includes a substrate, a switching IC element mounted on the substrate, and a choke coil connected to the switching IC element, The choke coil includes a first coil formed by a coiled conductor pattern built in the substrate, and a chip-like second coil connected in series to the first coil and mounted on the substrate. Yes.
　この構成によれば、メインインダクタとして基板内蔵型コイルである前記第１コイルを利用し、サブインダクタとして、表面実装型のチップインダクタである前記第２コイルを利用する。そして、前記第１コイルと前記第２コイルとを直列に接続して前記チョークコイルを構成する。 According to this configuration, the first coil that is a substrate built-in coil is used as the main inductor, and the second coil that is a surface-mounted chip inductor is used as the sub-inductor. The choke coil is configured by connecting the first coil and the second coil in series.
　これにより、モジュールの低背化および小型化を維持しつつ、広い負荷範囲での効率を改善することができる。具体的には、チョークコイルの直流重畳特性を向上させることができ、特にＤＣＤＣコンバータの重負荷時において、リプル電圧を抑えることができる。また、ＤＣＤＣコンバータの重負荷時のインダクタンス値不足に起因する不安定動作を抑えることができる。 This makes it possible to improve the efficiency over a wide load range while maintaining the low profile and small size of the module. Specifically, the DC superimposition characteristics of the choke coil can be improved, and particularly when the DCDC converter is under heavy load, the ripple voltage can be suppressed. In addition, unstable operation due to insufficient inductance value at the time of heavy load of the DCDC converter can be suppressed.
　なお、前記第２コイルは、複数の磁性体層を積層してなる素体にコイルパターンを内蔵した積層型チップコイルや、金属磁性粉の圧粉成型体にコイル導体を内蔵したメタルコンポジット型チップコイル等が好適である。この第２コイルは、第１コイルのインダクタンス値よりも小さなインダクタンス値、直流抵抗値を持ったものであることが好ましい。 The second coil is a laminated chip coil in which a coil pattern is incorporated in an element body formed by laminating a plurality of magnetic layers, or a metal composite chip in which a coil conductor is incorporated in a compacted body of metal magnetic powder. A coil or the like is suitable. The second coil preferably has an inductance value and a DC resistance value smaller than the inductance value of the first coil.
　また、前記第１コイルは、直流重畳電流が印加されないときのインダクタンス値が第１初期インダクタンス値であり、かつ印加される直流重畳電流の増大に対して第１低下率でインダクタンス値が低下する第１直流重畳特性を有し、前記第２コイルは、直流重畳電流が印加されないときのインダクタンス値が第２初期インダクタンス値であり、かつ印加される直流重畳電流の増大に対して第２低下率でインダクタンス値が低下する第２直流重畳特性を有し、前記第１初期インダクタンス値は前記第２初期インダクタンス値より大きく、かつ前記第１低下率は前記第２低下率より大きくてもよい。 The first coil has a first initial inductance value when the DC superimposed current is not applied, and the inductance value decreases at a first reduction rate with respect to the increase of the applied DC superimposed current. The second coil has an inductance value when the DC superimposed current is not applied, a second initial inductance value, and a second reduction rate with respect to an increase of the applied DC superimposed current. It may have a second direct current superposition characteristic in which an inductance value decreases, the first initial inductance value may be greater than the second initial inductance value, and the first decrease rate may be greater than the second decrease rate.
　この構成によれば、前記第１コイルおよび前記第２コイルに印加される直流重畳電流が小さいＤＣＤＣコンバータの軽負荷時には、前記チョークコイルに必要なインダクタンス値を、初期インダクタンス値が大きい前記第１コイルによって確保できる。また、直流重畳電流が大きいＤＣＤＣコンバータの重負荷時には、前記第１コイルのインダクタンス値の低下を、インダクタンス値の低下率が小さい前記第２コイルによって補うことができる。このように、直流重畳特性が互いに異なる前記第１コイルと前記第２コイルとを組み合わせることによって、ＤＣＤＣコンバータの負荷の広い範囲で、前記チョークコイルに必要なインダクタンス値を確保できる。 According to this configuration, when the DCDC converter with a small DC superimposed current applied to the first coil and the second coil is lightly loaded, the inductance value required for the choke coil is set to be the first coil having a large initial inductance value. Can be secured. Further, when the DCDC converter with a large DC superimposed current is heavily loaded, a decrease in the inductance value of the first coil can be compensated by the second coil having a small inductance value decrease rate. In this way, by combining the first coil and the second coil having different direct current superposition characteristics, an inductance value necessary for the choke coil can be secured in a wide range of the load of the DCDC converter.
　また、前記第２コイルは、金属線をコイル状に巻回してなる巻線コイルによって構成されていてもよい。 Further, the second coil may be constituted by a winding coil formed by winding a metal wire in a coil shape.
　この構成によれば、一般的に直流抵抗が小さい巻き線型のチップインダクタを前記第２コイルに用いることで、ＤＣＤＣコンバータの効率の劣化を抑制できる。 According to this configuration, it is possible to suppress deterioration of the efficiency of the DCDC converter by using a wound-type chip inductor having a generally low DC resistance for the second coil.
　また、前記基板はフェライト焼結体からなる磁性体基板であって、前記第１コイルはフェライト焼結体に内蔵された金属焼結体によって構成されていてもよい。 Further, the substrate may be a magnetic substrate made of a ferrite sintered body, and the first coil may be constituted by a metal sintered body incorporated in the ferrite sintered body.
　この構成によれば、前記第１コイルは、前記フェライト焼結体をコアに用いた基板内蔵型のコイルであり、比較的小さな体積で大きな初期インダクタンス値を持つことができるので、前記ＤＣＤＣコンバータモジュールの低背化および小型化に役立つ。 According to this configuration, the first coil is a coil with a built-in substrate using the ferrite sintered body as a core, and can have a large initial inductance value with a relatively small volume. Therefore, the DCDC converter module Useful for low profile and small size.
　本発明の一態様に係るＤＣＤＣコンバータ回路は、第１コイルと、前記第１コイルに直列接続された第２コイルとで構成されたチョークコイルを備え、前記第１コイルは、直流重畳電流が印加されないときのインダクタンス値が第１初期インダクタンス値であり、かつ印加される直流重畳電流の増大に対して第１低下率でインダクタンス値が低下する第１直流重畳特性を有し、前記第２コイルは、直流重畳電流が印加されないときのインダクタンス値が第２初期インダクタンス値であり、かつ印加される直流重畳電流の増大に対して第２低下率でインダクタンス値が低下する第２直流重畳特性を有し、前記第１初期インダクタンス値は前記第２初期インダクタンス値より大きく、かつ前記第１低下率は前記第２低下率より大きい。 A DCDC converter circuit according to an aspect of the present invention includes a choke coil including a first coil and a second coil connected in series to the first coil, and a DC superimposed current is applied to the first coil. And the second coil has a first DC superposition characteristic in which the inductance value decreases at a first decrease rate with respect to an increase in the applied DC superposition current. In addition, the inductance value when the DC superimposed current is not applied is the second initial inductance value, and the second DC superimposed characteristic is such that the inductance value decreases at a second reduction rate with respect to the increase of the applied DC superimposed current. The first initial inductance value is greater than the second initial inductance value, and the first decrease rate is greater than the second decrease rate.
　この構成によれば、前記第１コイルおよび前記第２コイルに印加される直流重畳電流が小さいＤＣＤＣコンバータの軽負荷時には、前記チョークコイルに必要なインダクタンス値を、初期インダクタンス値が大きい前記第１コイルによって確保できる。また、直流重畳電流が大きいＤＣＤＣコンバータの重負荷時には、前記第１コイルのインダクタンス値の低下を、インダクタンス値の低下率が小さい前記第２コイルによって補うことができる。このように、直流重畳特性が互いに異なる前記第１コイルと前記第２コイルとを組み合わせることによって、ＤＣＤＣコンバータの負荷の広い範囲で、前記チョークコイルに必要なインダクタンス値を確保できる。 According to this configuration, when the DCDC converter with a small DC superimposed current applied to the first coil and the second coil is lightly loaded, the inductance value required for the choke coil is set to be the first coil having a large initial inductance value. Can be secured. Further, when the DCDC converter with a large DC superimposed current is heavily loaded, a decrease in the inductance value of the first coil can be compensated by the second coil having a small inductance value decrease rate. In this way, by combining the first coil and the second coil having different direct current superposition characteristics, an inductance value necessary for the choke coil can be secured in a wide range of the load of the DCDC converter.
　これにより、ＤＣＤＣコンバータの重負荷時において、リプル電圧を抑えることができる。また、ＤＣＤＣコンバータの重負荷時のインダクタンス値不足に起因する不安定動作を抑えることができる。また、前記第２コイルにチップインダクタを用いて、前記スイッチングＩＣ素子とともに前記基板に表面実装すれば、モジュールの低背化および小型化を阻害しにくく、かつ特性に優れたＤＣＤＣコンバータを得ることができる。 This makes it possible to suppress the ripple voltage when the DCDC converter is heavily loaded. In addition, unstable operation due to insufficient inductance value at the time of heavy load of the DCDC converter can be suppressed. In addition, if a chip inductor is used for the second coil and is surface-mounted on the substrate together with the switching IC element, it is possible to obtain a DCDC converter which is less likely to hinder a reduction in the height and size of the module and which has excellent characteristics. it can.
　また、前記チョークコイルに基準電流値の直流重畳電流が印加される基準負荷状態において、前記ＤＣＤＣコンバータ回路が目的の出力電圧を生成するために、前記チョークコイルに基準インダクタンス値以上のインダクタンスが必要となる場合に、前記第１コイルのインダクタンス値は、前記基準電流値の直流重畳電流が印加された状態で、前記基準インダクタンス値より小さく、前記第２コイルのインダクタンス値は、前記基準電流値の直流重畳電流が印加された状態で、前記基準インダクタンス値から前記第１コイルのインダクタンス値を減じたインダクタンス値より大きくてもよい。 In addition, in a reference load state where a DC superimposed current of a reference current value is applied to the choke coil, the choke coil needs to have an inductance greater than a reference inductance value in order to generate a target output voltage. In this case, the inductance value of the first coil is smaller than the reference inductance value in a state where the DC superimposed current of the reference current value is applied, and the inductance value of the second coil is a DC current of the reference current value. It may be larger than an inductance value obtained by subtracting the inductance value of the first coil from the reference inductance value in a state where the superimposed current is applied.
　この構成によれば、前記基準負荷状態において、前記第１コイルのインダクタンス値が前記チョークコイルに必要なインダクタンス値に満たない場合に、不足分を前記第２コイルのインダクタンス値で確実に補うことができる。 According to this configuration, when the inductance value of the first coil is less than the inductance value necessary for the choke coil in the reference load state, the shortage can be reliably compensated with the inductance value of the second coil. it can.
　また、前記第１コイルは、フェライト磁性体で構成されたコアを有し、前記第２コイルは、金属磁性体で構成されたコアを有していてもよい。 Further, the first coil may have a core made of a ferrite magnetic material, and the second coil may have a core made of a metal magnetic material.
　この構成によれば、初期インダクタンス値と低下率とがいずれも大きい前記第１コイルの前記第１直流重畳特性と、初期インダクタンス値と低下率とがいずれも小さい前記第２コイルの前記第２直流重畳特性とを、それぞれの特性に適した材料を用いて実現できる。 According to this configuration, the first DC superposition characteristic of the first coil having both a large initial inductance value and a decrease rate, and the second DC of the second coil having both a small initial inductance value and a decrease rate. Superimposition characteristics can be realized using a material suitable for each characteristic.
　本発明に係るＤＣＤＣコンバータモジュールによれば、メインインダクタとして基板内蔵型コイルである第１コイルを利用し、サブインダクタとして直流重畳特性がよくかつインダクタンス値の小さな表面実装型のチップインダクタである第２コイルを利用する。そして、前記第１コイルと前記第２コイルとを直列に接続して前記チョークコイルを構成する。 According to the DCDC converter module of the present invention, the first coil, which is a substrate built-in type coil, is used as the main inductor, and the second inductor, which is a surface-mounted chip inductor having a good DC superposition characteristic and a small inductance value, as the sub-inductor. Use a coil. The choke coil is configured by connecting the first coil and the second coil in series.
　これにより、ＤＣＤＣコンバータの重負荷時において、リプル電圧を抑えることができる。また、ＤＣＤＣコンバータの重負荷時のインダクタンス値不足に起因する不安定動作を抑えることができる。また、前記第２コイルを、前記スイッチングＩＣ素子とともに前記基板に表面実装するので、モジュールの低背化および小型化を阻害しにくい。 This makes it possible to suppress the ripple voltage when the DCDC converter is heavily loaded. In addition, unstable operation due to insufficient inductance value at the time of heavy load of the DCDC converter can be suppressed. Further, since the second coil is surface-mounted on the substrate together with the switching IC element, it is difficult to hinder the reduction in the height and size of the module.
図１は、実施の形態に係るＤＣＤＣコンバータモジュールの外観の一例を示す斜視図である。FIG. 1 is a perspective view showing an example of the appearance of a DCDC converter module according to an embodiment. 図２は、実施の形態に係るＤＣＤＣコンバータモジュールの構造の一例を示す断面図である。FIG. 2 is a cross-sectional view illustrating an example of the structure of the DCDC converter module according to the embodiment. 図３は、実施の形態に係るＤＣＤＣコンバータ回路の一例を示す回路図である。FIG. 3 is a circuit diagram illustrating an example of the DCDC converter circuit according to the embodiment. 図４は、実施の形態に係る第１インダクタおよび第２インダクタの直流重畳特性の一例を示すグラフである。FIG. 4 is a graph illustrating an example of the DC superposition characteristics of the first inductor and the second inductor according to the embodiment. 図５は、実施の形態に係るＤＣＤＣコンバータのリプル特性の一例を示すグラフである。FIG. 5 is a graph illustrating an example of ripple characteristics of the DCDC converter according to the embodiment.
　以下、本発明の実施の形態について、図面を用いて詳細に説明する。なお、以下で説明する実施の形態は、いずれも包括的又は具体的な例を示すものである。以下の実施の形態で示される数値、形状、材料、構成要素、構成要素の配置および接続形態などは、一例であり、本発明を限定する主旨ではない。以下の実施の形態における構成要素のうち、独立請求項に記載されていない構成要素については、任意の構成要素として説明される。また、図面に示される構成要素の大きさ又は大きさの比は、必ずしも厳密ではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that each of the embodiments described below shows a comprehensive or specific example. Numerical values, shapes, materials, constituent elements, arrangement of constituent elements, connection forms, and the like shown in the following embodiments are merely examples, and are not intended to limit the present invention. Among the constituent elements in the following embodiments, constituent elements not described in the independent claims are described as optional constituent elements. In addition, the size or ratio of components shown in the drawings is not necessarily strict.
　（実施の形態）
　実施の形態に係るＤＣＤＣコンバータモジュールおよびＤＣＤＣコンバータ回路は、互いに直流重畳特性が異なる第１コイルと第２コイルとを直列接続して構成されるチョークコイルを備えるものである。直流重畳特性とは、コイルに直流重畳電流が印加されないときのインダクタンス値の初期値と、直流重畳電流の増大に対するインダクタンス値の低下率と、で規定されるコイルの特性である。前記第１コイルはインダクタンス値の初期値および低下率が何れも大きい第１直流重畳特性を有し、前記第２コイルはインダクタンス値の初期値および低下率が何れも小さい第２直流重畳特性を有している。 (Embodiment)
The DCDC converter module and the DCDC converter circuit according to the embodiment include a choke coil configured by connecting in series a first coil and a second coil having different direct current superposition characteristics. The DC superimposition characteristic is a coil characteristic defined by an initial value of an inductance value when a DC superimposition current is not applied to the coil and a decrease rate of the inductance value with respect to an increase of the DC superimposition current. The first coil has a first DC superimposition characteristic with both a large initial value and a decrease rate of the inductance value, and the second coil has a second DC superimposition characteristic with a small initial value and a decrease rate of the inductance value. is doing.
　これにより、直流重畳電流が大きくなるＤＣＤＣコンバータの重負荷状態において、前記第１コイルのインダクタンス値の低下を、インダクタンス値の低下率が小さい前記第２コイルによって補うことができる。 Thereby, in the heavy load state of the DCDC converter in which the DC superimposed current becomes large, the decrease in the inductance value of the first coil can be compensated by the second coil having a small decrease rate of the inductance value.
　以下では、実施の形態に係るＤＣＤＣコンバータモジュールおよびＤＣＤＣコンバータ回路について、具体例を参照しながら詳細に説明する。 Hereinafter, the DCDC converter module and the DCDC converter circuit according to the embodiment will be described in detail with reference to specific examples.
　図１は、実施の形態に係るＤＣＤＣコンバータモジュールの外観の一例を示す斜視図である。図１に示されるように、ＤＣＤＣコンバータモジュール１は、コイル３１を内蔵する多層基板１０に、表面実装部品であるスイッチングＩＣチップ３２、チップコンデンサ３３、およびチップインダクタ３４を実装して構成されている。ここで、多層基板１０が基板の一例であり、スイッチングＩＣチップ３２がスイッチング素子の一例である。また、多層基板１０に内蔵されたコイル３１が第１コイルの一例であり、多層基板１０に表面実装されたチップインダクタ３４が第２コイルの一例である。コイル３１とチップインダクタ３４とは、直列接続されている。チップインダクタ３４の高さ寸法がチップコンデンサ３３の高さ寸法と同等もしくはそれより小さければ、ＤＣＤＣコンバータモジュールとしての高背化を招くことはない。 FIG. 1 is a perspective view showing an example of the appearance of a DCDC converter module according to an embodiment. As shown in FIG. 1, the DCDC converter module 1 is configured by mounting a switching IC chip 32, a chip capacitor 33, and a chip inductor 34, which are surface-mounted components, on a multilayer substrate 10 that incorporates a coil 31. . Here, the multilayer substrate 10 is an example of a substrate, and the switching IC chip 32 is an example of a switching element. The coil 31 built in the multilayer substrate 10 is an example of a first coil, and the chip inductor 34 surface-mounted on the multilayer substrate 10 is an example of a second coil. The coil 31 and the chip inductor 34 are connected in series. When the height dimension of the chip inductor 34 is equal to or smaller than the height dimension of the chip capacitor 33, the height of the DCDC converter module is not increased.
　図２は、ＤＣＤＣコンバータモジュール１の構造の一例を示す断面図であり、図１のＩＩ－ＩＩ断面を矢印の方向に見た図に対応する。以下では、簡明のため、同種の構成要素を同じ模様で示して符号を適宜省略し、また、厳密には別断面にある構成要素を同一図面内に示して説明することがある。 FIG. 2 is a cross-sectional view showing an example of the structure of the DCDC converter module 1, and corresponds to a view of the II-II cross section of FIG. 1 viewed in the direction of the arrow. In the following, for the sake of simplicity, the same type of components are shown in the same pattern, the reference numerals are omitted as appropriate, and strictly speaking, components in different cross sections may be shown in the same drawing and described.
　図２に示されるように、多層基板１０は、コア磁性体層１１と、コア磁性体層１１の一方主面および他方主面にそれぞれ形成された第１非磁性体層１２および第２非磁性体層１３と、を有している。第１非磁性体層１２および第２非磁性体層１３は、多層基板１０の前記一方主面の表層および前記他方主面の表層としてそれぞれ形成され、多層基板１０において露出している。第１非磁性体層１２には、スイッチングＩＣチップ３２、チップコンデンサ３３（図１を参照）、およびチップインダクタ３４が実装されている。 As shown in FIG. 2, the multilayer substrate 10 includes a core magnetic layer 11, a first nonmagnetic layer 12 and a second nonmagnetic layer formed on one main surface and the other main surface of the core magnetic layer 11, respectively. And a body layer 13. The first nonmagnetic layer 12 and the second nonmagnetic layer 13 are formed as a surface layer on the one main surface and a surface layer on the other main surface of the multilayer substrate 10, respectively, and are exposed on the multilayer substrate 10. A switching IC chip 32, a chip capacitor 33 (see FIG. 1), and a chip inductor 34 are mounted on the first nonmagnetic layer 12.
　図２の例では、第２非磁性体層１３は、非磁性体層１３１、１３２を積層してなり、コア磁性体層１１は、磁性体層１１１～１１９を積層してなり、第１非磁性体層１２は、非磁性体層１２１、１２２を積層してなる。 In the example of FIG. 2, the second nonmagnetic layer 13 is formed by stacking nonmagnetic layers 131 and 132, and the core magnetic layer 11 is formed by stacking magnetic layers 111 to 119. The magnetic layer 12 is formed by laminating nonmagnetic layers 121 and 122.
　多層基板１０には、コイル３１を含むＤＣＤＣコンバータ回路を形成するための各種の導体が設けられる。前記導体には、表面電極１７、１８、面内導体１９、および層間導体２０が含まれる。表面電極１７は、ＤＣＤＣコンバータモジュール１をプリント配線基板等のマザー基板に実装するための導体である。表面電極１８は、スイッチングＩＣチップ３２、チップコンデンサ３３、およびチップインダクタ３４を多層基板１０に実装するための導体である。面内導体１９は、各磁性体層や各非磁性体層の主面に沿って形成された導体である。層間導体２０は、各磁性体層や各非磁性体層の厚み方向に貫通して形成された導体である。面内導体１９および層間導体２０は、それぞれパターンおよびビアと称されることがある。 The multilayer substrate 10 is provided with various conductors for forming a DCDC converter circuit including the coil 31. The conductors include surface electrodes 17 and 18, in-plane conductors 19, and interlayer conductors 20. The surface electrode 17 is a conductor for mounting the DCDC converter module 1 on a mother board such as a printed wiring board. The surface electrode 18 is a conductor for mounting the switching IC chip 32, the chip capacitor 33, and the chip inductor 34 on the multilayer substrate 10. The in-plane conductor 19 is a conductor formed along the main surface of each magnetic layer or each non-magnetic layer. The interlayer conductor 20 is a conductor formed so as to penetrate in the thickness direction of each magnetic layer or each nonmagnetic layer. The in-plane conductor 19 and the interlayer conductor 20 may be referred to as a pattern and a via, respectively.
　コア磁性体層１１の各磁性体層は、第１非磁性体層１２および第２非磁性体層１３の各非磁性体層と比べて透磁率が大きい磁性セラミックスで構成される。第１非磁性体層１２および第２非磁性体層１３の各非磁性体層は、低透磁率または非磁性のセラミックスで構成される。 Each magnetic layer of the core magnetic layer 11 is made of magnetic ceramics having a larger magnetic permeability than the nonmagnetic layers of the first nonmagnetic layer 12 and the second nonmagnetic layer 13. Each nonmagnetic material layer of the first nonmagnetic material layer 12 and the second nonmagnetic material layer 13 is made of low magnetic permeability or nonmagnetic ceramics.
　磁性セラミックスには、例えば、磁性フェライトセラミックスが用いられる。具体的には、酸化鉄を主成分とし、亜鉛、ニッケルおよび銅のうち少なくとも１つ以上を含むフェライトが用いられる。また、低透磁率または非磁性のセラミックスには、例えば、非磁性フェライトセラミックスやアルミナを主成分とするアルミナセラミックスが用いられる。 For example, magnetic ferrite ceramics are used as the magnetic ceramics. Specifically, ferrite containing iron oxide as a main component and containing at least one of zinc, nickel, and copper is used. For example, non-magnetic ferrite ceramics or alumina ceramics mainly composed of alumina are used as the low magnetic permeability or non-magnetic ceramics.
　磁性体層１１２～１１９の各々には平面視でループ状の面内導体１９が配置されている。積層方向に隣接する面内導体１９同士を、磁性体層を貫通する層間導体（図示せず）で接続して、コイル３１が構成されている。 Each of the magnetic layers 112 to 119 is provided with a loop-shaped in-plane conductor 19 in plan view. A coil 31 is configured by connecting in-plane conductors 19 adjacent to each other in the stacking direction with an interlayer conductor (not shown) penetrating the magnetic layer.
　面内導体１９には、例えば、銅を主成分とする金属又は合金が用いられる。表面電極１７、１８には、例えば、ニッケル、パラジウム、又は金によるめっきが施されていてもよい。層間導体２０には、例えば、錫を主成分とする金属又は合金が用いられる。 For the in-plane conductor 19, for example, a metal or alloy mainly composed of copper is used. The surface electrodes 17 and 18 may be plated with, for example, nickel, palladium, or gold. For the interlayer conductor 20, for example, a metal or alloy containing tin as a main component is used.
　多層基板１０は、例えば、図２に示される各種の導体が形成される予定位置に導体ペーストを配置した非磁性または磁性の複数のセラミックグリーンシートを重ねて未焼成ブロックに一体化し、当該未焼成ブロックを一括して焼成することにより作製される。この場合、多層基板１０はフェライト焼結体からなる磁性体基板であって、コイル３１はフェライト焼結体に内蔵された金属焼結体によって構成されている。 For example, the multilayer substrate 10 is formed by stacking a plurality of non-magnetic or magnetic ceramic green sheets in which a conductor paste is disposed at a position where various conductors shown in FIG. It is produced by firing the blocks all at once. In this case, the multilayer substrate 10 is a magnetic substrate made of a ferrite sintered body, and the coil 31 is composed of a metal sintered body incorporated in the ferrite sintered body.
　多層基板１０の各層を構成する磁性または非磁性のフェライトセラミックスに、焼成温度が銀の融点以下であるＬＴＣＣセラミックス（Low Temperature Co-fired Ceramics）を用いてもよい。これにより、面内導体１９および層間導体２０を、銀を用いて構成することが可能になる。 LTCC ceramics (Low セ ラ ミ ッ ク ス Temperature Co-fired Ceramics) whose firing temperature is not higher than the melting point of silver may be used for the magnetic or nonmagnetic ferrite ceramics constituting each layer of the multilayer substrate 10. Thereby, the in-plane conductor 19 and the interlayer conductor 20 can be configured using silver.
　抵抗率の低い銀を用いて面内導体１９および層間導体２０を構成することで、損失が少なく電力効率などの回路特性に優れたＤＣＤＣコンバータが得られる。特に、前記導体に銀を用いることで、例えば大気などの酸化性雰囲気下で多層基板１０を焼成できる。 By forming the in-plane conductor 19 and the interlayer conductor 20 using silver having a low resistivity, a DCDC converter with low loss and excellent circuit characteristics such as power efficiency can be obtained. In particular, by using silver for the conductor, the multilayer substrate 10 can be fired in an oxidizing atmosphere such as air.
　図３は、ＤＣＤＣコンバータモジュール１を利用したＤＣＤＣコンバータ回路の一例を示す回路図である。 FIG. 3 is a circuit diagram showing an example of a DCDC converter circuit using the DCDC converter module 1.
　図３に示されるＤＣＤＣコンバータ回路１００は、スイッチングＩＣ、チョークコイルＬ０、およびコンデンサＣ１、Ｃ２を備えている。スイッチングＩＣ、チョークコイルＬ０、およびコンデンサＣ１は、ＤＣＤＣコンバータモジュール１に統合されている。 The DCDC converter circuit 100 shown in FIG. 3 includes a switching IC, a choke coil L0, and capacitors C1 and C2. The switching IC, the choke coil L0, and the capacitor C1 are integrated into the DCDC converter module 1.
　具体的に、スイッチングＩＣはスイッチングＩＣチップ３２で構成され、コンデンサＣ１はチップコンデンサ３３で構成される。チョークコイルＬ０は、第１インダクタＬ１と第２インダクタＬ２とを直列接続してなり、第１インダクタＬ１は基板内蔵型のコイル３１で構成され、第２インダクタＬ２はチップインダクタ３４で構成される。なお、コンデンサＣ２が、ＤＣＤＣコンバータモジュール１にさらに統合されていてもよい。 Specifically, the switching IC is composed of a switching IC chip 32, and the capacitor C1 is composed of a chip capacitor 33. The choke coil L0 is formed by connecting a first inductor L1 and a second inductor L2 in series. The first inductor L1 is composed of a substrate-embedded coil 31, and the second inductor L2 is composed of a chip inductor. The capacitor C2 may be further integrated into the DCDC converter module 1.
　スイッチングＩＣは、ＤＣＤＣコンバータ回路１００のスイッチング動作を制御するためのＩＣであり、内部には、例えばＭＯＳ型ＦＥＴ等のスイッチング素子を有している。 The switching IC is an IC for controlling the switching operation of the DCDC converter circuit 100, and has a switching element such as a MOS type FET inside.
　ＤＣＤＣコンバータ回路１００において、スイッチングＩＣの端子Ｖｉｎには入力電圧が印加され、スイッチングＩＣの端子Ｌｘからは、チョークコイルＬ０を介して出力電圧が出力される。 In DCDC converter circuit 100, to the terminal V in the switching IC input voltage is applied from the terminal Lx of the switching IC, the output voltage via a choke coil L0 is output.
　コンデンサＣ１の一端は、端子Ｐｉｎと端子Ｖｉｎとの間の入力電圧用電源ラインに接続され、コンデンサＣ１の他端はグランド端子ＰＧＮＤに接続されている。コンデンサＣ２の一端は、端子Ｐｏｕｔと端子Ｐ１との間の出力電圧用電源ラインに接続され、コンデンサＣ２の他端はグランド端子ＰＧＮＤに接続されている。 One end of the capacitor C1 is connected to the input voltage supply line between the terminal P in and the terminal V in, the other end of the capacitor C1 is connected to the ground terminal P GND. One end of the capacitor C2 is connected to the output voltage power supply line between the terminal P out and the terminal P1, the other end of the capacitor C2 is connected to the ground terminal P GND.
　スイッチングＩＣのフィードバック端子ＦＢは、チョークコイルＬ０と端子Ｐｏｕｔとの間の出力電圧用電源ラインに接続され、スイッチングＩＣのグランド端子ＧＮＤはグランド端子ＰＧＮＤに接続され、スイッチングＩＣのイネーブル端子ＥＮはイネーブル端子ＰＥＮに接続されている。 Feedback terminal FB of the switching IC is connected to the output voltage power supply line between the choke coil L0 and the terminal P out, a ground terminal GND of the switching IC is connected to the ground terminal P GND, the enable terminal EN of the switching IC is It is connected to the enable terminal PEN .
　ＤＣＤＣコンバータ回路１００は、端子Ｐｉｎに供給された入力電圧を、スイッチングＩＣに内蔵されているスイッチング素子で所定の周波数にてスイッチングし、チョークコイルＬ０とコンデンサＣ２とで平滑することにより、所望の出力電圧に調整して出力する。また、スイッチングＩＣは、フィードバック端子ＦＢに入力された出力電圧に基づいて、例えば、スイッチング周波数を一定としてパルス幅を可変するＰＷＭ（Pulse Width Modulation）制御を行い、出力電圧を設定電圧に安定させる。 DCDC converter circuit 100, an input voltage supplied to the terminal P in, switched at a predetermined frequency in the switching elements incorporated in the switching IC, by smoothed by the choke coil L0 and a capacitor C2, a desired Adjust to output voltage and output. In addition, the switching IC performs, for example, PWM (Pulse Width Modulation) control that varies the pulse width while keeping the switching frequency constant based on the output voltage input to the feedback terminal FB, and stabilizes the output voltage at the set voltage.
　なお、図３では、一例として、降圧動作を行うスイッチングＩＣチップ３２を用いた降圧型のＤＣＤＣコンバータ回路１００を示しているが、ＤＣＤＣコンバータ回路はこの例には限られない。昇圧動作または昇降圧動作を行うスイッチングＩＣを実装したＤＣＤＣコンバータモジュールを用いて、昇圧型または昇降圧型のＤＣＤＣコンバータ回路を構成してもよい。 In FIG. 3, the step-down DCDC converter circuit 100 using the switching IC chip 32 that performs the step-down operation is shown as an example. However, the DCDC converter circuit is not limited to this example. A step-up or step-up / step-down DCDC converter circuit may be configured using a DCDC converter module in which a switching IC that performs step-up or step-up / step-down operations is mounted.
　図４は、第１インダクタＬ１および第２インダクタＬ２のそれぞれの直流重畳特性の一例を示すグラフである。図４では、チョークコイルＬ０のインダクタンスを、第１インダクタＬ１のインダクタンスと第２インダクタＬ２のインダクタンスとの和によって示している。 FIG. 4 is a graph showing an example of the DC superposition characteristics of the first inductor L1 and the second inductor L2. In FIG. 4, the inductance of the choke coil L0 is indicated by the sum of the inductance of the first inductor L1 and the inductance of the second inductor L2.
　図４に示される基準電流値Ｉｒｅｆは、基準負荷状態においてチョークコイルＬ０（つまり、第１インダクタＬ１および第２インダクタＬ２）に印加される直流重畳電流の大きさを示している。ここで、基準負荷状態とは、ＤＣＤＣコンバータ回路１００の定格、または当該定格よりも低い条件で設定される負荷状態であり、例えば、ＤＣＤＣコンバータ回路１００が、ユーザの応用回路に対し当該応用回路が必要とする最大の電力を供給する状態に対応する。つまり、基準負荷状態は、実際の利用において想定されるＤＣＤＣコンバータ回路１００の最大負荷状態であってもよい。 The reference current value Iref shown in FIG. 4 indicates the magnitude of the DC superimposed current applied to the choke coil L0 (that is, the first inductor L1 and the second inductor L2) in the reference load state. Here, the reference load state is a load state that is set under a rating of the DCDC converter circuit 100 or under a condition lower than the rating. For example, the DCDC converter circuit 100 is connected to a user application circuit by the application circuit. Corresponds to the state of supplying the maximum power required. That is, the reference load state may be the maximum load state of the DCDC converter circuit 100 assumed in actual use.
　第１インダクタＬ１は、直流重畳電流が印加されないときのインダクタンス値が第１初期インダクタンス値Ｌ１ｉｎｉｔであり、かつ印加される直流重畳電流の増大に対して第１低下率ΔＬ１でインダクタンス値が低下する第１直流重畳特性を有している。 The first inductor L1 has a first initial inductance value L1init when the DC superimposed current is not applied, and the inductance value decreases at a first reduction rate ΔL1 with respect to the increase of the applied DC superimposed current. 1 It has direct current superposition characteristics.
　第２インダクタＬ２は、直流重畳電流が印加されないときのインダクタンス値が第２初期インダクタンス値Ｌ２ｉｎｉｔであり、かつ印加される直流重畳電流の増大に対して第２低下率ΔＬ２でインダクタンス値が低下する第２直流重畳特性を有している。 The inductance value of the second inductor L2 when the DC superimposed current is not applied is the second initial inductance value L2init, and the inductance value decreases at a second reduction rate ΔL2 with respect to the increase of the applied DC superimposed current. 2 Has direct current superposition characteristics.
　ここで、第１初期インダクタンス値Ｌ１ｉｎｉｔは第２初期インダクタンス値Ｌ２ｉｎｉｔより大きく（Ｌ１ｉｎｉｔ＞Ｌ２ｉｎｉｔ）、かつ第１低下率ΔＬ１は第２低下率ΔＬ２より大きい（ΔＬ１＞ΔＬ２）。 Here, the first initial inductance value L1init is larger than the second initial inductance value L2init (L1init> L2init), and the first decrease rate ΔL1 is larger than the second decrease rate ΔL2 (ΔL1> ΔL2).
　なお、図４では、第１低下率ΔＬ１および第２低下率ΔＬ２を、前記基準負荷状態におけるインダクタンス値の初期インダクタンス値からの低下量によって示しているが、この例には限られない。第１低下率および第２低下率には、例えば、インダクタンス値のグラフの傾きの最大値など、印加される直流重畳電流の増大に対するインダクタンス値の低下率を反映する適宜の指標が用いられ得る。 In FIG. 4, the first decrease rate ΔL1 and the second decrease rate ΔL2 are shown by the amount of decrease from the initial inductance value of the inductance value in the reference load state, but are not limited to this example. For the first reduction rate and the second reduction rate, for example, an appropriate index that reflects the reduction rate of the inductance value with respect to the increase of the applied DC superimposed current, such as the maximum value of the slope of the inductance value graph, can be used.
　前記第１直流重畳特性を得るために、第１インダクタＬ１（ＤＣＤＣコンバータモジュール１のコイル３１）は、フェライト磁性体で構成されたコアを有するコイルによって構成されてもよい。一般的に、フェライト磁性体のコアを有するコイルは、直流重畳特性におけるインダクタンスの低下率が大きい反面、大きな初期インダクタンス値を持つため、前記第１直流重畳特性を得るために適している。 In order to obtain the first direct current superimposition characteristic, the first inductor L1 (the coil 31 of the DCDC converter module 1) may be constituted by a coil having a core made of a ferrite magnetic material. In general, a coil having a ferrite magnetic core has a large inductance reduction rate in the DC superposition characteristic, but has a large initial inductance value, and is therefore suitable for obtaining the first DC superposition characteristic.
　前記第２直流重畳特性を得るために、第２インダクタＬ２（ＤＣＤＣコンバータモジュール１のチップインダクタ３４）は、メタルコンポジット材（金属磁性体）で構成されたコア（磁心）を有するメタルコンポジット型コイルによって構成されてもよい。 In order to obtain the second direct current superimposition characteristic, the second inductor L2 (chip inductor 34 of the DCDC converter module 1) is a metal composite type coil having a core (magnetic core) made of a metal composite material (metal magnetic material). It may be configured.
　メタルコンポジット材とは、鉄などの主成分とニッケルやクロムなどの副成分とを含んだ金属磁性粒子とバインダ樹脂とを圧粉成型してなる材料を言う。また、メタルコンポジット型コイルとは、コアがメタルコンポジット材で構成されたコイルを言い、具体的には、メタルコンポジット材にコイル状の導体を埋め込んでなるコイルが含まれる。 The metal composite material is a material obtained by compacting metal magnetic particles containing a main component such as iron and subcomponents such as nickel and chromium and a binder resin. Moreover, the metal composite type coil means a coil whose core is made of a metal composite material, and specifically includes a coil in which a coil-shaped conductor is embedded in a metal composite material.
　メタルコンポジット型コイルは、フェライトセラミックをコアとしたコイル（第１インダクタＬ１）に比べて、飽和磁束密度が大きいため、磁気飽和による直流重畳特性が劣化しにくく、前記第２直流重畳特性を得るために適している。 Since the metal composite type coil has a higher saturation magnetic flux density than a coil (first inductor L1) having a ferrite ceramic core, the direct current superimposition characteristic due to magnetic saturation is not easily deteriorated, and the second direct current superimposition characteristic is obtained. Suitable for
　ＤＣＤＣコンバータの効率をさらに考慮して、第２インダクタＬ２は、金属線をコイル状に巻回してなる巻き線型のチップインダクタで構成されてもよい。一般的に、巻き線型のチップインダクタは直流抵抗が小さいため、ＤＣＤＣコンバータの効率の劣化を抑制するために適している。 Further considering the efficiency of the DCDC converter, the second inductor L2 may be formed of a wound type chip inductor formed by winding a metal wire in a coil shape. Generally, a wound-type chip inductor has a small direct current resistance and is suitable for suppressing deterioration in efficiency of a DCDC converter.
　以下では、直流重畳特性が互いに異なる第１インダクタＬ１と第２インダクタＬ２とを直列接続してチョークコイルＬ０を構成する効果について説明する。 Hereinafter, the effect of configuring the choke coil L0 by connecting the first inductor L1 and the second inductor L2 having different DC superimposing characteristics in series will be described.
　図５は、ＤＣＤＣコンバータのリプル特性の一例を示すグラフである。図５では、チョークコイルＬ０に印加される直流重畳電流に応じてＤＣＤＣコンバータ回路１００の出力電圧に生じるリプル電圧の一例を示している。 FIG. 5 is a graph showing an example of the ripple characteristic of the DCDC converter. FIG. 5 shows an example of a ripple voltage generated in the output voltage of the DCDC converter circuit 100 in accordance with the DC superimposed current applied to the choke coil L0.
　直流重畳電流が小さい軽負荷時には、ＤＣＤＣコンバータ回路１００におけるスイッチング動作のデューティ比が小さくなり、さらにはスイッチング動作が間欠的になることで、リプル電圧が大きくなる。これに対し、直流重畳電流が大きい重負荷時には、チョークコイルＬ０のインダクタンス値が直流重畳特性に従って低下することで、リプル電圧が大きくなる。 When the DC superimposed current is small and the load is light, the duty ratio of the switching operation in the DCDC converter circuit 100 is reduced, and further, the switching operation becomes intermittent, so that the ripple voltage is increased. On the other hand, at the time of heavy load with a large DC superimposed current, the ripple voltage increases because the inductance value of the choke coil L0 decreases according to the DC superimposed characteristic.
　重負荷時に過大なリプル電圧が生じると、不安定動作（例えば、過電流保護の誤作動）や雑音を増大させる要因になり得る。そのため、特に、重負荷時におけるリプル電圧に対し、ＤＣＤＣコンバータが適正に動作するための上限が規定される。例えば、前述した基準負荷状態（チョークコイルＬ０に基準電流値Ｉｒｅｆの直流重畳電流が印加される状態）において、リプル電圧の上限値Ｒｌｉｍが規定される。 If an excessive ripple voltage is generated under heavy load, it may cause unstable operation (for example, malfunction of overcurrent protection) and increase noise. Therefore, in particular, an upper limit for proper operation of the DCDC converter is defined for the ripple voltage under heavy load. For example, the upper limit value Rlim of the ripple voltage is defined in the above-described reference load state (a state in which the DC superimposed current having the reference current value Iref is applied to the choke coil L0).
　前記基準負荷状態において、チョークコイルＬ０には、リプル電圧を上限値Ｒｌｉｍ以下に抑えるためにある基準値以上のインダクタンス値を持つ必要がある。図４では、そのような基準値を、一例として、基準インダクタンス値Ｌｒｅｆで表している。つまり、図４は、前記基準負荷状態においてＤＣＤＣコンバータ回路１００が目的の出力電圧を適正に生成するために、チョークコイルＬ０には、基準インダクタンス値Ｌｒｅｆ以上のインダクタンスが必要とされる一例を表している。この例において、目的の出力電圧とは、リプル電圧が上限値Ｒｌｉｍ以下に抑えられた電圧である。 In the reference load state, the choke coil L0 needs to have an inductance value equal to or greater than a certain reference value in order to keep the ripple voltage below the upper limit value Rlim. In FIG. 4, such a reference value is represented by a reference inductance value Lref as an example. That is, FIG. 4 illustrates an example in which the choke coil L0 requires an inductance greater than the reference inductance value Lref in order for the DCDC converter circuit 100 to properly generate the target output voltage in the reference load state. Yes. In this example, the target output voltage is a voltage in which the ripple voltage is suppressed to the upper limit value Rlim or less.
　この要件を満たすために、前記基準負荷状態において、第１インダクタＬ１のインダクタンス値Ｌ１ｒｅｆは基準インダクタンス値Ｌｒｅｆより小さく（Ｌ１ｒｅｆ＜Ｌｒｅｆ）、かつ、第２インダクタＬ２のインダクタンス値Ｌ２ｒｅｆは基準インダクタンス値Ｌｒｅｆから第１インダクタＬ１のインダクタンス値Ｌ１ｒｅｆを減じた値より大きくてもよい（Ｌ２ｒｅｆ＞Ｌｒｅｆ－Ｌ１ｒｅｆ）。これにより、前記基準負荷状態において、チョークコイルＬ０は、基準インダクタンス値Ｌｒｅｆ以上のインダクタンス値Ｌ０ｒｅｆを持つことができる。 In order to satisfy this requirement, in the reference load state, the inductance value L1ref of the first inductor L1 is smaller than the reference inductance value Lref (L1ref <Lref), and the inductance value L2ref of the second inductor L2 is calculated from the reference inductance value Lref. It may be larger than the value obtained by subtracting the inductance value L1ref of the first inductor L1 (L2ref> Lref−L1ref). Thus, in the reference load state, the choke coil L0 can have an inductance value L0ref that is greater than or equal to the reference inductance value Lref.
　言い換えれば、前記基準負荷状態におけるインダクタンス値がチョークコイルＬ０に必要な基準インダクタンス値Ｌｒｅｆに満たない第１インダクタＬ１を意図的に使用し、不足分を第２インダクタＬ２で補ってもよい。 In other words, the first inductor L1 whose inductance value in the reference load state is less than the reference inductance value Lref necessary for the choke coil L0 may be intentionally used, and the shortage may be compensated by the second inductor L2.
　前記基準負荷状態においてチョークコイルＬ０に必要な基準インダクタンス値Ｌｒｅｆを第１インダクタＬ１だけで賄おうとすると、第１インダクタＬ１では、インダクタンス値の低下率ΔＬ１が大きいため、第１初期インダクタンス値Ｌ１ｉｎｉｔをかなり大きくする必要がある。そのため、第１インダクタＬ１の形状が大きくなり、モジュールの小型化、低背化を損なう懸念がある。 If the reference inductance value Lref necessary for the choke coil L0 in the reference load state is to be covered only by the first inductor L1, the first inductor L1 has a large decrease rate ΔL1 of the inductance value, so that the first initial inductance value L1init is considerably increased. It needs to be bigger. For this reason, the shape of the first inductor L1 is increased, and there is a concern that the module is reduced in size and height.
　その点、第１インダクタＬ１と比べて第２初期インダクタンス値Ｌ２ｉｎｉｔもインダクタンス値の低下率ΔＬ２も小さい第２インダクタＬ２は、その形状においても第１インダクタＬ１より小さく形成し得る。そこで、直流重畳特性が互いに異なる第１インダクタＬ１と第２インダクタＬ２とを直列接続してチョークコイルＬ０を構成するＤＣＤＣコンバータ回路を採用する。これにより、モジュールの低背化および小型化を阻害しにくく、かつ特性に優れたＤＣＤＣコンバータモジュールを構成することができる。 In that respect, the second inductor L2 in which the second initial inductance value L2init and the inductance value decrease rate ΔL2 are smaller than the first inductor L1 can be formed smaller than the first inductor L1 in its shape. Therefore, a DCDC converter circuit is employed in which a choke coil L0 is configured by connecting a first inductor L1 and a second inductor L2 having different DC superimposing characteristics in series. As a result, it is possible to configure a DCDC converter module that is unlikely to hinder a reduction in the height and size of the module and that has excellent characteristics.
　以上説明したように、本発明に係るＤＣＤＣコンバータモジュールおよびＤＣＤＣコンバータ回路によれば、メインインダクタとして基板内蔵型コイルである第１コイルを利用し、サブインダクタとして直流重畳特性がよくかつインダクタンス値の小さな表面実装型のチップインダクタである第２コイルを利用する。そして、前記第１コイルと前記第２コイルとを直列に接続して前記チョークコイルを構成し、前記チョークコイルの直流重畳特性を向上させている。 As described above, according to the DCDC converter module and the DCDC converter circuit according to the present invention, the first coil, which is a substrate built-in type coil, is used as the main inductor, the DC superposition characteristics are good as the sub-inductor, and the inductance value is small. A second coil which is a surface mount type chip inductor is used. And the said 1st coil and the said 2nd coil are connected in series, the said choke coil is comprised, and the direct current superimposition characteristic of the said choke coil is improved.
　これにより、ＤＣＤＣコンバータの重負荷時において、リプル電圧を抑えることができる。また、ＤＣＤＣコンバータの重負荷時のインダクタンス値不足に起因する不安定動作を抑えることができる。また、前記第２コイルを、前記スイッチングＩＣ素子とともに前記基板に表面実装するので、モジュールの低背化および小型化を阻害しにくい。 This makes it possible to suppress the ripple voltage when the DCDC converter is heavily loaded. In addition, unstable operation due to insufficient inductance value at the time of heavy load of the DCDC converter can be suppressed. Further, since the second coil is surface-mounted on the substrate together with the switching IC element, it is difficult to hinder the reduction in the height and size of the module.
　以上、本発明の実施の形態に係るモジュール部品、モジュール部品の製造方法、および多層基板について説明したが、本発明は、個々の実施の形態には限定されない。本発明の趣旨を逸脱しない限り、当業者が思いつく各種変形を本実施の形態に施したものや、異なる実施の形態における構成要素を組み合わせて構築される形態も、本発明の一つ又は複数の態様の範囲内に含まれてもよい。 As mentioned above, although the module component which concerns on embodiment of this invention, the manufacturing method of a module component, and the multilayer substrate were demonstrated, this invention is not limited to each embodiment. Unless it deviates from the gist of the present invention, the embodiment in which various modifications conceived by those skilled in the art have been made in the present embodiment, and forms constructed by combining components in different embodiments are also applicable to one or more of the present invention. It may be included within the scope of the embodiments.
　本発明は、コイルを内蔵したセラミック多層基板、および当該セラミック多層基板を用いた超小型のＤＣＤＣコンバータとして、携帯情報端末やデジタルカメラなどの電子機器に広く利用できる。 The present invention can be widely used in electronic devices such as portable information terminals and digital cameras as a ceramic multilayer substrate with a built-in coil and an ultra-small DCDC converter using the ceramic multilayer substrate.
　　１　ＤＣＤＣコンバータモジュール
　　１０　多層基板（基板）
　　１１　コア磁性体層
　　１１１～１１９　磁性体層
　　１２　第１非磁性体層
　　１２１、１２２　非磁性体層
　　１３　第２非磁性体層
　　１３１、１３２　非磁性体層
　　１７、１８　表面電極
　　１９　面内導体
　　２０　層間導体
　　３１　コイル（第１コイル）
　　３２　スイッチングＩＣチップ（スイッチングＩＣ素子）
　　３３　チップコンデンサ
　　３４　チップインダクタ（第２コイル）
　　１００　ＤＣＤＣコンバータ回路 1 DCDC converter module 10 Multilayer substrate (substrate)
11 Core magnetic layer 111 to 119 Magnetic layer 12 First nonmagnetic layer 121, 122 Nonmagnetic layer 13 Second nonmagnetic layer 131, 132 Nonmagnetic layer 17, 18 Surface electrode 19 In-plane conductor 20 Interlayer Conductor 31 coil (first coil)
32 Switching IC chip (Switching IC element)
33 Chip capacitor 34 Chip inductor (second coil)
100 DCDC converter circuit

Claims (7)

  1. 　基板と、
    　前記基板に実装されたスイッチングＩＣ素子と、
    　前記スイッチングＩＣ素子に接続されたチョークコイルと、
    を備え、
    　前記チョークコイルは、前記基板に内蔵されたコイル状導体パターンによって形成された第１コイルと、前記第１コイルに直列接続され、前記基板に実装されたチップ状の第２コイルと、で構成されている、
    　ＤＣＤＣコンバータモジュール。     A substrate,
    A switching IC element mounted on the substrate;
    A choke coil connected to the switching IC element;
    With
    The choke coil includes a first coil formed by a coiled conductor pattern built in the substrate, and a chip-like second coil connected in series to the first coil and mounted on the substrate. ing,
    DCDC converter module.
  2. 　前記第１コイルは、直流重畳電流が印加されないときのインダクタンス値が第１初期インダクタンス値であり、かつ印加される直流重畳電流の増大に対して第１低下率でインダクタンス値が低下する第１直流重畳特性を有し、
    　前記第２コイルは、直流重畳電流が印加されないときのインダクタンス値が第２初期インダクタンス値であり、かつ印加される直流重畳電流の増大に対して第２低下率でインダクタンス値が低下する第２直流重畳特性を有し、
    　前記第１初期インダクタンス値は前記第２初期インダクタンス値より大きく、かつ前記第１低下率は前記第２低下率より大きい、
    　請求項１に記載のＤＣＤＣコンバータモジュール。     The first coil has an inductance value that is a first initial inductance value when no DC superimposed current is applied, and an inductance value that decreases at a first reduction rate with respect to an increase in the applied DC superimposed current. Has superposition characteristics,
    The second coil has an inductance value that is a second initial inductance value when no DC superimposed current is applied, and an inductance value that decreases at a second reduction rate with respect to an increase in the applied DC superimposed current. Has superposition characteristics,
    The first initial inductance value is greater than the second initial inductance value, and the first reduction rate is greater than the second reduction rate;
    The DCDC converter module according to claim 1.
  3. 　前記第２コイルは、金属線をコイル状に巻回してなる巻線コイルによって構成されている、
    　請求項１又は２に記載のＤＣＤＣコンバータモジュール。     The second coil is constituted by a winding coil formed by winding a metal wire in a coil shape.
    The DCDC converter module according to claim 1 or 2.
  4. 　前記基板はフェライト焼結体からなる磁性体基板であって、前記第１コイルはフェライト焼結体に内蔵された金属焼結体によって構成されている、
    　請求項１～３の何れか１項に記載のＤＣＤＣコンバータモジュール。     The substrate is a magnetic substrate made of a ferrite sintered body, and the first coil is constituted by a metal sintered body incorporated in the ferrite sintered body;
    The DCDC converter module according to any one of claims 1 to 3.
  5. 　第１コイルと、前記第１コイルに直列接続された第２コイルとで構成されたチョークコイルを備え、
    　前記第１コイルは、直流重畳電流が印加されないときのインダクタンス値が第１初期インダクタンス値であり、かつ印加される直流重畳電流の増大に対して第１低下率でインダクタンス値が低下する第１直流重畳特性を有し、
    　前記第２コイルは、直流重畳電流が印加されないときのインダクタンス値が第２初期インダクタンス値であり、かつ印加される直流重畳電流の増大に対して第２低下率でインダクタンス値が低下する第２直流重畳特性を有し、
    　前記第１初期インダクタンス値は前記第２初期インダクタンス値より大きく、かつ前記第１低下率は前記第２低下率より大きい、
    　ＤＣＤＣコンバータ回路。     A choke coil comprising a first coil and a second coil connected in series to the first coil;
    The first coil has an inductance value that is a first initial inductance value when no DC superimposed current is applied, and an inductance value that decreases at a first reduction rate with respect to an increase in the applied DC superimposed current. Has superposition characteristics,
    The second coil has an inductance value that is a second initial inductance value when no DC superimposed current is applied, and an inductance value that decreases at a second reduction rate with respect to an increase in the applied DC superimposed current. Has superposition characteristics,
    The first initial inductance value is greater than the second initial inductance value, and the first reduction rate is greater than the second reduction rate;
    DCDC converter circuit.
  6. 　前記チョークコイルに基準電流値の直流重畳電流が印加される基準負荷状態において、前記ＤＣＤＣコンバータ回路が目的の出力電圧を生成するために、前記チョークコイルに基準インダクタンス値以上のインダクタンスが必要となる場合に、
    　前記第１コイルのインダクタンス値は、前記基準電流値の直流重畳電流が印加された状態で、前記基準インダクタンス値より小さく、
    　前記第２コイルのインダクタンス値は、前記基準電流値の直流重畳電流が印加された状態で、前記基準インダクタンス値から前記第１コイルのインダクタンス値を減じたインダクタンス値より大きい、
    　請求項５に記載のＤＣＤＣコンバータ回路。     In a reference load state where a DC superimposed current of a reference current value is applied to the choke coil, the choke coil needs an inductance greater than a reference inductance value in order to generate a target output voltage In addition,
    The inductance value of the first coil is smaller than the reference inductance value in a state where a DC superimposed current of the reference current value is applied,
    The inductance value of the second coil is larger than the inductance value obtained by subtracting the inductance value of the first coil from the reference inductance value in a state where a DC superimposed current of the reference current value is applied.
    The DCDC converter circuit according to claim 5.
  7. 　前記第１コイルは、フェライト磁性体で構成されたコアを有し、
    　前記第２コイルは、金属磁性体で構成されたコアを有している、
    　請求項５又は６に記載のＤＣＤＣコンバータ回路。     The first coil has a core made of ferrite magnetic material,
    The second coil has a core made of a metal magnetic material.
    The DCDC converter circuit according to claim 5 or 6.
PCT/JP2017/013006 2016-04-06 2017-03-29 Dc/dc converter module and dc/dc converter circuit WO2017175645A1 (en)

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JP2021078172A (en) * 2019-11-05 2021-05-20 ルネサスエレクトロニクス株式会社 Semiconductor device and power supply management ic
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