WO2017166925A1 - 一种自适应时钟恢复方法及装置 - Google Patents

一种自适应时钟恢复方法及装置 Download PDF

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Publication number
WO2017166925A1
WO2017166925A1 PCT/CN2017/072903 CN2017072903W WO2017166925A1 WO 2017166925 A1 WO2017166925 A1 WO 2017166925A1 CN 2017072903 W CN2017072903 W CN 2017072903W WO 2017166925 A1 WO2017166925 A1 WO 2017166925A1
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Prior art keywords
time stamp
stamp data
data
clock recovery
adaptive clock
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PCT/CN2017/072903
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English (en)
French (fr)
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程胜飞
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中兴通讯股份有限公司
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Publication of WO2017166925A1 publication Critical patent/WO2017166925A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps

Definitions

  • the present disclosure relates to the field of communications technologies, and, for example, to an adaptive clock recovery method and apparatus.
  • TDM Time Division Multiplexing
  • the adaptive clock mode does not require a reference clock, and the clock can be adaptively restored according to the time stamp data of the received message in the communication network to achieve synchronization of the networking clock.
  • a PTN (Packet Transport Network) device encapsulates TDM service data in an encapsulated form of an Ethernet service, and uses a specific chip or a NIOS-based (embedded processor) architecture to implement an adaptive clock.
  • Recovery function the module that normally implements this function will be loaded into a specific chip or FPGA (Field Programmable Gate Array), integrated soft core function on the FPGA, restored by software configuration and hardware processing.
  • FPGA Field Programmable Gate Array
  • Adaptive clocking for example, software-to-hardware processing requires the use of interrupts to periodically transfer information such as reference time accumulated values and time-stamped data to the hardware, which then restores the time-stamp value to a clock signal.
  • the main technical problem to be solved by the present disclosure is to provide an adaptive clock recovery method and apparatus, which can solve the problem that the abnormal time stamp data in the message cannot be corrected when the adaptive clock recovery is performed in the related art, thereby affecting the clock recovery. Accuracy and stability, reducing the computational efficiency of clock recovery Problems.
  • an adaptive clock recovery method including:
  • the time stamp data including a serial number and a time stamp
  • the modifying the acquired time stamp data includes:
  • the time stamp data not arranged at the preset interval is corrected.
  • the time stamp data that is not arranged according to the preset interval is modified as follows:
  • the serial number of the latter time stamp data the serial number of the previous time stamp data + the serial number difference;
  • Timestamp of the last timestamp data timestamp of the previous timestamp data + message delay
  • the subsequent time stamp data is sequentially corrected.
  • the performing adaptive clock recovery according to the correction result may be:
  • the acquired time stamp data is subjected to adaptive clock recovery.
  • the performing adaptive clock recovery according to the correction result may be:
  • the frequency dividing factor will be calculated based on the corrected result
  • Adaptive clock recovery is performed according to the frequency division factor.
  • the method before detecting whether the time stamp data is filled in any of the buffers, the method further includes:
  • the adaptive clock recovery function is enabled when detecting the time division multiplexing service of any port configured with adaptive clock mode.
  • the present disclosure further provides an adaptive clock recovery device, including:
  • a buffer detection module configured to detect whether any time stamp data is filled in any of the buffers, the time stamp data including a serial number and a time stamp;
  • An obtaining module configured to acquire time stamp data in the buffer if the time stamp data is full
  • the correction module is configured to correct the acquired time stamp data such that the sequence numbers of the time stamp data are arranged according to a preset interval, and the time stamps are arranged in chronological order;
  • the recovery module is configured to perform adaptive clock recovery based on the corrected result.
  • the correction module includes:
  • the determining submodule is configured to determine whether the sequence numbers of the time stamp data in the buffer are arranged according to a preset interval
  • the correction sub-module is configured to correct the time stamp data that are not arranged according to the preset interval if they are not arranged according to the preset interval.
  • the time stamp data that is not arranged according to the preset interval is modified in the following manner:
  • the serial number of the latter time stamp data the serial number of the previous time stamp data + the serial number difference;
  • Timestamp of the last timestamp data timestamp of the previous timestamp data + message delay
  • the subsequent time stamp data is sequentially corrected.
  • the recovery module includes:
  • Obtaining a submodule configured to obtain a set of time stamp data with a most time stamp according to the correction result
  • the recovery submodule is configured to perform adaptive clock recovery on the acquired time stamp data.
  • the recovery module includes:
  • An operation submodule configured to calculate a frequency division factor according to the correction result
  • the recovery submodule is configured to perform adaptive clock recovery according to the frequency division factor.
  • the method further includes:
  • the service detection module is configured to enable the adaptive clock recovery function when detecting the time division multiplexing service of the adaptive clock mode configured on any port before detecting whether the time stamp data is full in any of the buffers.
  • the present disclosure provides an adaptive clock recovery method, including: detecting whether any time stamp data is filled in any buffer, the time stamp data includes a sequence number and a time stamp; if the time stamp data is full, the buffer is obtained. Each time stamp data is corrected, and the acquired time stamp data is corrected such that the sequence numbers of the time stamp data are arranged according to a preset interval, and the time stamps are arranged in chronological order; adaptive clock recovery is performed according to the correction result.
  • the process of performing adaptive clock recovery by correcting the abnormal time stamp data, the time stamp data that is not sorted according to the set rule is corrected into the ideal time stamp data, and the clock recovery efficiency is improved. It also improves the stability of clock recovery.
  • the present disclosure also provides an adaptive clock recovery apparatus, which implements an adaptive clock recovery function originally implemented by hardware, thereby reducing hardware requirements and occupying no additional hardware resources to reduce equipment cost. Improve design flexibility.
  • Embodiments of the present disclosure also provide a non-transitory computer readable storage medium storing computer executable instructions arranged to perform the above method.
  • An embodiment of the present disclosure further provides an electronic device, including:
  • At least one processor At least one processor
  • the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the method described above.
  • FIG. 1 is a flowchart of an adaptive clock recovery method according to Embodiment 1 of the present disclosure
  • FIG. 2 is a schematic diagram of an adaptive clock-to-TDM service recovery process in a PTN network according to Embodiment 1 of the present disclosure
  • FIG. 3 is a flowchart of an adaptive clock recovery function according to Embodiment 1 of the present disclosure
  • FIG. 4 is a schematic diagram of an adaptive clock recovery apparatus according to Embodiment 2 of the present disclosure.
  • FIG. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the time stamp data is 64 bit data, the first 16 bits are the serial number of the time stamp data, and the last 48 bits are the time stamp of the time stamp data;
  • the data is included in the transmitted message.
  • this embodiment provides an adaptive clock recovery method.
  • the recovery steps may be as follows:
  • S104 Perform adaptive clock recovery according to the correction result.
  • the time stamp data that is not sorted according to the set rule is corrected to the ideal time stamp data by correcting the abnormal time stamp data, thereby improving the clock recovery efficiency. It also improves the stability of clock recovery.
  • the abnormal time stamp data refers to partial data loss due to network failure or the like when transmitting time stamp data in the packet, or partial data due to hardware instability when storing time stamp data to the hardware. An error occurred so that the serial number and time stamp in the partial time stamp data could not be stored according to the normal rules.
  • the recovery process of the adaptive clock can be as follows:
  • the PTN access device divides the E1 service flow into a plurality of data segments, and then encapsulates the data segments into a plurality of bearer messages in the PTN network in a standard format, and the TDM services are sequentially transmitted in the form of packets to the other through the PTN network.
  • the PTN accesses the device, and the packet carries time stamp data.
  • the time stamp data includes a sequence number and a time point when the packet is received.
  • another PTN access device splits each received packet to obtain a plurality of packets.
  • the data segment and the E1 service flow are recovered through several data segments.
  • the buffer in step S101 can be a slice in a logical FPGA.
  • the logical FPGA is hardware.
  • a total of 4 slices are allocated to store time stamp data, and each slice can store 255 time stamp data, and only
  • the software allows the software to read the entire piece of data when all of the slices are full. That is, when it is detected that one of the slice full flag bits is set, the software will fetch all the time stamp data of the slice.
  • the logic FPGA in this embodiment is only configured to store time stamp data, and the processing of the data is implemented by software;
  • the time stamp data in this embodiment is composed of a serial number and a time stamp, and each time stamp
  • the serial number of the data is ideally equally spaced (sequentially increasing or decreasing sequentially), and the timestamp is the point in time at which the message is received. It should be understood that the above four areas and 255 are only used to describe the embodiment, and the value cannot be determined to be limited to the above description.
  • step S102 after all the time stamp data in the buffer is obtained, the sequence numbers of the time stamp data need to be sorted in an increasing or decreasing manner, so that the sequence numbers of the time stamp data are sorted according to the setting rules.
  • the equal spacing is an arithmetic progression between the serial numbers of the time stamp data, and the time stamp corresponds to the serial number one by one. Therefore, if the serial numbers are arranged in descending order, the time stamp with a large serial number Relatively small; if the serial numbers are arranged in order from small to large, the timestamp with a small serial number is correspondingly small.
  • the preset interval may be an incomplete interval between the serial numbers.
  • the interval between the sequence numbers of the time stamp data is A; after the time period, the interval may be The preset interval is adjusted to B such that the sequence number interval of subsequent time stamp data becomes B.
  • the preset interval is a ratio in the arithmetic progression column, that is, the serial number difference between the front and back time stamp data, and the time stamp data satisfies the law of the arithmetic progression.
  • the following is an example of correcting the time stamp data by using the law of the arithmetic progression as an example. The process is described.
  • the time stamp data is corrected, and the corrected time stamp data is used as the next time stamp data, and the previously stored time stamp data is discarded. , that is, the time stamp data that does not satisfy the law of the arithmetic progression is discarded, and can be corrected according to the following formula:
  • the serial number of the latter time stamp data the serial number of the previous time stamp data + the serial number difference;
  • the timestamp of the last timestamp data the timestamp of the previous timestamp data + the delay of the message.
  • the above formula corrects the time stamp data that does not currently satisfy the law of the arithmetic progression. If the time stamp data after the time stamp data does not satisfy the law of the arithmetic progression, the correction is also performed according to the above formula.
  • the serial number of the previous time stamp data is the serial number of the current time stamp data
  • the time stamp is the time stamp of the current time stamp data. It should be understood that for time stamp data that does not satisfy the law of the arithmetic progression, the correction method adopted in this embodiment is to correct it in an ideal manner, and is not corrected to the time stamp data lost in the actual sense.
  • the correction method can reduce the time stamp data with large difference between the front and the back according to the ideal state, but the corrected data still has an error with the lost time stamp data, so that the unsatisfied time stamp data can be corrected as much as possible.
  • Time stamp data is required to minimize the error in clock recovery.
  • TimeSequence_2 TimeSequence_1+DisStgValue
  • TimeSequence_1 is the serial number of the previous timestamp data
  • TimeSequence_2 is the serial number of the subsequent timestamp data
  • TimeStamp_1 is the timestamp of the previous timestamp data
  • TimeStamp_2 is the timestamp of the latter timestamp data
  • DisStgValue is the sequence of the subsequent timestamp data.
  • FrameSpeed is the E1 frame rate, which uses synchronous TDM technology to combine 30 voice channels and 2 control channels on a high-speed channel of 2.048 Mbits/s, one frame.
  • the length is 125us
  • ConjNum is a cascading number, which ranges from 1-40.
  • the time stamp data that does not satisfy the law of the difference series can be corrected, so that the sequence numbers of all the time stamp data obtained satisfy the law of the difference series, that is, the interval between the sequence numbers of the time stamp data is equal, and the time stamp is also Increment by small to large.
  • the correction result refers to correcting the time stamp data that does not satisfy the law of the difference series, and satisfying the equal spacing between the sequence numbers and increasing the time stamps sequentially. All acquired time stamp data, obtain a set of time stamp data with the most time stamp from the time stamp data, and calculate the set of time stamp data according to a preset algorithm to obtain a frequency division factor, and then according to the frequency division factor The adaptive clock is recovered.
  • the preset algorithm includes but is not limited to an adaptive clock recovery algorithm.
  • the method further includes: creating a TDM service in an adaptive clock mode, and configuring a cascading number of the packet, a service channel number, and related information about the adaptive clock recovery in the process of creating. Then, each port is detected to determine whether the port transmits the TDM service in the adaptive clock mode. If the TDM service in the adaptive clock mode is enabled, the adaptive clock recovery function is enabled. Referring to FIG. 3, the enabling process can be as follows:
  • the process in Figure 1 is executed after the self-use adaptive clock recovery is enabled.
  • the number of concatenations of the packet and the number of the service channel are included in the TDM service, and the corresponding time stamp data can be obtained according to the service channel number and the number of concatenations, thereby implementing the entire processing flow in FIG.
  • the packet loss policy value (that is, the sequence number difference value) is configured for the logical FPGA according to the number of concatenations.
  • the calculation formula of the packet loss policy value can be as follows:
  • DisStgValue is the packet loss policy value (ie, the serial number difference value);
  • FrameSpeed is the E1 frame rate, 8000 frames/s;
  • TimeStampNum is the number of timestamps stored in one slice, a total of 255;
  • ConjNum is the concatenation number, which is taken Values range from 1-40.
  • the logic FPGA stores the time stamp data of the message in the TDM service according to the packet loss policy value obtained by the above calculation formula, so that the time stamp data satisfies the law of the arithmetic progression.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • This embodiment provides an adaptive clock recovery device.
  • the device includes:
  • the buffer detection module 401 is configured to detect whether any time stamp data is filled in any of the buffers, where the time stamp data includes a serial number and a time stamp;
  • the obtaining module 402 is configured to acquire time stamp data in the buffer if the time stamp data is full;
  • the correction module 403 is configured to correct the acquired time stamp data such that the sequence numbers of the time stamp data are arranged according to a preset interval, and the time stamps are arranged in chronological order;
  • the recovery module 404 is configured to perform adaptive clock recovery based on the corrected result.
  • the preset interval refers to an incomplete interval between the serial numbers.
  • the interval between the sequence numbers of the time stamp data is A; after the time period, the preset interval may be adjusted. Is B such that the sequence number interval of subsequent time stamp data becomes B.
  • the preset interval is a ratio in the arithmetic progression column, that is, the serial number difference between the front and back time stamp data, and the time stamp data satisfies the law of the arithmetic progression. The following is an example of correcting the time stamp data by using the law of the arithmetic progression as an example. The process is described.
  • the adaptive clock recovery device is applied to the PTN device, and the adaptive clock recovery can be performed at the software level, so that the device does not run without the adaptive clock recovery function being enabled.
  • Device when enabled, it enables complete adaptive clock recovery through software, thereby eliminating the need for additional hardware resources, reducing equipment costs, and thus increasing design flexibility.
  • the apparatus further includes a service detection module 405 configured to detect a time division multiplexing service of an adaptive clock mode on any port before detecting whether the time stamp data is full in any of the buffers, Enable adaptive clock recovery.
  • a service detection module 405 configured to detect a time division multiplexing service of an adaptive clock mode on any port before detecting whether the time stamp data is full in any of the buffers, Enable adaptive clock recovery.
  • the device can be initialized first, such as initializing the internal dog feed operation, initializing the IP clock related components, initializing the state machine, and the like.
  • the feeding operation refers to clearing the watchdog counter. For example, when the program is running normally, it needs to be emptied before the watchdog counter reaches the maximum value to restart counting. Then, the timer of the 100 ms timing period in the device is enabled, and the port is periodically queried whether the TDM service is transmitted, and whether the service clock is an adaptive clock type; and the buffer of the logical FPGA is detected at the same time to confirm the time stamp data in the buffer. Is it full?
  • the timer has a timing period of 20 ms, is configured to implement a timing function, and performs operations such as network packet selection, packet loss detection, and comparison calculation after time stamp data is collected.
  • the state switching of each phase of the clock is based on the counting list. Based on the bit.
  • the timer timing period in this embodiment includes, but is not limited to, the foregoing values, and can be reasonably set according to actual needs, which is not limited herein.
  • the board software receives the TDM service creation instruction and assigns it to the SDK (Software Development, software development kit) for TDM service creation.
  • the SDK configures information for the adaptive clock recovery device, configures the number of packets and the service channel number, and transmits the configured cascade number and service channel number to
  • the adaptive clock recovery device sets the packet loss policy value for the logical FPGA according to the number of concatenations, and the logic FPGA stores the time stamp data according to the packet loss policy value.
  • the device detects the TDM service in which the adaptive clock mode is transmitted in each port, the adaptive clock device is turned on to process the time stamp data and perform clock recovery.
  • the PTN access device divides the E1 service flow (that is, the TDM service to be carried) into a plurality of data segments, and then encapsulates the data segments into a plurality of bearer packets in the PTN network in a standard format.
  • the TDM service is in the form of a packet.
  • the PTN network is sequentially transmitted to another PTN access device, where the packet carries time stamp data, and the time stamp data includes a sequence number and a time point when the packet is received; and then another PTN access device receives the received message.
  • the text is split, several data segments are obtained, and the E1 service flow is recovered through several data segments.
  • the buffer may be a slice in a logic FPGA.
  • the logic FPGA is hardware. A total of 4 slices are allocated to store time stamp data, and each slice can store 255 time stamp data, and only when one slice is full.
  • the software is allowed to read the entire piece of data, that is, when it is detected that one of the slice full flag bits is set, the software will fetch all the time stamp data of the slice.
  • the logic FPGA in this embodiment is only configured to store time stamp data, and the processing of the data is implemented by software; the time stamp data in this embodiment is composed of a serial number and a time stamp, and each time stamp The serial number of the data is ideally equally spaced (sequentially increasing or decreasing sequentially), and the timestamp is the point in time at which the message is received. It should be understood that the above four areas and 255 are only used to describe the embodiment, and the value cannot be determined to be limited to the above description.
  • the obtaining module 402 After obtaining all the time stamp data in the buffer, the obtaining module 402 needs to sort the sequence numbers of the time stamp data in an increasing or decreasing manner, so that the sequence numbers of the time stamp data can be sorted according to the setting rules. Whether the sequence numbers of all the time stamp data in the buffer are equal intervals and whether the time stamps are arranged in order from small to large, thereby judging whether or not the message is lost during the transmission of the message.
  • the equal spacing is an arithmetic progression between the serial numbers of the time stamp data, and the time stamp corresponds to the serial number one by one. Therefore, if the serial numbers are arranged in descending order, the time stamp with a large serial number Relatively small; if the serial numbers are arranged in order from small to large, the timestamp with a small serial number is correspondingly small.
  • the correction module 403 can include:
  • the determining sub-module 4031 is configured to determine whether the sequence numbers of the time stamp data in the buffer are arranged according to a preset interval
  • the correction sub-module 4032 is configured to correct the time stamp data that are not arranged according to the preset interval if they are not arranged according to the preset interval.
  • the determining sub-module 4031 finds that the time stamp data not arranged according to the preset interval appears in all the time stamp data acquired, the time stamp data is corrected, and the corrected time stamp data is used as the next time stamp data, and is stored before being discarded.
  • the time stamp data that is, the time stamp data that is not arranged according to the preset interval, can be corrected according to the following formula:
  • the serial number of the latter time stamp data the serial number of the previous time stamp data + the serial number difference;
  • the timestamp of the last timestamp data the timestamp of the previous timestamp data + the delay of the message.
  • the above formula is corrected for the time stamp data that is not currently arranged according to the preset interval. If the time stamp data after the time stamp data is also not arranged according to the preset interval, the above formula is also used for correction, for the latter time stamp data,
  • the serial number of the previous time stamp data is the serial number of the current time stamp data
  • the time stamp is the time stamp of the current time stamp data.
  • the correction method adopted in this embodiment is to modify it in an ideal manner, and is not corrected to the time stamp data that is actually lost.
  • the correction method can follow the time stamp data with large difference between the front and the back according to the time stamp data.
  • the ideal state reduces the gap, but the corrected data still has errors with the lost time stamp data, so that the unsatisfied time stamp data can be corrected as much as possible to meet the required time stamp data, thereby minimizing the clock recovery. error.
  • TimeSequence_2 TimeSequence_1+DisStgValue
  • TimeSequence_1 is the serial number of the previous timestamp data
  • TimeSequence_2 is the serial number of the subsequent timestamp data
  • TimeStamp_1 is the timestamp of the previous timestamp data
  • TimeStamp_2 is the timestamp of the latter timestamp data
  • DisStgValue is the sequence of the subsequent timestamp data.
  • FrameSpeed is the E1 frame rate, which uses synchronous TDM technology to match 30 voice channels and 2 control channels to a high-speed channel of 2.048 Mbits/s, one frame.
  • the length is 125us
  • ConjNum is a cascading number, which ranges from 1-40.
  • the sequence numbers of all the obtained time stamp data are arranged according to the preset interval, and the time stamps are also arranged in chronological order.
  • the recovery module 404 includes:
  • the obtaining submodule 4041 is configured to obtain a set of time stamp data with the most concentrated time stamp according to the correction result;
  • the recovery sub-module 4042 is configured to perform adaptive clock recovery on the acquired time stamp data.
  • the recovery module includes:
  • the operation sub-module is configured to calculate a frequency division factor according to the correction result, for example, calculating the set of time stamp data according to a preset algorithm to obtain a frequency division factor;
  • the recovery submodule is configured to perform adaptive clock recovery according to the frequency division factor.
  • the correction result in the obtaining sub-module 4041 refers to all acquired time-stamp data satisfying the time-stamp data that does not satisfy the law of the difference series, and satisfying the time-stamp data in which the spacing between the serial numbers is equal and the time-stamp is sequentially increased, from the time-stamp data.
  • the preset algorithm includes but is not limited to an adaptive clock recovery algorithm.
  • Embodiments of the present disclosure also provide a non-transitory computer readable storage medium storing computer executable instructions arranged to perform the method of any of the above embodiments.
  • the embodiment of the present disclosure further provides a schematic structural diagram of an electronic device.
  • the electronic device includes:
  • At least one processor 50 which is exemplified by a processor 50 in FIG. 5; and a memory 51, may further include a communication interface 52 and a bus 53.
  • the processor 50, the communication interface 52, and the memory 51 can complete communication with each other through the bus 53.
  • Communication interface 52 can be used for information transmission.
  • Processor 50 can invoke logic instructions in memory 51 to perform the methods of the above-described embodiments.
  • logic instructions in the memory 51 described above may be implemented in the form of software functional units and sold or used as separate products, and may be stored in a computer readable storage medium.
  • the memory 51 is used as a computer readable storage medium for storing software programs, computer executable programs, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure.
  • the processor 50 executes the function application and the data processing by executing software programs, instructions, and modules stored in the memory 51, that is, implementing the adaptive clock recovery method in the above method embodiments.
  • the memory 51 may include a storage program area and an storage data area, wherein the storage program area may store an operating system, an application required for at least one function; the storage data area may store data created according to use of the terminal device, and the like. Further, the memory 51 may include a high speed random access memory, and may also include a nonvolatile memory.
  • the technical solution of the embodiments of the present disclosure may be embodied in the form of a software product stored in a storage medium, including one or more instructions for causing a computer device ( All or part of the steps of the method described in the embodiments of the present disclosure are performed by a personal computer, a server, or a network device.
  • the foregoing storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like.
  • modules or steps of the present disclosure can be implemented by a general computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in a storage medium (ROM/RAM, diskette, optical disk) by a computing device, and in some cases The steps shown or described may be performed in an order different than that herein, or they may be separately fabricated into individual integrated circuit modules, or a plurality of the modules or steps may be implemented as a single integrated circuit module. Therefore, the present disclosure is not limited to any specific combination of hardware and software.
  • the adaptive clock recovery method and apparatus provided by the present disclosure reduce clock recovery errors, improve clock recovery efficiency and stability, reduce hardware requirements, and improve design flexibility.

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Abstract

本公开提供了一种自适应时钟恢复方法，包括：检测任一缓冲区中是否存满时戳数据，该时戳数据包括序列号和时间戳；若存满时戳数据，则获取缓冲区中的各时戳数据，并对获取的时戳数据进行修正使得各时戳数据的序列号按照预设间隔排列、时间戳按照时间先后顺序排列；根据修正结果进行自适应时钟恢复。通过本公开的实施，在进行自适应时钟恢复的过程中，通过对异常时戳数据进行修正，将未按照设定规则排序的时戳数据修正成理想时戳数据，从而降低时钟恢复的误差，提高时钟恢复的效率和稳定性。此外，本公开还提供了一种自适应时钟恢复装置，将原本由硬件实现的自适应时钟恢复功能通过该装置来完实现，从而降低对硬件的需求，提高设计的灵活度。

Description

一种自适应时钟恢复方法及装置 技术领域
本公开涉及通信技术领域，例如涉及一种自适应时钟恢复方法及装置。
背景技术
对于TDM(Time Division Multiplexing，时分复用)业务，可以配置多种业务时钟模式，包括系统时钟、差分时钟和自适应时钟，并且对时钟同步要求较高。自适应时钟模式不需要参考时钟，可以根据通信网络中收到报文的时戳数据自适应地恢复时钟，达到组网时钟的同步。
目前PTN(Packet Transport Network，分组传送网)设备中是将TDM业务数据采用以太网业务的封装形式封装后进行传送，其使用特定芯片或者基于NIOS系统(嵌入式处理器)架构来实现自适应时钟恢复功能，一般实现该功能的模块都会被加载到特定的芯片或者FPGA(Field Programmable Gate Array，现场可编程门阵列)中，在FPGA上集成软核功能，通过软件的配置以及硬件的处理来恢复自适应时钟，例如，软件配合硬件的处理要求使用中断的方式定时将基准时间累加值和时戳数据等信息传输给硬件，然后再由硬件将时戳值恢复成时钟信号。
但这样的处理方式需要耗费很多硬件资源，对硬件的要求也相对较高，同时，采用中断的方式会使得整个单板软件的设计受到制约，从而无法适应市场需求。此外，在进行自适应时钟恢复的过程中，因为网络故障、网络丢包、硬件不稳定性等问题，使得数据在传输或者存储的过程中会出现错误，而现有的自适应时钟恢复方式由于不能对报文中的异常时戳数据进行修正，从而影响时钟恢复的准确性和稳定性，降低时钟恢复时的运算效率。
发明内容
本公开要解决的主要技术问题是，提供一种自适应时钟恢复方法及装置，以解决相关技术中在进行自适应时钟恢复时无法对报文中的异常时戳数据进行修正，从而影响时钟恢复的准确性和稳定性，降低时钟恢复时的运算效率的技 术问题。
为解决上述技术问题，本公开提供一种自适应时钟恢复方法，包括：
检测任一缓冲区中是否存满时戳数据，所述时戳数据包括序列号和时间戳；
若存满时戳数据，获取所述缓冲区中的各时戳数据；
对获取的时戳数据进行修正使得各时戳数据的序列号按照预设间隔排列、时间戳按照时间先后顺序排列；
根据修正结果进行自适应时钟恢复。
在本公开一种实施例中，所述对获取的时戳数据进行修正包括：
判断所述缓冲区中各时戳数据的序列号是否按照预设间隔排列；
若未按照预设间隔排列，对未按照预设间隔排列的时戳数据进行修正。
在本公开一种实施例中，对未按照预设间隔排列的时戳数据按照如下方式进行修正：
后一时戳数据的序列号＝前一时戳数据的序列号+序列号差值；
后一时戳数据的时间戳＝前一时戳数据的时间戳+报文时延；
根据上述修正方式，对后续时戳数据依次进行修正。
在本公开一种实施例中，所述根据修正结果进行自适应时钟恢复可以为：
根据修正结果获取时间戳最集中的时戳数据；
将获取的时戳数据进行自适应时钟恢复。
在本公开一种实施例中，所述根据修正结果进行自适应时钟恢复可以为：
将根据修正结果计算出分频因子；
根据所述分频因子进行自适应时钟恢复。
在本公开一种实施例中，在所述检测任一缓冲区中是否存满时戳数据之前还包括：
当检测到任一端口配置自适应时钟模式的时分复用业务时，启用自适应时钟恢复功能。
本公开还一提供了一种自适应时钟恢复装置，包括：
缓冲区检测模块，被配置为检测任一缓冲区中是否存满时戳数据，所述时戳数据包括序列号和时间戳；
获取模块，被配置为若存满时戳数据，获取所述缓冲区中的各时戳数据；
修正模块，被配置为对获取的时戳数据进行修正使得各时戳数据的序列号按照预设间隔排列、时间戳按照时间先后顺序排列；
恢复模块，被配置为根据修正结果进行自适应时钟恢复。
在本公开一种实施例中，所述修正模块包括：
判断子模块，被配置为判断所述缓冲区中各时戳数据的序列号是否按照预设间隔排列；
修正子模块，被配置为若未按照预设间隔排列，对未按照预设间隔排列的时戳数据进行修正。
在本公开一种实施例中，对未按照预设间隔排列的时戳数据按照以下方式进行修正：
后一时戳数据的序列号＝前一时戳数据的序列号+序列号差值；
后一时戳数据的时间戳＝前一时戳数据的时间戳+报文时延；
根据上述修正方式，对后续时戳数据依次进行修正。
在本公开一种实施例中，所述恢复模块包括：
获取子模块，被配置为根据修正结果获取时间戳最集中的一组时戳数据；
恢复子模块，被配置为将获取的时戳数据进行自适应时钟恢复。
在本公开一种实施例中，所述恢复模块包括：
运算子模块，被配置为根据修正结果计算出分频因子；
恢复子模块，被配置为根据所述分频因子进行自适应时钟恢复。
在本公开一种实施例中，还包括：
业务检测模块，被配置为在检测任一缓冲区中是否存满时戳数据之前，当检测到任一端口配置自适应时钟模式的时分复用业务时，启用自适应时钟恢复功能。
本公开的有益效果是：
本公开提供了一种自适应时钟恢复方法，包括：检测任一缓冲区中是否存满时戳数据，该时戳数据包括序列号和时间戳；若存满时戳数据，则获取缓冲区中的各时戳数据，并对获取的时戳数据进行修正使得各时戳数据的序列号按照预设间隔排列、时间戳按照时间先后顺序排列；根据修正结果进行自适应时钟恢复。通过本公开的实施，在进行自适应时钟恢复的过程中，通过对异常时戳数据进行修正，将未按照设定规则排序的时戳数据修正成理想时戳数据，在提高时钟恢复效率的同时也提高了时钟恢复的稳定性。
本公开还提供了一种自适应时钟恢复装置，将原本由硬件实现的自适应时钟恢复功能通过该装置来完实现，从而降低对硬件的需求，不占用额外的硬件资源以降低设备成本，进而提高设计的灵活度。
本公开实施例还提供了一种非暂态计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述方法。
本公开实施例还提供了一种电子设备，包括：
至少一个处理器；以及
与所述至少一个处理器通信连接的存储器；其中，
所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器执行上述的方法。
附图概述
图1为本公开实施例一提供的一种自适应时钟恢复方法流程图；
图2为本公开实施例一提供的PTN网络中自适应时钟对TDM业务恢复过程示意图；
图3为本公开实施例一提供的一种启用自适应时钟恢复功能的流程图；
图4为本公开实施例二提供的一种自适应时钟恢复装置示意图；以及
图5为本公开实施例提供的电子设备的结构示意图。
具体实施方式
下面通过实施方式结合附图对本公开进行详细说明。
实施例一：
首先，对本实施例中提到的是时戳数据进行说明，该时戳数据是64bit的数据，前16bit是时戳数据的序列号，后48bit是时戳数据的时间戳；此外，该时戳数据包含于传输的报文中。
然后本实施例提供了一种自适应时钟恢复方法，请参见图1，其恢复步骤可以如下：
S101，检测任一缓冲区中是否存满时戳数据，该时戳数据包括序列号和时间戳；
S102，若存满时戳数据，获取缓冲区中的各时戳数据；
S103，对获取的时戳数据进行修正使得各时戳数据的序列号按照预设间隔排列、时间戳按照时间先后顺序排列；
S104，根据修正结果进行自适应时钟恢复。
基于上述自适应时钟恢复步骤，在进行自适应时钟恢复的过程中，通过对异常时戳数据进行修正，将未按照设定规则排序的时戳数据修正成理想时戳数据，在提高时钟恢复效率的同时也提高了时钟恢复的稳定性。其中，异常时戳数据是指，在对报文中的时戳数据进行传输时由于网络故障等原因导致部分数据丢包，或者在向硬件存储时戳数据时因为硬件的不稳定性导致部分数据出现错误，使得部分时戳数据中的序列号和时间戳不能按照正常规则存储。
如图2所示，自适应时钟的恢复过程可以如下：
PTN接入设备将E1业务流分割成若干个数据段，然后将若干个数据段按标准格式封装到PTN网络的多个承载报文中，TDM业务以报文形式通过PTN网络依次传送至另一PTN接入设备，该报文中携带时戳数据，时戳数据中包括序列号和接收报文时的时间点；然后另一PTN接入设备对接收的各报文进行拆分，得到若干个数据段，并通过若干数据段恢复出E1业务流。
S101步骤中的缓冲区可以为逻辑FPGA中的片区，该逻辑FPGA为硬件，总共分配4个片区来存储时戳数据，每个片区可存储255个时戳数据，且只有 在一个片区全部存满的情况下，才允许软件读取整片数据，即当检测到其中一个片区满标志位被置位，则软件会取出该片区所有的时戳数据。此外，本实施例中的逻辑FPGA仅被配置为对时戳数据进行存储，对于数据的处理是通过软件实现的；本实施例中的时戳数据由序列号和时间戳组成，且各时戳数据的序列号理想情况下是等间距的(规律性的依次递增或依次递减)，时间戳是此刻收到报文的时间点。需要明白的是，上述4个片区、255个其仅用于对本实施例做出说明，不能认定取值仅限于上述说明。
在S102步骤中，获取到缓冲区中的所有时戳数据后，需要对各时戳数据的序列号按照递增或递减的形式进行排序，这样可以通过将时戳数据的序列号按照设定规则排序，识别出缓冲区中的所有时戳数据的序列号之间是否等间距、时间戳是否按照从小到大的顺序排列，从而判断在报文传输的过程中是否出现丢包或者因为硬件的不稳定导致数据存储错误的情况。所述等间距即为各时戳数据的序列号之间呈等差数列，时间戳与序列号一一对应，因此，若序列号按照从大到小的顺序排列，则序列号大的时间戳相对较小；若序列号按照从小到大的顺序排列，则序列号小的时间戳相应较小。
对获取的所有时戳数据排序后，检测所有时戳数据的序列号是否均满足等差数列规律，若满足等差数列规律，说明该缓冲区中所有的时戳数据在传输时都是连续的，在进行报文传输的过程中，未出现丢包或硬件不稳定的情况；相反，若存在序列号不满足等差数列规律的时戳数据，则表明在进行报文传输的过程，有些报文丢包或对报文中的时戳数据进行存储时因为硬件原因导致后续报文中的时戳数据的序列号不能满足等差数列规律。应该明白的是，在进行报文传输的过程中，由于前后报文中的序列号均等间距，且序列号与时戳值一一对应，不会因为丢包或者硬件的不稳定性影响后续时戳数据中的序列号和时间戳。因此，若获取的时戳数据不能满足等差数列规律，就可说明时戳数据出现异常，如丢包或者硬件不稳定性，从而影响整个时戳数据的连续性。
在S103步骤中，预设间隔可以是指各序列号之间不完全等间隔，例如：在某一时间段中，时戳数据的序列号之间间隔为A；在该时间段之后，可将预设间隔调整为B，使得后续的时戳数据的序列号间隔变成B。例如，该预设间隔为等差数列中的比值，即前后时戳数据的序列号差值，时戳数据满足等差数列规律，下文将以等差数列规律为例对时戳数据进行修正的过程进行说明。
当发现获取的所有时戳数据中出现不满足等差数列规律的时戳数据时，对这些时戳数据进行修正，将修正后的时戳数据作为下一时戳数据，丢弃之前存储的时戳数据，即将未满足等差数列规律的时戳数据丢弃，可以按照如下公式进行修正：
后一时戳数据的序列号＝前一时戳数据的序列号+序列号差值；
后一时戳数据的时间戳＝前一时戳数据的时间戳+报文的时延。
上述公式针对当前不满足等差数列规律的时戳数据进行修正，对于该时戳数据之后的时戳数据，若同样不满足等差数列规律，也按照上述公式进行修正，对于后一时戳数据，其前一时戳数据的序列号即为当前时戳数据的序列号，时间戳即为当前时戳数据的时间戳。应该明白的是，对于不满足等差数列规律的时戳数据，本实施采用的修正方式是将其以理想的方式进行修正，并非修正成实际意义上丢掉的时戳数据。该修正方式可以将前后相差较大的时戳数据按照理想状态减小差距，但修正后的数据与丢掉的时戳数据依然存在误差，这样可以将不满足的时戳数据尽可能的修正成满足要求的时戳数据，从而最小可能的降低时钟恢复的误差。
上述公式完整过程可以如下：
TimeSequence_2＝TimeSequence_1+DisStgValue
Figure PCTCN2017072903-appb-000001
其中，TimeSequence_1为前一时戳数据的序列号；TimeSequence_2为后一时戳数据的序列号；TimeStamp_1为前一时戳数据的时间戳；TimeStamp_2为后一时戳数据的时间戳；DisStgValue为后一时戳数据的序列号与前一时戳数据的序列号之间的差值；FrameSpeed为E1帧速率，其采用同步TDM技术将30个语音信道和2个控制信道复合在一条2.048Mbits/s的高速信道上，一帧的长度为125us；ConjNum为级联数，其取值范围为1-40。
可以对不满足等差数列规律的时戳数据进行修正后，使得获取的所有时戳数据的序列号都满足等差数列规律，即各时戳数据的序列号之间间距相等，其时间戳也依次由小到大递增。然后，在S104步骤中，修正结果是指将不满足等差数列规律的时戳数据修正后，满足序列号之间间距相等、时间戳依次递增的 所有获取的时戳数据，从这些时戳数据中获取时间戳最集中的一组时戳数据，并将该组时戳数据按照预设算法进行计算，得到分频因子，然后根据分频因子对自适应时钟进行恢复。从这些时戳数据中获取时间戳最集中的一组时戳数据，这样，这一组或一片时戳数据可以正常反应出这段时间内时间的变化情况，在进行时钟恢复时时间误差也相对较小，从而更精准的对自适应时钟进行恢复。需要注意的是，所述预设算法包括但不限于自适应时钟恢复算法。
在S101步骤之前，还可以包括创建自适应时钟模式的TDM业务，在创建的过程中，配置报文的级联数、业务通道编号以及自适应时钟恢复的相关信息。然后对各个端口进行检测，判断该端口是否传输自适应时钟模式的TDM业务，若是自适应时钟模式的TDM业务，则启用自适应时钟恢复功能，请参见图3，启用过程可以如下：
S301，遍历各端口并判断是否传输TDM业务，若传输TDM业务，执行S302；若不传输TDM业务，执行S301；
S302，检测该TDM业务模式是否为自适应时钟模式，若是自适应时钟模式，执行S303；若不是自适应时钟模式，执行S302；
S303，启用自适应时钟恢复功能。
在启用自用适应时钟恢复后，才会执行图1中的流程。例如，在TDM业务中包括报文的级联数和业务通道编号，其中，根据业务通道编号和级联数才能获取对应时戳数据，从而实现图1中整个处理流程。根据级联数为逻辑FPGA配置丢包策略值(即序列号差值)。其中，丢包策略值的计算公式可以如下：
Figure PCTCN2017072903-appb-000002
其中，DisStgValue为丢包策略值(即序列号差值)；FrameSpeed为E1帧速率，8000帧/s；TimeStampNum为一个片区存储的时间戳个数，共255个；ConjNum为级联数，其取值范围为1-40。
逻辑FPGA根据上述计算公式得出的丢包策略值，将TDM业务中报文的时戳数据进行存储，从而使得时戳数据满足等差数列规律。
实施例二：
本实施例提供了一种自适应时钟恢复装置，请参见图4，该装置包括：
缓冲区检测模块401，被配置为检测任一缓冲区中是否存满时戳数据，该时戳数据包括序列号和时间戳；
获取模块402，被配置为若存满时戳数据，获取缓冲区中的各时戳数据；
修正模块403，被配置为对获取的时戳数据进行修正使得各时戳数据的序列号按照预设间隔排列、时间戳按照时间先后顺序排列；
恢复模块404，被配置为根据修正结果进行自适应时钟恢复。
其中，预设间隔是指各序列号之间不完全等间隔，例如：在某一时间段中，时戳数据的序列号之间间隔为A；在该时间段之后，可将预设间隔调整为B，使得后续的时戳数据的序列号间隔变成B。例如，该预设间隔为等差数列中的比值，即前后时戳数据的序列号差值，时戳数据满足等差数列规律，下文将以等差数列规律为例对时戳数据进行修正的过程进行说明。
通过本实施例的自适应时钟恢复装置，该自适应时钟恢复装置应用于PTN设备中，可以在软件层面进行自适应时钟恢复，使其在未启用自适应时钟恢复功能的情况下，不运行本装置；当启用后，使其通过软件实现完整的自适应时钟恢复功能，从而不占用额外的硬件资源，降低设备成本，进而提高设计的灵活度。
该装置还包括业务检测模块405，该业务检测模块405被配置为在检测任一缓冲区中是否存满时戳数据之前，当检测到任一端口配置自适应时钟模式的时分复用业务时，启用自适应时钟恢复功能。
在通过自适应时钟恢复装置实现时钟恢复的功能时，可以首先将装置初始化，如初始化装至内部的喂狗操作，初始化IP时钟相关的组件，初始化状态机等。其中，喂狗操作是指清空看门狗计数器，例如，在程序正常运行时，需要在看门狗计数器达到最大值之前将其清空，使其重新开始计数。然后，启用装置中的100ms定时周期的定时器，定时查询端口是否传输TDM业务，且业务时钟是否为自适应时钟类型；同时定时对逻辑FPGA的缓冲区进行检测，确认缓冲区中的时戳数据是否存满。与此同时，启用装置中的另一定时器，该定时器定时周期为20ms，被配置为实现计时的功能，执行网络选包、丢包检测、时戳数据收齐后的对比计算等操作，时钟每个阶段的状态切换等都是按照该计数单 位为基础来进行的。本实施例中定时器定时周期包括但不限于上述数值，可根据实际需要进行合理设置，这里不做限定。
初始化完成后开始定时，然后单板软件接收TDM业务创建指令，并指派给SDK(Software Development，软件开发工具包)进行TDM业务创建。SDK在创建自适应时钟模式的TDM业务过程中，会配置针对自适应时钟恢复装置的信息，并配置报文的级联数和业务通道编号，并将配置的级联数和业务通道编号传输给自适应时钟恢复装置，然后装置根据级联数为逻辑FPGA配置丢包策略值，逻辑FPGA根据丢包策略值对时戳数据进行存储。该丢包策略值请参见实施例一，这里不再赘述。当装置检测到各端口中传输了自适应时钟模式的TDM业务，就会开启自适应时钟装置对时戳数据进行处理并进行时钟恢复。
如图2所示，自适应时钟的恢复过程如下：
PTN接入设备将E1业务流(即需要承载的TDM业务)分割成若干个数据段，然后将若干个数据段按标准格式封装到PTN网络的多个承载报文中，TDM业务以报文形式通过PTN网络依次传送至另一PTN接入设备，该报文中携带时戳数据，时戳数据中包括序列号和接收报文时的时间点；然后另一PTN接入设备对接收的各报文进行拆分，得到若干个数据段，并通过若干数据段恢复出E1业务流。
上述缓冲区可以为逻辑FPGA中的片区，该逻辑FPGA为硬件，总共分配4个片区来存储时戳数据，每个片区可存储255个时戳数据，且只有在一个片区全部存满的情况下，才允许软件读取整片数据，即当检测到其中一个片区满标志位被置位，则软件会取出该片区所有的时戳数据。此外，本实施例中的逻辑FPGA仅被配置为对时戳数据进行存储，对于数据的处理是通过软件实现的；本实施例中的时戳数据由序列号和时间戳组成，且各时戳数据的序列号理想情况下是等间距的(规律性的依次递增或依次递减)，时间戳是此刻收到报文的时间点。需要明白的是，上述4个片区、255个其仅用于对本实施例做出说明，不能认定取值仅限于上述说明。
获取模块402获取到缓冲区中的所有时戳数据后，需要对各时戳数据的序列号按照递增或递减的形式进行排序，这样可以通过将时戳数据的序列号按照设定规则排序，识别出缓冲区中的所有时戳数据的序列号之间是否等间距、时间戳是否按照从小到大的顺序排列，从而判断在报文传输的过程中是否出现丢 包的情况。所述等间距即为各时戳数据的序列号之间呈等差数列，时间戳与序列号一一对应，因此，若序列号按照从大到小的顺序排列，则序列号大的时间戳相对较小；若序列号按照从小到大的顺序排列，则序列号小的时间戳相应较小。
对获取的所有时戳数据排序后，检测所有时戳数据的序列号是否均满足等差数列规律，若满足等差数列规律，说明该缓冲区中所有的时戳数据在传输时都是连续的，在进行报文传输的过程中未出现丢包的情况，或者在数据存储的过程中未出现错误；相反，若存在序列号不满足等差数列规律的时戳数据，则表明时戳数据出现异常，导致后续报文中的时戳数据的序列号不能满足等差数列规律。应该明白的是，在进行报文传输的过程中，由于前后报文中的序列号均等间距，且序列号与时戳值一一对应，不会因为丢包或硬件的不稳定性而影响后续时戳数据中的序列号和时间戳。
修正模块403可以包括：
判断子模块4031，被配置为判断所述缓冲区中各时戳数据的序列号是否按照预设间隔排列；
修正子模块4032，被配置为若未按照预设间隔排列，对未按照预设间隔排列的时戳数据进行修正。
当判断子模块4031发现获取的所有时戳数据中出现未按照预设间隔排列的时戳数据时，对这些时戳数据进行修正，将修正后的时戳数据作为下一时戳数据，丢弃之前存储的时戳数据，即将未按照预设间隔排列的时戳数据丢弃，可以按照如下公式进行修正：
后一时戳数据的序列号＝前一时戳数据的序列号+序列号差值；
后一时戳数据的时间戳＝前一时戳数据的时间戳+报文的时延。
上述公式针对当前未按照预设间隔排列的时戳数据进行修正，对于该时戳数据之后的时戳数据，若同样未按照预设间隔排列，也以上述公式进行修正，对于后一时戳数据，其前一时戳数据的序列号即为当前时戳数据的序列号，时间戳即为当前时戳数据的时间戳。应该明白的是，对于未按照预设间隔排列的时戳数据，本实施采用的修正方式是将其以理想的方式进行修正，并非修正成实际意义上丢掉的时戳数据。该修正方式可以将前后相差较大的时戳数据按照 理想状态减小差距，但修正后的数据与丢掉的时戳数据依然存在误差，这样可以将不满足的时戳数据尽可能的修正成满足要求的时戳数据，从而最小可能的降低时钟恢复的误差。
上述公式完整过程可以如下：
TimeSequence_2＝TimeSequence_1+DisStgValue
Figure PCTCN2017072903-appb-000003
其中，TimeSequence_1为前一时戳数据的序列号；TimeSequence_2为后一时戳数据的序列号；TimeStamp_1为前一时戳数据的时间戳；TimeStamp_2为后一时戳数据的时间戳；DisStgValue为后一时戳数据的序列号与前一时戳数据的序列号之间的差值；FrameSpeed为E1帧速率，其采用同步TDM技术将30个语音信道和2个控制信道符合在一条2.048Mbits/s的高速信道上，一帧的长度为125us；ConjNum为级联数，其取值范围为1-40。
可以对未按照预设间隔排列的时戳数据进行修正后，使得获取的所有时戳数据的序列号都按照预设间隔排列，其时间戳也按照时间先后顺序排列。
然后，恢复模块404包括：
获取子模块4041，被配置为根据修正结果获取时间戳最集中的一组时戳数据；
恢复子模块4042，被配置为将获取的时戳数据进行自适应时钟恢复。
或者，恢复模块包括：
运算子模块，被配置为根据修正结果计算出分频因子，例如，将所述一组时戳数据按照预设算法进行计算，得到分频因子；
恢复子模块，被配置为根据所述分频因子进行自适应时钟恢复。
获取子模块4041中的修正结果是指将不满足等差数列规律的时戳数据修正后，满足序列号之间间距相等、时间戳依次递增的所有获取的时戳数据，从这些时戳数据中获取时间戳最集中的一组时戳数据，并将该组时戳数据按照预设算法进行计算，得到分频因子，然后根据分频因子对自适应时钟进行恢复。从这些时戳数据中获取时间戳最集中的一组时戳数据，这样，这一组或一片时戳 数据可以正常反应出这段时间内时间的变化情况，在进行时钟恢复时时间误差也相对较小，从而更精准的对自适应时钟进行恢复。需要注意的是，所述预设算法包括但不限于自适应时钟恢复算法。
本公开实施例还提供了一种非暂态计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述任一实施例中的方法。
本公开实施例还提供了一种电子设备的结构示意图。参见图5，该电子设备包括：
至少一个处理器(processor)50，图5中以一个处理器50为例；和存储器(memory)51，还可以包括通信接口(Communications Interface)52和总线53。其中，处理器50、通信接口52、存储器51可以通过总线53完成相互间的通信。通信接口52可以用于信息传输。处理器50可以调用存储器51中的逻辑指令，以执行上述实施例的方法。
此外，上述的存储器51中的逻辑指令可以通过软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。
存储器51作为一种计算机可读存储介质，可用于存储软件程序、计算机可执行程序，如本公开实施例中的方法对应的程序指令/模块。处理器50通过运行存储在存储器51中的软件程序、指令以及模块，从而执行功能应用以及数据处理，即实现上述方法实施例中的自适应时钟恢复方法。
存储器51可包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据终端设备的使用所创建的数据等。此外，存储器51可以包括高速随机存取存储器，还可以包括非易失性存储器。
本公开实施例的技术方案可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括一个或多个指令用以使得一台计算机设备(可 以是个人计算机，服务器，或者网络设备等)执行本公开实施例所述方法的全部或部分步骤。而前述的存储介质可以是非暂态存储介质，包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等多种可以存储程序代码的介质，也可以是暂态存储介质。
显然，本领域的技术人员应该明白，上述本公开的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储介质(ROM/RAM、磁碟、光盘)中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。所以，本公开不限制于任何特定的硬件和软件结合。
以上内容是结合实施方式对本公开所作的详细说明，不能认定本公开的实施只局限于这些说明。对于本公开所属技术领域的普通技术人员来说，在不脱离本公开实施例范围的前提下，还可以做出若干简单推演或替换，都应当视为属于本公开的保护范围。
工业实用性
本公开提供的自适应时钟恢复方法及装置降低时钟恢复的误差，提高时钟恢复的效率和稳定性，降低对硬件的需求，提高设计的灵活度。

Claims (13)

  1. 一种自适应时钟恢复方法，包括：
    检测任一缓冲区中是否存满时戳数据，所述时戳数据包括序列号和时间戳；
    若存满时戳数据，获取所述缓冲区中的各时戳数据；
    对获取的时戳数据进行修正使得各时戳数据的序列号按照预设间隔排列、时间戳按照时间先后顺序排列；
    根据修正结果进行自适应时钟恢复。
  2. 如权利要求1所述的方法，其中，所述对获取的时戳数据进行修正包括：
    判断所述缓冲区中各时戳数据的序列号是否按照预设间隔排列；
    若未按照预设间隔排列，对未按照预设间隔排列的时戳数据进行修正。
  3. 如权利要求2所述的方法，其中，对未按照预设间隔排列的时戳数据按照以下方式进行修正：
    后一时戳数据的序列号＝前一时戳数据的序列号+序列号差值；
    后一时戳数据的时间戳＝前一时戳数据的时间戳+报文时延；
    根据上述修正方式，对后续时戳数据依次进行修正。
  4. 如权利要求1-3任一项所述的方法，其中，所述根据修正结果进行自适应时钟恢复为：
    根据修正结果获取时间戳最集中的时戳数据；
    将获取的时戳数据进行自适应时钟恢复。
  5. 如权利要求1-3任一项所述的方法，其中，所述根据修正结果进行自适应时钟恢复为：
    根据修正结果计算出分频因子；
    根据所述分频因子进行自适应时钟恢复。
  6. 如权利要求1-3任一项所述的方法，其中，在所述检测任一缓冲区中是否存满时戳数据之前还包括：
    当检测到任一端口配置自适应时钟模式的时分复用业务时，启用自适应时钟恢复功能。
  7. 一种自适应时钟恢复装置，包括：
    缓冲区检测模块，被配置为检测任一缓冲区中是否存满时戳数据，所述时戳数据包括序列号和时间戳；
    获取模块，被配置为若存满时戳数据，获取所述缓冲区中的各时戳数据；
    修正模块，被配置为对获取的时戳数据进行修正使得各时戳数据的序列号按照预设间隔排列、时间戳按照时间先后顺序排列；
    恢复模块，被配置为根据修正结果进行自适应时钟恢复。
  8. 如权利要求7所述的装置，其中，所述修正模块包括：
    判断子模块，被配置为判断所述缓冲区中各时戳数据的序列号是否按照预设间隔排列；
    修正子模块，被配置为若未按照预设间隔排列，对未按照预设间隔排列的时戳数据进行修正。
  9. 如权利要求8所述的装置，其中，对未按照预设间隔排列的时戳数据按照以下方式进行修正：
    后一时戳数据的序列号＝前一时戳数据的序列号+序列号差值；
    后一时戳数据的时间戳＝前一时戳数据的时间戳+报文时延；
    根据上述修正方式，对后续时戳数据依次进行修正。
  10. 如权利要求7-9任一项所述的装置，其中，所述恢复模块包括：
    获取子模块，被配置为根据修正结果获取时间戳最集中的时戳数据；
    恢复子模块，被配置为将获取的时戳数据进行自适应时钟恢复。
  11. 如权利要求7-9任一项所述的装置，其中，所述恢复模块包括：
    运算子模块，被配置为根据修正结果计算出分频因子；
    恢复子模块，被配置为根据所述分频因子进行自适应时钟恢复。
  12. 如权利要求7-9任一项所述的装置，还包括：
    业务检测模块，被配置为在检测任一缓冲区中是否存满时戳数据之前，当检测到任一端口配置自适应时钟模式的时分复用业务时，启用自适应时钟恢复功能。
  13. 一种非暂态计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行权利要求1-6中任一项的方法。
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