WO2017161960A1

WO2017161960A1 - Logic gate circuit based on magnetic field triggered superlattice phase-change unit

Info

Publication number: WO2017161960A1
Application number: PCT/CN2017/071756
Authority: WO
Inventors: 程晓敏; 陆彬; 冯金龙; 缪向水
Original assignee: 华中科技大学
Priority date: 2016-03-23
Filing date: 2017-01-19
Publication date: 2017-09-28
Also published as: CN105845173B; CN105845173A

Abstract

The present invention discloses a logic gate circuit based on a magnetic field triggered superlattice phase-change unit. The logic gate circuit comprises a magnetic field generation module, a superlattice phase-change module, a voltage divider resistor and a controllable switch element; a switch of a resistance state of the superlattice phase-change module is controlled by applying a pulsed magnetic field and a voltage pulse; the voltage divider resistor is connected to the superlattice phase-change module, and a connection point thereof acts as an output terminal of the logic gate circuit; the controllable switch element is disposed on a connection line between the superlattice phase-change module and the voltage divider resistor; by switching on the controllable switch element, logic writing is carried out by applying high-voltage or low-voltage pulse signals to the superlattice phase-change module; by switching off the controllable switch element, a logic operation result is read from an output terminal of the logic gate circuit; logic functions such as AND, OR, NOT, NOR, NAND, XNOR, XOR, implication, inverse implication, multi-terminal AND, multi-terminal NAND, multi-terminal OR, and multi-terminal NOR can be achieved; the circuit structure is simple and achieves a range of logic functions, and the circuit is simple in structure, low in power consumption and non-volatile.

Description

Logic gate circuit of superlattice phase change unit based on magnetic field trigger

[Technical Field]

The invention belongs to the field of digital circuits, and more particularly to a logic gate circuit based on a magnetic field triggered superlattice phase change unit.

【Background technique】

The architecture followed by modern computers is the von Neumann machine structure, which separates processing and storage, which greatly restricts the performance of computer processing real-time massive data, resulting in "von Neumann performance bottleneck." To solve this problem, non-volatile memory based logic devices have emerged. Compared with CMOS circuit memory, this type of device has a simpler structure, faster read/write speed, higher durability, lower power consumption, and can maintain data after power-off; and, non-volatile The memory has a distinction between high resistance and low resistance. It can represent

logic states

0 and 1, thus realizing the operation of state logic, and the result of the operation can be directly saved through its resistance, thereby realizing the fusion of information processing and storage.

The logic devices based on non-volatile memory in the prior art are mainly implemented by phase change memory PCM, magnetic random access memory MRAM, and resistive memory RRAM; phase change memory utilizes chalcogenide (typical material GST) in crystalline state and non- Crystalline large difference in conductivity to achieve data storage, fully compatible with standard CMOS technology in process, has broad application prospects in low voltage, low power, high speed and embedded memory; but set/reset pulse of GST material The current is large, and it is necessary to realize the phase change by the driving of the transistor, thereby causing a large power consumption. The magnetic random access memory uses an external magnetic field to change the magnetization direction of the free layer of the MTJ (Magnetic Tunnel Junction), thereby changing the resistance of the memory cell, achieving infinite erasing, and fast reading and writing speed, but the TMR of the magnetic tunnel junction The value of (Tunnel Magneto Resistance) is relatively small, requiring complex readout circuits to distinguish its resistance state, and the process of preparing MTJ is relatively complicated; the resistive memory utilizes the characteristics of resistive effect of materials under electrical excitation. The processing and storage are simple, the production cost is low, the reading and writing speed is fast, but the stability of the device is not high.

[Summary of the Invention]

In view of the above defects or improvement requirements of the prior art, the present invention provides a logic gate circuit based on a magnetic field triggered superlattice phase change unit, which solves the complicated structure and high power consumption of the existing non-volatile memory based logic device. Technical problems with poor stability.

To achieve the above object, according to an aspect of the present invention, a logic gate circuit for a superlattice phase change unit based on a magnetic field trigger is provided, including a superlattice phase change module, a voltage dividing resistor, and a controllable switching element;

The superlattice phase change module is connected with the voltage dividing resistor, and the connection point is used as an output terminal based on the logic gate circuit; the controllable switching element is disposed on a connection line between the superlattice phase change module and the voltage dividing resistor for controlling The flow direction of the voltage pulse: only flows through the superlattice phase change module or simultaneously flows through the superlattice phase change module and the voltage dividing resistor;

Controlling the resistance state switching by applying a pulsed magnetic field and a voltage pulse to the superlattice phase change module;

By closing the controllable switching element, after applying a reset voltage pulse to the superlattice phase change module, writing it to the high-impedance state, applying a high or low voltage pulse signal to the superlattice phase change module to simulate

logic

0 or 1 to achieve logic write The output voltage pulse amplitude is obtained at the output of the logic gate circuit to read the logical operation result by disconnecting the controllable switching element and applying a read voltage pulse to the superlattice phase change module.

Preferably, the logic gate circuit further includes a magnetic field generating module for generating a stable and controllable pulse magnetic field.

Preferably, the magnetic field generating module is implemented by a solenoid, and a voltage pulse is applied to the solenoid to generate a pulsed magnetic field.

Preferably, the superlattice phase change module comprises a superlattice phase change unit; and the resistive state is controlled by a voltage pulse in combination with a pulsed magnetic field acting on the superlattice phase change unit;

When the module includes a superlattice phase change unit, a voltage pulse is applied to the superlattice phase change unit, and the resistance state is controlled by the pulse magnetic field; the magnetic field triggered superlattice is formed The logic gate of the phase change unit can realize the logic of double-ended and single-ended inputs. Features;

When the module includes two series-connected superlattice phase change units, two voltage pulse sections are applied to the two superlattice phase change units, and the control of the resistive state is realized by combining the pulsed magnetic fields; The logic gate circuit of the magnetic field-triggered superlattice phase change unit can realize the logic functions of the three-terminal and four-terminal input.

Preferably, the superlattice phase change material used in the superlattice phase change unit is a combination of two or more phase change materials in a superlattice manner; and has the following characteristics: after adding a magnetic field, the superlattice phase change unit The threshold voltage from the amorphous state to the crystalline phase transition increases significantly; in the corresponding RV characteristic curve, the amplitude of the set/reset voltage pulse also increases significantly; thus, the resistance of the superlattice phase change unit is added. The combined effect of voltage pulse and magnetic field, with or without a magnetic field (applying magnetic field to characterize logic 1, without magnetic field characterizing logic 0), select different voltage pulse amplitudes (higher pulse amplitude representation logic 1, The lower pulse amplitude characterizes the logic 0), allowing the superlattice phase change cell to be in a high impedance or low impedance state, thereby characterizing the

logic outputs

0 and 1 for logic operation.

Preferably, a logic gate circuit based on a magnetic field triggered superlattice phase change unit comprises a superlattice phase change unit, a solenoid, a controllable switching element and a resistor;

Wherein the first end of the superlattice phase change unit is the first input end of the logic gate circuit, and the input end of the solenoid is the second input end of the logic gate circuit; the first end of the controllable switching element and the superlattice The second end of the phase change unit is connected to the first end of the resistor, and the connection point is the output end of the logic gate circuit; the second end of the controllable switching element is grounded, and the second end of the resistor is grounded;

By closing the controllable switching element, inputting a reset voltage pulse at the first input terminal, writing the superlattice phase change unit to a high impedance state to reset it, and inputting the first voltage pulse to the first input terminal to simulate

logic

0 or 1 And inputting a second voltage pulse

analog logic

0 or 1 at the second input terminal, generating a pulse magnetic field by applying a second voltage pulse to the solenoid; and applying a first voltage pulse and a pulse magnetic field to the superlattice phase change unit, It implements resistive switching to implement logical AND, NOT, or NOT, the same or the inverse implication function;

The output voltage pulse amplitude is obtained at the output of the logic gate circuit to read the logic operation result by disconnecting the controllable switching element and inputting a low level read voltage pulse at the first input terminal.

Preferably, the resistance of the resistor in the logic gate circuit is a crystalline resistance of the superlattice phase change unit.

Wherein the first end of the resistor is the first input end of the logic gate circuit, and the input end of the solenoid is the second input end of the logic gate circuit; one end of the controllable switching element is connected to the first end of the resistor, and the other end is connected The second end of the resistor is connected; one end of the superlattice phase change unit is connected to the second end of the resistor, the connection end is used as the output end of the logic gate circuit, and the other end of the superlattice phase change unit is grounded;

logic

0 or 1 And inputting a second voltage pulse

analog logic

0 or 1 at the second input terminal, generating a pulse magnetic field by applying a second voltage pulse to the solenoid; and applying a first voltage pulse and a pulse magnetic field to the superlattice phase change unit, It implements resistive switching to implement logical OR, NAND, XOR, and implication functions;

Preferably, the resistance of the resistor in the logic gate circuit is an amorphous resistance of a superlattice phase change unit.

Preferably, a logic gate circuit based on a magnetic field triggered superlattice phase change unit includes a first superlattice phase change unit, a second superlattice phase change unit, a first solenoid, and a second solenoid , controllable switching element and resistor;

Wherein the first end of the first superlattice phase change unit serves as a first input end of the logic gate circuit, The input end of the first solenoid is used as the second input end of the logic gate circuit, the input end of the second solenoid is the third input end of the logic gate circuit, and the first end of the second superlattice phase change unit is used as the logic a fourth input end of the gate circuit; one end of the controllable switching element is connected to the second end of the first superlattice phase change unit and the second end of the second superlattice phase change unit, and the other end of the controllable switching element is grounded One end of the resistor is connected to the first end of the second superlattice phase change unit, and the other end of the resistor is grounded; the first end of the second superlattice phase change unit is used as an output end of the logic gate circuit;

By closing the controllable switching element, simultaneously inputting a reset voltage pulse at the first input end and the fourth input end, writing the first superlattice phase change unit and the second superlattice phase change unit to a high impedance state to reset After the first input terminal inputs the first voltage pulse

analog logic

0 or 1, the second input terminal inputs the second voltage pulse

analog logic

0 or 1, and the third input terminal inputs the third voltage pulse

analog logic

0 or 1, the fourth The input terminal inputs a fourth voltage pulse

analog logic

0 or 1, and the second voltage pulse and the third voltage pulse act on the solenoid to generate a pulse magnetic field; and the first voltage pulse, the fourth voltage pulse and the pulse magnetic field act on the two super a lattice phase change unit that implements a resistive state switching to implement a logical AND or non-function of the four-terminal input;

When the second voltage pulse and the third voltage pulse are completely identical, the logical input and/or non-function of the three-terminal input is realized by combining the second input end and the third input end into one input end;

Preferably, the resistance of the resistor in the logic gate circuit is a crystalline resistance of any one of the superlattice phase change units.

Preferably, a logic gate circuit based on a magnetic field triggered superlattice phase change unit includes a first superlattice phase change unit, a second superlattice phase change unit, a first solenoid, and a second solenoid a first controllable switching element, a second controllable switching element, a third controllable switching element, and a resistor;

Wherein the first end of the resistor is the first input end of the logic gate circuit, the input end of the first solenoid is the second input end of the logic gate circuit, and the input end of the second solenoid is used as the logic gate circuit a third input end, the first end of the second superlattice phase change unit is a fourth input end of the logic gate circuit; one end of the first controllable switching element is connected to the first end of the resistor, and the other end is connected to the resistor a two-terminal connection; a first end of the first superlattice phase change unit is connected to the second end of the resistor, and a connection end thereof is used as an output end of the logic gate circuit; and the first end of the second controllable switching element is coupled with the first super crystal The second end of the phase change unit is connected to the second end of the second lattice phase change unit, and the second end of the second controllable switching element is grounded; the first end of the third controllable switching element is connected to the second lattice phase The first end of the variable unit is connected, and the second end of the third controllable switching element is grounded;

Passing the first controllable switching element and the second controllable switching element, and disconnecting the third controllable switching element, simultaneously inputting a reset voltage pulse at the first input end and the fourth input end, the first superlattice After the phase change unit and the second superlattice phase change unit are written to the high impedance state to reset, the first voltage pulse is input to the first input terminal to simulate

logic

0 or 1, and the second input terminal is input to the second voltage input analog logic 0. Or 1, the third input terminal inputs a third voltage pulse

analog logic

0 or 1, the fourth input terminal inputs a fourth voltage pulse

analog logic

0 or 1, and the second voltage pulse and the third voltage pulse act on the solenoid to generate a pulse The magnetic field, and the first voltage pulse, the fourth voltage pulse and the pulse magnetic field act on the two superlattice phase change units, so that the resistance state switching is implemented to realize the logical NAND function of the four-terminal input;

When the second voltage pulse and the third voltage pulse are completely identical, the logical input and the NAND function of the three-terminal input is realized by combining the second input end and the third input end into one input end;

Disconnecting the first controllable switching element and the second controllable switching element, and closing the third controllable switching element, and inputting a low level read voltage pulse at the first input terminal, at the output of the logic gate circuit The terminal obtains the output voltage pulse amplitude to read the logical operation result.

Preferably, the resistance of the resistor in the logic gate circuit is an amorphous resistance of any one of the superlattice phase change units.

In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art:

(1) The logic gate circuit of the superlattice phase change unit based on the magnetic field triggering provided by the invention adopts a superlattice phase change unit to realize Boolean logic operation and storage; and generates electromagnetic conversion by inputting one or more voltage pulses. The pulsed magnetic field is applied to the superlattice phase change unit by a pulsed magnetic field combined with a voltage pulse to control the resistance state switching, thereby implementing logic operations; since the superlattice phase change material is nonvolatile, and the logical operation results are 0 and 1 It completely corresponds to the low resistance and high resistance state of the superlattice phase change unit, so that the result of the logic operation is directly stored in the resistance state of the superlattice phase change unit, thereby realizing the storage of the operation result; thereby reaching a logic gate The circuit simultaneously stores and processes information;

On the one hand, compared with the prior art MRAM, since the superlattice phase change unit used in the present invention has an ultra-high ratio of high and low resistance, the high resistance and low resistance states can be easily distinguished, so that complicated readout circuits are not required. To distinguish its resistance state, greatly simplify the circuit structure of the logic gate device;

On the other hand, compared with the prior art RRAM, it has an extremely long erasing life and an extremely high durability, so that the stability of the logic gate device formed by it can be greatly improved;

On the other hand, compared with the prior art GST phase change memory, the voltage pulse amplitude of the superlattice phase change unit set and the voltage pulse amplitude of the reset are greatly reduced, thereby reducing the logic gate device formed thereby. Power consumption

(2) The logic gate circuit of the superlattice phase change unit based on the magnetic field trigger provided by the present invention, since the superlattice phase change unit undergoes a phase change under the action of a very short voltage pulse, the logic gate circuit thereof Storage speed has superior characteristics;

(3) The logic gate circuit of the superlattice phase change unit based on the magnetic field trigger provided by the invention has simple circuit structure, convenient logic operation, and diversified logic functions realized; and, after electromagnetic conversion, utilizes the generated pulse magnetic field As one of the input terminals of the superlattice phase change unit, its energy is only consumed on the wire that generates the magnetic field. Since the wire resistance is low, the energy consumed is low, thereby further reducing the power consumption of the logic gate circuit.

[Description of the Drawings]

1 is an I-V characteristic curve of a superlattice phase change unit used in an embodiment of the present invention, respectively Measured with a magnetic field of 0.1T and without a magnetic field;

2 is a R-V characteristic curve of a superlattice phase change unit used in an embodiment of the present invention, measured under a condition of adding a magnetic field of 0.1 T and a state without a magnetic field;

3 is a schematic diagram of functional blocks of a logic gate circuit according to an embodiment of the present invention;

4 is a logic gate circuit provided in Embodiment 1; AND, NOR, XNOR, NIMP, and single-ended input NOT capable of implementing double-ended input;

5 is a logic gate circuit provided by Embodiment 2; NAND, OR, XOR, IMP capable of implementing double-ended input;

6 is a logic gate circuit provided by Embodiment 3; capable of implementing AND and NOR of three-terminal and four-segment input;

7 is a logic gate circuit provided in Embodiment 4; NAND and OR capable of implementing three-terminal and four-segment input.

【detailed description】

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Further, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not constitute a conflict with each other.

An object of the present invention is to provide a non-volatile logic gate circuit based on a superlattice phase change unit, which converts a voltage pulse received by at least one input end of a logic gate circuit into a pulsed magnetic field by electromagnetic conversion, and combines a voltage with a pulsed magnetic field. The pulse acts on the superlattice phase change unit, and uses the characteristics of the superlattice phase change unit to increase the threshold voltage of the resistance state switching under the magnetic field condition, and realizes the harmony, or not, or the non, the NAND, the same or the different OR, implication, inverse implication, multi-end and multi-end, multi-end, multi-end or multi-end or non-logic; simple circuit structure, diverse logic functions; and super-lattice phase change material with non-volatility and logic The operation results 0 and 1 completely correspond to the low-resistance and high-resistance states of the superlattice phase change unit, so that the result of the logic operation is directly stored in the superlattice In the resistance state of the phase change unit, the fusion of information processing and storage is realized, which is expected to solve the Von Neumann bottleneck problem faced by the computer development.

The invention utilizes the electrical characteristics of the superlattice phase change unit under the condition of no magnetic field and magnetic field addition; the superlattice phase change material used includes, but not limited to, GeTe/Sb ₂ Te ₃ , which can be any two Or a combination of a plurality of phase change materials in a superlattice manner.

1 is a typical I-V characteristic curve of a superlattice phase change unit according to an embodiment of the present invention, and FIG. 2 is a typical R-V characteristic curve thereof. Referring to FIG. 1, when the magnetic field is not applied, the threshold voltage of the superlattice phase change unit from high resistance to low resistance is about 0.87V, and after adding a magnetic field of 0.1T, the threshold voltage is significantly increased, increasing from 0.87V. At 1.52V; referring to Figure 2, after adding a magnetic field of 0.1T, the amplitude of the set/reset voltage pulse of the superlattice phase change unit is also increased from 0.8V/1.8V when the magnetic field is applied to 2.6V/3.8V. It can be seen that, after adding the external magnetic field, in order to realize the switching of the superlattice phase change unit from high resistance to low resistance, it is necessary to apply the voltage pulse amplitude of the superlattice phase change unit compared to the voltage pulse amplitude used when no magnetic field is applied. The value is higher.

The functional module diagram of the logic gate circuit provided by the embodiment of the present invention is as shown in FIG. 3, and includes a magnetic field generating module, a superlattice phase change module, a voltage dividing resistor and a controllable switching component; and a voltage pulse acts on the magnetic field generating module to generate a pulse. a magnetic field, the pulse magnetic field acts on the superlattice phase change module together with the voltage pulse, and the controllable switching element is connected with the superlattice phase change module and the voltage dividing resistor; the specific implementation of each logic gate function will be described below in conjunction with specific embodiments. method.

In an embodiment, the logical high and low levels are defined as follows: for a voltage pulse applied to a solenoid for generating a pulsed magnetic field: a high level (logic 1) when a voltage pulse is applied, no voltage pulse is applied Time is low (logic 0);

For voltage pulses applied directly to the superlattice phase change unit, the definition is as follows:

AND, NAND: 3V is a high level threshold (logic 1), 2V is a low level threshold (logic 0);

OR, NOR, NOT: 2V is a high level threshold (logic 1), 1V is a low level threshold (logic 0);

XOR, XNOR: 3V is the high level threshold (logic 1), 1V is the low level threshold (logic 0);

IMP, NIMP: 4V is the high level threshold (logic 1) and 3V is the low level threshold (logic 0).

Example 1

The logic gate circuit provided in Embodiment 1 is as illustrated in FIG. 4, including a superlattice phase change unit 101, a solenoid 107, a controllable switching element 102, and a resistor 103;

The first end of the superlattice phase change unit 101 serves as the first input end 104 of the logic gate circuit, the input end of the solenoid 107 serves as the second input end 106 of the logic gate circuit; the first of the controllable switching element 102 The second end of the superlattice phase change unit 101 is connected to the first end of the resistor 103, the connection point is the output end 105 of the logic gate circuit; the second end of the controllable switching element 102 is grounded, and the resistor 103 is The second end is grounded.

The principle and process of implementing the logic function of the logic gate circuit are specifically described below in conjunction with the logic gate circuit provided in Embodiment 1.

When the amplitude of the voltage pulse applied at the first input terminal 104 is greater than or equal to 3V, the terminal input is defined as a high level (logic 1); when the amplitude of the voltage pulse applied at the first input terminal 104 is less than or equal to 2V, The input of this terminal is low (logic 0);

When a voltage pulse is applied to the second input terminal 106, the terminal input is defined as a high level (logic 1), and when the second input terminal 106 has no voltage pulse input, the terminal input is defined as a low level (logic 0). .

Firstly, the principle and process of implementing logic and operation using the logic gate circuit provided in Embodiment 1 are explained. Since the threshold voltage of the superlattice phase change unit changes from high resistance to low resistance after applying a magnetic field, logic operation is performed. Before, the superlattice phase change unit should be in a high impedance state: specifically, by closing the controllable switching element 103 and applying a voltage pulse of 4V-50 ns at the first input terminal 104, the superlattice phase change unit 101 In an amorphous state with high resistance;

When the second input terminal 106 has no voltage pulse input (logic 0), and the first input terminal 104 applies a voltage pulse of 2V-50 ns (logic 0); since the amplitude of the voltage pulse input on the first input terminal 104 exceeds the super crystal The magnitude of the RESET pulse of the phase change unit 101 under this condition, so that the superlattice phase change unit 101 maintains a high resistance, and the series resistance 103 in the circuit is low resistance; at this time, the high resistance state superlattice phase change unit 101 will divide most of the voltage, so the output of the logic gate circuit 105 The voltage is small and is determined to be logic 0;

When the second input terminal 106 has no voltage pulse input (logic 0) and the first input terminal 104 applies a voltage pulse of 3V-50 ns (logic 1), as in the above case, the output of the logic gate circuit at the output terminal 105 is low. Voltage, determined to be logic 0;

When the second input 106 applies a voltage pulse (logic 1) and the first input 104 applies a voltage pulse of 2V-50 ns (logic 0), the magnitude of the voltage pulse applied by the first input 104 does not reach the superlattice. The pulse amplitude of the phase change unit 101set, so the superlattice phase change unit 101 maintains a high resistance state, and outputs a low level at the output terminal 105, and is determined to be a logic 0;

When the second input 106 applies a voltage pulse (logic 1) and the first input 104 applies a voltage pulse of 3V-50 ns (logic 1), the superlattice is reached under the condition that the pulse voltage amplitude of 3V-50 ns is reached. The condition of the phase change unit 101 is crystallized, the superlattice phase change unit 101 changes from high impedance to low resistance, and a high voltage is outputted at the output terminal 105, which is determined to be logic 1; in summary, only when the first input terminal 104 and the first The two input terminals 106 all input logic 1, and the output is only 1, which realizes the function of logical AND operation.

By using the logic gate circuit provided in Embodiment 1, it is also possible to implement a non-operational NOT input or non-NOR, the same or XNOR, an inverse implication of NIMP and a single-ended input at both ends; for the logic operations listed herein, the implementation process and The principle is the same, the difference lies in the correspondence between the amplitude of the voltage pulse and the high and low levels; the details are as follows:

For logical OR operations: define 2V as the high level threshold (logic 1) and 1V as the low level threshold (logic 0); only when the second input 106 has no voltage pulse input (logic 0), and first When the input terminal 104 applies a voltage pulse of 1V-50ns (logic 0), the superlattice phase change unit 101 changes from high impedance to low resistance, and a high level (logic 1) is outputted at the output terminal 105; in other cases The output terminal 105 outputs a low level (logic 0).

For a logical OR operation: define 3V as a high level threshold (logic 1), 1V as a low level threshold (logic 0); when the second input 106 has a voltage pulse input (logic 1), only when A voltage pulse (logic 1) of 3V-50ns is applied to an input terminal 104, and the superlattice phase change unit 101 Will change from high impedance to low impedance, thus outputting a high level (logic 1) at the output terminal 105; when the second input terminal 106 is not applying a voltage pulse (logic 0), only when the first input terminal 104 applies 1V -50 ns voltage pulse (logic 0), the superlattice phase change unit 101 will change from high impedance to low resistance, thereby outputting a high level (logic 1) at the output terminal 105; thus, only when the first When the input terminal 104 and the second input terminal 106 input high or low level at the same time, the logic 1 is output; otherwise, the output is logic 0, and the function of the logical OR operation is realized.

For the logical inverse implication operation: define 4V as the high level threshold (logic 1), 3V as the low level threshold (logic 0); in the first embodiment, specifically the second input level level NIMP first input terminal In the inverse implication, only the current piece is true (logic 1) and the output is true (logic 1) when the post is false (logic 1), and the output is false (logic 0) in other cases; when the second input 106 When a voltage pulse (logic 1) is applied and a voltage pulse (logic 0) of 3V-50 ns is applied to the first input terminal 104, the superlattice phase change unit 101 changes from high impedance to low resistance, thereby outputting high at the output terminal 105. Level (logic 1); the rest of the situation outputs a low level (logic 0) to implement the logic function of the inverse implication.

For the logic non-operation: define 2V as the high level threshold (logic 1), 1V as the low level threshold (logic 0), at this time, the second input terminal 106 is fixed to not apply the voltage pulse, when the first input end When a voltage pulse of 2V-50ns is applied (logic 1), the superlattice phase change unit 101 maintains a high resistance, and the output terminal 105 outputs a low level (logic 0); when the first input terminal 104 applies a voltage of 1V to 50 ns. At the time of the pulse (logic 0), the superlattice phase change unit 101 undergoes a phase change and becomes a low resistance, thereby outputting a high level (logic 1) at the output terminal 105, thereby realizing a function of logical non-operation.

Example 2

The logic gate circuit provided in Embodiment 2 is as shown in FIG. 5, including a superlattice phase change unit 203, a solenoid 207, a controllable switching element 202, and a resistor 201;

The first end of the resistor 201 serves as the first input end 204 of the logic gate circuit, the input end of the solenoid 207 serves as the second input end 206 of the logic gate circuit; the one end of the controllable switching element 202 and the first end of the resistor 201 The other end is connected to the second end of the resistor 201; one end of the superlattice phase change unit 203 is connected to the second end of the resistor 201, and the connection end is used as the input of the logic gate circuit. At the output 205, the other end of the superlattice phase change unit 203 is grounded.

The logic gate circuit provided in Embodiment 2 can implement logic OR, NAND, XOR, and IMP function; the logic gate circuit provided in Embodiment 2 and FIG. 5 are specifically described to realize the logic function of the logic gate circuit. Principles and processes.

First, the principle and process of implementing the logical OR operation by using the logic gate circuit provided in Embodiment 2 will be explained: as in Embodiment 1, the reset operation is performed before the logic operation, specifically, by closing the controllable switching element 202 and at the first input. The terminal 204 applies a voltage pulse of 4V-50 ns to make the superlattice phase change unit 203 in a high resistance amorphous state;

When the second input terminal 206 does not apply a voltage pulse (logic 0), a 1V-50 ns voltage pulse (logic 0) is applied to the first input terminal 204; since the 1V-50 ns pulse voltage exceeds the superlattice phase change unit under the condition Under the condition of crystallization 203, the superlattice phase change unit 203 changes from high resistance to low resistance; while the series resistor 201 is high resistance, and the voltage is mostly divided by the resistor 201, so the lower voltage is output at the output terminal 205. , determined to be logic 0;

When the second input 206 does not apply a voltage pulse (logic 0), a voltage pulse of 2V-50 ns is applied at the first input 204 (logic 1); since the amplitude of the voltage pulse of 2V-50 ns exceeds the condition Reset pulse amplitude, so the superlattice phase change unit 203 maintains a high resistance, so a higher voltage is output at the output terminal 205, and the determination is logic 1;

When the second input 206 applies a voltage pulse (logic 1), a 1V-50 ns voltage pulse (logic 0) is applied to the first input terminal 204, and the voltage pulse does not reach the pulse amplitude of the superlattice phase change unit 203set, so The superlattice phase change unit 203 maintains a high resistance state, and outputs a high level at the output terminal 205, and is determined to be a logic 1;

When the second input terminal 206 applies a voltage pulse (logic 1), a 2V-50 ns voltage pulse (logic 0) is applied to the first input terminal 204. Since the pulse voltage of 2V-50 ns still does not reach the set pulse amplitude, the super The lattice phase change unit 203 maintains a high impedance state, and outputs a high level at the output terminal 205, and is determined to be a logic 1; in summary, the output is 0 only when both inputs are 0, realizing a logical OR function. .

By using the logic gate circuit provided in Embodiment 2, the NAND and XOR of the input at both ends can be realized, and the IMP function is implied; for the logic operation listed in this section, the implementation process is the same as the principle, and the difference lies in the voltage pulse. Correspondence between amplitude and high and low level; the details are as follows:

For logic NAND operations: define 3V as a high level threshold (logic 1), 2V as a low level threshold (logic 0); only apply a voltage pulse (logic 1) at the second input 206, and the first input The terminal 204 applies a voltage pulse of 3V-50ns (logic 1), and the superlattice phase change unit 203 changes from high impedance to low resistance, thereby outputting a low level (logic 0) at the output terminal 205, and outputting in other cases. High level (logic 1) to implement the function of logic and non-operation.

For a logical XOR operation: define 3V as a high level threshold (logic 1), 1V as a low level threshold (logic 0); when the second input 206 applies a voltage pulse (logic 1), only the first input The terminal 204 applies a voltage pulse of 3V-50ns (logic 1), and the superlattice phase change unit 203 changes from high impedance to low resistance, thereby outputting a low level (logic 0) at the output terminal 205; when the second input When terminal 206 does not apply a voltage pulse (logic 0), only when the first input terminal 204 applies a voltage pulse of 1V-50ns (logic 0), the superlattice phase change unit 203 changes from high impedance to low resistance, thereby outputting At the terminal 205, a low level (logic 0) is output; in summary, when the first input terminal 204 and the second input terminal 206 simultaneously input a high or low level, a logic 0 is output; otherwise, a logic 1 is output, and a logical exclusive OR is implemented. The function.

For logical implication: define 4V as the high threshold (logic 1) and 3V as the low threshold (logic 0); in embodiment 2, here is the second input level IMP first input level In the implication, only the current piece is true (logic 1) and the output is false (logic 0), and the output is true (logic 1); in other cases, the voltage is applied to the second input 206. Pulse (logic 1), and the first input 204 applies a voltage pulse of 3V-50ns (logic 0), the superlattice phase change unit 203 changes from high impedance to low resistance, thereby outputting a low level at the output terminal 205. (Logic 0), the rest of the situation outputs a high level (logic 1); thus implementing the logical implication function.

Example 3

The logic gate circuit provided in Embodiment 3 is as illustrated in FIG. 6 and includes a first superlattice phase change unit 301, a controllable switching element 302, a second superlattice phase change unit 303, a resistor 304, and a first solenoid. 308 and a second solenoid 309;

The first end of the first superlattice phase change unit 301 serves as the first input end 305 of the logic gate circuit, and the input end of the first solenoid 308 serves as the second input end 310 of the logic gate circuit, and the second spiral The input end of the tube 309 serves as the third input end 311 of the logic gate circuit, and the first end of the second superlattice phase change unit 303 serves as the fourth input end 306 of the logic gate circuit; one end of the controllable switching element 302 and the first end The second end of the superlattice phase change unit 301 is connected to the second end of the second superlattice phase change unit 303, and the other end of the controllable switching element 302 is grounded; one end of the resistor 304 and the second superlattice phase change unit The first end of the 303 is connected, and the other end of the resistor 304 is grounded; the first end of the second superlattice phase change unit 303 serves as the output 307 of the logic gate circuit.

The logic gate circuit provided in Embodiment 3 can implement the logical AND, XOR or NOR function of the three-terminal input, and the logical AND, XOR or NOR function of the four-terminal input; the following relates to the logic gate circuit provided in Embodiment 3 and FIG. Explain the principle and process of the logic function of the logic gate circuit.

First, the principle and process of implementing the logic and operation of the four-terminal input by using the logic gate circuit provided in Embodiment 3 are explained. As in

Embodiments

1 and 2, the reset operation is performed before the logic operation, specifically, by closing the controllable switching element 302. And applying a voltage pulse of 4V-50 ns at the first input end 305 and the fourth input end 306 respectively, so that the first superlattice phase change unit 301 and the second superlattice phase change unit 303 are both in a high resistance amorphous state. state;

When neither the second input terminal 310 nor the third input terminal 311 applies a voltage pulse (logic 0), at this time, at the first input terminal 305, whether 2V-50 ns (logic 0) or 3V-50 ns (logic 1) is applied. The voltage pulse exceeds the reset voltage of the first superlattice phase change unit 301 at this time. Similarly, at the fourth input terminal 306, whether a voltage pulse of 2V-50ns (logic 0) or 3V-50ns (logic 1) is applied. , both exceed the reset voltage of the second superlattice phase change unit 303 at this time, the two superlattice phase change units are in a high impedance state, and output a low level at the output terminal 307, and the logic 0 is determined;

When the second input terminal 310 does not apply a voltage pulse (logic 0), the third input terminal 311 applies a voltage. At the time of the pulse (logic 1), whether the voltage pulse of 2V-50 ns (logic 0) or 3V-50 ns (logic 1) is applied to the first input terminal 305 exceeds the first superlattice phase change unit 301 at this time. Reset voltage, the first superlattice phase change unit 301 is in a high resistance state, and the second superlattice phase change unit 303 is in a high resistance state regardless of the state, the series resistance of the two superlattice phase change units is The output terminal 307 outputs a low level, and is determined to be a logic 0;

When the second input 310 applies a voltage pulse (logic 1) and the third input 311 does not apply a voltage pulse (logic 0), the second input 306 applies either 2V-50 ns (logic 0) or 3V-50 ns ( The voltage pulse of logic 1) exceeds the reset voltage of the second superlattice phase change unit 303 at this time, and the second superlattice phase change unit 303 is in a high resistance state, and the first superlattice phase change unit 301 In what state, the series resistance values of the two superlattice phase change units are all high impedance states, and the low level is output at the output terminal 307, and is determined to be logic 0;

When a voltage pulse (logic 1) is applied to both the second input terminal 310 and the third input terminal 311, only a voltage pulse of 3V-50 ns (logic 1) is applied to both the first input terminal 305 and the fourth input terminal 306. The pulse amplitude of the superlattice phase change unit set, so that the first superlattice phase change unit 301 and the second superlattice phase change unit 303 both become a low resistance state, and the series connection of two superlattice phase change units The resistance is low impedance, and the output is high at the output terminal 307, and the logic is 1; in summary, the output is only 1 when the 4 inputs are all logic 1, and the AND gate of the four-terminal input is realized. .

In particular, when the input voltage pulses of the second input terminal 310 and the third input terminal 311 are completely identical, the two input terminals can be combined into the same input terminal, that is, the first superlattice phase change unit 301 and the first The magnetic field applied on the two superlattice phase change unit 303 is controlled by the same voltage pulse to realize the logical AND function of the three inputs.

For the logic or non-operation of the four inputs: define 2V as the high level threshold (logic 1), 1V as the low level threshold (logic 0); only when the second input terminal 310 and the third input terminal 311 do not apply voltage When the pulse (logic 0) and the pulse input amplitudes of the first input terminal 305 and the fourth input terminal 306 are both 1V-50 ns (logic 0), the first superlattice phase change unit 301 and the second superlattice phase The variable unit 303 is in a low resistance state, and its series resistance is low resistance, thereby outputting a high level (logic 1), and the rest The situation outputs a low level (logic 0);

In particular, when the input voltage pulses of the second input terminal 310 and the third input terminal 311 are completely identical, the two input terminals can be combined into the same input terminal, that is, the first superlattice phase change unit 301 and the first The magnetic field applied on the two superlattice phase change unit 303 is controlled by the same voltage pulse to realize the NOR gate of the three inputs.

Example 4

The logic gate circuit provided in Embodiment 4 is illustrated in FIG. 7 and includes a first superlattice phase change unit 402, a second superlattice phase change unit 404, a first solenoid 411, and a second solenoid 413. a first controllable switching element 409, a second controllable switching element 403, a third controllable switching element 405 and a resistor 401;

The first end of the resistor 401 is the first input end 406 of the logic gate circuit, the input end of the first solenoid 411 is the second input end 410 of the logic gate circuit, and the input end of the second solenoid 413 is used as the logic. The third input end 412 of the gate circuit, the first end of the second superlattice phase change unit 401 is the fourth input end 407 of the logic gate circuit; one end of the first controllable switching element 409 is connected to the first end of the resistor 401 The other end is connected to the second end of the resistor 401; the first end of the first superlattice phase change unit 402 is connected to the second end of the resistor 401, and the connection end thereof serves as the output end 408 of the logic gate circuit; the second controllable The first end of the switching element 403 is connected to the second end of the first superlattice phase change unit 402 and the second end of the second lattice phase change unit 404, and the second end of the second controllable switching element 403 is grounded; The first end of the three controllable switching element 405 is coupled to the first end of the second lattice phase change unit 404, and the second end of the third controllable switching element 405 is coupled to ground.

The logic gate circuit provided in Embodiment 4 can implement logic and non-NAND, logic non-OR function of three-terminal input, and logic and non-NAND, logic non-OR function of four-terminal input; the logic gate circuit provided in combination with Embodiment 4 is FIG. 7 is a detailed diagram illustrating the principle and process of implementing logic functions of the logic gate circuit.

Firstly, the principle and process of implementing the logic non-operation of the four-terminal input by using the logic gate circuit provided in Embodiment 4 are explained: as in

Embodiments

1, 2 and 3, the reset operation is performed before the logic operation, Body, by closing the first controllable switching element 409 and the second controllable switching element 403, and opening the third controllable switching element 405, and applying 4V-50ns respectively at the first input end 406 and the fourth input end 407 The voltage pulse causes the superlattice phase change unit 402 and the superlattice phase change unit 404 to be in a high resistance amorphous state;

When a voltage pulse (logic 1) is applied to both the second input terminal 410 and the third input terminal 412, whether a voltage pulse of 1V-50ns (logic 0) or 2V-50ns (logic 1) is applied to the first input terminal 406, Neither exceeds the set voltage of the first superlattice phase change unit 402 at this time; at the fourth input terminal 407, whether a voltage pulse of 1V-50ns (logic 0) or 2V-50ns (logic 1) is applied, no more than this The set voltage of the first superlattice phase change unit 402, at this time, the two superlattice phase change units are all in a high impedance state, and output a high level at the output terminal 408, which is determined to be a logic 1;

When the second input 410 applies a voltage pulse (logic 1) and the third input 412 does not apply a voltage pulse (logic 0), either 1V-50 ns (logic 0) or 2V-50 ns is applied at the first input 406 ( The voltage pulse of logic 1) does not exceed the set voltage of the first superlattice phase change unit 402 at this time, the first superlattice phase change unit 402 is in a high resistance state, and the second superlattice phase change unit 404 is In what state, the series resistance of the two superlattice phase change cells is a high resistance state, and a high level is output at the output terminal 408, and is determined to be a logic 1;

When the second input 410 is not applied with a voltage pulse (logic 0) and the third input 412 applies a voltage pulse (logic 1), either a 1V-50 ns (logic 0) or 2V-50 ns is applied at the fourth input 407 ( The voltage pulse of logic 1) does not exceed the set voltage of the second superlattice phase change unit 404 at this time, the second superlattice phase change unit 404 is in a high resistance state, and the first superlattice phase change unit 402 In what state, the series resistance of the two superlattice phase change cells is a high resistance state, and a high level is output at the output terminal 408, and is determined to be a logic 1;

When neither the second input terminal 410 nor the third input terminal 412 is applied with a voltage pulse (logic 0), only when a voltage pulse of 1V-50 ns (logic 0) is applied to both the first input terminal 406 and the fourth input terminal 407, The pulse amplitude of the superlattice phase change unit set can be reached and the amplitude of the reset pulse is not exceeded, so that the first superlattice phase change unit 402 and the second superlattice phase change unit 404 both become low impedance states. The series resistance of the two superlattice phase change cells is a low resistance state, and a low level is output at the output terminal 408, which is determined to be a logic 0; in summary, the output is 0 only when all four inputs are logic 0. To achieve the four-terminal input OR gate function;

In particular, when the input voltage pulses of the second input terminal 410 and the third input terminal 412 are completely identical, the two input terminals can be combined into the same input terminal, that is, in the first superlattice phase change unit 402 and the second The magnetic field applied on the superlattice phase change unit 404 is controlled by a voltage pulse to realize an OR gate of the three inputs;

For the four-input logic NAND operation: define 3V as the high level threshold (logic 1), 2V as the low level threshold (logic 0); only when the second input terminal 410 and the third input terminal 412 are applied with voltage Pulse (logic 1), and when the pulse input amplitudes of the first input terminal 406 and the fourth input terminal 407 are both 3V-50 ns (logic 0), the first superlattice phase change unit 402 and the second superlattice phase The variable unit 404 is in a low resistance state, and the series resistance is low resistance, thereby outputting a low level (logic 0), and the other cases output a high level (logic 1);

In particular, when the voltage pulses applied on the second input terminal 410 and the third input terminal 412 are completely identical, the two input terminals can be combined into the same input terminal, that is, the first superlattice phase change unit 402 and the second. The magnetic field applied on the superlattice phase change unit 404 is controlled by the same voltage pulse to achieve a NAND gate at the three inputs.

The logic gate circuit of the superlattice phase change unit based on the magnetic field triggering provided by the above four embodiments has a simple circuit structure, convenient logic operation, and diversified logic functions realized; wherein the set/reset of the superlattice phase change unit The lower voltage pulse amplitude makes the logic gate circuit have the advantage of low power consumption.

Those skilled in the art will appreciate that the above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present invention, All should be included in the scope of protection of the present invention.

Claims

A logic gate circuit based on a magnetic field triggered superlattice phase change unit, characterized by comprising a superlattice phase change module, a voltage dividing resistor and a controllable switching element;

The voltage dividing resistor is connected to the superlattice phase change module, and the connection point thereof is used as an output end of the logic gate circuit; the controllable switching element is disposed at a connection line between the superlattice phase change module and the voltage dividing resistor Controlling the resistance state switching by applying a pulsed magnetic field and a voltage pulse to the superlattice phase change module;

By closing the controllable switching element, applying a reset voltage pulse to the superlattice phase change module, writing it to a high resistance state, applying a high voltage or low voltage pulse signal to the superlattice phase change module to simulate logic 0 or 1 Implementing logic writing; by disconnecting the controllable switching element and applying a read voltage pulse to the superlattice phase change module, thereby obtaining an output voltage pulse amplitude at the output of the logic gate circuit to read the logical operation result .
The logic gate circuit of claim 1 wherein said logic gate circuit further comprises a magnetic field generating module for generating said pulsed magnetic field.
The logic gate circuit of claim 2 wherein said magnetic field generating module is implemented using a solenoid, and a voltage pulse is applied to the solenoid to generate said pulsed magnetic field.
The logic gate circuit according to claim 1, wherein said superlattice phase change module comprises a superlattice phase change unit; and a voltage pulse is applied to said superlattice phase change unit in combination with a pulse magnetic field to realize Its resistance state control.
The logic gate circuit of claim 4 wherein the superlattice phase change material employed by the superlattice phase change unit is a combination of two or more phase change materials in a superlattice manner.
A logic gate circuit based on a magnetic field triggered superlattice phase change unit, characterized by comprising a superlattice phase change unit, a solenoid, a controllable switching element and a resistor;

The first end of the superlattice phase change unit serves as a first input end of the logic gate circuit, and the input end of the solenoid serves as a second input end of the logic gate circuit; the first end of the controllable switching element and the super a second end of the lattice phase change unit is connected to the first end of the resistor, and a connection point thereof is used as an output end of the logic gate circuit; a second end of the controllable switching element is grounded, and a second end of the resistor is grounded;

After the controllable switching element is closed, a reset voltage pulse is input to the first input terminal, and the superlattice phase change unit is written to a high impedance state to be reset, and the first voltage pulse is input to the first input terminal to simulate logic 0. Or 1, and inputting a second voltage pulse analog logic 0 or 1 at the second input terminal, generating a pulse magnetic field by applying the second voltage pulse to the solenoid; and the first voltage pulse and the pulse magnetic field acting on the super crystal a phase change unit that implements a resistive state switch to implement logical AND, NOT, or NOT, the same or an inverse implication function;

The output voltage pulse amplitude is obtained at the output of the logic gate circuit to read the logic operation result by disconnecting the controllable switching element and inputting a low level read voltage pulse at the first input terminal.
A logic gate circuit based on a magnetic field triggered superlattice phase change unit, characterized by comprising a superlattice phase change unit, a solenoid, a controllable switching element and a resistor;

The first end of the resistor is a first input end of the logic gate circuit, and the input end of the solenoid is a second input end of the logic gate circuit; one end of the controllable switching element is connected to the first end of the resistor, and One end is connected to the second end of the resistor; one end of the superlattice phase change unit is connected to the second end of the resistor, the connection end is used as the output end of the logic gate circuit, and the other end of the superlattice phase change unit is grounded;

By closing the controllable switching element, inputting a reset voltage pulse at the first input terminal, writing the superlattice phase change unit to a high impedance state to reset it, and inputting the first voltage pulse to the first input terminal to simulate logic 0 or 1 And inputting a second voltage pulse analog logic 0 or 1 at the second input, generating a pulsed magnetic field by applying the second voltage pulse to the solenoid; and the first voltage pulse and the pulse magnetic field acting on the superlattice phase Transform the unit to implement a resistive state switch to implement logical OR, NAND, XOR, and implication functions;

The output voltage pulse amplitude is obtained at the output of the logic gate circuit to read the logic operation result by disconnecting the controllable switching element and inputting a low level read voltage pulse at the first input terminal.
A logic gate circuit based on a magnetic field triggered superlattice phase change unit, comprising: a first superlattice phase change unit, a second superlattice phase change unit, a first solenoid, a second spiral Tube, controllable switching element and resistor;

a first end of the first superlattice phase change unit serves as a first input end of the logic gate circuit, an input end of the first solenoid as a second input end of the logic gate circuit, and a second solenoid The input end serves as a third input end of the logic gate circuit, and the first end of the second superlattice phase change unit serves as a fourth input end of the logic gate circuit; one end of the controllable switching element changes phase with the first superlattice The second end of the unit is connected to the second end of the second superlattice phase change unit, and the other end of the controllable switching element is grounded; one end of the resistor is connected to the first end of the second superlattice phase change unit, and the other end of the resistor One end is grounded; the first end of the second superlattice phase change unit serves as an output end of the logic gate circuit;

By closing the controllable switching element, simultaneously inputting a reset voltage pulse at the first input terminal and the fourth input terminal, writing the first superlattice phase change unit and the second superlattice phase change unit to a high impedance state After resetting, input a first voltage pulse analog logic 0 or 1 at the first input terminal, a second voltage input analog logic 0 or 1 at the second input terminal, and a third voltage pulse analog logic 0 or 1 at the third input terminal, The fourth input terminal inputs a fourth voltage pulse analog logic 0 or 1, and generates a pulse magnetic field by applying the second voltage pulse and the third voltage pulse to the solenoid; and the first voltage pulse, the fourth voltage pulse and the pulse The magnetic field acts on the superlattice phase change unit to achieve a resistive state switching to achieve a logical AND or non-function of the four-terminal input;

When the second voltage pulse and the third voltage pulse are completely coincident, the logical AND or non-function of the three-terminal input is realized by combining the second input terminal and the third input terminal into one input terminal.

The output voltage pulse amplitude is obtained at the output of the logic gate circuit to read the logic operation result by disconnecting the controllable switching element and inputting a low level read voltage pulse at the first input terminal.
A logic gate circuit based on a magnetic field triggered superlattice phase change unit, comprising: a first superlattice phase change unit, a second superlattice phase change unit, a first solenoid, a second spiral a first controllable switching element, a second controllable switching element, a third controllable switching element and a resistor;

The first end of the resistor is the first input end of the logic gate circuit, the input end of the first solenoid is the second input end of the logic gate circuit, and the input end of the second solenoid is the third logic gate circuit The first end of the second superlattice phase change unit serves as a fourth input end of the logic gate circuit; one end of the first controllable switching element is connected to the first end of the resistor, and the other end is connected to the second end of the resistor a first end of the first superlattice phase change unit is connected to a second end of the resistor, and a connection end thereof is an output end of the logic gate circuit; and the first end of the second controllable switching element is connected to the first super a second end of the lattice phase change unit and a second end of the second lattice phase change unit, the second controllable switching element The second end is grounded; the first end of the third controllable switching element is connected to the first end of the second lattice phase change unit, and the second end of the third controllable switching element is grounded;

Disconnecting the third controllable switching element by closing the first controllable switching element and the second controllable switching element, simultaneously inputting a reset voltage pulse at the first input end and the fourth input end, the first superlattice phase After the variable cell and the second superlattice phase change cell are written to the high impedance state to be reset, the first voltage pulse is input to the first input terminal to simulate logic 0 or 1, and the second input terminal is input to the second voltage pulse to simulate logic 0 or 1. The third input terminal inputs a third voltage pulse analog logic 0 or 1, and the fourth input terminal inputs a fourth voltage pulse analog logic 0 or 1, and the second voltage pulse and the third voltage pulse act on the solenoid to generate a pulsed magnetic field; and the first voltage pulse, the fourth voltage pulse, and the pulsed magnetic field act on the superlattice phase change unit to implement a resistance state switching to implement logic and/or functions of the four-terminal input;

When the second voltage pulse and the third voltage pulse are completely identical, the logical input and the NAND function of the three-terminal input is realized by combining the second input end and the third input end into one input end;

Closing the third controllable switching element by disconnecting the first controllable switching element and the second controllable switching element, and inputting a low level read voltage pulse at the first input terminal at the output of the logic gate circuit The output voltage pulse amplitude is obtained to read the logical operation result.
A logic gate circuit according to claim 6 or 8, wherein the resistance of said resistor is a crystalline resistance of any superlattice phase change unit in said logic gate circuit.
A logic gate circuit according to claim 7 or 9, wherein the resistance of said resistor is an amorphous resistance of any superlattice phase change unit in said logic gate circuit.