WO2017157105A1 - 一种调制方法和装置 - Google Patents

一种调制方法和装置 Download PDF

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Publication number
WO2017157105A1
WO2017157105A1 PCT/CN2017/071926 CN2017071926W WO2017157105A1 WO 2017157105 A1 WO2017157105 A1 WO 2017157105A1 CN 2017071926 W CN2017071926 W CN 2017071926W WO 2017157105 A1 WO2017157105 A1 WO 2017157105A1
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WIPO (PCT)
Prior art keywords
sequence
codeword
bits
symbols
delay
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PCT/CN2017/071926
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English (en)
French (fr)
Inventor
严茜
马会肖
梁伟光
罗龙
崔岩
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP17765647.7A priority Critical patent/EP3413488A4/en
Publication of WO2017157105A1 publication Critical patent/WO2017157105A1/zh
Priority to US16/130,293 priority patent/US10673563B2/en
Priority to US16/887,915 priority patent/US11283545B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H04L1/0058—Block-coded modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • the present application relates to the field of communications technologies, and in particular, to a modulation method and apparatus.
  • High-order modulation is the first way for communication systems to develop toward high spectral efficiency. Although high-order modulation can greatly improve the spectral efficiency of the system, it requires the system to provide a larger signal to noise ratio (SNR) value. In other words, at the same SNR, the higher the modulation order. The higher the bit error rate of the system.
  • SNR signal to noise ratio
  • the embodiment of the present application discloses a modulation method and device, which can solve the problem that a high-order modulation needs to provide a larger signal-to-noise ratio.
  • an embodiment of the present application provides a modulation method, which may be implemented by a modulator at a transmitting end, for modulating a codeword into a symbol, and first receiving each codeword in the sequence of codewords includes N bits,
  • the codeword sequence includes at least a first codeword, and then maps the codeword sequence into an M-path sequence, each sequence includes N/M bits from the first codeword, and finally maps the M-path sequence into a symbol sequence, each The symbol corresponds to M bits, and the M bits are respectively from the M-path sequence, wherein the first bit corresponding to the N/M first-type symbols is from the first codeword, and N/M are second.
  • the second bit corresponding to the class symbol is from the first codeword.
  • each path includes N/M bits from the first codeword, for the second type of symbol, the corresponding first bit must be from other codewords other than the first codeword, so the first codeword can be used.
  • the information demodulates the bits of other codewords of the second type of symbols, which can improve the demodulation accuracy of the bits of other codewords in the second type of symbols, thereby reducing the requirement of high order modulation on the signal to noise ratio.
  • symbol corresponds to 2 m constellation point in a constellation diagram of 2 m constellation points in the constellation diagram 2 m minimum Euclidean distance between constellation points of a first Euclidean distance; the first The class-like symbol has a minimum Euclidean distance between constellation points that may correspond in the 2 m constellation after the bits from the first codeword are determined as a second Euclidean distance, the second Euclidean distance being greater than the first Euclidean distance. Since the minimum Euclidean distance of the possible constellation points of the first codeword is determined to be larger, demodulation can be performed more accurately, thereby better reducing the signal-to-noise ratio requirement of the high-order modulation.
  • the mapping the codeword sequence into an M-channel sequence may include: performing serial-to-parallel conversion on the codeword sequence to obtain an M-channel sequence, where each sequence includes N/M sequences. a bit of the first codeword; delay processing at least one sequence of the M-path sequence, the number of delay bits is X*(N/M), and X is an integer greater than or equal to 1.
  • the solution implemented by the serial-to-parallel conversion plus delayer is simple and easy to implement.
  • the mapping the codeword sequence into an M-path sequence comprises: interleaving the codeword sequence to obtain an M-channel sequence, where each sequence includes N/M from the first A bit of a codeword.
  • Pick The scheme implemented by the interleaver needs to design the interleaving rules of the interleaver, which has higher requirements for the designer, but may reduce the system cost.
  • mapping the codeword sequence into an M-path sequence includes: performing serial-to-parallel conversion on the codeword sequence to obtain a 3-way sequence, where each sequence includes N/ 3 bits from the first codeword; delay processing the first sequence, the number of delay bits is N/3.
  • mapping the codeword sequence into an M-path sequence includes: performing serial-to-parallel conversion on the codeword sequence to obtain a 3-way sequence, where each sequence includes N/ 3 bits from the first codeword; delay processing the first sequence, the number of delay bits is N/3; delay processing the second sequence, the number of delay bits is N/3.
  • mapping the codeword sequence into an M-path sequence includes: performing serial-to-parallel conversion on the codeword sequence to obtain a 3-way sequence, where each sequence includes N/ 3 bits from the first codeword; delay processing the first sequence, the number of delay bits is 2 (N/3); delay processing the second sequence, the number of delay bits is N/3 One.
  • an embodiment of the present application provides a receiving method, where a demodulator at a receiving end receives a symbol sequence generated by a modulation method provided by the first aspect, and first receives a symbol sequence transmitted through a channel, and performs a solution on the first type of symbol.
  • Tuning process to obtain a log likelihood ratio of bits from the first codeword; demodulating the second type of symbols to obtain a log likelihood ratio of bits from the first codeword; Deciphering the log likelihood ratio of the bits of a codeword to obtain first outer information; demodulating the second type of symbols by using the first outer information to obtain pairs of bits from other codewords Number likelihood ratio.
  • the second type of symbols may be demodulated using the first outer information associated with the first codeword to improve the demodulation accuracy of the bits from the other codewords in the second type of symbols.
  • the first type of symbols further includes bits from a second codeword
  • the demodulating process is performed on the first type of symbols to obtain a log likelihood ratio of bits from the first codeword.
  • the method further includes: decoding, according to a log likelihood ratio of all bits from the second codeword, to obtain second outer information; performing demodulation processing on the first type of symbols to obtain a first codeword
  • the log likelihood ratio of the bits includes demodulating the first type of symbols with the second outer information to obtain a log likelihood ratio of bits from the first codeword.
  • the first outer information is obtained by subtracting the decoded a priori information from the decoded a posteriori information; or the first outer information is the decoded a posteriori information.
  • an embodiment of the present application provides a modulating apparatus, for example, a modulator, including: a first mapper, configured to receive a codeword sequence, each codeword includes N bits, and the codeword sequence is at least The first codeword is further included; and is further configured to map the codeword sequence into an M-path sequence, each sequence includes N/M bits from the first codeword; and a second mapper for mapping the M-channel sequence a symbol sequence, each symbol corresponding to M bits, the M bits are respectively from the M-path sequence, wherein a first bit corresponding to the N/M first-type symbols is from the first codeword, The second bit corresponding to the N/M second type symbols is from the first codeword.
  • a modulator including: a first mapper, configured to receive a codeword sequence, each codeword includes N bits, and the codeword sequence is at least The first codeword is further included; and is further configured to map the codeword sequence into an M-path sequence, each sequence includes N/M bits from the first codeword; and a second map
  • the symbols correspond to 2 m in the constellation diagram of 2 m a constellation point of the constellation points in the constellation diagram 2 m minimum Euclidean distance between constellation points of a first Euclidean distance; the The first Euclidean distance between the constellation points that may correspond in the 2 m constellation after the bits from the first codeword are determined is the second Euclidean distance, and the second Euclidean distance is greater than the first Euclidean distance distance.
  • the first mapper includes a serial to parallel converter and a delay, the serial to parallel converter for receiving a sequence of codewords, each codeword comprising N bits, the codeword The sequence includes at least a first codeword; and is further configured to serially convert the sequence of codewords to obtain an M-path sequence, each sequence comprising N/M bits from the first codeword; the delay device, It is used to delay processing at least one sequence in the M-path sequence, the number of delay bits is X*(N/M), and X is an integer greater than or equal to 1.
  • the first mapper includes an interleaver, and the interleaver is configured to receive a sequence of codewords, each codeword includes N bits, and the codeword sequence includes at least a first codeword; It is further configured to perform interleaving processing on the codeword sequence to obtain an M-path sequence, where each sequence includes N/M bits from the first codeword.
  • the first mapper includes a serial to parallel converter and a delay, the serial to parallel converter for receiving a sequence of codewords, each codeword comprising N bits, the codeword
  • the sequence includes at least a first codeword; and is further configured to serially convert the sequence of codewords to obtain a 3-way sequence, each sequence comprising N/3 bits from the first codeword; the delay device, It is used for delay processing of the first sequence, and the number of delay bits is N/3.
  • the first mapper includes a serial to parallel converter and a delay, the serial to parallel converter for receiving a sequence of codewords, each codeword comprising N bits, the codeword
  • the sequence includes at least a first codeword; and is further configured to serially convert the sequence of codewords to obtain a 3-way sequence, each sequence comprising N/3 bits from the first codeword; the delay device, It is used for delay processing of the first sequence, and the number of delay bits is N/3; delay processing is performed on the second sequence, and the number of delay bits is N/3.
  • the first mapper includes a serial to parallel converter and a delay, the serial to parallel converter for receiving a sequence of codewords, each codeword comprising N bits, the codeword
  • the sequence includes at least a first codeword; and is further configured to serially convert the sequence of codewords to obtain a 3-way sequence, each sequence comprising N/3 bits from the first codeword; the delay device, It is used for delay processing of the first sequence, and the number of delay bits is 2 (N/3); delay processing is performed on the second sequence, and the number of delay bits is N/3.
  • an embodiment of the present application provides a receiving apparatus, including: a demodulator, configured to receive a sequence of symbols transmitted through a channel, where the sequence of symbols is a sequence of symbols generated according to any one of claims 11-17 Demodulating the first type of symbols to obtain a log likelihood ratio of the bits from the first codeword, and demodulating the second type of symbols to obtain a logarithm of the bits from the first codeword a decoder for decoding a log likelihood ratio of all bits from the first codeword to obtain first outer information; and the demodulator for receiving the channel transmission
  • the symbol sequence is further configured to perform demodulation processing on the second type of symbols by using the first outer information to obtain a log likelihood ratio of bits from other code words.
  • the first type of symbols further includes bits from a second codeword
  • the decoder is further configured to translate based on a log likelihood ratio of all bits from the second codeword.
  • the demodulator is configured to perform demodulation processing on the first type of symbols, and obtain a log likelihood ratio of the bits from the first codeword, where the demodulator is used to utilize
  • the second outer information demodulates the first type of symbols to obtain a log likelihood ratio of bits from the first codeword.
  • the first outer information is obtained by subtracting the decoded a priori information from the decoded a posteriori information; or the first outer information is the decoded a posteriori information.
  • each sequence in the M-channel sequence includes N/M bits from the first codeword, and the first bit corresponding to the N/M first-type symbols in the symbol sequence comes from The first codeword, the second bit corresponding to the N/M second type symbols is from the first codeword. So for the second type of symbol, its correspondence The first bit must be from other codewords outside the first codeword, so the bits of the other codewords of the second type of symbol can be demodulated using the information of the first codeword, and other codes in the second type of symbol can be improved.
  • the demodulation accuracy of the bits of the word can reduce the signal-to-noise ratio requirement of the high-order modulation.
  • 1A is a network structure diagram of information transmission provided by an embodiment of the present application.
  • FIG. 1B is a constellation diagram provided by an embodiment of the present application.
  • FIG. 2A is a structural diagram of a device at a transmitting end according to an embodiment of the present application
  • 3A is a schematic diagram of an input bit stream of a mapper according to an embodiment of the present application.
  • 2B is a structural diagram of another device at the transmitting end according to an embodiment of the present application.
  • FIG. 3B is a schematic diagram of an input bit stream of another mapper according to an embodiment of the present application.
  • FIG. 2C is a structural diagram of still another transmitting end device according to an embodiment of the present application.
  • 3C is a schematic diagram of an input bit stream of another mapper according to an embodiment of the present application.
  • 2D is a structural diagram of still another transmitting end device according to an embodiment of the present application.
  • FIG. 3D is a schematic diagram of an input bit stream of another mapper according to an embodiment of the present application.
  • 4A is an 8QAM constellation diagram provided by an embodiment of the present application.
  • FIG. 4B is another 8QAM constellation diagram provided by an embodiment of the present application.
  • FIG. 2E is a structural diagram of still another transmitting end device according to an embodiment of the present application.
  • FIG. 5 is a structural diagram of a receiving end device according to an embodiment of the present application.
  • FIG. 5B is a structural diagram of another receiving end device according to an embodiment of the present application.
  • FIG. 6 is a flowchart of processing of a receiving end device according to an embodiment of the present application.
  • the application scenarios of the embodiments of the present application are relatively wide, and may be a microwave backhaul system, a copper wire system, a satellite communication system, a wireless communication system, a fiber optic communication system, or the like.
  • the embodiment of the present application is mainly applied to information transmission between devices, as shown in FIG. 1A, which is a typical network structure diagram for information transmission, including a sender device 101 and a receiver device 102, a sender device 101, and a receiver device.
  • the link 103 between the 102s may be a microwave link, a copper link, a satellite link, a wireless communication link, a fiber link, etc.
  • the sender device 101 sends a signal to the receiver device 102
  • the sender device 101 transmits a signal. I need to encode and adjust the information bits to be sent. Processing and other processing.
  • the coding in the embodiment of the present application refers to channel coding, which is essentially to increase the reliability of communication and reduce the bit error rate of transmission.
  • the process of channel coding is to insert some redundant bits into a bitstream of a source data of a certain length, so as to use the relationship between the redundant bits and the source data bits to check and correct errors in the source data bits at the receiving end, thereby achieving error correction. the goal of.
  • source data bits are referred to as information bits and redundant bits are referred to as parity bits.
  • Output coded bit stream Q ⁇ q 1,1 , q 1,2 ,...,q 1,n ⁇ q 2,1 ,q 2,2 ,...,q 2,n ⁇ , ⁇ q 3,1 , q 3,2 ,...,q 3,n ... ⁇ , where ⁇ q i,1 ,q i,2 ,...,q i,n ⁇ is called a codeword and is denoted as Q i .
  • these codewords may be processed to obtain a new codeword, such as a new codeword generated by shortening or puncturing n bits satisfying the check relationship; n bits that will satisfy the check relationship A new codeword generated by filling a known bit; a new codeword in which a plurality of codewords are combined; and n-bit codewords satisfying a check relationship are interleaved to obtain a new codeword or the like.
  • a 2 m QAM modulator maps the input m-bit stream to one symbol stream.
  • the total of the 2 m modulation symbols Corresponding to 2 m complex constellation points in the modulation constellation, each complex constellation point is composed of I component and Q component, and each modulation symbol s j is composed of m bits (b 1 , b 2 , ... b m ) Mapped.
  • an 8QAM modulator has eight constellation points in the constellation, corresponding to eight modulation symbols. And each symbol is mapped by 3 bits, as shown in FIG. 1B, the 8QAM constellation diagram, wherein the mapping relationship between bits and symbols is as shown in Table 1.
  • a variety of schemes can be used for modulating a symbol onto a carrier.
  • the I and Q components of each symbol can be amplitude modulated, and the corresponding modulations are transmitted on two orthogonal carriers, where the carrier can be an electrical carrier.
  • the carrier can be an electrical carrier.
  • Optical carrier etc.
  • each codeword in the codeword sequence to be modulated includes N bits, and the codeword sequence to be modulated includes at least a first codeword; the codeword sequence is mapped into an M-path sequence, and each sequence includes N/M a bit from the first codeword; mapping the M-path sequence into a symbol sequence, each symbol corresponding to M bits, the M bits being respectively from the M-channel sequence, wherein the N/M first-class symbols correspond to The first bit of the first codeword is from the first codeword, and the second bit corresponding to the N/M second type of symbols is from the first codeword.
  • the present application proposes a method of coding mapping modulation bits such that bits mapped to the same higher order modulation symbol are derived from two or more code words.
  • the bits from the previous codeword are decoded to obtain more accurate information to assist the demodulation of the bits from the second codeword, and the demodulated bits are second.
  • the decoding of the codewords after obtaining accurate information, helps the bits from the third codeword to be demodulated, and so on, and demodulates all bits.
  • 8 constellation points in the 8QAM constellation corresponding to 8 modulation symbols, and each modulation symbol is mapped by 3 bits.
  • a structure diagram of a device at a transmitting end includes an encoder 201, an interleaver 202, and a modulator 203.
  • the encoding rule encodes each information sequence, and adds p parity bits to each information subsequence to form a codeword of length n.
  • Output coded bit stream Q ⁇ q 1,1 , q 1,2 ,...,q 1,n ⁇ q 2,1 ,q 2,2 ,...,q 2,n ⁇ , ⁇ q 3,1 , q 3,2 ,...,q 3,n ... ⁇ , where ⁇ q i,1 ,q i,2 ,...,q i,n ⁇ is called a codeword and is denoted as Q i .
  • the length of the codeword after interleaving can be different from the length of the codeword before interleaving.
  • the interlace 202 is not necessary, and the encoded bit stream output by the encoder 201 can be directly sent to the modulator 203.
  • the modulator 203 includes a serial to parallel converter 2031, a delayer 2032, and a mapper 2033.
  • the codeword A i ⁇ A i,1 can be , A i,2 ,...,A i,n ⁇ perform padding of known bits to generate a new codeword;
  • a plurality of codewords A i ⁇ A i,1 ,A i,2 ,...,A i,n ⁇
  • the merge process is performed to obtain a new code word and the like.
  • A ⁇ A 1,1 ,A 1,2 ,...,A 1,n ⁇ A 2,1 ,A 2,2 ,...,A 2,n ⁇ , ⁇ A 3,1 ,A 3, 2 ,...,A 3,n ⁇ ... ⁇ performs serial-to-parallel conversion, which can be serial-to-parallel conversion in bits, for example, A 1,1 is in the first way, A 1,1 , A 1,2 in the second way, ...; can also perform serial-to-parallel conversion in units of n/m bits, for example, A 1,1 , A 1,2 ,..., A 1,n/m in the first way, A 1,(n/m)+1 , A 1, (n / m) + 2 , ..., A 1 , 2 (n / m) in the second way, of course, other conversion methods can also be used, even the bits of the code words A 1 and A 2 can be in the same way Alternately, as long as one codeword is satisfied to be equally divided into n/m shares, in the
  • the first path sequence of the embodiment of the present application includes n/3 delays 3032, which are indicated by T, and the number of delay bits is n/3.
  • n/3 delays 3032 may be included in the second or third sequence.
  • the mapper 2032 is configured to map the input 3-way bit sequence into the symbol sequence S.
  • each of the input 3-way bit sequences is called a modulation sequence, and each modulation sequence can be mapped to one symbol.
  • the input bit stream of mapper 2032 is shown in Figure 3A, where X represents 0 or 1, which can be set by the user, and A i indicates that the bit is from codeword A i .
  • X represents 0 or 1
  • a i indicates that the bit is from codeword A i .
  • the nth modulation sequence shown in the dotted circle, d 1, n is from the code word A 2
  • the other d 2, n , d 3 n bits are from the code word A 3 , that is, the nth modulation sequence corresponds to
  • the input bits are derived from codeword A 2 and codeword A 3 , respectively .
  • the first bit corresponding to n/3 first type symbols is satisfied from the first code word
  • the second bit corresponding to n/3 second type symbols also comes from the first code word. .
  • the first to Total The symbols are the first type of symbols, and the corresponding second bits are derived from the codeword A 1 .
  • To Total The symbols are the second type of symbols, and their corresponding first bits are also derived from the codeword A 1 .
  • FIG. 2B is a structural diagram of a transmitting device according to an embodiment of the present application. The difference from FIG. 2A is that the second sequence also includes n/3 delays 3032.
  • the input bit stream of the mapper 2032 is as shown in FIG. 3B, where X represents 0 or 1, which can be set by the user, A i indicates that the bit is from the code word A i , d i, j indicates that the bit stream D i is modulated
  • the bit entered by sequence j For example, the nth modulation sequence shown in the dashed circle, d 1, n and d 2, n are from the codeword A 2 , d 3 , n bits from the codeword A 3 , ie the corresponding nth modulation sequence
  • the input bits are derived from codeword A 2 and codeword A 3 , respectively .
  • FIG. 2C a structure diagram of a transmitting device is provided in the embodiment of the present application.
  • the difference from FIG. 2B is that the first path sequence also includes 2 (n/3) delays 3032.
  • the input bit stream of the mapper 2032 is as shown in Fig. 3C, where X represents 0 or 1, which can be set by the user, A i indicates that the bit is from the code word A i , d i, j indicates that the bit stream D i is modulated
  • the bit entered by sequence j For example, the nth modulation sequence shown in the dashed circle, d 1, n from the codeword A 1 , d 2, n from the codeword A 2 , d 3 , n bits from the codeword A 3 , ie modulation sequence corresponding to the n bits are input to the code word from the a 1, a 2 codewords and codeword a 3.
  • m may be other values of 3 or more for 2 m QAM modulation.
  • FIG. 2D a structural diagram of a transmitting device is provided in the embodiment of the present application, and the difference from FIG. 2A is mainly in the following places.
  • NUM i is an integer greater than or equal to 1
  • x i is an integer greater than or equal to 0, for example, NUM 1
  • the path sequence includes x 1 *(n/m) delays 3032; NUM 2 channels all include x 2 *(n/m) delays 3032, and NUM z channels include x z * (n / m) delays 3032, preferably, x i > x i+1 can be set.
  • Mapper 2032 m for the passage of the input bit sequence bit sequence is mapped to m channel symbol sequence, for ease of description, the input of each parallel m bits is called a modulation sequence, each sequence may be mapped to a modulation symbol s j . 2 m QAM modulation, a total of 2 m modulation symbols Each modulation symbol s j is mapped from m bits (b 1 , b 2 , ... b m ).
  • the input bit stream of mapper 2032 is shown in Figure 3D, where X represents 0 or 1, which can be set by the user, and A i indicates that the bit is from codeword A i .
  • X represents 0 or 1
  • a i indicates that the bit is from codeword A i .
  • a Z the bits corresponding to the (x 1 +1)*(n/m) modulation sequences are derived from Z code words, that is, NUM 1 is extracted from Z code words A 1 , A 2 , . . . , A Z , respectively. NUM 2 , ... NUM Z bits, where NUM i is an integer greater than or equal to 1, less than or equal to m, and Z is an integer greater than 1, less than or equal to m, and
  • the parameter value of NUM i can be as shown in FIG. 7A
  • the parameter value of NUM i can also be other permutation combination of the values shown.
  • the parameter value of NUM i can be as shown in FIG. 7B, for the case shown in each row in FIG. 7B, the parameter value of NUM i can also be other permutation combination of the values shown.
  • the parameter value of NUM i can be as shown in FIG. 7C, for the case shown in each row in FIG. 7C, the parameter value of NUM i can also be other permutation combination of the values shown.
  • the parameter value of NUM i can be as shown in FIG. 7D, for the case shown in each row in FIG. 7D, the parameter value of NUM i can also be other permutation combination of the values shown.
  • the parameter value of NUM i can be as shown in FIG. 7E, for the case shown in each row in FIG. 7E, the parameter value of NUM i can also be other permutation combination of the values shown.
  • the parameter value of NUM i can be as shown in FIG. 7F, for the case shown in each row in FIG. 7F, the parameter value of NUM i can also be other permutation combination of the values shown.
  • the parameter value of NUM i can be as shown in FIG. 7G, for the case shown in each row in FIG. 7G, the parameter value of NUM i can also be other permutation combination of the values shown.
  • the parameter value of NUM i can be as shown in FIG. 7H, for the case shown in each row of FIG. 7H, the parameter value of NUM i can also be other permutation combination of the values shown.
  • the parameter value of NUM i can be as shown in FIG. 7I, for the case shown in each row of FIG. 7I, the parameter value of NUM i can also be other permutation combination of the values shown.
  • each modulation symbol s j is mapped by m bits (b 1 , b 2 , ... b m ) .
  • W 1 min(W 1,0 , W 1,1 ), preferably, W 1 ⁇ W 0
  • W 2 min(W 2,0,0 , W 2,0,1 , W 2,1,0, W 2,1,1 ), preferably, W 2 ⁇ W 1 .
  • each modulation symbol s j is composed of 3 data bits ( d 1 , d 2 , d 3 ) are mapped.
  • the constellation point corresponding to the symbol can be regarded as a QPSK constellation.
  • the corresponding constellation point of the symbol is the four constellation points shown in the inner circle, which can be regarded as a QPSK constellation.
  • the constellation point corresponding to the symbol may be four constellation points in the outer circle, and may also be regarded as a QPSK constellation. It is well known that the minimum Euclidean distance of a QPSK constellation point is greater than the minimum Euclidean distance of an 8QAM constellation point. When the first bit is known, it is equivalent to amplifying the Euclidean distance.
  • the constellation point that the symbol may correspond to can also be regarded as a QPSK constellation.
  • the corresponding constellation point of the symbol is the square constellation (solid line part) shown in the upper right figure.
  • the corresponding constellation point of the symbol is the constellation diagram shown in the lower right (solid line part).
  • the Euclidean distance of the constellation points in the two constellation diagrams on the right is greater than the Euclidean distance between the eight points in the left diagram.
  • FIG. 2E is a structural diagram of a transmitting device according to an embodiment of the present application. The difference from FIG. 2A is that the modulator includes an interleaver 2034 and a mapper 2033, and does not include the interleaver 202.
  • Column output, where L%m is the remainder of L/m, Take an integer for L/m. It can be seen that when row NUM i-1 +1, NUM i-1 +2,...NUM i ,
  • D1 ⁇ X,X,X,X,X,X,X,a 1 ,a 4 ,a 7 ,a 10 ,a 13 ,a 16 ,a 19 ,a 22 .. ⁇ ;
  • D2 ⁇ X,X,X,X,a 2 ,a 5 ,a 8 ,a 11 ,a 14 ,a 17 ,a 20 ,a 23 ... ⁇ ;
  • D1 ⁇ X,X,X,X,X,X,X,X,Q 1,1 ,Q 1,4 ,Q 1,7 ,Q 1,10 ,Q 2,1 ,Q 2,4 ,Q 2,7, Q 2,10 ... ⁇ ;
  • D2 ⁇ X,X,X,X,Q 1,2 ,Q 1,5 ,Q 1,8 ,Q 1,11 ,Q 2,2 ,Q 2,5 ,Q 2,8 ,Q 2,11 ... ⁇ ;
  • D3 ⁇ Q 1,3 ,Q 1,6 ,Q 1,9 ,Q 1,12 ,Q 2,3 ,Q 2,6 ,Q 2,9 ,Q 2,12 ... ⁇
  • D1 ⁇ X,X,X,X,X,X,X,Q 1,1 ,Q 1,2 ,Q 1,3 ,Q 1,4 ,Q 2,1 ,Q 2,2 ,Q 2,3 ,Q 2,4 ... ⁇ ;
  • D2 ⁇ X,X,X,X,Q 1,5 ,Q 1,6 ,Q 1,7 ,Q 1,8 ,Q 2,5 ,Q 2,6 ,Q 2,7 ,Q 2,8 ... ⁇ ;
  • each sequence in the M-path sequence satisfies N/M bits from the first codeword, and the finally mapped symbols satisfy N/M first-class symbol correspondences.
  • the first bit of the second code is from the first codeword, and the second bit corresponding to the N/M second type of symbols is from the first codeword.
  • the order between the bits can be scrambled, and the bits between the codeword and the codeword can also be interleaved.
  • the codeword sequence is mapped into an M-channel sequence, each sequence includes N/M bits from the first codeword; the M-channel sequence is mapped into a symbol sequence, and each symbol corresponds to M bits,
  • the M bits are respectively from the M path sequence, wherein the first bit corresponding to the N/M first type symbols is from the first
  • the codeword the second bit corresponding to the N/M second type of symbols is from the first codeword. That is, a misalignment occurs between the first codeword related bits in the M-path sequence.
  • For the first type of symbols some of the corresponding M bits are from the first codeword, some bits are from other codewords, and for the second type of symbols, some of the corresponding M bits are from the first code.
  • Word some bits are from other code words.
  • the receiving end may perform demodulation for the first type of symbol, demodulate the second type of symbol for the first time, and after decoding the first code word related bit, A type of symbol or a second type of symbol is demodulated again, since the bits from the first codeword in the first type of symbols have been determined, so that the demodulation accuracy of bits from other codewords in the first type of symbols can be improved.
  • a structure diagram of a receiving end device includes a demodulator 501 and a decoder 502.
  • the demodulator 501 is configured to receive a symbol sequence transmitted through a channel, where the symbol sequence is a symbol sequence generated according to any one of claims 1-8, and demodulate the first type of symbol to obtain a symbol sequence. a log likelihood ratio of bits of the first codeword, demodulating the second type of symbols to obtain a log likelihood ratio of bits from the first codeword;
  • the decoder 502 is configured to perform decoding according to a log likelihood ratio of all bits from the first codeword to obtain first external information.
  • the demodulator 501 is further configured to receive the sequence of symbols transmitted by using a channel, and further configured to perform demodulation processing on the second type of symbols by using the first external information to obtain a pair of bits from other codewords. Number likelihood ratio.
  • the decoder 502 is further configured to perform decoding according to a log likelihood ratio of all bits from the second codeword to obtain second external information.
  • the demodulator 501 is configured to perform demodulation processing on the first type of symbols, and obtain a log likelihood ratio of the bits from the first codeword, including:
  • the demodulator 501 is configured to perform demodulation processing on the first type of symbols by using the second outer information to obtain a log likelihood ratio of bits from the first codeword.
  • the receiving device can receive a plurality of schemes by using the information of the first codeword to demodulate the bits of the other codewords of the second type of symbol.
  • a specific implementation device and implementation scheme are given below.
  • FIG. 5B is a structural diagram of another receiving device according to an embodiment of the present disclosure, including: a demodulator 501, a parallel-serial converter 503, a de-interleaver 504, a decoder 502, and an interleaver 505.
  • the demodulator 501 specifically includes a demodulation sub-module 5011, a buffer 5012, a demodulation sub-module 5013, and a selector 5014.
  • each modulation symbol s j of 8QAM is mapped by 3 data bits (d 1 , d 2 , d 3 ).
  • d 1 comes from the previous code word
  • d 2 comes from the second code word.
  • the received signal after s passing through the channel is:
  • n is the additive noise of the channel, and each dimension obeys a complex Gaussian distribution with a mean of 0 variance of ⁇ 2 .
  • Receive symbol y f let y f be mapped from 3 bits, denoted as ⁇ d 1 , d 2 , d 3 ⁇ , bit d 1 from code word A i , d 2 , d 3 from code word A i+1
  • FIG. 6 is a flowchart of processing of a receiving end device according to an embodiment of the present application. Specifically:
  • the received symbol y f is subjected to the first demodulation of the demodulation sub-module 5011, and the log likelihood ratio of the bits from the codeword A 1 mapped in the D2 and D3 sequences is obtained, and the log likelihood ratio of the bits is obtained.
  • the remaining bits of the buffer waiting code word A 1 complete the demodulation.
  • the parallel-to-serial converter 503 performs parallel-to-serial conversion of the log likelihood ratio of the demodulated bits into one-way information, and then the deinterleaver 504 performs deinterleaving, and the de-interleaving rule is a reverse process of the interleaving at the transmitting end.
  • the demultiplexed bit log likelihood ratio is sent to the decoder 502 for decoding to obtain hard decision information and external information.
  • the hard decision information is the final information obtained by the receiver.
  • the interleaver 505 reinterleaves the decoded outer information, and the interleaving process is the same as the interleaving process at the transmitting end.
  • a 2 maps the log likelihood ratio of the bits in the D2 and D3 sequences, and the log likelihood ratio of the bits is buffered to wait for the remaining bits of the codeword A 2 to be demodulated.
  • the demodulation sub-module 5011 performs first demodulation on the received symbol y f to obtain a log likelihood ratio of the bits of the codeword A 2 mapped in the D1 sequence, and the buffer 5012 buffers the information of the symbol y f . All bits of codeword A 2 are demodulated.
  • steps (7) and (8) are repeated to demodulate and decode the received symbols.
  • the first demodulation of the demodulation sub-module 5011 is described below:
  • the symbol probability that the transmitted symbol s i is s j according to the received signal is:
  • y i is the symbol received by the receiving system at the ith time
  • s i is the symbol transmitted by the transmitting end corresponding to y i .
  • p(s i s j
  • y i ) represents the probability that the symbol s i transmitted by the transmitting end is s j when the received signal y i is known.
  • ⁇ is the standard deviation of the Gaussian channel, and exp is the exponential operation.
  • the log likelihood ratio for each bit is:
  • p(d k 0
  • y i ) represents the probability that the kth bit of the symbol s i transmitted by the transmitting end is 0 when the received signal y i is known.
  • p(d k 1
  • y i ) is a probability that the kth bit of the symbol s i transmitted by the transmitting end is 1 when the received signal y i is known.
  • ⁇ is the standard deviation of the Gaussian channel.
  • Exp represents the exponential operation.
  • p(d k 0
  • y i ) represents the probability that the kth bit of the symbol s i transmitted by the transmitting end is 0 when the received signal y i is known.
  • p(d k 1
  • y i ) is a probability that the kth bit of the symbol s i transmitted by the transmitting end is 1 when the received signal y i is known.
  • ⁇ is the standard deviation of the Gaussian channel.
  • Exp represents the exponential operation.
  • the second demodulation of the demodulation sub-module 5013 is described below:
  • the sign probability is calculated in such a way that the formula (1) remains unchanged.
  • y i receives the symbol received by the system at time i
  • s i is the symbol transmitted by the transmitting end corresponding to y i
  • p(s i s j
  • y i ) represents the probability that the symbol s i transmitted by the transmitting end is s j when the received signal y i is known.
  • ⁇ is the standard deviation of the Gaussian channel.
  • Exp represents the exponential operation.
  • the external information mentioned above may have three values, respectively
  • the outer information is the a posteriori information obtained by the decoder minus the a priori information input to the decoder.
  • the external information is the a posteriori information obtained by the decoder.
  • embodiments of the present application can be provided as a method, or a computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

本申请实施例提供一种调制方法和装置，该方法包括：接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；将所述码字序列映射为M路序列,每路序列包括N/M个来自于第一码字的比特；将M路序列映射为符号序列，每个符号对应M个比特，所述M个比特分别来自于所述M路序列，其中N/M个第一类符号对应的的第一比特来自于所述第一码字，N/M个第二类符号对应的第二比特来自于所述第一码字。因此对于第二类符号，其对应的第一比特一定是来自第一码字外的其它码字，可以使用第一码字的信息对第二类符号的其它码字的比特进行解调，可以提高第二类符号中其它码字的比特的解调正确率，从而可以降低高阶调制对信噪比的要求。

Description

一种调制方法和装置 技术领域
本申请涉及通信技术领域，尤其涉及一种调制方法和装置。
背景技术
随着通信技术的发展，通信系统需要的传输速率呈指数增长趋势，而通信频谱的资源匮乏的问题越来越严重，需要全面提升系统的频谱利用率，各个通信系统都在研究各种提升系统频谱效率的方式，如微波回传系统、铜线系统、卫星通信系统、无线通信系统、光纤通信系统等。
高阶调制是通信系统往高频谱效率发展的第一途径。高阶调制虽然能很大的提升系统的频谱效率，但是要求系统可以提供更大的信噪比(signal to Noise Ratio，SNR)值，换句话说，在相同的SNR下，调制阶数越高，系统的误码率越高。
发明内容
本申请实施例公开了一种调制方法和装置，可以解决高阶调制需要提供更大信噪比的问题。
第一方面，本申请的实施例提供一种调制方法，该方法可以由发送端的调制器来实现，用于将码字调制为符号，首先接收码字序列中每个码字包括N个比特，码字序列至少包括第一码字，然后将码字序列映射为M路序列,每路序列包括N/M个来自于第一码字的比特，最后将M路序列映射为符号序列，每个符号对应M个比特，所述M个比特分别来自于所述M路序列，其中N/M个第一类符号对应的的第一比特来自于所述第一码字，N/M个第二类符号对应的第二比特来自于所述第一码字。因为每一路包括N/M个来自于第一码字的比特，因此对于第二类符号，其对应的第一比特一定是来自第一码字外的其它码字，因此可以使用第一码字的信息对第二类符号的其它码字的比特进行解调，可以提高第二类符号中其它码字的比特的解调正确率，从而可以降低高阶调制对信噪比的要求。
在一个可能的设计中，符号对应2m星座图中2m个星座点中的一个星座点，所述2m星座图中星座点之间的最小欧式距离为第一欧式距离；所述第一类符号在来自于第一码字的比特确定后在2m星座图中可能对应的星座点之间的最小欧式距离为第二欧式距离，所述第二欧式距离大于所述第一欧式距离。因为第一码字的比特确定后的可能星座点的最小欧式距离为变大，因此可以更准确的进行解调，从而更好地降低高阶调制对信噪比的要求。
在另一个可能的设计中，所述将所述码字序列映射为M路序列，可以包括：将所述码字序列进行串并转换，得到M路序列,每路序列包括N/M个来自于第一码字的比特；对M路序列中的至少一路序列进行延时处理，延时比特数为X*(N/M)个，X为大于等于1的整数。采用串并转换加延时器来实现的方案简单容易实现。
在另一个可能的设计中，所述将所述码字序列映射为M路序列，包括：将所述码字序列进行交织处理，得到M路序列,每路序列包括N/M个来自于第一码字的比特。采 用交织器来实现的方案需要设计交织器的交织规则，对设计人员的要求较高，但是可能降低系统成本。
在另一个可能的设计中，M等于3时，将所述码字序列映射为M路序列，具体包括：将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；对第一序列进行延时处理，延时比特数为N/3个。
在另一个可能的设计中，M等于3时，将所述码字序列映射为M路序列，具体包括：将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；对第一序列进行延时处理，延时比特数为N/3个；对第二序列进行延时处理，延时比特数为N/3个。
在另一个可能的设计中，M等于3时，将所述码字序列映射为M路序列，具体包括：将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；对第一序列进行延时处理，延时比特数为2(N/3)个；对第二序列进行延时处理，延时比特数为N/3个。
第二方面，本申请实施例提供一种接收方法，用于接收端的解调器接收第一方面提供的调制方法产生的符号序列，首先接收经过信道传输的符号序列，对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比；对第二类符号进行解调处理，得到来自于第一码字的比特的对数似然比；根据所有来自于第一码字的比特的对数似然比进行译码，得到第一外信息；利用所述第一外信息对所述第二类符号进行解调处理，得到来自于其它码字的比特的对数似然比。可以利用第一码字相关的第一外信息对第二类符号进行解调处理，从而提高第二类符号中来自于其它码字的比特的解调正确率。
在一个可能的设计中，所述第一类符号还包括来自第二码字的比特，所述对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比之前还包括：根据所有来自于第二码字的比特的对数似然比进行译码，得到第二外信息；所述对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比包括：利用所述第二外信息对所述第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比。
在一个可能的设计中，所述第一外信息为译码得到的后验信息减去译码的先验信息得到的信息；或者所述第一外信息为译码得到的后验信息。
第三方面，本申请的实施例提供一种调制装置，例如可以使调制器，包括：第一映射器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列映射为M路序列,每路序列包括N/M个来自于第一码字的比特；第二映射器，用于将M路序列映射为符号序列，每个符号对应M个比特，所述M个比特分别来自于所述M路序列，其中N/M个第一类符号对应的的第一比特来自于所述第一码字，N/M个第二类符号对应的第二比特来自于所述第一码字。
在一个可能的设计中，所述符号对应2m星座图中2m个星座点中的一个星座点，所述2m星座图中星座点之间的最小欧式距离为第一欧式距离；所述第一类符号在来自于第一码字的比特确定后在2m星座图中可能对应的星座点之间的最小欧式距离为第二欧式距离，所述第二欧式距离大于所述第一欧式距离。
在一个可能的设计中，所述第一映射器包括串并转换器和延时器，所述串并转换器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列进行串并转换，得到M路序列,每路序列包括N/M个来自于第一码字的比特；所述延时器，用于对M路序列中的至少一路序列进行延时处理，延时比特数为X*(N/M)个，X为大于等于1的整数。
在一个可能的设计中，所述第一映射器包括交织器，所述交织器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列进行交织处理，得到M路序列,每路序列包括N/M个来自于第一码字的比特。
在一个可能的设计中，所述第一映射器包括串并转换器和延时器，所述串并转换器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；所述延时器，用于对第一序列进行延时处理，延时比特数为N/3个。
在一个可能的设计中，所述第一映射器包括串并转换器和延时器，所述串并转换器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；所述延时器，用于对第一序列进行延时处理，延时比特数为N/3个；对第二序列进行延时处理，延时比特数为N/3个。
在一个可能的设计中，所述第一映射器包括串并转换器和延时器，所述串并转换器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；所述延时器，用于对第一序列进行延时处理，延时比特数为2(N/3)个；对第二序列进行延时处理，延时比特数为N/3个。
第四方面，本申请的实施例提供一种接收装置，包括：解调器，用于接收经过信道传输的符号序列，所述符号序列为权利要求11-17任一项权利要求产生的符号序列，对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比，对第二类符号进行解调处理，得到来自于第一码字的比特的对数似然比；译码器，用于根据所有来自于第一码字的比特的对数似然比进行译码，得到第一外信息；所述解调器，还用于接收经过信道传输的所述符号序列，还用于利用所述第一外信息对所述第二类符号进行解调处理，得到来自于其它码字的比特的对数似然比。
在一个可能的设计中，所述第一类符号还包括来自第二码字的比特，所述译码器，还用于根据所有来自于第二码字的比特的对数似然比进行译码，得到第二外信息；所述解调器用于对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比包括：所述解调器，用于利用所述第二外信息对所述第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比。
在一个可能的设计中，所述第一外信息为译码得到的后验信息减去译码的先验信息得到的信息；或者所述第一外信息为译码得到的后验信息。
本申请实施提供的调制方法中，M路序列中每路序列包括N/M个来自于第一码字的比特，符号序列中有N/M个第一类符号对应的的第一比特来自于所述第一码字，N/M个第二类符号对应的第二比特来自于所述第一码字。因此对于第二类符号，其对应 的第一比特一定是来自第一码字外的其它码字，因此可以使用第一码字的信息对第二类符号的其它码字的比特进行解调，可以提高第二类符号中其它码字的比特的解调正确率，从而可以降低高阶调制对信噪比的要求。
附图说明
图1A是本申请实施例提供的一种信息发送的网络结构图；
图1B是本申请实施例提供的一种星座图；
图2A为本申请实施例提供的一种发送端设备结构图；
图3A为本申请实施例提供的一种映射器的输入比特流示意图；
图2B为本申请实施例提供的另一种发送端设备结构图；
图3B为本申请实施例提供的另一种映射器的输入比特流示意图；
图2C为本申请实施例提供的再一种发送端设备结构图；
图3C为本申请实施例提供的再一种映射器的输入比特流示意图；
图2D为本申请实施例提供的再一种发送端设备结构图；
图3D为本申请实施例提供的再一种映射器的输入比特流示意图；
图4A为本申请实施例提供的一种8QAM星座图；
图4B为本申请实施例提供的另一种8QAM星座图；
图2E为本申请实施例提供的再一种发送端设备结构图；
图5A为本申请实施例提供的一种接收端设备结构图；
图5B为本申请实施例提供的另一种接收端设备结构图；
图6为本申请实施例提供的一种接收端设备处理流程图；
图7A为本申请实施例提供的m＝4时NUMi的参数配置示意图；
图7B为本申请实施例提供的m＝5时NUMi的参数配置示意图；
图7C为本申请实施例提供的m＝6时NUMi的参数配置示意图；
图7D为本申请实施例提供的m＝7时NUMi的参数配置示意图；
图7E为本申请实施例提供的m＝8时NUMi的参数配置示意图；
图7F为本申请实施例提供的m＝9时NUMi的参数配置示意图；
图7G为本申请实施例提供的m＝10时NUMi的参数配置示意图；
图7H为本申请实施例提供的m＝11时NUMi的参数配置示意图；
图7I为本申请实施例提供的m＝12时NUMi的参数配置示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
本申请实施例的应用场景比较广泛，可以是微波回传系统、铜线系统、卫星通信系统、无线通信系统、光纤通信系统等等。本申请实施例主要应用于设备之间信息的发送，如图1A所示为一种典型的信息发送的网络结构图，包括发送端设备101和接收端设备102，发送端设备101和接收端设备102之间的链路103可以是微波链路、铜线链路、卫星链路、无线通信链路、光纤链路等，发送端设备101发送信号到接收端设备102，发送端设备101发送信号之前需要对将要发送的信息比特进行编码、调 制等处理。
为了下面描述的方便，首先介绍几个概念：
信息比特流，为U＝{{u1,1,u1,2,…,u1,k}{u2,1,u2,2,…,u2,k},{u3,1,u3,2,…,u3,k}…}，其中{u1,1,u1,2,…,u1,k}为一个信息序列。
编码，本申请实施例中的编码指的是信道编码，其本质是增加通信的可靠性，降低传输的误码率。信道编码的过程是在一定长度的源数据比特流中插入一些冗余比特，从而达到在接收端利用这些冗余比特和源数据比特的关系检查和纠正源数据比特中的错误，从而达到纠错的目的。通常，源数据比特称之为信息比特，冗余比特称之为校验比特。例如，信息比特流U＝{{u1,1,u1,2,…,u1,k}，{u2,1,u2,2,…,u2,k},{u3,1,u3,2,…,u3,k}…}进入编码器，每k个比特组成一个信息序列,记为Ui，利用同一个编码规则对每个信息序列进行编码，在每个信息子序列中添加p个校验比特，组成长度为n的码字。输出编码比特流Q＝{{q1,1,q1,2,…,q1,n}{q2,1,q2,2,…,q2,n},{q3,1,q3,2,…,q3,n…},其中{qi,1,qi,2,…,qi,n}称之为一个码字，记为Qi.
码字，经过编码处理后可以得到码字，例如上面提到的码字Qi＝{qi,1,qi,2,…,qi,n}，其长度为n，即包括n个比特，这n个比特满足校验关系。在一些场景下，可以对这些码字进行处理得到新的码字，例如将满足校验关系的n个比特进行缩短或打孔后生成的新码字；将满足校验关系的n个比特中填充已知比特生成的新码字；将多个码字合并成的新码字；将满足校验关系的n个比特码字进行交织处理，得到新码字等。
调制，2mQAM调制器将输入的m路比特流映射为一路符号流。对于2mQAM的调制模式，共有2m种调制符号
Figure PCTCN2017071926-appb-000001
对应调制星座图中的2m个复数星座点，每个复数星座点由I分量和Q分量组成，每一个调制符号sj都由m个比特(b1,b2,...bm)映射而成。例如8QAM调制器，星座图中共有8个星座点，对应于8个调制符号。且每个符号由3个比特映射而成，如图1B所示8QAM星座图，其中比特与符号间的映射关系如表1所示。将符号调制到载波上可以使用多种方案，例如可以将每个符号的I，Q分量采用幅度调制，分别对应调制在相互正交的两个载波上进行发送，这里的载波可以是电载波、光载波等。
比特 I Q
000 -1 -1
001 3 -1
011 1 -3
010 -3 -3
110 -1 3
111 3 3
101 1 1
100 -3 1
表1 8QAM的符号与比特映射关系
本申请实施例对待调制的码字序列进行处理，使得调制后的符号和待调制的码字之间存在一定的对应关系。具体的，待调制的码字序列中每个码字包括N个比特，待调制的码字序列至少包括第一码字；将码字序列映射为M路序列，每路序列包括N/M个来自于第一码字的比特；将M路序列映射为符号序列，每个符号对应M个比特，所述M个比特分别来自于所述M路序列，其中N/M个第一类符号对应的第一比特来自于所述第一码字，N/M个第二类符号对应的第二比特来自于所述第一码字。
为了补偿高阶调制带来的SNR代价，本申请提出一种编码映射调制比特的方法，使得映射为同一个高阶调制符号的比特来自于两个或两个以上的码字。这样，在解调时，来自于前一个码字的比特来完成译码后，获得更准确的信息，来帮助来自于第二个码字的比特进行解调，解调后的比特进行第二个码字的译码，获得准确的信息后，帮助来自第三个码字的比特进行解调，以此类推，完成所有比特的解调。
下面以8QAM调制为例进行说明，8QAM星座图中共有8个星座点，对应于8个调制符号，每个调制符号由3个比特映射而成。
如图2A所示，为本申请实施例提供的一种发送端设备结构图,包括：编码器201、交织器202、调制器203。
其中编码器201用于实现上面提到的编码功能，例如信息比特流U＝{{u1,1,u1,2,…,u1,k}，{u2,1,u2,2,…,u2,k},{u3,1,u3,2,…,u3,k}…}进入编码器，每k个比特组成一个信息序列,记为Ui，利用同一个编码规则对每个信息序列进行编码，在每个信息子序列中添加p个校验比特，组成长度为n的码字。输出编码比特流Q＝{{q1,1,q1,2,…,q1,n}{q2,1,q2,2,…,q2,n},{q3,1,q3,2,…,q3,n…},其中{qi,1,qi,2,…,qi,n}称之为一个码字，记为Qi。
交织器202可以对编码器201输出的编码比特流进行比特级交织处理，输出交织后的编码比特流，例如可以记为A＝{{A1,1,A1,2,…,A1,n}{A2,1,A2,2,…,A2,n},{A3,1,A3,2,…,A3,n}…}，其中Ai＝{A1,1,A1,2,…,A1,n}记为交织后的一个码字，当然交织后的码字长度可以和交织前的码字长度不同。本申请实施例中，交织202并不是必须的，可以直接将编码器201输出的编码比特流发送到调制器203中。
调制器203包括串并转换器2031、延时器2032、映射器2033。
其中串并转换器2031将交织后的编码比特流进行串并转换，转换为3路序列，其中每个码字Ai＝{Ai,1,Ai,2,…,Ai,n}被等分为3份。如果码字Ai＝{Ai,1,Ai,2,…,Ai,n}不能被等分，可以在串并转换前对码字进行处理得到新的码字，新的码字能够被等分为3份。例如可以将码字Ai＝{Ai,1,Ai,2,…,Ai,n}进行缩短或打孔后生成新的码字；可以对码字Ai＝{Ai,1,Ai,2,…,Ai,n}进行填充已知比特生成新的码字；将多个码字Ai＝{Ai,1,Ai,2,…,Ai,n}进行合并处理得到新的码字等等。当然，如果没有交织器202，调制器从编码器201接收编码比特流，则可以对Qi＝{qi,1,qi,2,…,qi,n}进行处理得到新的码字。
对A＝{{A1,1,A1,2,…,A1,n}{A2,1,A2,2,…,A2,n},{A3,1,A3,2,…,A3,n}…}进行串并转换，可以以比特为单位进行串并转换，例如A1,1在第一路，A1,1,A1,2在第二路，…；也可以以n/m比特为单位进行串并转换，例如A1,1,A1,2,…,A1,n/m在第一路，A1,(n/m)+1,A1,(n/m) +2,…,A1,2(n/m)在第二路，当然也可以采用其它转换方法，甚至码字A1和A2的比特在 一路中可以交替出现，只要满足一个码字被均分为n/m份即可，在本实施例中，只要满足一个码字被均分为n/3份即可。
如图2A所示，本申请实施例的第一路序列上包括n/3个延时器3032，由T来标示，延时比特数为n/3个。当然，在其他实施例中，可以是第二路序列或第三路序列上包括n/3个延时器3032。
映射器2032用于将输入的3路比特序列映射为符号序列S，为描述方便，输入的3路比特序列中，每3个并行比特叫做一个调制序列，每个调制序列可以映射为一个符号。
映射器2032的输入比特流如图3A所示，其中X表示0或1，可以由用户自行设定，Ai表示该比特来自于码字Ai。例如，虚线圈中所示的第n个调制序列，d1,n来自于码字A2，其他d2,n,d3,n比特来自于码字A3，即第n个调制序列对应的的输入比特分别来自于码字A2和码字A3。只要满足有n/3个第一类符号对应的的第一比特来自于所述第一码字，同时有n/3个第二类符号对应的第二比特也来自于所述第一码字。例如如图3A所示，第1到
Figure PCTCN2017071926-appb-000002
共
Figure PCTCN2017071926-appb-000003
个符号为第一类符号，它们对应的第二比特来自于码字A1，第
Figure PCTCN2017071926-appb-000004
到
Figure PCTCN2017071926-appb-000005
共
Figure PCTCN2017071926-appb-000006
个符号为第二类符号，它们对应的第一比特也来自于码字A1。
如图2B所示，为本申请实施例提供的一种发送端设备结构图,其和图2A的区别为第二路序列也包括n/3个延时器3032。
映射器2032的输入比特流如图3B所示，其中X表示0或1，可以由用户自行设定，Ai表示该比特来自于码字Ai，di,j表示比特流Di在调制序列j输入的比特。例如，虚线圈中所示的第n个调制序列，d1,n和d2,n来自于码字A2，d3,n比特来自于码字A3，即第n个调制序列对应的输入比特分别来自于码字A2和码字A3。
如图2C所示，为本申请实施例提供的一种发送端设备结构图,其和图2B的区别为第一路序列也包括2(n/3)个延时器3032。
映射器2032的输入比特流如图3C所示，其中X表示0或1，可以由用户自行设定，Ai表示该比特来自于码字Ai，di,j表示比特流Di在调制序列j输入的比特。例如，虚线圈中所示的第n个调制序列，d1,n来自于码字A1，d2,n来自于码字A2，d3,n比特来自于码字A3，即第n个调制序列对应的输入比特分别来自于码字A1，码字A2和码字A3。
在其它实施例中，可以采用8QAM调制之外的其它调制模式，对于2mQAM调制，m可以为3以上的其它值。
如图2D所示，为本申请实施例提供的一种发送端设备结构图,其和图2A的区别主要为以下几个地方。
串并转换器2031直接从编码器201接收编码比特流，例如可以为Q＝{{q1,1,q1,2,…,q1,n}{q2,1,q2,2,…,q2,n},{q3,1,q3,2,…,q3,n…}。
串并转换器2031将接收到的编码比特流进行串并转换，转换为m路序列，其中每个码字Qi＝{qi,1,qi,2,…,qi,n}被等分为m份，分别对应m路序列。
如图2D所示，有NUMi路序列上均包括xi*(n/m)个延时器3032，NUMi为大于等于1的整数，xi为大于等于0的整数，例如有NUM1路序列上均包括x1*(n/m)个延 时器3032；有NUM2路序列上均包括x2*(n/m)个延时器3032，有NUMz路序列上均包括xz*(n/m)个延时器3032,优选的，可以设置xi〉xi+1。
映射器2032用于将输入的m路比特序列映射为符号序列，为描述方便，输入的m路比特序列中，每m个并行比特叫做一个调制序列，每个调制序列可以映射为一个符号sj。2mQAM调制中，共有2m个调制符号
Figure PCTCN2017071926-appb-000007
每一个调制符号sj都由m个比特(b1,b2,...bm)映射而成。
映射器2032的输入比特流如图3D所示，其中X表示0或1，可以由用户自行设定，Ai表示该比特来自于码字Ai。例如，虚线圈中所示的第(x1+1)*(n/m)个调制序列，d1,(x1+1)*(n/m),d2,(x1+1)*(n/m),…dNUM1,(x1+1)*(n/m)来自于码字A1,dNUM1+1,(x1+1)*(n/m),dNUM1+2,x1*(n/m),…dNUM1+NUM2,x1*(n/m)来自于码字A2,dm-NUMZ+1,(x1+1)*(n/m),dm-NUMZ+2,(x1+1)*(n/m),…dm,(x1+1)*(n/m)来自于码字AZ，即第(x1+1)*(n/m)个调制序列对应的输入比特分别来自于码字A1,A2…AZ。即第(x1+1)*(n/m)个调制序列对应的比特来自于Z个码字，即是从Z个码字A1，A2，…,AZ中分别提取NUM1，NUM2，…NUMZ个比特组成的，其中NUMi为大于等于1，小于等于m的整数，Z为大于1，小于等于m的整数，且
Figure PCTCN2017071926-appb-000008
当m＝3时，一个23QAM符号所映射比特数为3，分别来自于Z个码字，分别为Ai,0＜i≤Z,且属于码字Ai的比特数记为NUMi。对于图2D所示的实施例，如果m＝3，Z＝2,NUM1＝1,NUM2＝2，则可以得到图2A的实施例，如果m＝3,Z＝2,NUM1＝2,NUM2＝1，则可以得到图2B的实施例，m＝3,Z＝3,NUM1＝1,NUM2＝1,NUM3＝1，则可以得到图2C的实施例。
对于m＝4至12时，当Z取不同值时，其中NUMi的参数取值有较优的配置方式，该配置方式中xi>xi+1。
例如，针对m＝4，其中NUMi的参数取值可以如图7A所示，针对图7A中每一行所示的情况，NUMi的参数取值还可以为所示取值的其它排列组合。
针对m＝5，其中NUMi的参数取值可以如图7B所示，针对图7B中每一行所示的情况，NUMi的参数取值还可以为所示取值的其它排列组合。
针对m＝6，其中NUMi的参数取值可以如图7C所示，针对图7C中每一行所示的情况，NUMi的参数取值还可以为所示取值的其它排列组合。
针对m＝7，其中NUMi的参数取值可以如图7D所示，针对图7D中每一行所示的情况，NUMi的参数取值还可以为所示取值的其它排列组合。
针对m＝8，其中NUMi的参数取值可以如图7E所示，针对图7E中每一行所示的情况，NUMi的参数取值还可以为所示取值的其它排列组合。
针对m＝9，其中NUMi的参数取值可以如图7F所示，针对图7F中每一行所示的情况，NUMi的参数取值还可以为所示取值的其它排列组合。
针对m＝10，其中NUMi的参数取值可以如图7G所示，针对图7G中每一行所示的情况，NUMi的参数取值还可以为所示取值的其它排列组合。
针对m＝11，其中NUMi的参数取值可以如图7H所示，针对图7H中每一行所示的情况，NUMi的参数取值还可以为所示取值的其它排列组合。
针对m＝12，其中NUMi的参数取值可以如图7I所示，针对图7I中每一行所示的情况，NUMi的参数取值还可以为所示取值的其它排列组合。
对于m大于12时，当Z取不同值时，也可以有类似的配置方式，再此不再赘述。
本申请实施例中，对于2mQAM调制，映射出的符号对应2m星座图中2m个星座点中的一个星座点，所述2m星座图中星座点之间的最小欧式距离为第一欧式距离；优选的，所述第一类符号在来自于第一码字的比特确定后在2m星座图中可能对应的星座点之间的最小欧式距离为第二欧式距离，所述第二欧式距离大于所述第一欧式距离。
对于2mQAM的调制模式，共有2m个调制符号
Figure PCTCN2017071926-appb-000009
对应调制星座图中的2m个星座点，每一个调制符号sj都由m个比特(b1,b2,...bm)映射而成。
设m个比特(b1,b2,...bm)可以映射为2m个符号，记为集合为S0，符号之间的最小欧式距离为W0。
第一次分割：
当集合中的b1＝b2＝..＝bNUM1＝0时，所对应的符号组成集合S0,0，为S0的子集，且子集中符号之间的最小距离为W1,0。，即b1,b2,..,bNUM1为来自于第一码字的比特，确定为0后，可能的星座点之间的最小欧式距离为W1,0。
当集合中的b1＝b2＝..＝bNUM1＝1时，所对应的符号组成集合S0,1，为S0的子集，且子集中符号之间的最小距离为W1,1，即b1,b2,..,bNUM1为来自于第一码字的比特，确定为1后，可能的星座点之间的最小欧式距离为W1,1。
且W1＝min(W1,0,W1,1)，优选的，W1〉W0
进一步的，第二次分割：
当集合中的
Figure PCTCN2017071926-appb-000010
且
Figure PCTCN2017071926-appb-000011
时，所对应的符号组成集合S1,0,0,，为S1,0的子集，且子集中符号之间的最小距离为W2,0,0。
当集合中的
Figure PCTCN2017071926-appb-000012
且
Figure PCTCN2017071926-appb-000013
时，所对应的符号组成集合S1,0,1，为S1,0的子集，且子集中符号之间的最小距离为W2,0,1。
当集合中的
Figure PCTCN2017071926-appb-000014
且
Figure PCTCN2017071926-appb-000015
时，所对应的符号组成集合S1,0,0,为S1,0的子集，且子集中符号之间的最小距离为W2,1,0。
当集合中的
Figure PCTCN2017071926-appb-000016
且
Figure PCTCN2017071926-appb-000017
时，所对应的符号组成集合S1,0,1，为S1,0的子集，且子集中符号之间的最小距离为W2,1,1。
且W2＝min(W2,0,0,W2,0,1,W2,1,0,W2,1,1)，优选的，W2〉W1。
…
第z-1次分割：
集合S0经过z次分割后，共产生2z个集合，且每个集合都是S0的一部分。且将记为z-1次分割后，集合内的最小欧式距离记为Wz-1。
优选的，有Wz>Wz-1.
下面以8QAM调制为例进行说明，假设Z＝2，NUM1＝1，NUM2＝2，即图2A和图3A所示的情形。
对于8QAM的调制模式，共有8个调制符号{s1,...,s6,s8}，对应调制星座图中的8个星座点，每一个调制符号sj都由3个数据比特(d1,d2,d3)映射而成。
表2给出了一种将3个比特映射为复数的符号s＝I+jQ的方法，根据表1映射为的星座图如图4A所示。
比特 I Q
000 -2 0
001 0 2
011 2 0
010 0 -2
110 3 -3
111 3 3
101 -3 3
100 -3 -3
表2 8QAM的星座点映射
从图中可以看出，在第一个比特确定时，符号可能对应的星座点可以视为QPSK星座图。例如当第一个比特为0时，符号可能对应的星座点为内圈所示的4个星座点，可以视为QPSK星座图。当第一个比特为1时，符号可能对应的星座点为外圈中的4个星座点，也可以视为QPSK星座图。众所周知，QPSK星座点的最小欧式距离大于8QAM星座点的最小欧式距离。当第一个比特已知时，等价于将欧式距离进行放大。
表3给出了另外一种将3个比特映射为复数的符号s＝I+jQ的方法，根据表2映射为的星座图如图4B所示。
比特 I Q
000 3 -1
001 1 -3
010 3 3
011 -3 -3
100 1 1
101 -1 -1
110 -1 3
111 -3 1
表3 8QAM的星座点映射
从图4B中可以看出，在第一个比特确定后，符号可能对应的星座点也可以视为QPSK星座图。第一个比特为0时，符号可能对应的星座点为右上图所示的方形星座图(实线部分)。当第一个比特为1时，符号可能对应的星座点为右下所示的星座图(实线部分)。右边两个星座图中星座点的欧式距离大于左图中八个点之间的欧式距离。当第一个比特已知时，等价于将欧式距离进行放大。
如图2E所示，为本申请实施例提供的一种发送端设备结构图,其和图2A的区别为调制器包括交织器2034和映射器2033，不包括交织器202。
交织器2032将接收到的编码比特流进行交织处理，例如接收到的编码比特流为Q＝{{q1,1,q1,2,…,q1,n}{q2,1,q2,2,…,q2,n},{q3,1,q3,2,…,q3,n…}，假设n＝12。
假设A＝{a1,a2,a3,a4,a5,a6,a7,a8,a9a10,a11,a12…}＝{{Q1,1,Q1,2,Q1,3,Q1,4,Q1,5,Q1,6,Q1,7,Q1,8,Q1,9,Q1,10,Q1,11,Q1,12}，{Q2,1,Q2,2,Q2,3,Q2,4,Q2,5,Q2,6,Q2,7,Q2,8,Q2,9,Q2,10,Q2,11,Q2,12}…}，即{a1,a2,a3,a4,a5,a6,a7,a8,a9a10,a11,a12}对应于码字Q1＝{Q1,1,Q1,2,Q1,3,Q1,4,Q1,5,Q1,6,Q1,7,Q1,8,Q1,9,Q1,10,Q1,11,Q1,12}，比特a13-比特a24对应于码字A2。
下面说明交织器2034对序列A的处理，处理后输出m个序列，下面说明两种典型的交织规则，
规则一，输出的m个序列分别为：
Figure PCTCN2017071926-appb-000018
此时交织器的交织规则为：输出m路序列，比特比特aL经过交织后在第row＝L％m行的
Figure PCTCN2017071926-appb-000019
列输出，其中L％m为L/m的取余数，
Figure PCTCN2017071926-appb-000020
为L/m取整数。可知当row＝NUMi-1+1,NUMi-1+2，…NUMi,时，
Figure PCTCN2017071926-appb-000021
对于此交织规则，如果m＝3，x1＝2,x2＝1,x3＝0，则
D1＝{X,X,X,X,X,X,X,X,a1,a4,a7,a10,a13,a16,a19,a22..}；
D2＝{X,X,X,X,a2,a5,a8,a11,a14,a17,a20,a23...}；
D3＝{a3,a6,a9,a12,a15,a18,a21,a24…}
即：
D1＝{X,X,X,X,X,X,X,X,Q1,1,Q1,4,Q1,7,Q1,10,Q2,1,Q2,4,Q2,7,Q2,10…}；
D2＝{X,X,X,X,Q1,2,Q1,5,Q1,8,Q1,11,Q2,2,Q2,5,Q2,8,Q2,11...}；
D3＝{Q1,3,Q1,6,Q1,9,Q1,12,Q2,3,Q2,6,Q2,9,Q2,12...}
规则二，输出的m个序列分别为：
Figure PCTCN2017071926-appb-000022
此时交织器的交织规则为：输出m路序列，比特比特aL经过交织后在第
Figure PCTCN2017071926-appb-000023
行的
Figure PCTCN2017071926-appb-000024
列输出，其中L％(n/m)为L/(n/m)的取余数，
Figure PCTCN2017071926-appb-000025
为L/m取整数。可知当row＝NUMi-1+1,NUMi-1+2，…NUMi,时，
Figure PCTCN2017071926-appb-000026
对于此交织规则，如果m＝3，x1＝2,x2＝1,x3＝0，则
D1＝{X,X,X,X,X,X,X,X,a1,a2,a3,a4,a13,a14,a15,a16..}；
D2＝{X,X,X,X,a5,a6,a7,a8,a17,a18,a19,a20...}；
D3＝{a9,a10,a11,a12,a21,a22,a23,a24...}
即：
D1＝{X,X,X,X,X,X,X,X,Q1,1,Q1,2,Q1,3,Q1,4,Q2,1,Q2,2,Q2,3,Q2,4…}；
D2＝{X,X,X,X,Q1,5,Q1,6,Q1,7,Q1,8,Q2,5,Q2,6,Q2,7,Q2,8...}；
D3＝{Q1,9,Q1,10,Q1,11,Q1,12,Q2,9,Q2,10,Q2,11,Q2,12...}
在实际应用中，可以有很多种交织规则，只要满足M路序列中每路序列包括N/M个来自于第一码字的比特，最终映射出的符号满足N/M个第一类符号对应的的第一比特来自于所述第一码字，N/M个第二类符号对应的第二比特来自于所述第一码字即可。比特之间的顺序可以打乱交织，码字和码字之间的比特也可以打乱交织。
本申请实施例中将码字序列映射为M路序列,每路序列包括N/M个来自于第一码字的比特；将M路序列映射为符号序列，每个符号对应M个比特，所述M个比特分别来自于所述M路序列，其中N/M个第一类符号对应的的第一比特来自于所述第一 码字，N/M个第二类符号对应的第二比特来自于所述第一码字。也就是说，M路序列中的第一码字相关比特之间产生错位。对于第一类符号，其对应的M个比特中有些比特来自于第一码字，有些比特来自于其它码字，对于第二类符号，其对应的M个比特中有些比特来自于第一码字，有些比特来自于其它码字。
接收端接收到第一类符号后，可以对第一类符号进行第一次解调，对第二类符号进行第一次解调，对第一码字相关比特完成译码后，可以对第一类符号或第二类符号进行再次解调，因为第一类符号中来自于第一码字的比特已经确定，所以可以提高第一类符号中来自于其它码字的比特的解调准确率。
如图5A所示，为本申请实施例提供的一种接收端设备结构图,包括：解调器501、译码器502。
其中，解调器501，用于接收经过信道传输的符号序列，所述符号序列为权利要求1-8任一项权利要求产生的符号序列，对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比，对第二类符号进行解调处理，得到来自于第一码字的比特的对数似然比；
译码器502，用于根据所有来自于第一码字的比特的对数似然比进行译码，得到第一外信息；
解调器501，还用于接收经过信道传输的所述符号序列，还用于利用所述第一外信息对所述第二类符号进行解调处理，得到来自于其它码字的比特的对数似然比。
如果所述第一类符号还包括来自第二码字的比特，
所述译码器502，还可以用于根据所有来自于第二码字的比特的对数似然比进行译码，得到第二外信息；
所述解调器501用于对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比包括：
所述解调器501，用于利用所述第二外信息对所述第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比。
接收端设备进行接收可以采用很多种方案，只要使用第一码字的信息对第二类符号的其它码字的比特进行解调即可。下面给出一种具体的实现装置和实现方案。
如图5B所示，为本申请实施例提供的另一种接收端设备结构图,包括：解调器501、并串转换器503，解交织器504、译码器502、交织器505，所述解调器501具体包括解调子模块5011、缓存器5012、解调子模块5013、选择器5014。
以8QAM为例说明图5B的接收端设备的接收方法。根据前面图2A和图3A相关的实施例对发送端的介绍，8QAM的每一个调制符号sj都由3个数据比特(d1,d2,d3)映射而成。d1来自于前一个码字，d2，d3来自于第二个码字。
假设编码后码字通过调制得到调制符号s。s经过信道后的接收信号为：
y＝s+n            (1)
其中，n为信道的加性噪声，其各维均服从均值为0方差为σ2的复高斯分布。
接收符号yf，设yf由3个比特映射而成，记为{d1,d2,d3}，比特d1来自码字Ai，d2,d3来自码字Ai+1
图6为本申请实施例提供的一种接收端设备处理流程图。具体为：
对于f＝1到n/3，和图3A对应。
(1)接收符号yf进行解调子模块5011的第一解调，得到来自于码字A1映射在D2和D3序列中的比特的对数似然比，将比特的对数似然比缓存等待码字A1的剩余比特完成解调。
对于f＝1+3/n到2*n/3，
(2)接收符号yf进行解调子模块5011的第一解调，得到码字A1映射在D1序列中的比特的对数似然比，同时缓存器5012缓存符号yf的信息，至此码字A1的所有比特完成解调。
(3)并串转换器503将解调后的比特的对数似然比进行并串转换为一路信息后，解交织器504进行解交织，解交织规则为发送端交织的逆向过程。
(4)将解交织后的比特对数似然比送入译码器502进行译码，得到硬判决信息和外信息。硬判决信息为接收端译码得到的最终信息。
(5)交织器505将译码得到的外信息重新进行交织，交织过程与发送端交织过程相同。
(6)解调子模块5013利用步骤(4)得到的外信息对yf(f＝3/n到2*n/3)中来自码字A2的比特进行第二解调，得到码字A2映射在D2和D3序列中的比特的对数似然比，将比特的对数似然比缓存等待码字A2的剩余比特完成解调。
对于f＝1+2*n/3到n，
(7)解调子模块5011对接收符号yf进行第一解调，得到码字A2映射在D1序列中的比特的对数似然比，同时缓存器5012缓存符号yf的信息，至此码字A2的所有比特完成解调.
(8)执行步骤(3)-(6)，得到码字A2的硬判决信息和外信息，并利用外信息得到接收符号yf(f＝2*n/3到n)中来自码字A3映射在D2和D3序列中的比特的对数似然比。
当f等于其他值时，重复步骤(7)和步骤(8)，对接收符号进行解调和译码。
下面对解调子模块5011的第一解调进行说明：
计算接收符号与各星座点的欧式距离。对于比特di的比特LLR为该符号到di＝1的星座点的欧式距离之和减去该符号到di＝0的星座点的欧式距离之和。也可进一步简化为，比特di的比特LLR为该符号到di＝1的星座点的欧式距离的最小值减去该符号到di＝0的星座点的欧式距离的最小值。
具体可以用公式(1)-(4)表示。
则有根据接收信号得到发送符号si为sj的符号概率为：
Figure PCTCN2017071926-appb-000027
其中yi为接收系统在第i个时刻接收到的符号，si为与yi对应的发送端发送的符号。
p(si＝sj|yi)表示在已知接收信号yi时，发送端发送的符号si为sj的概率。σ为高斯信道的标准差,exp为指数操作。
每个比特的对数似然比为：
Figure PCTCN2017071926-appb-000028
Figure PCTCN2017071926-appb-000029
其中yi接收系统在时刻i接收到的符号，si为与yi对应的发送端发送的符号。LLR(dk)为第k个比特的对数似然比，ln为自然对数。
p(dk＝0|yi)表示在已知接收信号yi时，发送端发送的符号si的第k个比特为0的概率。p(dk＝1|yi)为表示在已知接收信号yi时，发送端发送的符号si的第k个比特为1的概率。σ为高斯信道的标准差。exp表示指数操作。
实际使用时可以只取求和项中的最大值，这时每个码字比特的对数似然比可以简化为：
Figure PCTCN2017071926-appb-000030
其中yi接收系统在时刻i接收到的符号，si为与yi对应的发送端发送的符号。LLR(dk)为第k个比特的对数似然比，ln为自然对数。
p(dk＝0|yi)表示在已知接收信号yi时，发送端发送的符号si的第k个比特为0的概率。p(dk＝1|yi)为表示在已知接收信号yi时，发送端发送的符号si的第k个比特为1的概率。σ为高斯信道的标准差。exp表示指数操作。
下面对解调子模块5013的第二解调进行说明：.
(1)计算接收符号与各星座点的欧式距离。其中接收符号到d＝0的星座点的欧式距离更新为原始的欧式距离叠加译码器输出的外信息。到d1＝1的星座点的欧式距离保持不变。
(2)对于比特dk的比特LLR为该符号到dk＝1的星座点的欧式距离之和减去该符号到dk＝0的星座点的欧式距离之和。也可进一步简化为，比特dk的比特LLR为该符号到dk＝1的星座点的欧式距离的最小值减去该符号到dk＝0的星座点的欧式距离的最小值。
具体可用公式(5)
对于d1＝0的符号，其符号概率的计算方式更新为：
Figure PCTCN2017071926-appb-000031
对于d1＝1的符号，其符号概率的计算方式保持公式(1)不变
然后按照解调操作1计算每个d2,d3的对数似然比(参考公式(2)(3)(4))。
其中yi接收系统在时刻i接收到的符号，si为与yi对应的发送端发送的符号。p(si＝sj|yi)表示在已知接收信号yi时，发送端发送的符号si为sj的概率。σ为高斯信道的标准差。exp表示指数操作。
作为一种实施例，上文提到的外信息可以有三种取值方式，分别为
(1)外信息为译码器得到的后验信息减去输入译码器的先验信息。
(2)外信息为译码器得到的后验信息。
(3)将(1)或(2)中的值保持符号不变，如果译码正确，则将值设为无穷大，否则值设为0。
本领域内的技术人员应明白，本申请的实施例可提供为方法、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、装置(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理装置的处理器以产生一个机器，使得通过计算机或其他可编程数据处理装置的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理装置以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理装置上，使得在计算机或其他可编程装置上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程装置上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解 释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (20)

  1. 一种调制方法，其特征在于，包括：
    接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；
    将所述码字序列映射为M路序列,每路序列包括N/M个来自于第一码字的比特；
    将M路序列映射为符号序列，每个符号对应M个比特，所述M个比特分别来自于所述M路序列，其中N/M个第一类符号对应的的第一比特来自于所述第一码字，N/M个第二类符号对应的第二比特来自于所述第一码字。
  2. 根据权利要求1所述的方法，其特征在于，所述符号对应2m星座图中2m个星座点中的一个星座点，所述2m星座图中星座点之间的最小欧式距离为第一欧式距离；所述第一类符号在来自于第一码字的比特确定后在2m星座图中可能对应的星座点之间的最小欧式距离为第二欧式距离，所述第二欧式距离大于所述第一欧式距离。
  3. 根据权利要求1或2所述的方法，其特征在于，所述将所述码字序列映射为M路序列，包括：
    将所述码字序列进行串并转换，得到M路序列,每路序列包括N/M个来自于第一码字的比特；
    对M路序列中的至少一路序列进行延时处理，延时比特数为X*(N/M)个，X为大于等于1的整数。
  4. 根据权利要求1或2所述的方法，其特征在于，所述将所述码字序列映射为M路序列，包括：
    将所述码字序列进行交织处理，得到M路序列,每路序列包括N/M个来自于第一码字的比特。
  5. 根据权利要求1所述的方法，其特征在于，M等于3时，将所述码字序列映射为M路序列，具体包括：
    将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；
    对第一序列进行延时处理，延时比特数为N/3个。
  6. 根据权利要求1所述的方法，其特征在于，M等于3时，将所述码字序列映射为M路序列，具体包括：
    将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；
    对第一序列进行延时处理，延时比特数为N/3个；
    对第二序列进行延时处理，延时比特数为N/3个。
  7. 根据权利要求1所述的方法，其特征在于，M等于3时，将所述码字序列映射为M路序列，具体包括：
    将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；
    对第一序列进行延时处理，延时比特数为2(N/3)个；
    对第二序列进行延时处理，延时比特数为N/3个。
  8. 一种接收方法，其特征在于，包括：
    接收经过信道传输的符号序列，所述符号序列为权利要求1-7任一项权利要求产生的符号序列；
    对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比；
    对第二类符号进行解调处理，得到来自于第一码字的比特的对数似然比；
    根据所有来自于第一码字的比特的对数似然比进行译码，得到第一外信息；
    利用所述第一外信息对所述第二类符号进行解调处理，得到来自于其它码字的比特的对数似然比。
  9. 根据权利要求8所述的方法，其特征在于，所述第一类符号还包括来自第二码字的比特，所述对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比之前还包括：
    根据所有来自于第二码字的比特的对数似然比进行译码，得到第二外信息；
    所述对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比包括：
    利用所述第二外信息对所述第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比。
  10. 根据权利要求8所述的方法，其特征在于，所述第一外信息为译码得到的后验信息减去译码的先验信息得到的信息；或者所述第一外信息为译码得到的后验信息。
  11. 一种调制装置，其特征在于，包括：
    第一映射器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列映射为M路序列,每路序列包括N/M个来自于第一码字的比特；
    第二映射器，用于将M路序列映射为符号序列，每个符号对应M个比特，所述M个比特分别来自于所述M路序列，其中N/M个第一类符号对应的的第一比特来自于所述第一码字，N/M个第二类符号对应的第二比特来自于所述第一码字。
  12. 根据权利要求11所述的装置，其特征在于，所述符号对应2m星座图中2m个星座点中的一个星座点，所述2m星座图中星座点之间的最小欧式距离为第一欧式距离；所述第一类符号在来自于第一码字的比特确定后在2m星座图中可能对应的星座点之间的最小欧式距离为第二欧式距离，所述第二欧式距离大于所述第一欧式距离。
  13. 根据权利要求11或12所述的装置，其特征在于，所述第一映射器包括串并转换器和延时器，
    所述串并转换器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列进行串并转换，得到M路序列,每路序列包括N/M个来自于第一码字的比特；
    所述延时器，用于对M路序列中的至少一路序列进行延时处理，延时比特数为X*(N/M)个，X为大于等于1的整数。
  14. 根据权利要求11或12所述的装置，其特征在于，所述第一映射器包括交织器，所述交织器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列进行交织处理，得到M路序列,每路序列包括N/M个来自于第一码字的比特。
  15. 根据权利要求11所述的装置，其特征在于，所述第一映射器包括串并转换器 和延时器，
    所述串并转换器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；
    所述延时器，用于对第一序列进行延时处理，延时比特数为N/3个。
  16. 根据权利要求11所述的装置，其特征在于，所述第一映射器包括串并转换器和延时器，
    所述串并转换器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；
    所述延时器，用于对第一序列进行延时处理，延时比特数为N/3个；对第二序列进行延时处理，延时比特数为N/3个。
  17. 根据权利要求11所述的装置，其特征在于，所述第一映射器包括串并转换器和延时器，
    所述串并转换器，用于接收码字序列，每个码字包括N个比特，所述码字序列至少包括第一码字；还用于将所述码字序列进行串并转换，得到3路序列,每路序列包括N/3个来自于第一码字的比特；
    所述延时器，用于对第一序列进行延时处理，延时比特数为2(N/3)个；对第二序列进行延时处理，延时比特数为N/3个。
  18. 一种接收装置，其特征在于，包括：
    解调器，用于接收经过信道传输的符号序列，所述符号序列为权利要求11-17任一项权利要求产生的符号序列，对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比，对第二类符号进行解调处理，得到来自于第一码字的比特的对数似然比；
    译码器，用于根据所有来自于第一码字的比特的对数似然比进行译码，得到第一外信息；
    所述解调器，还用于接收经过信道传输的所述符号序列，还用于利用所述第一外信息对所述第二类符号进行解调处理，得到来自于其它码字的比特的对数似然比。
  19. 根据权利要求18所述的装置，其特征在于，所述第一类符号还包括来自第二码字的比特，
    所述译码器，还用于根据所有来自于第二码字的比特的对数似然比进行译码，得到第二外信息；
    所述解调器用于对第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比包括：
    所述解调器，用于利用所述第二外信息对所述第一类符号进行解调处理，得到来自于第一码字的比特的对数似然比。
  20. 根据权利要求18所述的装置，其特征在于，所述第一外信息为译码得到的后验信息减去译码的先验信息得到的信息；或者所述第一外信息为译码得到的后验信息。
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