WO2017149362A1 - Consultation de paramètre mémoire du circuit intégré spécifique à une application (asic) - Google Patents

Consultation de paramètre mémoire du circuit intégré spécifique à une application (asic) Download PDF

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Publication number
WO2017149362A1
WO2017149362A1 PCT/IB2016/051254 IB2016051254W WO2017149362A1 WO 2017149362 A1 WO2017149362 A1 WO 2017149362A1 IB 2016051254 W IB2016051254 W IB 2016051254W WO 2017149362 A1 WO2017149362 A1 WO 2017149362A1
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WO
WIPO (PCT)
Prior art keywords
memory
line card
vendor
memory interface
interfaces
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PCT/IB2016/051254
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English (en)
Inventor
Danny Lee
Original Assignee
Telefonaktiebolaget Lm Ericsson (Publ)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Telefonaktiebolaget Lm Ericsson (Publ) filed Critical Telefonaktiebolaget Lm Ericsson (Publ)
Priority to PCT/IB2016/051254 priority Critical patent/WO2017149362A1/fr
Publication of WO2017149362A1 publication Critical patent/WO2017149362A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types

Definitions

  • Embodiments of the invention relate to the field of application-specific integrated circuits (ASICs), and more specifically, to the configuration of ASIC memory interfaces.
  • ASICs application-specific integrated circuits
  • An Application Specific Integrated Circuit can include memory interfaces that provide access to a high-speed memory device (e.g., double data rate fourth generation synchronous dynamic random-access memory (DDR4 SDRAM)).
  • ASIC memory interfaces are typically soldered onto a printed circuit board along with the ASIC.
  • the memory interface needs to be configured with the timing parameter values and shmooing data of the memory device.
  • the timing parameter values and shmooing data may vary depending on the vendor and die revision of the memory device.
  • the timing parameter values and shmooing data are hardcoded into the software that operates the ASIC, and these parameter values and shmooing data are particular to a specific memory device vendor and die revision.
  • any changes to the memory device requires a software modification.
  • Software modification in live systems may cause service interruptions, which may result in customer dissatisfaction and loss of revenue.
  • Reworking a card e.g., a line card
  • Memory components can undergo die revisions almost yearly, and thus this requires last time buys (of memory devices) and associated storage costs, and also incurs upfront costs.
  • each ASIC memory interface is required to use the same memory device vendor and die revision.
  • the contract manufacturer is usually told to use the same memory device vendor and die revision for the entire card. If the contract manufacturer mixes two memory devices from different vendors or having different die revisions on the same card, the memory interfaces may fail. The contract manufacturer then must rework the card so that all the memory devices installed on the card have the same vendor and die revision.
  • a method is implemented by a processor of a line card to provide individualized configuration of one or more application-specific integrated circuit (ASIC) memory interfaces on the line card.
  • the individualized configuration is to allow the one or more memory interfaces to operate with memory devices having different operational characteristics.
  • the method includes selecting a first memory interface to be configured from the one or more memory interfaces, accessing, from a non-volatile memory on the line card, a vendor identifier (ID) and part number of a first memory device installed in the first memory interface, accessing, from the non-volatile memory, one or more timing parameter values associated with the vendor ID and part number of the first memory device, and configuring the first memory interface with the one or more timing parameter values associated with the vendor ID and part number of the first memory device.
  • ID vendor identifier
  • a line card provides individualized configuration of one or more application-specific integrated circuit (ASIC) memory interfaces on the line card.
  • the individualized configuration is to allow the one or more memory interfaces to operate with memory devices having different operational characteristics.
  • the line card includes transceiver circuitry, one or more memory interfaces, a non-transitory machine-readable medium having stored therein a memory interface configuration component, and a processor communicatively coupled to the non-transitory machine-readable medium.
  • the processor is configured to execute the memory interface configuration component.
  • the memory interface configuration component is configured to select a first memory interface to be configured from the one or more memory interfaces, access, from a non- volatile memory on the line card, a vendor identifier (ID) and part number of a first memory device installed in the first memory interface, access, from the non-volatile memory, one or more timing parameter values associated with the vendor ID and part number of the first memory device, and configure the first memory interface with the one or more timing parameter values associated with the vendor ID and part number of the first memory device.
  • ID vendor identifier
  • a non-transitory machine-readable storage medium has computer code stored therein, which when executed by a set of one or more processors of a line card, causes the line card to perform operations for providing individualized configuration of one or more application-specific integrated circuit (ASIC) memory interfaces on the line card.
  • ASIC application-specific integrated circuit
  • the operations include selecting a first memory interface to be configured from the one or more memory interfaces, accessing, from a nonvolatile memory on the line card, a vendor identifier (ID) and part number of a first memory device installed in the first memory interface, accessing, from the non-volatile memory, one or more timing parameter values associated with the vendor ID and part number of the first memory device, and configuring the first memory interface with the one or more timing parameter values associated with the vendor ID and part number of the first memory device.
  • ID vendor identifier
  • FIG. 1 is a block diagram of a line card that implements individualized memory interface configuration, according to some embodiments.
  • Fig. 2 is a flow diagram of a process for storing memory device inventory information, timing parameter values, and shmooing data, according to some embodiments.
  • Fig. 3 is a flow diagram of a process for configuring memory interfaces with appropriate timing parameter values, according to some embodiments.
  • Fig. 4 is a flow diagram of a process for configuring memory interfaces with shmooing data, according to some embodiments.
  • Fig. 5 is a diagram illustrating an image format for a memory device inventory image, where a card has a single application- specific integrated circuit (ASIC), according to some embodiments.
  • ASIC application- specific integrated circuit
  • Fig. 6 is a diagram illustrating an image format for a memory device inventory image, where the card has four ASICs, according to some embodiments.
  • Fig. 7 is a diagram illustrating an image format for a timing parameter image that stores timing parameter values for a single approved memory device, according to some embodiments.
  • Fig. 8 is a diagram illustrating an image format for a timing parameter image that stores timing parameter values for six approved memory devices, according to some embodiments.
  • Fig. 9 is a diagram illustrating an image format for a shmooing data image that stores shmooing data for a single ASIC, according to some embodiments.
  • Fig. 10 is a diagram illustrating an image format for a shmooing data image that stores shmooing data for four ASICs, according to some embodiments.
  • ASIC application-specific integrated circuit
  • references in the specification to "one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
  • Bracketed text and blocks with dashed borders may be used herein to illustrate optional operations that add additional features to embodiments of the invention. However, such notation should not be taken to mean that these are the only options or optional operations, and/or that blocks with solid borders are not optional in certain embodiments of the invention.
  • Coupled is used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, co-operate or interact with each other.
  • Connected is used to indicate the establishment of communication between two or more elements that are coupled with each other.
  • a circuit card assembly (sometimes referred to simply as a "card” - e.g., a line card) may include one or more ASICs.
  • Each ASIC may include one or more memory interfaces that are operable to provide access to a memory device such as a double data rate fourth generation synchronous dynamic random-access memory (DDR4 SDRAM), a reduced latency dynamic random- access memory (RLDRAM3), or other type of volatile memory device.
  • DDR4 SDRAM double data rate fourth generation synchronous dynamic random-access memory
  • RLDRAM3 reduced latency dynamic random- access memory
  • the memory interface needs to be configured with the appropriate timing parameter values of the memory device. Examples of timing parameters include, but are not limited to, refresh rate of the memory device and the number of addressable rows and columns in a memory matrix of the memory device.
  • the timing parameter values are specific to a particular memory device vendor and die revision. Typically, the timing parameter values are hardcoded in the card's software. As a result, each memory interface on the card is forced to use the same memory device vendor and die revision. Also, any replacement of the memory device requires that the new memory device be an exact replacement of the old memory device (e.g., have the same vendor and die revision). Any change to the vendor or die revision of the memory device may require a software rollout.
  • the memory interface In order for a memory interface to operate correctly with a memory device, the memory interface also needs to be shmooed with the memory device.
  • Memory shmooing is typically performed each time the card is powered up. The shmooing results can be used to center the clock with respect to the data pulse. Memory shmooing may take several minutes per memory interface, which can be problematic when the bootup time for an entire card is expected to be less than five minutes.
  • Embodiments described herein overcome the disadvantages of existing techniques by storing, in the card, the vendor identifier (ID) and part numbers of the memory devices installed in the respective memory interfaces of the card, as well as storing timing parameter values for approved memory devices that are indexed by vendor ID and part number.
  • the card can store this information during the manufacturing stage of the card.
  • the card can access the stored information to determine the vendor ID and part number of the memory device installed in a particular memory interface and use that vendor ID and part number as an index to determine the appropriate timing parameter values that should be used to configure that particular memory interface.
  • Each memory interface can be individually configured in a similar fashion, according to the vendor ID and part number of the memory device installed in that particular memory interface.
  • the card can also perform memory shmooing and store the shmooing results as shmooing data.
  • the card can access this information to determine the appropriate shmooing data that should be used to configure each memory interface.
  • This individualized approach to configuring memory interfaces allows the card to be populated with memory devices having different operational characteristics (e.g., having different vendor or die revision), and thus the card is no longer restricted to having a single memory device vendor or die revision. The card no longer assumes that every memory interface should be configured with the same timing parameter values.
  • the card can individually configure each memory interface with the appropriate timing parameter values, according to the vendor and die revision of the memory device installed in that particular memory interface.
  • An advantage of configuring memory interfaces in this way is that during rework of a card, failed memory devices can be replaced with any approved memory device. That is, the memory device need not be the same as the memory device that was originally used during the production of the card. Also, since the card stores the shmooing data, memory shmooing is not required each time the card powers up or re-boots. This allows for faster memory interface configuration. Other embodiments are also described and claimed.
  • Embodiments will primarily be described in the context of a line card. However, it should be understood that embodiments described herein are applicable to other types of circuit card assemblies that include ASIC memory interfaces.
  • Fig. 1 is a block diagram of a line card that implements individualized memory interface configuration, according to some embodiments.
  • the line card 100 includes a processor 110, a non-transitory machine-readable medium 120, a non-volatile memory 130, transceiver circuitry 155, and multiple ASICs 160A-Z.
  • the ASICs 160 may include circuitry to perform various functionalities of the line card.
  • the ASICs 160 may include circuitry to process packets received over a network via transceiver circuitry 155.
  • ASIC 160A includes one or more memory interfaces (e.g., memory interfaces 170A-Z). Each memory interface 170 is operable to provide access to one or more memory devices installed in that memory interface 170.
  • memory interface 170A is operable to provide ASIC 160A with access to memory device 175A and memory interface 170B is operable to provide ASIC 160A with access to memory device 175B.
  • the memory devices 175 may be, for example, a DDR4 SDRAM, a RLDRAM3, or other type of volatile memory device.
  • the other ASICs 160 on the line card 100 (ASICs 160B-160Z) may have a similar configuration to that of ASIC 160A.
  • Timing parameters may include parameters that specify the operational characteristics of a memory device 175 such as a refresh rate of the memory device 175 and the number of addressable rows and columns in a memory matrix of the memory device 175.
  • the shmooing data may include information that is used to center a clock with respect to a data pulse.
  • the non-transitory machine-readable medium 120 has stored therein a memory interface configuration component 125.
  • the line card 100 (and more specifically, the processor 110 of the line card) may execute the memory interface configuration component 125 to perform one or more of the operations described herein to configure the memory interfaces 170 on the line card 100 with the appropriate timing parameter values and shmooing data so that the memory interfaces 170 can operate correctly with their respective memory devices 175.
  • the line card 100 may store information about the memory devices 175 installed in the respective memory interfaces 170.
  • This information may include the vendor ID and part numbers of the memory devices 175 installed in the respective memory interfaces 170, where the vendor ID and part number of a memory device 175 identifies the vendor and die revision of that memory device 175.
  • the line card 100 may store this information in the non-volatile memory 130.
  • the non-volatile memory 130 may include one or more electrically erasable programmable read-only memories
  • the non-volatile memory 130 includes two EEPROMS - a first EEPROM (manufacturing EEPROM 140) and a second EEPROM (parameter EEPROM 150).
  • the information about the memory devices 175 installed in the respective memory interfaces 170 is stored in the manufacturing EEPROM 140 of the non-volatile memory 130.
  • the line card 100 may store timing parameter values associated with various approved memory devices (e.g., the memory devices that the card designer or card manufacturer has approved to be installed in the line card 100). This information may include associations between the vendor ID and part numbers of approved memory devices and the timing parameter values for those approved memory devices.
  • the line card 100 can obtain the timing parameter values of the approved memory devices by parsing and extracting the timing parameter values from an extensible markup language (XML) file that contains the timing parameter values for the approved memory devices.
  • XML extensible markup language
  • the XML file may have been created and maintained by the card designer or manufacturer.
  • the line card 100 may also shmoo the memory interfaces 170 and store the shmooing results as shmooing data.
  • the line card 100 may store the timing parameter values and shmooing data in the non- volatile memory 130. In one embodiment, the timing parameter values and shmooing data are stored in the parameter
  • the line card 100 may access the information stored in the non-volatile memory 130 to determine the appropriate timing parameter values and shmooing data with which to configure each of the memory interfaces 170.
  • the line card 100 may access the non-volatile memory 130 (e.g., manufacturing EEPROM 140) to determine the vendor ID and part number of the memory device 175 installed in a particular memory interface 170.
  • the line card 100 may then access the non-volatile memory 130 (e.g., parameter EEPROM 150) to determine the timing parameter values associated with the vendor ID and part number of that memory device 175 and configure the particular memory interface 170 with those timing parameter values (e.g., by programming a memory controller that manages the particular memory interface 170).
  • the line card 100 can perform similar operations to configure each memory interface 170 with the appropriate timing parameter values, according to the memory device installed in that memory interface 170.
  • the line card 100 may also access the non-volatile memory 130 (e.g., parameter EEPROM 150) to determine the shmooing data associated with a particular memory interface 170 and configure the particular memory interface 170 with the appropriate shmooing data (e.g., by programming a memory controller that manages the particular memory interface 170).
  • the line card 100 can perform similar operations to configure each memory interface 170 with the appropriate shmooing data.
  • the line card 100 individually configures one or more memory interfaces 170 with the appropriate timing parameter values and shmooing data.
  • the line card 100 is provided by way of example and not limitation. It should be understood that the memory interface configuration techniques described herein can be implemented in line cards having a different configuration than the line card 100 depicted in the block diagram.
  • the line card 100 may include any number of ASICs 160 and each ASIC 160 may include any number of memory interfaces 170.
  • the non-volatile memory 130 may be implemented using non-volatile memories other than EEPROMs.
  • Fig. 2 is a flow diagram of a process for storing memory device inventory information, timing parameter values, and shmooing data, according to some embodiments.
  • the process is implemented by a line card 100 or other type of circuit card assembly.
  • the line card 100 may implement the process during the manufacturing stage and/or FVT stage of the line card 100 to store information that can be used by the line card 100 to configure its memory interfaces 170.
  • the operations in the flow diagrams will be described with reference to the exemplary embodiments of the other figures. However, it should be understood that the operations of the flow diagrams can be performed by embodiments of the invention other than those discussed with reference to the other figures, and the embodiments of the invention discussed with reference to these other figures can perform operations different than those discussed with reference to the flow diagrams.
  • the line card 100 stores, for each of the one or more memory interfaces 170 on the line card 100, a vendor ID and part number of a memory device 175 installed in that memory interface 170 in a non-volatile memory 130 of the line card (block 210).
  • the vendor ID and part number of a memory device 175 indicate the vendor and die revision of that memory device 175.
  • the vendor ID is a Joint Electron Device Engineering Council (JEDEC) Manufacturer ID and the part number is a number assigned by the manufacturer of the memory device 175 that identifies the die revision of that memory device 175.
  • JEDEC Joint Electron Device Engineering Council
  • the vendor ID and part number of a memory device 175 can be any value or combination of values that identifies a particular vendor and die revision of a memory device 175.
  • the line card 100 stores, for each memory interface 170, at least an ASIC identifier (ID) and memory interface identifier (ID) of that memory interface 170 (where the ASIC ID identifies the ASIC 160 on which the memory interface 170 resides and the memory interface ID identifies the memory interface 170 on the ASIC 160) and a vendor ID and part number of the memory device 175 installed in that memory interface 170.
  • ID ASIC identifier
  • ID memory interface identifier
  • the line card 100 may store associations between a particular memory interface 170 (identified by ASIC ID and memory interface ID) and a memory device 175 installed in that particular memory interface 170 (identified by vendor ID and part number). These associations may be stored using the ASIC ID and memory interface ID as an index.
  • This information regarding the vendor ID and part numbers of the memory devices 175 installed in the respective memory interfaces 170 may be referred to herein as memory device inventory information and may be stored as an image (referred to herein as a memory device inventory image) in the non-volatile memory 130 (e.g., in the manufacturing EEPROM 140).
  • the memory device inventory image is stored in an image format such as the image format described below with reference to Fig. 5 or Fig. 6.
  • the line card 100 stores, for each of a plurality of vendor ID and part numbers of approved memory devices, one or more timing parameter values associated with that vendor ID and part number in the non-volatile memory 130 (block 220).
  • the approved memory devices are the memory devices 175 that have been approved by the card designer or card manufacturer to be installed in the line card 100.
  • the line card 100 parses and extracts the timing parameter values from an XML file that contains the timing parameter values for approved memory devices.
  • the XML file may have been generated and maintained by the card designer or card manufacturer.
  • the line card 100 stores, for each approved memory device, at least a vendor ID and part number of that approved memory device and one or more timing parameter values for that approved memory device.
  • the line card may store associations between an approved memory device (identified by vendor ID and part number) and timing parameter values for that approved memory device. These associations may be stored using the vendor ID and part number as an index.
  • This information regarding the timing parameter values for approved memory devices may be stored as an image (referred to herein as a timing parameter image) in the non-volatile memory 130 (e.g., in the parameter EEPROM 150).
  • the timing parameter image is stored in an image format such as the image format described below with reference to Fig. 7 or Fig. 8.
  • the line card 100 shmoos each of the one or more memory interfaces 170 on the line card 100 (block 230).
  • the line card 100 then stores, for each of the one or more memory interfaces 170 on the line card 100, shmooing data associated with that memory interface 170 in the non- volatile memory 130 (block 240).
  • this information is stored as an image (referred to herein as a shmooing data image) in the non-volatile memory 130 (e.g., in the parameter EEPROM 150).
  • the shmooing data image is stored in an image format such as the image format described below with reference to Fig. 9 or Fig. 10.
  • the line card 100 stores memory device inventory information, timing parameter values, and shmooing data in the non-volatile memory 130. As will be described in additional detail below, the line card 100 may access this information from the non-volatile memory 130 to configure the memory interfaces 170 with the appropriate timing parameter values and shmooing data.
  • Fig. 3 is a flow diagram of a process for configuring memory interfaces with appropriate timing parameter values, according to some embodiments.
  • the process is implemented by a line card 100 or other type of circuit card assembly.
  • the line card 100 may implement the process when the line card powers up or re-boots to individually configure one or more memory interfaces 170 with the appropriate timing parameter values.
  • the line card 100 selects a memory interface 170 to be configured (block 310).
  • the line card 100 accesses, from a non-volatile memory 130 on the line card 100, a vendor ID and part number of a memory device 175 installed in the selected memory interface 170 (block 320).
  • memory interfaces 170 can be uniquely identified by ASIC ID and memory interface ID, where the ASIC ID identifies an ASIC 160 on which the memory interface 170 resides and the memory interface ID identifies a particular memory interface 170 on the ASIC 160.
  • the line card 100 can use the ASIC ID and memory interface ID of the selected memory interface as a key when accessing the vendor ID and part number from the non-volatile memory 130 (e.g., in the case that vendor ID and part numbers are indexed by ASIC ID and memory interface ID).
  • the line card 100 accesses, from the non-volatile memory 130, one or more timing parameter values associated with the vendor ID and part number of the memory device 175 (block 330).
  • the one or more timing parameter values include, but are not limited to, a value indicative of the refresh rate of the memory device 175 and/or a value indicative of the number of addressable rows and columns in a memory matrix of the memory device 175.
  • timing parameter values include, but are not limited to, a value indicative of any of the following parameters: a refresh to activate or refresh command period (t_rfc), an activate to activate or refresh command period (t_rc), an activate to internal read or write delay (t_rcd_wr), an activate to activate to activate command period to same bank groups for 1/2 kilobyte (KB) page size (t_rrd_l), an activate to activate command period to different bank groups for n KB page size (t_rrd_s), an activate to precharge command period (t_ras), a precharge command period (t_rp), a write recovery time (t_wr), a four activate windows for n KB page size (t_faw), a read to precharge time (t_rtp_s), a delay from start or internal write transaction to internal read command - different bank group (t_wtr_s), a column access strobe n (CAS_n) to CAS_n command delay to same bank
  • the vendor ID and part number of the memory device 175 (obtained in block 320) can be used as a key when accessing the one or more timing parameter values from the non-volatile memory 130 (e.g., in the case that timing parameter values are indexed by vendor ID and part number).
  • the line card 100 then configures the selected memory interface 170 with the one or more timing parameter values associated with the vendor ID and part number of the memory device 175 (block 340).
  • the line card 100 configures the selected memory interface 170 by programming a memory controller that manages the selected memory interface 170 with the one or more timing parameter values.
  • the line card 100 checks whether all memory interfaces 170 have been configured with timing parameter values (decision block 350). If all memory interfaces 170 have not been configured, then the process returns to block 310 to select the next memory interface 170 to be configured. The line card 100 may then repeat the operations of blocks 320-340 for the next memory interface 170. In one embodiment, the line card 100 may include memory interfaces 170 that reside on different ASICs 160 on the line card. The line card 100 can repeat the operations of blocks 320-340 for memory interfaces 170 spanning over multiple ASICs.
  • Fig. 4 is a flow diagram of a process for configuring memory interfaces with shmooing data, according to some embodiments.
  • the process is implemented by a line card 100 or other type of circuit card assembly.
  • the line card 100 may implement the process when the line card powers up or re-boots to individually configure one or more memory interfaces 170 with the appropriate shmooing data.
  • the line card 100 selects a memory interface 170 to be configured (block 410).
  • the line card 100 accesses, from a non-volatile memory 130 on the line card 100, shmooing data associated with the selected memory interface 170 (block 420).
  • memory interfaces 170 can be uniquely identified by ASIC ID and memory interface ID, where the ASIC ID identifies an ASIC 160 on which the memory interface 170 resides and the memory interface ID identifies a particular memory interface 170 on the ASIC 160.
  • the line card 100 can use the ASIC ID and memory interface ID of the selected memory interface 170 as a key when accessing the shmooing data from the non-volatile memory 130 (e.g., in the case that shmooing data is indexed by ASIC ID and memory interface ID).
  • the line card 100 configures the selected memory interface 170 with the shmooing data associated with the selected memory interface 170 (block 430).
  • the line card 100 configures the selected memory interface 170 by programming a memory controller that manages the selected memory interface 170 with the shmooing data.
  • the line card 100 checks whether all memory interfaces 170 have been configured with shmooing data (decision block 440). If all memory interfaces 170 have not been configured, then the process returns to block 410 to select the next memory interface 170 to be configured. The line card 100 may then repeat the operations of blocks 420-430 for the next memory interface 170. In one embodiment, the line card 100 may include memory interfaces 170 that reside on different ASICs 160 on the line card 100. The line card 100 can repeat the operations of blocks 420-430 for memory interfaces 170 spanning over multiple ASICs 160. Returning to decision block 440, if all memory interface 170 have been configured, then the process ends.
  • Fig. 5 is a diagram illustrating an image format for a memory device inventory image, where a card has a single ASIC, according to some embodiments.
  • the card e.g., line card 100
  • the ASIC 160 has thirteen memory interfaces.
  • Each memory interface can be identified by a memory interface number/ID (memory interface number 0 to 12).
  • the first four bytes of the image include header information (e.g., to identify the image).
  • a memory inventory data block follows the header information.
  • the memory inventory data block includes an entry for each memory interface on the ASIC.
  • Each entry in the memory inventory data block associates a memory interface number/ID of a particular memory interface with the vendor ID (e.g., JEDEC Manufacturer ID) and part number of the memory device installed in that particular memory interface.
  • the vendor ID e.g., JEDEC Manufacturer ID
  • memory interface number/ID 0 is associated with a DDR4 memory device part number, indicating that a DDR4 memory device is installed in the memory interface identified by memory interface number/ID 0.
  • Memory interface number 11 is associated with a
  • FIG. 6 is a diagram illustrating an image format for a memory device inventory image, where the card has four ASICs, according to some embodiments. In this example, the card has four ASICs. Each ASIC is identified by an ASIC number/ID (ASIC number 0 to 3).
  • the image includes four memory inventory data blocks, one for each ASIC.
  • Each of the memory inventory data blocks can have a format similar to the format described with reference to the memory inventory data block in Fig. 5.
  • Fig. 7 is a diagram illustrating an image format for a timing parameter image that stores timing parameter values for a single approved memory device, according to some embodiments.
  • the first 20 bytes of the image include header information (e.g., to identify the image).
  • a parameter block follows the header information.
  • the parameter block includes timing parameter values for an approved memory device.
  • the parameter block associates a vendor ID (e.g., JEDEC Manufacturer ID) and part number of the approved memory device with the timing parameter values for that approved memory device.
  • the timing parameter values can be stored as a set of register address offset and register value pairs, which can be used to configure a memory interface with timing parameter values.
  • Fig. 8 is a diagram illustrating an image format for a timing parameter image that stores timing parameter values for six approved memory devices, according to some embodiments.
  • the image stores timing parameter values for six different approved memory devices.
  • the image includes six parameter blocks, one for each approved memory device.
  • Each of the parameter blocks can have a format similar to the format described with reference to the parameter block in Fig. 7.
  • the first parameter block includes the timing parameter values for a DDR4 4Gbit memory device from vendor 1.
  • the second parameter block includes the timing parameter values for a DDR4 4Gbit memory device from vendor 2.
  • the third parameter block includes the timing parameter values for a DDR4 8Gbit memory device from vendor 1.
  • the fourth parameter block includes the timing parameter values for a DDR4 8Gbit memory device from vendor 2.
  • the fifth parameter block includes the timing parameter values for an RLDRAM3 1Gbit memory device from vendor 1.
  • the sixth parameter block includes the timing parameter values for an RLDRAM3 1Gbit memory device from vendor 2.
  • Fig. 9 is a diagram illustrating an image format for a shmooing data image that stores shmooing data for a single ASIC, according to some embodiments.
  • the first 20 bytes of the image include header information (e.g., to identify the image).
  • a shmooing data block follows the header information.
  • the shmooing data block includes the shmooing data associated with an ASIC.
  • the shmooing data block associates an ASIC ID of the ASIC with the shmooing data for that ASIC.
  • the shmooing data can be stored as a set of register address offset and register value pairs, which can be used to configure memory interfaces of the ASIC with shmooing data.
  • Fig. 10 is a diagram illustrating an image format for a shmooing data image that stores shmooing data for four ASICs, according to some embodiments.
  • the image stores shmooing data for four different ASICs.
  • the image includes four shmooing data blocks, one for each ASIC.
  • Each of the shmooing data blocks can have a format similar to the format described with reference to the shmooing data block in Fig. 9.
  • An embodiment of the invention may be an article of manufacture in which a non- transitory machine-readable storage medium (such as microelectronic memory) has stored thereon instructions (e.g., computer code) which program one or more data processing components (generically referred to here as a "processor") to perform the operations described above.
  • a non- transitory machine-readable storage medium such as microelectronic memory
  • instructions e.g., computer code
  • data processing components program one or more data processing components (generically referred to here as a "processor") to perform the operations described above.
  • some of these operations might be performed by specific hardware components that contain hardwired logic (e.g., dedicated digital filter blocks and state machines). Those operations might alternatively be performed by any combination of programmed data processing components and fixed hardwired circuit components.

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Abstract

La présente invention concerne un procédé mis en œuvre par le processeur d'une carte de ligne afin d'obtenir une configuration individualisée d'au moins une interface mémoire du circuit intégré spécifique à une application (ASIC) sur la carte de ligne. La configuration individualisée a pour objectif de permettre à au moins une interface mémoire de fonctionner avec des dispositifs de mémoire ayant différentes caractéristiques de fonctionnement. Ce procédé consiste à sélectionner une première interface mémoire à configurer parmi lesdits interfaces mémoire; à accéder, dans une mémoire non volatile sur la carte de ligne, à un identifiant (ID) de vendeur et à un numéro de pièce d'un premier dispositif de mémoire installé dans la première interface mémoire; à accéder, dans la mémoire non volatile, à une ou plusieurs valeurs de paramètre de temporisation associées à l'ID de vendeur et au numéro de pièce du premier dispositif de mémoire; et à configurer la première interface mémoire avec la ou les valeurs de paramètre de temporisation associées à l'ID de vendeur et au numéro de pièce du premier dispositif de mémoire.
PCT/IB2016/051254 2016-03-04 2016-03-04 Consultation de paramètre mémoire du circuit intégré spécifique à une application (asic) WO2017149362A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0549139A1 (fr) * 1991-12-20 1993-06-30 Sun Microsystems, Inc. Temporisation programmable pour mémoire
US20080082750A1 (en) * 2006-09-28 2008-04-03 Okin Kenneth A Methods of communicating to, memory modules in a memory channel
WO2011090479A1 (fr) * 2010-01-21 2011-07-28 Hewlett-Packard Development Company, L.P. Contrôleur de mémoire

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0549139A1 (fr) * 1991-12-20 1993-06-30 Sun Microsystems, Inc. Temporisation programmable pour mémoire
US20080082750A1 (en) * 2006-09-28 2008-04-03 Okin Kenneth A Methods of communicating to, memory modules in a memory channel
WO2011090479A1 (fr) * 2010-01-21 2011-07-28 Hewlett-Packard Development Company, L.P. Contrôleur de mémoire

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